1/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 * Copyright(c) 2008 - 2010 Realtek Corporation. All rights reserved.
4 *
5 * Contact Information: wlanfae <wlanfae@realtek.com>
6 */
7#ifndef _R819XU_PHYREG_H
8#define _R819XU_PHYREG_H
9
10#define RF_DATA 0x1d4
11
12#define rPMAC_Reset 0x100
13#define rPMAC_TxStart 0x104
14#define rPMAC_TxLegacySIG 0x108
15#define rPMAC_TxHTSIG1 0x10c
16#define rPMAC_TxHTSIG2 0x110
17#define rPMAC_PHYDebug 0x114
18#define rPMAC_TxPacketNum 0x118
19#define rPMAC_TxIdle 0x11c
20#define rPMAC_TxMACHeader0 0x120
21#define rPMAC_TxMACHeader1 0x124
22#define rPMAC_TxMACHeader2 0x128
23#define rPMAC_TxMACHeader3 0x12c
24#define rPMAC_TxMACHeader4 0x130
25#define rPMAC_TxMACHeader5 0x134
26#define rPMAC_TxDataType 0x138
27#define rPMAC_TxRandomSeed 0x13c
28#define rPMAC_CCKPLCPPreamble 0x140
29#define rPMAC_CCKPLCPHeader 0x144
30#define rPMAC_CCKCRC16 0x148
31#define rPMAC_OFDMRxCRC32OK 0x170
32#define rPMAC_OFDMRxCRC32Er 0x174
33#define rPMAC_OFDMRxParityEr 0x178
34#define rPMAC_OFDMRxCRC8Er 0x17c
35#define rPMAC_CCKCRxRC16Er 0x180
36#define rPMAC_CCKCRxRC32Er 0x184
37#define rPMAC_CCKCRxRC32OK 0x188
38#define rPMAC_TxStatus 0x18c
39
40#define MCS_TXAGC 0x340
41#define CCK_TXAGC 0x348
42
43/* Mac block on/off control register */
44#define rFPGA0_RFMOD 0x800 /* RF mode & CCK TxSC */
45#define rFPGA0_TxInfo 0x804
46#define rFPGA0_PSDFunction 0x808
47#define rFPGA0_TxGainStage 0x80c
48#define rFPGA0_RFTiming1 0x810
49#define rFPGA0_RFTiming2 0x814
50#define rFPGA0_XA_HSSIParameter2 0x824
51#define rFPGA0_XB_HSSIParameter2 0x82c
52#define rFPGA0_XA_LSSIParameter 0x840
53#define rFPGA0_XB_LSSIParameter 0x844
54#define rFPGA0_RFWakeUpParameter 0x850
55#define rFPGA0_RFSleepUpParameter 0x854
56#define rFPGA0_XA_RFInterfaceOE 0x860
57#define rFPGA0_XB_RFInterfaceOE 0x864
58#define rFPGA0_XAB_RFInterfaceSW 0x870
59#define rFPGA0_AnalogParameter1 0x880
60#define rFPGA0_AnalogParameter2 0x884
61#define rFPGA0_AnalogParameter3 0x888
62#define rFPGA0_AnalogParameter4 0x88c
63#define rFPGA0_XA_LSSIReadBack 0x8a0
64#define rFPGA0_XB_LSSIReadBack 0x8a4
65#define rFPGA0_PSDReport 0x8b4
66
67/* Page 9 - RF mode & OFDM TxSC */
68#define rFPGA1_RFMOD 0x900
69#define rFPGA1_TxBlock 0x904
70#define rFPGA1_DebugSelect 0x908
71#define rFPGA1_TxInfo 0x90c
72
73#define rCCK0_System 0xa00
74#define rCCK0_AFESetting 0xa04
75#define rCCK0_CCA 0xa08
76/* AGC default value, saturation level */
77#define rCCK0_RxAGC1 0xa0c
78#define rCCK0_RxAGC2 0xa10 /* AGC & DAGC */
79#define rCCK0_RxHP 0xa14
80/* Timing recovery & channel estimation threshold */
81#define rCCK0_DSPParameter1 0xa18
82#define rCCK0_DSPParameter2 0xa1c /* SQ threshold */
83#define rCCK0_TxFilter1 0xa20
84#define rCCK0_TxFilter2 0xa24
85#define rCCK0_DebugPort 0xa28 /* Debug port and TX filter 3 */
86#define rCCK0_FalseAlarmReport 0xa2c
87#define rCCK0_TRSSIReport 0xa50
88#define rCCK0_RxReport 0xa54
89#define rCCK0_FACounterLower 0xa5c
90#define rCCK0_FACounterUpper 0xa58
91
92#define rOFDM0_LSTF 0xc00
93#define rOFDM0_TRxPathEnable 0xc04
94#define rOFDM0_TRMuxPar 0xc08
95#define rOFDM0_TRSWIsolation 0xc0c
96#define rOFDM0_RxDetector1 0xc30 /* PD, BW & SBD */
97#define rOFDM0_RxDetector2 0xc34 /* SBD */
98#define rOFDM0_RxDetector3 0xc38 /* Frame Sync */
99/* PD, SBD, Frame Sync & Short-GI */
100#define rOFDM0_RxDetector4 0xc3c
101#define rOFDM0_RxDSP 0xc40 /* Rx Sync Path */
102#define rOFDM0_CFOandDAGC 0xc44 /* CFO & DAGC */
103#define rOFDM0_CCADropThreshold 0xc48
104#define rOFDM0_ECCAThreshold 0xc4c /* Energy CCA */
105#define rOFDM0_XAAGCCore1 0xc50
106#define rOFDM0_XBAGCCore1 0xc58
107#define rOFDM0_XCAGCCore1 0xc60
108#define rOFDM0_XDAGCCore1 0xc68
109#define rOFDM0_AGCParameter1 0xc70
110#define rOFDM0_AGCParameter2 0xc74
111#define rOFDM0_AGCRSSITable 0xc78
112#define rOFDM0_HTSTFAGC 0xc7c
113#define rOFDM0_XATxIQImbalance 0xc80
114#define rOFDM0_XATxAFE 0xc84
115#define rOFDM0_XCTxIQImbalance 0xc90
116#define rOFDM0_RxHPParameter 0xce0
117#define rOFDM0_TxPseudoNoiseWgt 0xce4
118#define rOFDM0_FrameSync 0xcf0
119#define rOFDM0_DFSReport 0xcf4
120#define rOFDM0_TxCoeff1 0xca4
121#define rOFDM0_TxCoeff2 0xca8
122#define rOFDM0_TxCoeff3 0xcac
123#define rOFDM0_TxCoeff4 0xcb0
124#define rOFDM0_TxCoeff5 0xcb4
125#define rOFDM0_TxCoeff6 0xcb8
126
127#define rOFDM1_LSTF 0xd00
128#define rOFDM1_TRxPathEnable 0xd04
129#define rOFDM1_CFO 0xd08
130#define rOFDM1_CSI1 0xd10
131#define rOFDM1_SBD 0xd14
132#define rOFDM1_CSI2 0xd18
133#define rOFDM1_CFOTracking 0xd2c
134#define rOFDM1_TRxMesaure1 0xd34
135#define rOFDM1_IntfDet 0xd3c
136#define rOFDM1_PseudoNoiseStateAB 0xd50
137#define rOFDM1_PseudoNoiseStateCD 0xd54
138#define rOFDM1_RxPseudoNoiseWgt 0xd58
139#define rOFDM_PHYCounter1 0xda0 /* cca, parity fail */
140#define rOFDM_PHYCounter2 0xda4 /* rate illegal, crc8 fail */
141#define rOFDM_PHYCounter3 0xda8 /* MCS not supported */
142#define rOFDM_ShortCFOAB 0xdac
143#define rOFDM_ShortCFOCD 0xdb0
144#define rOFDM_LongCFOAB 0xdb4
145#define rOFDM_LongCFOCD 0xdb8
146#define rOFDM_TailCFOAB 0xdbc
147#define rOFDM_TailCFOCD 0xdc0
148#define rOFDM_PWMeasure1 0xdc4
149#define rOFDM_PWMeasure2 0xdc8
150#define rOFDM_BWReport 0xdcc
151#define rOFDM_AGCReport 0xdd0
152#define rOFDM_RxSNR 0xdd4
153#define rOFDM_RxEVMCSI 0xdd8
154#define rOFDM_SIGReport 0xddc
155
156#define rTxAGC_Rate18_06 0xe00
157#define rTxAGC_Rate54_24 0xe04
158#define rTxAGC_CCK_Mcs32 0xe08
159#define rTxAGC_Mcs03_Mcs00 0xe10
160#define rTxAGC_Mcs07_Mcs04 0xe14
161#define rTxAGC_Mcs11_Mcs08 0xe18
162#define rTxAGC_Mcs15_Mcs12 0xe1c
163
164#define rZebra1_HSSIEnable 0x0
165#define rZebra1_TRxEnable1 0x1
166#define rZebra1_TRxEnable2 0x2
167#define rZebra1_AGC 0x4
168#define rZebra1_ChargePump 0x5
169#define rZebra1_Channel 0x7
170#define rZebra1_TxGain 0x8
171#define rZebra1_TxLPF 0x9
172#define rZebra1_RxLPF 0xb
173#define rZebra1_RxHPFCorner 0xc
174
175/* Zebra 4 */
176#define rGlobalCtrl 0
177#define rRTL8256_TxLPF 19
178#define rRTL8256_RxLPF 11
179
180/* RTL8258 */
181#define rRTL8258_TxLPF 0x11
182#define rRTL8258_RxLPF 0x13
183#define rRTL8258_RSSILPF 0xa
184
185/* Bit Mask - Page 1*/
186#define bBBResetB 0x100
187#define bGlobalResetB 0x200
188#define bOFDMTxStart 0x4
189#define bCCKTxStart 0x8
190#define bCRC32Debug 0x100
191#define bPMACLoopback 0x10
192#define bTxLSIG 0xffffff
193#define bOFDMTxRate 0xf
194#define bOFDMTxReserved 0x10
195#define bOFDMTxLength 0x1ffe0
196#define bOFDMTxParity 0x20000
197#define bTxHTSIG1 0xffffff
198#define bTxHTMCSRate 0x7f
199#define bTxHTBW 0x80
200#define bTxHTLength 0xffff00
201#define bTxHTSIG2 0xffffff
202#define bTxHTSmoothing 0x1
203#define bTxHTSounding 0x2
204#define bTxHTReserved 0x4
205#define bTxHTAggreation 0x8
206#define bTxHTSTBC 0x30
207#define bTxHTAdvanceCoding 0x40
208#define bTxHTShortGI 0x80
209#define bTxHTNumberHT_LTF 0x300
210#define bTxHTCRC8 0x3fc00
211#define bCounterReset 0x10000
212#define bNumOfOFDMTx 0xffff
213#define bNumOfCCKTx 0xffff0000
214#define bTxIdleInterval 0xffff
215#define bOFDMService 0xffff0000
216#define bTxMACHeader 0xffffffff
217#define bTxDataInit 0xff
218#define bTxHTMode 0x100
219#define bTxDataType 0x30000
220#define bTxRandomSeed 0xffffffff
221#define bCCKTxPreamble 0x1
222#define bCCKTxSFD 0xffff0000
223#define bCCKTxSIG 0xff
224#define bCCKTxService 0xff00
225#define bCCKLengthExt 0x8000
226#define bCCKTxLength 0xffff0000
227#define bCCKTxCRC16 0xffff
228#define bCCKTxStatus 0x1
229#define bOFDMTxStatus 0x2
230/* Bit Mask - Page 8 */
231#define bRFMOD 0x1
232#define bJapanMode 0x2
233#define bCCKTxSC 0x30
234#define bCCKEn 0x1000000
235#define bOFDMEn 0x2000000
236#define bOFDMRxADCPhase 0x10000
237#define bOFDMTxDACPhase 0x40000
238#define bXATxAGC 0x3f
239#define bXBTxAGC 0xf00
240#define bXCTxAGC 0xf000
241#define bXDTxAGC 0xf0000
242#define bPAStart 0xf0000000
243#define bTRStart 0x00f00000
244#define bRFStart 0x0000f000
245#define bBBStart 0x000000f0
246#define bBBCCKStart 0x0000000f
247/* Bit Mask - rFPGA0_RFTiming2 */
248#define bPAEnd 0xf
249#define bTREnd 0x0f000000
250#define bRFEnd 0x000f0000
251/* Channel gain at continue TX. */
252#define b3WireDataLength 0x800
253#define b3WireAddressLength 0x400
254/* 3-wire total control */
255#define bRFSI_RFENV 0x10
256#define bLSSIReadAddress 0x3f000000 /* LSSI "read" address */
257#define bLSSIReadEdge 0x80000000 /* LSSI "read" edge signal */
258#define bLSSIReadBackData 0xfff
259
260#define bDA6Swing 0x380000
261#define bADClkPhase 0x4000000
262#define b80MClkDelay 0x18000000
263#define bAFEWatchDogEnable 0x20000000
264#define bXtalCap 0x0f000000
265#define bXtalCap01 0xc0000000
266#define bXtalCap23 0x3
267#define bXtalCap92x 0x0f000000
268#define bIntDifClkEnable 0x400
269#define bExtSigClkEnable 0x800
270#define bBandgapMbiasPowerUp 0x10000
271#define bAD11SHGain 0xc0000
272#define bAD11InputRange 0x700000
273#define bAD11OPCurrent 0x3800000
274#define bIPathLoopback 0x4000000
275#define bQPathLoopback 0x8000000
276#define bAFELoopback 0x10000000
277#define bDA10Swing 0x7e0
278#define bDA10Reverse 0x800
279#define bDAClkSource 0x1000
280#define bAD7InputRange 0x6000
281#define bAD7Gain 0x38000
282#define bAD7OutputCMMode 0x40000
283#define bAD7InputCMMode 0x380000
284#define bAD7Current 0xc00000
285#define bRegulatorAdjust 0x7000000
286#define bAD11PowerUpAtTx 0x1
287#define bDA10PSAtTx 0x10
288#define bAD11PowerUpAtRx 0x100
289#define bDA10PSAtRx 0x1000
290
291#define bCCKRxAGCFormat 0x200
292
293#define bPSDFFTSamplepPoint 0xc000
294#define bPSDAverageNum 0x3000
295#define bIQPathControl 0xc00
296#define bPSDFreq 0x3ff
297#define bPSDAntennaPath 0x30
298#define bPSDIQSwitch 0x40
299#define bPSDRxTrigger 0x400000
300#define bPSDTxTrigger 0x80000000
301#define bPSDSineToneScale 0x7f000000
302#define bPSDReport 0xffff
303
304/* Page 8 */
305#define bOFDMTxSC 0x30000000
306#define bCCKTxOn 0x1
307#define bOFDMTxOn 0x2
308/* Reset debug page and also HWord, LWord */
309#define bDebugPage 0xfff
310/* Reset debug page and LWord */
311#define bDebugItem 0xff
312#define bAntL 0x10
313#define bAntNonHT 0x100
314#define bAntHT1 0x1000
315#define bAntHT2 0x10000
316#define bAntHT1S1 0x100000
317#define bAntNonHTS1 0x1000000
318
319/* Page a */
320#define bCCKBBMode 0x3
321#define bCCKTxPowerSaving 0x80
322#define bCCKRxPowerSaving 0x40
323#define bCCKSideBand 0x10
324#define bCCKScramble 0x8
325#define bCCKAntDiversity 0x8000
326#define bCCKCarrierRecovery 0x4000
327#define bCCKTxRate 0x3000
328#define bCCKDCCancel 0x0800
329#define bCCKISICancel 0x0400
330#define bCCKMatchFilter 0x0200
331#define bCCKEqualizer 0x0100
332#define bCCKPreambleDetect 0x800000
333#define bCCKFastFalseCCA 0x400000
334#define bCCKChEstStart 0x300000
335#define bCCKCCACount 0x080000
336#define bCCKcs_lim 0x070000
337#define bCCKBistMode 0x80000000
338#define bCCKCCAMask 0x40000000
339#define bCCKTxDACPhase 0x4
340#define bCCKRxADCPhase 0x20000000 /* r_rx_clk */
341#define bCCKr_cp_mode0 0x0100
342#define bCCKTxDCOffset 0xf0
343#define bCCKRxDCOffset 0xf
344#define bCCKCCAMode 0xc000
345#define bCCKFalseCS_lim 0x3f00
346#define bCCKCS_ratio 0xc00000
347#define bCCKCorgBit_sel 0x300000
348#define bCCKPD_lim 0x0f0000
349#define bCCKNewCCA 0x80000000
350#define bCCKRxHPofIG 0x8000
351#define bCCKRxIG 0x7f00
352#define bCCKLNAPolarity 0x800000
353#define bCCKRx1stGain 0x7f0000
354/* CCK Rx Initial gain polarity */
355#define bCCKRFExtend 0x20000000
356#define bCCKRxAGCSatLevel 0x1f000000
357#define bCCKRxAGCSatCount 0xe0
358/* AGCSAmp_dly */
359#define bCCKRxRFSettle 0x1f
360#define bCCKFixedRxAGC 0x8000
361/*#define bCCKRxAGCFormat 0x4000 remove to HSSI register 0x824 */
362#define bCCKAntennaPolarity 0x2000
363#define bCCKTxFilterType 0x0c00
364#define bCCKRxAGCReportType 0x0300
365#define bCCKRxDAGCEn 0x80000000
366#define bCCKRxDAGCPeriod 0x20000000
367#define bCCKRxDAGCSatLevel 0x1f000000
368#define bCCKTimingRecovery 0x800000
369#define bCCKTxC0 0x3f0000
370#define bCCKTxC1 0x3f000000
371#define bCCKTxC2 0x3f
372#define bCCKTxC3 0x3f00
373#define bCCKTxC4 0x3f0000
374#define bCCKTxC5 0x3f000000
375#define bCCKTxC6 0x3f
376#define bCCKTxC7 0x3f00
377#define bCCKDebugPort 0xff0000
378#define bCCKDACDebug 0x0f000000
379#define bCCKFalseAlarmEnable 0x8000
380#define bCCKFalseAlarmRead 0x4000
381#define bCCKTRSSI 0x7f
382#define bCCKRxAGCReport 0xfe
383#define bCCKRxReport_AntSel 0x80000000
384#define bCCKRxReport_MFOff 0x40000000
385#define bCCKRxRxReport_SQLoss 0x20000000
386#define bCCKRxReport_Pktloss 0x10000000
387#define bCCKRxReport_Lockedbit 0x08000000
388#define bCCKRxReport_RateError 0x04000000
389#define bCCKRxReport_RxRate 0x03000000
390#define bCCKRxFACounterLower 0xff
391#define bCCKRxFACounterUpper 0xff000000
392#define bCCKRxHPAGCStart 0xe000
393#define bCCKRxHPAGCFinal 0x1c00
394
395#define bCCKRxFalseAlarmEnable 0x8000
396#define bCCKFACounterFreeze 0x4000
397
398#define bCCKTxPathSel 0x10000000
399#define bCCKDefaultRxPath 0xc000000
400#define bCCKOptionRxPath 0x3000000
401
402/* Page c */
403#define bNumOfSTF 0x3
404#define bShift_L 0xc0
405#define bGI_TH 0xc
406#define bRxPathA 0x1
407#define bRxPathB 0x2
408#define bRxPathC 0x4
409#define bRxPathD 0x8
410#define bTxPathA 0x1
411#define bTxPathB 0x2
412#define bTxPathC 0x4
413#define bTxPathD 0x8
414#define bTRSSIFreq 0x200
415#define bADCBackoff 0x3000
416#define bDFIRBackoff 0xc000
417#define bTRSSILatchPhase 0x10000
418#define bRxIDCOffset 0xff
419#define bRxQDCOffset 0xff00
420#define bRxDFIRMode 0x1800000
421#define bRxDCNFType 0xe000000
422#define bRXIQImb_A 0x3ff
423#define bRXIQImb_B 0xfc00
424#define bRXIQImb_C 0x3f0000
425#define bRXIQImb_D 0xffc00000
426#define bDC_dc_Notch 0x60000
427#define bRxNBINotch 0x1f000000
428#define bPD_TH 0xf
429#define bPD_TH_Opt2 0xc000
430#define bPWED_TH 0x700
431#define bIfMF_Win_L 0x800
432#define bPD_Option 0x1000
433#define bMF_Win_L 0xe000
434#define bBW_Search_L 0x30000
435#define bwin_enh_L 0xc0000
436#define bBW_TH 0x700000
437#define bED_TH2 0x3800000
438#define bBW_option 0x4000000
439#define bRatio_TH 0x18000000
440#define bWindow_L 0xe0000000
441#define bSBD_Option 0x1
442#define bFrame_TH 0x1c
443#define bFS_Option 0x60
444#define bDC_Slope_check 0x80
445#define bFGuard_Counter_DC_L 0xe00
446#define bFrame_Weight_Short 0x7000
447#define bSub_Tune 0xe00000
448#define bFrame_DC_Length 0xe000000
449#define bSBD_start_offset 0x30000000
450#define bFrame_TH_2 0x7
451#define bFrame_GI2_TH 0x38
452#define bGI2_Sync_en 0x40
453#define bSarch_Short_Early 0x300
454#define bSarch_Short_Late 0xc00
455#define bSarch_GI2_Late 0x70000
456#define bCFOAntSum 0x1
457#define bCFOAcc 0x2
458#define bCFOStartOffset 0xc
459#define bCFOLookBack 0x70
460#define bCFOSumWeight 0x80
461#define bDAGCEnable 0x10000
462#define bTXIQImb_A 0x3ff
463#define bTXIQImb_B 0xfc00
464#define bTXIQImb_C 0x3f0000
465#define bTXIQImb_D 0xffc00000
466#define bTxIDCOffset 0xff
467#define bTxQDCOffset 0xff00
468#define bTxDFIRMode 0x10000
469#define bTxPesudoNoiseOn 0x4000000
470#define bTxPesudoNoise_A 0xff
471#define bTxPesudoNoise_B 0xff00
472#define bTxPesudoNoise_C 0xff0000
473#define bTxPesudoNoise_D 0xff000000
474#define bCCADropOption 0x20000
475#define bCCADropThres 0xfff00000
476#define bEDCCA_H 0xf
477#define bEDCCA_L 0xf0
478#define bLambda_ED 0x300
479#define bRxInitialGain 0x7f
480#define bRxAntDivEn 0x80
481#define bRxAGCAddressForLNA 0x7f00
482#define bRxHighPowerFlow 0x8000
483#define bRxAGCFreezeThres 0xc0000
484#define bRxFreezeStep_AGC1 0x300000
485#define bRxFreezeStep_AGC2 0xc00000
486#define bRxFreezeStep_AGC3 0x3000000
487#define bRxFreezeStep_AGC0 0xc000000
488#define bRxRssi_Cmp_En 0x10000000
489#define bRxQuickAGCEn 0x20000000
490#define bRxAGCFreezeThresMode 0x40000000
491#define bRxOverFlowCheckType 0x80000000
492#define bRxAGCShift 0x7f
493#define bTRSW_Tri_Only 0x80
494#define bPowerThres 0x300
495#define bRxAGCEn 0x1
496#define bRxAGCTogetherEn 0x2
497#define bRxAGCMin 0x4
498#define bRxHP_Ini 0x7
499#define bRxHP_TRLNA 0x70
500#define bRxHP_RSSI 0x700
501#define bRxHP_BBP1 0x7000
502#define bRxHP_BBP2 0x70000
503#define bRxHP_BBP3 0x700000
504/* The threshold for high power */
505#define bRSSI_H 0x7f0000
506/* The threshold for ant diversity */
507#define bRSSI_Gen 0x7f000000
508#define bRxSettle_TRSW 0x7
509#define bRxSettle_LNA 0x38
510#define bRxSettle_RSSI 0x1c0
511#define bRxSettle_BBP 0xe00
512#define bRxSettle_RxHP 0x7000
513#define bRxSettle_AntSW_RSSI 0x38000
514#define bRxSettle_AntSW 0xc0000
515#define bRxProcessTime_DAGC 0x300000
516#define bRxSettle_HSSI 0x400000
517#define bRxProcessTime_BBPPW 0x800000
518#define bRxAntennaPowerShift 0x3000000
519#define bRSSITableSelect 0xc000000
520#define bRxHP_Final 0x7000000
521#define bRxHTSettle_BBP 0x7
522#define bRxHTSettle_HSSI 0x8
523#define bRxHTSettle_RxHP 0x70
524#define bRxHTSettle_BBPPW 0x80
525#define bRxHTSettle_Idle 0x300
526#define bRxHTSettle_Reserved 0x1c00
527#define bRxHTRxHPEn 0x8000
528#define bRxHTAGCFreezeThres 0x30000
529#define bRxHTAGCTogetherEn 0x40000
530#define bRxHTAGCMin 0x80000
531#define bRxHTAGCEn 0x100000
532#define bRxHTDAGCEn 0x200000
533#define bRxHTRxHP_BBP 0x1c00000
534#define bRxHTRxHP_Final 0xe0000000
535#define bRxPWRatioTH 0x3
536#define bRxPWRatioEn 0x4
537#define bRxMFHold 0x3800
538#define bRxPD_Delay_TH1 0x38
539#define bRxPD_Delay_TH2 0x1c0
540#define bRxPD_DC_COUNT_MAX 0x600
541/*#define bRxMF_Hold 0x3800*/
542#define bRxPD_Delay_TH 0x8000
543#define bRxProcess_Delay 0xf0000
544#define bRxSearchrange_GI2_Early 0x700000
545#define bRxFrame_Guard_Counter_L 0x3800000
546#define bRxSGI_Guard_L 0xc000000
547#define bRxSGI_Search_L 0x30000000
548#define bRxSGI_TH 0xc0000000
549#define bDFSCnt0 0xff
550#define bDFSCnt1 0xff00
551#define bDFSFlag 0xf0000
552
553#define bMFWeightSum 0x300000
554#define bMinIdxTH 0x7f000000
555
556#define bDAFormat 0x40000
557
558#define bTxChEmuEnable 0x01000000
559
560#define bTRSWIsolation_A 0x7f
561#define bTRSWIsolation_B 0x7f00
562#define bTRSWIsolation_C 0x7f0000
563#define bTRSWIsolation_D 0x7f000000
564
565#define bExtLNAGain 0x7c00
566
567/* Page d */
568#define bSTBCEn 0x4
569#define bAntennaMapping 0x10
570#define bNss 0x20
571#define bCFOAntSumD 0x200
572#define bPHYCounterReset 0x8000000
573#define bCFOReportGet 0x4000000
574#define bOFDMContinueTx 0x10000000
575#define bOFDMSingleCarrier 0x20000000
576#define bOFDMSingleTone 0x40000000
577/* #define bRxPath1 0x01
578 * #define bRxPath2 0x02
579 * #define bRxPath3 0x04
580 * #define bRxPath4 0x08
581 * #define bTxPath1 0x10
582 * #define bTxPath2 0x20
583 */
584#define bHTDetect 0x100
585#define bCFOEn 0x10000
586#define bCFOValue 0xfff00000
587#define bSigTone_Re 0x3f
588#define bSigTone_Im 0x7f00
589#define bCounter_CCA 0xffff
590#define bCounter_ParityFail 0xffff0000
591#define bCounter_RateIllegal 0xffff
592#define bCounter_CRC8Fail 0xffff0000
593#define bCounter_MCSNoSupport 0xffff
594#define bCounter_FastSync 0xffff
595#define bShortCFO 0xfff
596#define bShortCFOTLength 12 /* total */
597#define bShortCFOFLength 11 /* fraction */
598#define bLongCFO 0x7ff
599#define bLongCFOTLength 11
600#define bLongCFOFLength 11
601#define bTailCFO 0x1fff
602#define bTailCFOTLength 13
603#define bTailCFOFLength 12
604
605#define bmax_en_pwdB 0xffff
606#define bCC_power_dB 0xffff0000
607#define bnoise_pwdB 0xffff
608#define bPowerMeasTLength 10
609#define bPowerMeasFLength 3
610#define bRx_HT_BW 0x1
611#define bRxSC 0x6
612#define bRx_HT 0x8
613
614#define bNB_intf_det_on 0x1
615#define bIntf_win_len_cfg 0x30
616#define bNB_Intf_TH_cfg 0x1c0
617
618#define bRFGain 0x3f
619#define bTableSel 0x40
620#define bTRSW 0x80
621
622#define bRxSNR_A 0xff
623#define bRxSNR_B 0xff00
624#define bRxSNR_C 0xff0000
625#define bRxSNR_D 0xff000000
626#define bSNREVMTLength 8
627#define bSNREVMFLength 1
628
629#define bCSI1st 0xff
630#define bCSI2nd 0xff00
631#define bRxEVM1st 0xff0000
632#define bRxEVM2nd 0xff000000
633
634#define bSIGEVM 0xff
635#define bPWDB 0xff00
636#define bSGIEN 0x10000
637
638#define bSFactorQAM1 0xf
639#define bSFactorQAM2 0xf0
640#define bSFactorQAM3 0xf00
641#define bSFactorQAM4 0xf000
642#define bSFactorQAM5 0xf0000
643#define bSFactorQAM6 0xf0000
644#define bSFactorQAM7 0xf00000
645#define bSFactorQAM8 0xf000000
646#define bSFactorQAM9 0xf0000000
647#define bCSIScheme 0x100000
648
649#define bNoiseLvlTopSet 0x3
650#define bChSmooth 0x4
651#define bChSmoothCfg1 0x38
652#define bChSmoothCfg2 0x1c0
653#define bChSmoothCfg3 0xe00
654#define bChSmoothCfg4 0x7000
655#define bMRCMode 0x800000
656#define bTHEVMCfg 0x7000000
657
658#define bLoopFitType 0x1
659#define bUpdCFO 0x40
660#define bUpdCFOOffData 0x80
661#define bAdvUpdCFO 0x100
662#define bAdvTimeCtrl 0x800
663#define bUpdClko 0x1000
664#define bFC 0x6000
665#define bTrackingMode 0x8000
666#define bPhCmpEnable 0x10000
667#define bUpdClkoLTF 0x20000
668#define bComChCFO 0x40000
669#define bCSIEstiMode 0x80000
670#define bAdvUpdEqz 0x100000
671#define bUChCfg 0x7000000
672#define bUpdEqz 0x8000000
673
674/* Page e */
675#define bTxAGCRate18_06 0x7f7f7f7f
676#define bTxAGCRate54_24 0x7f7f7f7f
677#define bTxAGCRateMCS32 0x7f
678#define bTxAGCRateCCK 0x7f00
679#define bTxAGCRateMCS3_MCS0 0x7f7f7f7f
680#define bTxAGCRateMCS7_MCS4 0x7f7f7f7f
681#define bTxAGCRateMCS11_MCS8 0x7f7f7f7f
682#define bTxAGCRateMCS15_MCS12 0x7f7f7f7f
683
684#define bRxPesudoNoiseOn 0x20000000 /* Rx Pseduo noise */
685#define bRxPesudoNoise_A 0xff
686#define bRxPesudoNoise_B 0xff00
687#define bRxPesudoNoise_C 0xff0000
688#define bRxPesudoNoise_D 0xff000000
689#define bPesudoNoiseState_A 0xffff
690#define bPesudoNoiseState_B 0xffff0000
691#define bPesudoNoiseState_C 0xffff
692#define bPesudoNoiseState_D 0xffff0000
693
694/* RF Zebra 1 */
695#define bZebra1_HSSIEnable 0x8
696#define bZebra1_TRxControl 0xc00
697#define bZebra1_TRxGainSetting 0x07f
698#define bZebra1_RxCorner 0xc00
699#define bZebra1_TxChargePump 0x38
700#define bZebra1_RxChargePump 0x7
701#define bZebra1_ChannelNum 0xf80
702#define bZebra1_TxLPFBW 0x400
703#define bZebra1_RxLPFBW 0x600
704
705/* Zebra4 */
706#define bRTL8256RegModeCtrl1 0x100
707#define bRTL8256RegModeCtrl0 0x40
708#define bRTL8256_TxLPFBW 0x18
709#define bRTL8256_RxLPFBW 0x600
710
711/* RTL8258 */
712#define bRTL8258_TxLPFBW 0xc
713#define bRTL8258_RxLPFBW 0xc00
714#define bRTL8258_RSSILPFBW 0xc0
715
716/* byte enable for sb_write */
717#define bByte0 0x1
718#define bByte1 0x2
719#define bByte2 0x4
720#define bByte3 0x8
721#define bWord0 0x3
722#define bWord1 0xc
723#define bDWord 0xf
724
725/* for PutRegsetting & GetRegSetting BitMask */
726#define bMaskByte0 0xff
727#define bMaskByte1 0xff00
728#define bMaskByte2 0xff0000
729#define bMaskByte3 0xff000000
730#define bMaskHWord 0xffff0000
731#define bMaskLWord 0x0000ffff
732#define bMaskDWord 0xffffffff
733
734/* for PutRFRegsetting & GetRFRegSetting BitMask */
735#define bMask12Bits 0xfff
736
737#define bEnable 0x1
738#define bDisable 0x0
739
740#define LeftAntenna 0x0
741#define RightAntenna 0x1
742
743#define tCheckTxStatus 500 /* 500 ms */
744#define tUpdateRxCounter 100 /* 100 ms */
745
746#define rateCCK 0
747#define rateOFDM 1
748#define rateHT 2
749
750#define bPMAC_End 0x1ff /* define Register-End */
751#define bFPGAPHY0_End 0x8ff
752#define bFPGAPHY1_End 0x9ff
753#define bCCKPHY0_End 0xaff
754#define bOFDMPHY0_End 0xcff
755#define bOFDMPHY1_End 0xdff
756
757#define bPMACControl 0x0
758#define bWMACControl 0x1
759#define bWNICControl 0x2
760
761#define PathA 0x0
762#define PathB 0x1
763#define PathC 0x2
764#define PathD 0x3
765
766#define rRTL8256RxMixerPole 0xb
767#define bZebraRxMixerPole 0x6
768#define rRTL8256TxBBOPBias 0x9
769#define bRTL8256TxBBOPBias 0x400
770#define rRTL8256TxBBBW 19
771#define bRTL8256TxBBBW 0x18
772
773#endif
774

source code of linux/drivers/staging/rtl8192e/rtl8192e/r8192E_phyreg.h