1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
2 | /* |
3 | * Driver for Realtek PCI-Express card reader |
4 | * |
5 | * Copyright(c) 2009-2013 Realtek Semiconductor Corp. All rights reserved. |
6 | * |
7 | * Author: |
8 | * Wei WANG (wei_wang@realsil.com.cn) |
9 | * Micky Ching (micky_ching@realsil.com.cn) |
10 | */ |
11 | |
12 | #ifndef __REALTEK_RTSX_CHIP_H |
13 | #define __REALTEK_RTSX_CHIP_H |
14 | |
15 | #include "rtsx.h" |
16 | |
17 | #define SUPPORT_CPRM |
18 | #define SUPPORT_OCP |
19 | #define SUPPORT_SDIO_ASPM |
20 | #define SUPPORT_MAGIC_GATE |
21 | #define SUPPORT_MSXC |
22 | #define SUPPORT_SD_LOCK |
23 | /* Hardware switch bus_ctl and cd_ctl automatically */ |
24 | #define HW_AUTO_SWITCH_SD_BUS |
25 | /* Enable hardware interrupt write clear */ |
26 | #define HW_INT_WRITE_CLR |
27 | /* #define LED_AUTO_BLINK */ |
28 | /* #define DISABLE_CARD_INT */ |
29 | |
30 | #ifdef SUPPORT_MAGIC_GATE |
31 | /* Using NORMAL_WRITE instead of AUTO_WRITE to set ICV */ |
32 | #define MG_SET_ICV_SLOW |
33 | /* HW may miss ERR/CMDNK signal when sampling INT status. */ |
34 | #define MS_SAMPLE_INT_ERR |
35 | /* |
36 | * HW DO NOT support Wait_INT function |
37 | * during READ_BYTES transfer mode |
38 | */ |
39 | #define READ_BYTES_WAIT_INT |
40 | #endif |
41 | |
42 | #ifdef SUPPORT_MSXC |
43 | #define XC_POWERCLASS |
44 | #define SUPPORT_PCGL_1P18 |
45 | #endif |
46 | |
47 | #ifndef LED_AUTO_BLINK |
48 | #define REGULAR_BLINK |
49 | #endif |
50 | |
51 | #define LED_BLINK_SPEED 5 |
52 | #define LED_TOGGLE_INTERVAL 6 |
53 | #define GPIO_TOGGLE_THRESHOLD 1024 |
54 | #define LED_GPIO 0 |
55 | |
56 | #define POLLING_INTERVAL 30 |
57 | |
58 | #define TRACE_ITEM_CNT 64 |
59 | |
60 | #ifndef STATUS_SUCCESS |
61 | #define STATUS_SUCCESS 0 |
62 | #endif |
63 | #ifndef STATUS_FAIL |
64 | #define STATUS_FAIL 1 |
65 | #endif |
66 | #ifndef STATUS_TIMEDOUT |
67 | #define STATUS_TIMEDOUT 2 |
68 | #endif |
69 | #ifndef STATUS_NOMEM |
70 | #define STATUS_NOMEM 3 |
71 | #endif |
72 | #ifndef STATUS_READ_FAIL |
73 | #define STATUS_READ_FAIL 4 |
74 | #endif |
75 | #ifndef STATUS_WRITE_FAIL |
76 | #define STATUS_WRITE_FAIL 5 |
77 | #endif |
78 | #ifndef STATUS_ERROR |
79 | #define STATUS_ERROR 10 |
80 | #endif |
81 | |
82 | #define PM_S1 1 |
83 | #define PM_S3 3 |
84 | |
85 | /* |
86 | * Transport return codes |
87 | */ |
88 | |
89 | #define TRANSPORT_GOOD 0 /* Transport good, command good */ |
90 | #define TRANSPORT_FAILED 1 /* Transport good, command failed */ |
91 | #define TRANSPORT_NO_SENSE 2 /* Command failed, no auto-sense */ |
92 | #define TRANSPORT_ERROR 3 /* Transport bad (i.e. device dead) */ |
93 | |
94 | /* |
95 | * Start-Stop-Unit |
96 | */ |
97 | #define STOP_MEDIUM 0x00 /* access disable */ |
98 | #define MAKE_MEDIUM_READY 0x01 /* access enable */ |
99 | #define UNLOAD_MEDIUM 0x02 /* unload */ |
100 | #define LOAD_MEDIUM 0x03 /* load */ |
101 | |
102 | /* |
103 | * STANDARD_INQUIRY |
104 | */ |
105 | #define QULIFIRE 0x00 |
106 | #define AENC_FNC 0x00 |
107 | #define TRML_IOP 0x00 |
108 | #define REL_ADR 0x00 |
109 | #define WBUS_32 0x00 |
110 | #define WBUS_16 0x00 |
111 | #define SYNC 0x00 |
112 | #define LINKED 0x00 |
113 | #define CMD_QUE 0x00 |
114 | #define SFT_RE 0x00 |
115 | |
116 | #define VEN_ID_LEN 8 /* Vendor ID Length */ |
117 | #define PRDCT_ID_LEN 16 /* Product ID Length */ |
118 | #define PRDCT_REV_LEN 4 /* Product LOT Length */ |
119 | |
120 | /* Dynamic flag definitions: used in set_bit() etc. */ |
121 | /* 0x00040000 transfer is active */ |
122 | #define RTSX_FLIDX_TRANS_ACTIVE 18 |
123 | /* 0x00100000 abort is in progress */ |
124 | #define RTSX_FLIDX_ABORTING 20 |
125 | /* 0x00200000 disconnect in progress */ |
126 | #define RTSX_FLIDX_DISCONNECTING 21 |
127 | |
128 | #define ABORTING_OR_DISCONNECTING ((1UL << US_FLIDX_ABORTING) | \ |
129 | (1UL << US_FLIDX_DISCONNECTING)) |
130 | |
131 | /* 0x00400000 device reset in progress */ |
132 | #define RTSX_FLIDX_RESETTING 22 |
133 | /* 0x00800000 SCSI midlayer timed out */ |
134 | #define RTSX_FLIDX_TIMED_OUT 23 |
135 | #define DRCT_ACCESS_DEV 0x00 /* Direct Access Device */ |
136 | #define RMB_DISC 0x80 /* The Device is Removable */ |
137 | #define ANSI_SCSI2 0x02 /* Based on ANSI-SCSI2 */ |
138 | |
139 | #define SCSI 0x00 /* Interface ID */ |
140 | |
141 | #define WRITE_PROTECTED_MEDIA 0x07 |
142 | |
143 | /*---- sense key ----*/ |
144 | #define ILI 0x20 /* ILI bit is on */ |
145 | |
146 | #define NO_SENSE 0x00 /* not exist sense key */ |
147 | #define RECOVER_ERR 0x01 /* Target/Logical unit is recoverd */ |
148 | #define NOT_READY 0x02 /* Logical unit is not ready */ |
149 | #define MEDIA_ERR 0x03 /* medium/data error */ |
150 | #define HARDWARE_ERR 0x04 /* hardware error */ |
151 | #define ILGAL_REQ 0x05 /* CDB/parameter/identify msg error */ |
152 | #define UNIT_ATTENTION 0x06 /* unit attention condition occur */ |
153 | #define DAT_PRTCT 0x07 /* read/write is desable */ |
154 | #define BLNC_CHK 0x08 /* find blank/DOF in read */ |
155 | /* write to unblank area */ |
156 | #define CPY_ABRT 0x0a /* Copy/Compare/Copy&Verify illegal */ |
157 | #define ABRT_CMD 0x0b /* Target make the command in error */ |
158 | #define EQUAL 0x0c /* Search Data end with Equal */ |
159 | #define VLM_OVRFLW 0x0d /* Some data are left in buffer */ |
160 | #define MISCMP 0x0e /* find inequality */ |
161 | |
162 | #define READ_ERR -1 |
163 | #define WRITE_ERR -2 |
164 | |
165 | #define FIRST_RESET 0x01 |
166 | #define USED_EXIST 0x02 |
167 | |
168 | /* |
169 | * SENSE_DATA |
170 | */ |
171 | /*---- valid ----*/ |
172 | #define SENSE_VALID 0x80 /* Sense data is valid as SCSI2 */ |
173 | #define SENSE_INVALID 0x00 /* Sense data is invalid as SCSI2 */ |
174 | |
175 | /*---- error code ----*/ |
176 | #define CUR_ERR 0x70 /* current error */ |
177 | #define DEF_ERR 0x71 /* specific command error */ |
178 | |
179 | /*---- sense key Information ----*/ |
180 | #define SNSKEYINFO_LEN 3 /* length of sense key information */ |
181 | |
182 | #define SKSV 0x80 |
183 | #define CDB_ILLEGAL 0x40 |
184 | #define DAT_ILLEGAL 0x00 |
185 | #define BPV 0x08 |
186 | #define BIT_ILLEGAL0 0 /* bit0 is illegal */ |
187 | #define BIT_ILLEGAL1 1 /* bit1 is illegal */ |
188 | #define BIT_ILLEGAL2 2 /* bit2 is illegal */ |
189 | #define BIT_ILLEGAL3 3 /* bit3 is illegal */ |
190 | #define BIT_ILLEGAL4 4 /* bit4 is illegal */ |
191 | #define BIT_ILLEGAL5 5 /* bit5 is illegal */ |
192 | #define BIT_ILLEGAL6 6 /* bit6 is illegal */ |
193 | #define BIT_ILLEGAL7 7 /* bit7 is illegal */ |
194 | |
195 | /*---- ASC ----*/ |
196 | #define ASC_NO_INFO 0x00 |
197 | #define ASC_MISCMP 0x1d |
198 | #define ASC_INVLD_CDB 0x24 |
199 | #define ASC_INVLD_PARA 0x26 |
200 | #define ASC_LU_NOT_READY 0x04 |
201 | #define ASC_WRITE_ERR 0x0c |
202 | #define ASC_READ_ERR 0x11 |
203 | #define ASC_LOAD_EJCT_ERR 0x53 |
204 | #define ASC_MEDIA_NOT_PRESENT 0x3A |
205 | #define ASC_MEDIA_CHANGED 0x28 |
206 | #define ASC_MEDIA_IN_PROCESS 0x04 |
207 | #define ASC_WRITE_PROTECT 0x27 |
208 | #define ASC_LUN_NOT_SUPPORTED 0x25 |
209 | |
210 | /*---- ASQC ----*/ |
211 | #define ASCQ_NO_INFO 0x00 |
212 | #define ASCQ_MEDIA_IN_PROCESS 0x01 |
213 | #define ASCQ_MISCMP 0x00 |
214 | #define ASCQ_INVLD_CDB 0x00 |
215 | #define ASCQ_INVLD_PARA 0x02 |
216 | #define ASCQ_LU_NOT_READY 0x02 |
217 | #define ASCQ_WRITE_ERR 0x02 |
218 | #define ASCQ_READ_ERR 0x00 |
219 | #define ASCQ_LOAD_EJCT_ERR 0x00 |
220 | #define ASCQ_WRITE_PROTECT 0x00 |
221 | |
222 | struct sense_data_t { |
223 | unsigned char err_code; /* error code */ |
224 | /* bit7 : valid */ |
225 | /* (1 : SCSI2) */ |
226 | /* (0 : Vendor * specific) */ |
227 | /* bit6-0 : error * code */ |
228 | /* (0x70 : current * error) */ |
229 | /* (0x71 : specific command error) */ |
230 | unsigned char seg_no; /* segment No. */ |
231 | unsigned char sense_key; /* byte5 : ILI */ |
232 | /* bit3-0 : sense key */ |
233 | unsigned char info[4]; /* information */ |
234 | unsigned char ad_sense_len; /* additional sense data length */ |
235 | unsigned char cmd_info[4]; /* command specific information */ |
236 | unsigned char asc; /* ASC */ |
237 | unsigned char ascq; /* ASCQ */ |
238 | unsigned char rfu; /* FRU */ |
239 | unsigned char sns_key_info[3];/* sense key specific information */ |
240 | }; |
241 | |
242 | /* PCI Operation Register Address */ |
243 | #define RTSX_HCBAR 0x00 |
244 | #define RTSX_HCBCTLR 0x04 |
245 | #define RTSX_HDBAR 0x08 |
246 | #define RTSX_HDBCTLR 0x0C |
247 | #define RTSX_HAIMR 0x10 |
248 | #define RTSX_BIPR 0x14 |
249 | #define RTSX_BIER 0x18 |
250 | |
251 | /* Host command buffer control register */ |
252 | #define STOP_CMD (0x01 << 28) |
253 | |
254 | /* Host data buffer control register */ |
255 | #define SDMA_MODE 0x00 |
256 | #define ADMA_MODE (0x02 << 26) |
257 | #define STOP_DMA (0x01 << 28) |
258 | #define TRIG_DMA (0x01 << 31) |
259 | |
260 | /* Bus interrupt pending register */ |
261 | #define CMD_DONE_INT BIT(31) |
262 | #define DATA_DONE_INT BIT(30) |
263 | #define TRANS_OK_INT BIT(29) |
264 | #define TRANS_FAIL_INT BIT(28) |
265 | #define XD_INT BIT(27) |
266 | #define MS_INT BIT(26) |
267 | #define SD_INT BIT(25) |
268 | #define GPIO0_INT BIT(24) |
269 | #define OC_INT BIT(23) |
270 | #define SD_WRITE_PROTECT BIT(19) |
271 | #define XD_EXIST BIT(18) |
272 | #define MS_EXIST BIT(17) |
273 | #define SD_EXIST BIT(16) |
274 | #define DELINK_INT GPIO0_INT |
275 | #define MS_OC_INT BIT(23) |
276 | #define SD_OC_INT BIT(22) |
277 | |
278 | #define CARD_INT (XD_INT | MS_INT | SD_INT) |
279 | #define NEED_COMPLETE_INT (DATA_DONE_INT | TRANS_OK_INT | TRANS_FAIL_INT) |
280 | #define RTSX_INT (CMD_DONE_INT | NEED_COMPLETE_INT | CARD_INT | \ |
281 | GPIO0_INT | OC_INT) |
282 | |
283 | #define CARD_EXIST (XD_EXIST | MS_EXIST | SD_EXIST) |
284 | |
285 | /* Bus interrupt enable register */ |
286 | #define CMD_DONE_INT_EN BIT(31) |
287 | #define DATA_DONE_INT_EN BIT(30) |
288 | #define TRANS_OK_INT_EN BIT(29) |
289 | #define TRANS_FAIL_INT_EN BIT(28) |
290 | #define XD_INT_EN BIT(27) |
291 | #define MS_INT_EN BIT(26) |
292 | #define SD_INT_EN BIT(25) |
293 | #define GPIO0_INT_EN BIT(24) |
294 | #define OC_INT_EN BIT(23) |
295 | #define DELINK_INT_EN GPIO0_INT_EN |
296 | #define MS_OC_INT_EN BIT(23) |
297 | #define SD_OC_INT_EN BIT(22) |
298 | |
299 | #define READ_REG_CMD 0 |
300 | #define WRITE_REG_CMD 1 |
301 | #define CHECK_REG_CMD 2 |
302 | |
303 | #define HOST_TO_DEVICE 0 |
304 | #define DEVICE_TO_HOST 1 |
305 | |
306 | #define RTSX_RESV_BUF_LEN 4096 |
307 | #define HOST_CMDS_BUF_LEN 1024 |
308 | #define HOST_SG_TBL_BUF_LEN (RTSX_RESV_BUF_LEN - HOST_CMDS_BUF_LEN) |
309 | |
310 | #define SD_NR 2 |
311 | #define MS_NR 3 |
312 | #define XD_NR 4 |
313 | #define SPI_NR 7 |
314 | #define SD_CARD BIT(SD_NR) |
315 | #define MS_CARD BIT(MS_NR) |
316 | #define XD_CARD BIT(XD_NR) |
317 | #define SPI_CARD BIT(SPI_NR) |
318 | |
319 | #define MAX_ALLOWED_LUN_CNT 8 |
320 | |
321 | #define XD_FREE_TABLE_CNT 1200 |
322 | #define MS_FREE_TABLE_CNT 512 |
323 | |
324 | /* Bit Operation */ |
325 | #define SET_BIT(data, idx) ((data) |= 1 << (idx)) |
326 | #define CLR_BIT(data, idx) ((data) &= ~(1 << (idx))) |
327 | #define CHK_BIT(data, idx) ((data) & (1 << (idx))) |
328 | |
329 | /* SG descriptor */ |
330 | #define RTSX_SG_INT 0x04 |
331 | #define RTSX_SG_END 0x02 |
332 | #define RTSX_SG_VALID 0x01 |
333 | |
334 | #define RTSX_SG_NO_OP 0x00 |
335 | #define RTSX_SG_TRANS_DATA (0x02 << 4) |
336 | #define RTSX_SG_LINK_DESC (0x03 << 4) |
337 | |
338 | struct rtsx_chip; |
339 | |
340 | typedef int (*card_rw_func)(struct scsi_cmnd *srb, struct rtsx_chip *chip, |
341 | u32 sec_addr, u16 sec_cnt); |
342 | |
343 | /* Supported Clock */ |
344 | enum card_clock {CLK_20 = 1, CLK_30, CLK_40, CLK_50, CLK_60, |
345 | CLK_80, CLK_100, CLK_120, CLK_150, CLK_200}; |
346 | |
347 | enum RTSX_STAT {RTSX_STAT_INIT, RTSX_STAT_IDLE, RTSX_STAT_RUN, RTSX_STAT_SS, |
348 | RTSX_STAT_DELINK, RTSX_STAT_SUSPEND, |
349 | RTSX_STAT_ABORT, RTSX_STAT_DISCONNECT}; |
350 | enum IC_VER {IC_VER_AB, IC_VER_C = 2, IC_VER_D = 3}; |
351 | |
352 | #define MAX_RESET_CNT 3 |
353 | |
354 | /* For MS Card */ |
355 | #define MAX_DEFECTIVE_BLOCK 10 |
356 | |
357 | struct zone_entry { |
358 | u16 *l2p_table; |
359 | u16 *free_table; |
360 | u16 defect_list[MAX_DEFECTIVE_BLOCK]; /* For MS card only */ |
361 | int set_index; |
362 | int get_index; |
363 | int unused_blk_cnt; |
364 | int disable_count; |
365 | /* To indicate whether the L2P table of this zone has been built. */ |
366 | int build_flag; |
367 | }; |
368 | |
369 | #define TYPE_SD 0x0000 |
370 | #define TYPE_MMC 0x0001 |
371 | |
372 | /* TYPE_SD */ |
373 | #define SD_HS 0x0100 |
374 | #define SD_SDR50 0x0200 |
375 | #define SD_DDR50 0x0400 |
376 | #define SD_SDR104 0x0800 |
377 | #define SD_HCXC 0x1000 |
378 | |
379 | /* TYPE_MMC */ |
380 | #define MMC_26M 0x0100 |
381 | #define MMC_52M 0x0200 |
382 | #define MMC_4BIT 0x0400 |
383 | #define MMC_8BIT 0x0800 |
384 | #define MMC_SECTOR_MODE 0x1000 |
385 | #define MMC_DDR52 0x2000 |
386 | |
387 | /* SD card */ |
388 | #define CHK_SD(sd_card) (((sd_card)->sd_type & 0xFF) == TYPE_SD) |
389 | #define CHK_SD_HS(sd_card) (CHK_SD(sd_card) && \ |
390 | ((sd_card)->sd_type & SD_HS)) |
391 | #define CHK_SD_SDR50(sd_card) (CHK_SD(sd_card) && \ |
392 | ((sd_card)->sd_type & SD_SDR50)) |
393 | #define CHK_SD_DDR50(sd_card) (CHK_SD(sd_card) && \ |
394 | ((sd_card)->sd_type & SD_DDR50)) |
395 | #define CHK_SD_SDR104(sd_card) (CHK_SD(sd_card) && \ |
396 | ((sd_card)->sd_type & SD_SDR104)) |
397 | #define CHK_SD_HCXC(sd_card) (CHK_SD(sd_card) && \ |
398 | ((sd_card)->sd_type & SD_HCXC)) |
399 | #define CHK_SD_HC(sd_card) (CHK_SD_HCXC(sd_card) && \ |
400 | ((sd_card)->capacity <= 0x4000000)) |
401 | #define CHK_SD_XC(sd_card) (CHK_SD_HCXC(sd_card) && \ |
402 | ((sd_card)->capacity > 0x4000000)) |
403 | #define CHK_SD30_SPEED(sd_card) (CHK_SD_SDR50(sd_card) || \ |
404 | CHK_SD_DDR50(sd_card) || \ |
405 | CHK_SD_SDR104(sd_card)) |
406 | |
407 | #define SET_SD(sd_card) ((sd_card)->sd_type = TYPE_SD) |
408 | #define SET_SD_HS(sd_card) ((sd_card)->sd_type |= SD_HS) |
409 | #define SET_SD_SDR50(sd_card) ((sd_card)->sd_type |= SD_SDR50) |
410 | #define SET_SD_DDR50(sd_card) ((sd_card)->sd_type |= SD_DDR50) |
411 | #define SET_SD_SDR104(sd_card) ((sd_card)->sd_type |= SD_SDR104) |
412 | #define SET_SD_HCXC(sd_card) ((sd_card)->sd_type |= SD_HCXC) |
413 | |
414 | #define CLR_SD_HS(sd_card) ((sd_card)->sd_type &= ~SD_HS) |
415 | #define CLR_SD_SDR50(sd_card) ((sd_card)->sd_type &= ~SD_SDR50) |
416 | #define CLR_SD_DDR50(sd_card) ((sd_card)->sd_type &= ~SD_DDR50) |
417 | #define CLR_SD_SDR104(sd_card) ((sd_card)->sd_type &= ~SD_SDR104) |
418 | #define CLR_SD_HCXC(sd_card) ((sd_card)->sd_type &= ~SD_HCXC) |
419 | |
420 | /* MMC card */ |
421 | #define CHK_MMC(sd_card) (((sd_card)->sd_type & 0xFF) == \ |
422 | TYPE_MMC) |
423 | #define CHK_MMC_26M(sd_card) (CHK_MMC(sd_card) && \ |
424 | ((sd_card)->sd_type & MMC_26M)) |
425 | #define CHK_MMC_52M(sd_card) (CHK_MMC(sd_card) && \ |
426 | ((sd_card)->sd_type & MMC_52M)) |
427 | #define CHK_MMC_4BIT(sd_card) (CHK_MMC(sd_card) && \ |
428 | ((sd_card)->sd_type & MMC_4BIT)) |
429 | #define CHK_MMC_8BIT(sd_card) (CHK_MMC(sd_card) && \ |
430 | ((sd_card)->sd_type & MMC_8BIT)) |
431 | #define CHK_MMC_SECTOR_MODE(sd_card) (CHK_MMC(sd_card) && \ |
432 | ((sd_card)->sd_type & MMC_SECTOR_MODE)) |
433 | #define CHK_MMC_DDR52(sd_card) (CHK_MMC(sd_card) && \ |
434 | ((sd_card)->sd_type & MMC_DDR52)) |
435 | |
436 | #define SET_MMC(sd_card) ((sd_card)->sd_type = TYPE_MMC) |
437 | #define SET_MMC_26M(sd_card) ((sd_card)->sd_type |= MMC_26M) |
438 | #define SET_MMC_52M(sd_card) ((sd_card)->sd_type |= MMC_52M) |
439 | #define SET_MMC_4BIT(sd_card) ((sd_card)->sd_type |= MMC_4BIT) |
440 | #define SET_MMC_8BIT(sd_card) ((sd_card)->sd_type |= MMC_8BIT) |
441 | #define SET_MMC_SECTOR_MODE(sd_card) ((sd_card)->sd_type |= MMC_SECTOR_MODE) |
442 | #define SET_MMC_DDR52(sd_card) ((sd_card)->sd_type |= MMC_DDR52) |
443 | |
444 | #define CLR_MMC_26M(sd_card) ((sd_card)->sd_type &= ~MMC_26M) |
445 | #define CLR_MMC_52M(sd_card) ((sd_card)->sd_type &= ~MMC_52M) |
446 | #define CLR_MMC_4BIT(sd_card) ((sd_card)->sd_type &= ~MMC_4BIT) |
447 | #define CLR_MMC_8BIT(sd_card) ((sd_card)->sd_type &= ~MMC_8BIT) |
448 | #define CLR_MMC_SECTOR_MODE(sd_card) ((sd_card)->sd_type &= ~MMC_SECTOR_MODE) |
449 | #define CLR_MMC_DDR52(sd_card) ((sd_card)->sd_type &= ~MMC_DDR52) |
450 | |
451 | #define CHK_MMC_HS(sd_card) (CHK_MMC_52M(sd_card) && \ |
452 | CHK_MMC_26M(sd_card)) |
453 | #define CLR_MMC_HS(sd_card) \ |
454 | do { \ |
455 | CLR_MMC_DDR52(sd_card); \ |
456 | CLR_MMC_52M(sd_card); \ |
457 | CLR_MMC_26M(sd_card); \ |
458 | } while (0) |
459 | |
460 | #define SD_SUPPORT_CLASS_TEN 0x01 |
461 | #define SD_SUPPORT_1V8 0x02 |
462 | |
463 | #define SD_SET_CLASS_TEN(sd_card) ((sd_card)->sd_setting |= \ |
464 | SD_SUPPORT_CLASS_TEN) |
465 | #define SD_CHK_CLASS_TEN(sd_card) ((sd_card)->sd_setting & \ |
466 | SD_SUPPORT_CLASS_TEN) |
467 | #define SD_CLR_CLASS_TEN(sd_card) ((sd_card)->sd_setting &= \ |
468 | ~SD_SUPPORT_CLASS_TEN) |
469 | #define SD_SET_1V8(sd_card) ((sd_card)->sd_setting |= \ |
470 | SD_SUPPORT_1V8) |
471 | #define SD_CHK_1V8(sd_card) ((sd_card)->sd_setting & \ |
472 | SD_SUPPORT_1V8) |
473 | #define SD_CLR_1V8(sd_card) ((sd_card)->sd_setting &= \ |
474 | ~SD_SUPPORT_1V8) |
475 | |
476 | struct sd_info { |
477 | u16 sd_type; |
478 | u8 err_code; |
479 | u8 sd_data_buf_ready; |
480 | u32 sd_addr; |
481 | u32 capacity; |
482 | |
483 | u8 raw_csd[16]; |
484 | u8 raw_scr[8]; |
485 | |
486 | /* Sequential RW */ |
487 | int seq_mode; |
488 | enum dma_data_direction pre_dir; |
489 | u32 pre_sec_addr; |
490 | u16 pre_sec_cnt; |
491 | |
492 | int cleanup_counter; |
493 | |
494 | int sd_clock; |
495 | |
496 | int mmc_dont_switch_bus; |
497 | |
498 | #ifdef SUPPORT_CPRM |
499 | int sd_pass_thru_en; |
500 | int pre_cmd_err; |
501 | u8 last_rsp_type; |
502 | u8 rsp[17]; |
503 | #endif |
504 | |
505 | u8 func_group1_mask; |
506 | u8 func_group2_mask; |
507 | u8 func_group3_mask; |
508 | u8 func_group4_mask; |
509 | |
510 | u8 sd_switch_fail; |
511 | u8 sd_read_phase; |
512 | |
513 | #ifdef SUPPORT_SD_LOCK |
514 | u8 sd_lock_status; |
515 | u8 sd_erase_status; |
516 | u8 sd_lock_notify; |
517 | #endif |
518 | int need_retune; |
519 | }; |
520 | |
521 | struct xd_delay_write_tag { |
522 | u32 old_phyblock; |
523 | u32 new_phyblock; |
524 | u32 logblock; |
525 | u8 pageoff; |
526 | u8 delay_write_flag; |
527 | }; |
528 | |
529 | struct xd_info { |
530 | u8 maker_code; |
531 | u8 device_code; |
532 | u8 block_shift; |
533 | u8 page_off; |
534 | u8 addr_cycle; |
535 | u16 cis_block; |
536 | u8 multi_flag; |
537 | u8 err_code; |
538 | u32 capacity; |
539 | |
540 | struct zone_entry *zone; |
541 | int zone_cnt; |
542 | |
543 | struct xd_delay_write_tag delay_write; |
544 | int cleanup_counter; |
545 | |
546 | int xd_clock; |
547 | }; |
548 | |
549 | #define MODE_512_SEQ 0x01 |
550 | #define MODE_2K_SEQ 0x02 |
551 | |
552 | #define TYPE_MS 0x0000 |
553 | #define TYPE_MSPRO 0x0001 |
554 | |
555 | #define MS_4BIT 0x0100 |
556 | #define MS_8BIT 0x0200 |
557 | #define MS_HG 0x0400 |
558 | #define MS_XC 0x0800 |
559 | |
560 | #define HG8BIT (MS_HG | MS_8BIT) |
561 | |
562 | #define CHK_MSPRO(ms_card) (((ms_card)->ms_type & 0xFF) == TYPE_MSPRO) |
563 | #define CHK_HG8BIT(ms_card) (CHK_MSPRO(ms_card) && \ |
564 | (((ms_card)->ms_type & HG8BIT) == HG8BIT)) |
565 | #define CHK_MSXC(ms_card) (CHK_MSPRO(ms_card) && \ |
566 | ((ms_card)->ms_type & MS_XC)) |
567 | #define CHK_MSHG(ms_card) (CHK_MSPRO(ms_card) && \ |
568 | ((ms_card)->ms_type & MS_HG)) |
569 | |
570 | #define CHK_MS8BIT(ms_card) (((ms_card)->ms_type & MS_8BIT)) |
571 | #define CHK_MS4BIT(ms_card) (((ms_card)->ms_type & MS_4BIT)) |
572 | |
573 | struct ms_delay_write_tag { |
574 | u16 old_phyblock; |
575 | u16 new_phyblock; |
576 | u16 logblock; |
577 | u8 pageoff; |
578 | u8 delay_write_flag; |
579 | }; |
580 | |
581 | struct ms_info { |
582 | u16 ms_type; |
583 | u8 block_shift; |
584 | u8 page_off; |
585 | u16 total_block; |
586 | u16 boot_block; |
587 | u32 capacity; |
588 | |
589 | u8 check_ms_flow; |
590 | u8 switch_8bit_fail; |
591 | u8 err_code; |
592 | |
593 | struct zone_entry *segment; |
594 | int segment_cnt; |
595 | |
596 | int pro_under_formatting; |
597 | int format_status; |
598 | u16 progress; |
599 | u8 raw_sys_info[96]; |
600 | #ifdef SUPPORT_PCGL_1P18 |
601 | u8 raw_model_name[48]; |
602 | #endif |
603 | |
604 | u8 multi_flag; |
605 | |
606 | /* Sequential RW */ |
607 | u8 seq_mode; |
608 | enum dma_data_direction pre_dir; |
609 | u32 pre_sec_addr; |
610 | u16 pre_sec_cnt; |
611 | u32 total_sec_cnt; |
612 | |
613 | struct ms_delay_write_tag delay_write; |
614 | |
615 | int cleanup_counter; |
616 | |
617 | int ms_clock; |
618 | |
619 | #ifdef SUPPORT_MAGIC_GATE |
620 | u8 magic_gate_id[16]; |
621 | u8 mg_entry_num; |
622 | int mg_auth; /* flag to indicate authentication process */ |
623 | #endif |
624 | }; |
625 | |
626 | struct spi_info { |
627 | u8 use_clk; |
628 | u8 write_en; |
629 | u16 clk_div; |
630 | u8 err_code; |
631 | |
632 | int spi_clock; |
633 | }; |
634 | |
635 | /************/ |
636 | /* LUN mode */ |
637 | /************/ |
638 | /* Single LUN, support xD/SD/MS */ |
639 | #define DEFAULT_SINGLE 0 |
640 | /* 2 LUN mode, support SD/MS */ |
641 | #define SD_MS_2LUN 1 |
642 | /* Single LUN, but only support SD/MS, for Barossa LQFP */ |
643 | #define SD_MS_1LUN 2 |
644 | |
645 | #define LAST_LUN_MODE 2 |
646 | |
647 | /* Barossa package */ |
648 | #define QFN 0 |
649 | #define LQFP 1 |
650 | |
651 | /******************/ |
652 | /* sd_ctl bit map */ |
653 | /******************/ |
654 | /* SD push point control, bit 0, 1 */ |
655 | #define SD_PUSH_POINT_CTL_MASK 0x03 |
656 | #define SD_PUSH_POINT_DELAY 0x01 |
657 | #define SD_PUSH_POINT_AUTO 0x02 |
658 | /* SD sample point control, bit 2, 3 */ |
659 | #define SD_SAMPLE_POINT_CTL_MASK 0x0C |
660 | #define SD_SAMPLE_POINT_DELAY 0x04 |
661 | #define SD_SAMPLE_POINT_AUTO 0x08 |
662 | /* SD DDR Tx phase set by user, bit 4 */ |
663 | #define SD_DDR_TX_PHASE_SET_BY_USER 0x10 |
664 | /* MMC DDR Tx phase set by user, bit 5 */ |
665 | #define MMC_DDR_TX_PHASE_SET_BY_USER 0x20 |
666 | /* Support MMC DDR mode, bit 6 */ |
667 | #define SUPPORT_MMC_DDR_MODE 0x40 |
668 | /* Reset MMC at first */ |
669 | #define RESET_MMC_FIRST 0x80 |
670 | |
671 | #define SEQ_START_CRITERIA 0x20 |
672 | |
673 | /* MS Power Class En */ |
674 | #define POWER_CLASS_2_EN 0x02 |
675 | #define POWER_CLASS_1_EN 0x01 |
676 | |
677 | #define MAX_SHOW_CNT 10 |
678 | #define MAX_RESET_CNT 3 |
679 | |
680 | #define SDIO_EXIST 0x01 |
681 | #define SDIO_IGNORED 0x02 |
682 | |
683 | #define CHK_SDIO_EXIST(chip) ((chip)->sdio_func_exist & SDIO_EXIST) |
684 | #define SET_SDIO_EXIST(chip) ((chip)->sdio_func_exist |= SDIO_EXIST) |
685 | #define CLR_SDIO_EXIST(chip) ((chip)->sdio_func_exist &= ~SDIO_EXIST) |
686 | |
687 | #define CHK_SDIO_IGNORED(chip) ((chip)->sdio_func_exist & SDIO_IGNORED) |
688 | #define SET_SDIO_IGNORED(chip) ((chip)->sdio_func_exist |= \ |
689 | SDIO_IGNORED) |
690 | #define CLR_SDIO_IGNORED(chip) ((chip)->sdio_func_exist &= \ |
691 | ~SDIO_IGNORED) |
692 | |
693 | struct rtsx_chip { |
694 | struct rtsx_dev *rtsx; |
695 | |
696 | u32 int_reg; /* Bus interrupt pending register */ |
697 | char max_lun; |
698 | void *context; |
699 | |
700 | void *host_cmds_ptr; /* host commands buffer pointer */ |
701 | dma_addr_t host_cmds_addr; |
702 | int ci; /* Command Index */ |
703 | |
704 | void *host_sg_tbl_ptr; /* SG descriptor table */ |
705 | dma_addr_t host_sg_tbl_addr; |
706 | int sgi; /* SG entry index */ |
707 | |
708 | struct scsi_cmnd *srb; /* current srb */ |
709 | struct sense_data_t sense_buffer[MAX_ALLOWED_LUN_CNT]; |
710 | |
711 | int cur_clk; /* current card clock */ |
712 | |
713 | /* Current accessed card */ |
714 | int cur_card; |
715 | |
716 | unsigned long need_release; /* need release bit map */ |
717 | unsigned long need_reset; /* need reset bit map */ |
718 | /* |
719 | * Flag to indicate that this card is just resumed from SS state, |
720 | * and need released before being resetted |
721 | */ |
722 | unsigned long need_reinit; |
723 | |
724 | int rw_need_retry; |
725 | |
726 | #ifdef SUPPORT_OCP |
727 | u32 ocp_int; |
728 | u8 ocp_stat; |
729 | #endif |
730 | |
731 | u8 card_exist; /* card exist bit map (physical exist) */ |
732 | u8 card_ready; /* card ready bit map (reset successfully) */ |
733 | u8 card_fail; /* card reset fail bit map */ |
734 | u8 card_ejected; /* card ejected bit map */ |
735 | u8 card_wp; /* card write protected bit map */ |
736 | |
737 | u8 lun_mc; /* |
738 | * flag to indicate whether to answer |
739 | * MediaChange |
740 | */ |
741 | |
742 | #ifndef LED_AUTO_BLINK |
743 | int led_toggle_counter; |
744 | #endif |
745 | |
746 | int sd_reset_counter; |
747 | int xd_reset_counter; |
748 | int ms_reset_counter; |
749 | |
750 | /* card bus width */ |
751 | u8 card_bus_width[MAX_ALLOWED_LUN_CNT]; |
752 | /* card capacity */ |
753 | u32 capacity[MAX_ALLOWED_LUN_CNT]; |
754 | /* read/write card function pointer */ |
755 | card_rw_func rw_card[MAX_ALLOWED_LUN_CNT]; |
756 | /* read/write capacity, used for GPIO Toggle */ |
757 | u32 rw_cap[MAX_ALLOWED_LUN_CNT]; |
758 | /* card to lun mapping table */ |
759 | u8 card2lun[32]; |
760 | /* lun to card mapping table */ |
761 | u8 lun2card[MAX_ALLOWED_LUN_CNT]; |
762 | |
763 | int rw_fail_cnt[MAX_ALLOWED_LUN_CNT]; |
764 | |
765 | int sd_show_cnt; |
766 | int xd_show_cnt; |
767 | int ms_show_cnt; |
768 | |
769 | /* card information */ |
770 | struct sd_info sd_card; |
771 | struct xd_info xd_card; |
772 | struct ms_info ms_card; |
773 | |
774 | struct spi_info spi; |
775 | |
776 | int auto_delink_cnt; |
777 | int auto_delink_allowed; |
778 | |
779 | int aspm_enabled; |
780 | |
781 | int sdio_aspm; |
782 | int sdio_idle; |
783 | int sdio_counter; |
784 | u8 sdio_raw_data[12]; |
785 | |
786 | u8 sd_io; |
787 | u8 sd_int; |
788 | |
789 | u8 rtsx_flag; |
790 | |
791 | int ss_counter; |
792 | int idle_counter; |
793 | enum RTSX_STAT rtsx_stat; |
794 | |
795 | u16 vendor_id; |
796 | u16 product_id; |
797 | u8 ic_version; |
798 | |
799 | int driver_first_load; |
800 | |
801 | #ifdef HW_AUTO_SWITCH_SD_BUS |
802 | int sdio_in_charge; |
803 | #endif |
804 | |
805 | u8 aspm_level[2]; |
806 | |
807 | int chip_insert_with_sdio; |
808 | |
809 | /* Options */ |
810 | |
811 | int adma_mode; |
812 | |
813 | int auto_delink_en; |
814 | int ss_en; |
815 | u8 lun_mode; |
816 | u8 aspm_l0s_l1_en; |
817 | |
818 | int power_down_in_ss; |
819 | |
820 | int sdr104_en; |
821 | int ddr50_en; |
822 | int sdr50_en; |
823 | |
824 | int baro_pkg; |
825 | |
826 | int asic_code; |
827 | int phy_debug_mode; |
828 | int hw_bypass_sd; |
829 | int sdio_func_exist; |
830 | int aux_pwr_exist; |
831 | u8 ms_power_class_en; |
832 | |
833 | int mspro_formatter_enable; |
834 | |
835 | int remote_wakeup_en; |
836 | |
837 | int ignore_sd; |
838 | int use_hw_setting; |
839 | |
840 | int ss_idle_period; |
841 | |
842 | int dynamic_aspm; |
843 | |
844 | int fpga_sd_sdr104_clk; |
845 | int fpga_sd_ddr50_clk; |
846 | int fpga_sd_sdr50_clk; |
847 | int fpga_sd_hs_clk; |
848 | int fpga_mmc_52m_clk; |
849 | int fpga_ms_hg_clk; |
850 | int fpga_ms_4bit_clk; |
851 | int fpga_ms_1bit_clk; |
852 | |
853 | int asic_sd_sdr104_clk; |
854 | int asic_sd_ddr50_clk; |
855 | int asic_sd_sdr50_clk; |
856 | int asic_sd_hs_clk; |
857 | int asic_mmc_52m_clk; |
858 | int asic_ms_hg_clk; |
859 | int asic_ms_4bit_clk; |
860 | int asic_ms_1bit_clk; |
861 | |
862 | u8 ssc_depth_sd_sdr104; |
863 | u8 ssc_depth_sd_ddr50; |
864 | u8 ssc_depth_sd_sdr50; |
865 | u8 ssc_depth_sd_hs; |
866 | u8 ssc_depth_mmc_52m; |
867 | u8 ssc_depth_ms_hg; |
868 | u8 ssc_depth_ms_4bit; |
869 | u8 ssc_depth_low_speed; |
870 | |
871 | u8 card_drive_sel; |
872 | u8 sd30_drive_sel_1v8; |
873 | u8 sd30_drive_sel_3v3; |
874 | |
875 | u8 sd_400mA_ocp_thd; |
876 | u8 sd_800mA_ocp_thd; |
877 | u8 ms_ocp_thd; |
878 | |
879 | int ssc_en; |
880 | int msi_en; |
881 | |
882 | int xd_timeout; |
883 | int sd_timeout; |
884 | int ms_timeout; |
885 | int mspro_timeout; |
886 | |
887 | int auto_power_down; |
888 | |
889 | int sd_ddr_tx_phase; |
890 | int mmc_ddr_tx_phase; |
891 | int sd_default_tx_phase; |
892 | int sd_default_rx_phase; |
893 | |
894 | int pmos_pwr_on_interval; |
895 | int sd_voltage_switch_delay; |
896 | int s3_pwr_off_delay; |
897 | |
898 | int force_clkreq_0; |
899 | int ft2_fast_mode; |
900 | |
901 | int do_delink_before_power_down; |
902 | int polling_config; |
903 | int sdio_retry_cnt; |
904 | |
905 | int delink_stage1_step; |
906 | int delink_stage2_step; |
907 | int delink_stage3_step; |
908 | |
909 | int auto_delink_in_L1; |
910 | int hp_watch_bios_hotplug; |
911 | int support_ms_8bit; |
912 | |
913 | u8 blink_led; |
914 | u8 phy_voltage; |
915 | u8 max_payload; |
916 | |
917 | u32 sd_speed_prior; |
918 | u32 sd_current_prior; |
919 | u32 sd_ctl; |
920 | }; |
921 | |
922 | static inline struct device *rtsx_dev(const struct rtsx_chip *chip) |
923 | { |
924 | return &chip->rtsx->pci->dev; |
925 | } |
926 | |
927 | #define rtsx_set_stat(chip, stat) \ |
928 | do { \ |
929 | if ((stat) != RTSX_STAT_IDLE) { \ |
930 | (chip)->idle_counter = 0; \ |
931 | } \ |
932 | (chip)->rtsx_stat = (enum RTSX_STAT)(stat); \ |
933 | } while (0) |
934 | #define rtsx_get_stat(chip) ((chip)->rtsx_stat) |
935 | #define rtsx_chk_stat(chip, stat) ((chip)->rtsx_stat == (stat)) |
936 | |
937 | #define RTSX_SET_DELINK(chip) ((chip)->rtsx_flag |= 0x01) |
938 | #define RTSX_CLR_DELINK(chip) ((chip)->rtsx_flag &= 0xFE) |
939 | #define RTSX_TST_DELINK(chip) ((chip)->rtsx_flag & 0x01) |
940 | |
941 | #define CHECK_PID(chip, pid) ((chip)->product_id == (pid)) |
942 | #define CHECK_BARO_PKG(chip, pkg) ((chip)->baro_pkg == (pkg)) |
943 | #define CHECK_LUN_MODE(chip, mode) ((chip)->lun_mode == (mode)) |
944 | |
945 | /* Power down control */ |
946 | #define SSC_PDCTL 0x01 |
947 | #define OC_PDCTL 0x02 |
948 | |
949 | int rtsx_force_power_on(struct rtsx_chip *chip, u8 ctl); |
950 | int rtsx_force_power_down(struct rtsx_chip *chip, u8 ctl); |
951 | |
952 | void rtsx_enable_card_int(struct rtsx_chip *chip); |
953 | void rtsx_enable_bus_int(struct rtsx_chip *chip); |
954 | void rtsx_disable_bus_int(struct rtsx_chip *chip); |
955 | int rtsx_reset_chip(struct rtsx_chip *chip); |
956 | int rtsx_init_chip(struct rtsx_chip *chip); |
957 | void rtsx_release_chip(struct rtsx_chip *chip); |
958 | void rtsx_polling_func(struct rtsx_chip *chip); |
959 | void rtsx_stop_cmd(struct rtsx_chip *chip, int card); |
960 | int rtsx_write_register(struct rtsx_chip *chip, u16 addr, u8 mask, u8 data); |
961 | int rtsx_read_register(struct rtsx_chip *chip, u16 addr, u8 *data); |
962 | int rtsx_write_cfg_dw(struct rtsx_chip *chip, |
963 | u8 func_no, u16 addr, u32 mask, u32 val); |
964 | int rtsx_read_cfg_dw(struct rtsx_chip *chip, u8 func_no, u16 addr, u32 *val); |
965 | int rtsx_write_cfg_seq(struct rtsx_chip *chip, |
966 | u8 func, u16 addr, u8 *buf, int len); |
967 | int rtsx_read_cfg_seq(struct rtsx_chip *chip, |
968 | u8 func, u16 addr, u8 *buf, int len); |
969 | int rtsx_write_phy_register(struct rtsx_chip *chip, u8 addr, u16 val); |
970 | int rtsx_read_phy_register(struct rtsx_chip *chip, u8 addr, u16 *val); |
971 | int rtsx_read_efuse(struct rtsx_chip *chip, u8 addr, u8 *val); |
972 | int rtsx_write_efuse(struct rtsx_chip *chip, u8 addr, u8 val); |
973 | int rtsx_clr_phy_reg_bit(struct rtsx_chip *chip, u8 reg, u8 bit); |
974 | int rtsx_set_phy_reg_bit(struct rtsx_chip *chip, u8 reg, u8 bit); |
975 | void rtsx_enter_ss(struct rtsx_chip *chip); |
976 | void rtsx_exit_ss(struct rtsx_chip *chip); |
977 | int rtsx_pre_handle_interrupt(struct rtsx_chip *chip); |
978 | void rtsx_enter_L1(struct rtsx_chip *chip); |
979 | void rtsx_exit_L1(struct rtsx_chip *chip); |
980 | void rtsx_do_before_power_down(struct rtsx_chip *chip, int pm_stat); |
981 | void rtsx_enable_aspm(struct rtsx_chip *chip); |
982 | void rtsx_disable_aspm(struct rtsx_chip *chip); |
983 | int rtsx_read_ppbuf(struct rtsx_chip *chip, u8 *buf, int buf_len); |
984 | int rtsx_write_ppbuf(struct rtsx_chip *chip, u8 *buf, int buf_len); |
985 | int rtsx_check_chip_exist(struct rtsx_chip *chip); |
986 | |
987 | #endif /* __REALTEK_RTSX_CHIP_H */ |
988 | |