| 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
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| 2 | /* |
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| 3 | * DRA752 bandgap registers, bitfields and temperature definitions |
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| 4 | * |
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| 5 | * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/ |
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| 6 | * Contact: |
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| 7 | * Eduardo Valentin <eduardo.valentin@ti.com> |
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| 8 | * Tero Kristo <t-kristo@ti.com> |
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| 9 | * |
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| 10 | * This is an auto generated file. |
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| 11 | */ |
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| 12 | #ifndef __DRA752_BANDGAP_H |
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| 13 | #define __DRA752_BANDGAP_H |
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| 14 | |
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| 15 | /** |
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| 16 | * *** DRA752 *** |
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| 17 | * |
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| 18 | * Below, in sequence, are the Register definitions, |
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| 19 | * the bitfields and the temperature definitions for DRA752. |
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| 20 | */ |
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| 21 | |
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| 22 | /** |
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| 23 | * DRA752 register definitions |
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| 24 | * |
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| 25 | * Registers are defined as offsets. The offsets are |
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| 26 | * relative to FUSE_OPP_BGAP_GPU on DRA752. |
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| 27 | * DRA752_BANDGAP_BASE 0x4a0021e0 |
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| 28 | * |
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| 29 | * Register below are grouped by domain (not necessarily in offset order) |
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| 30 | */ |
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| 31 | |
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| 32 | |
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| 33 | /* DRA752.common register offsets */ |
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| 34 | #define DRA752_BANDGAP_CTRL_1_OFFSET 0x1a0 |
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| 35 | #define DRA752_BANDGAP_STATUS_1_OFFSET 0x1c8 |
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| 36 | #define DRA752_BANDGAP_CTRL_2_OFFSET 0x39c |
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| 37 | #define DRA752_BANDGAP_STATUS_2_OFFSET 0x3b8 |
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| 38 | |
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| 39 | /* DRA752.core register offsets */ |
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| 40 | #define DRA752_STD_FUSE_OPP_BGAP_CORE_OFFSET 0x8 |
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| 41 | #define DRA752_TEMP_SENSOR_CORE_OFFSET 0x154 |
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| 42 | #define DRA752_BANDGAP_THRESHOLD_CORE_OFFSET 0x1ac |
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| 43 | #define DRA752_DTEMP_CORE_1_OFFSET 0x20c |
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| 44 | #define DRA752_DTEMP_CORE_2_OFFSET 0x210 |
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| 45 | |
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| 46 | /* DRA752.iva register offsets */ |
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| 47 | #define DRA752_STD_FUSE_OPP_BGAP_IVA_OFFSET 0x388 |
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| 48 | #define DRA752_TEMP_SENSOR_IVA_OFFSET 0x398 |
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| 49 | #define DRA752_BANDGAP_THRESHOLD_IVA_OFFSET 0x3a4 |
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| 50 | #define DRA752_DTEMP_IVA_1_OFFSET 0x3d4 |
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| 51 | #define DRA752_DTEMP_IVA_2_OFFSET 0x3d8 |
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| 52 | |
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| 53 | /* DRA752.mpu register offsets */ |
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| 54 | #define DRA752_STD_FUSE_OPP_BGAP_MPU_OFFSET 0x4 |
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| 55 | #define DRA752_TEMP_SENSOR_MPU_OFFSET 0x14c |
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| 56 | #define DRA752_BANDGAP_THRESHOLD_MPU_OFFSET 0x1a4 |
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| 57 | #define DRA752_DTEMP_MPU_1_OFFSET 0x1e4 |
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| 58 | #define DRA752_DTEMP_MPU_2_OFFSET 0x1e8 |
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| 59 | |
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| 60 | /* DRA752.dspeve register offsets */ |
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| 61 | #define DRA752_STD_FUSE_OPP_BGAP_DSPEVE_OFFSET 0x384 |
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| 62 | #define DRA752_TEMP_SENSOR_DSPEVE_OFFSET 0x394 |
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| 63 | #define DRA752_BANDGAP_THRESHOLD_DSPEVE_OFFSET 0x3a0 |
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| 64 | #define DRA752_DTEMP_DSPEVE_1_OFFSET 0x3c0 |
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| 65 | #define DRA752_DTEMP_DSPEVE_2_OFFSET 0x3c4 |
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| 66 | |
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| 67 | /* DRA752.gpu register offsets */ |
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| 68 | #define DRA752_STD_FUSE_OPP_BGAP_GPU_OFFSET 0x0 |
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| 69 | #define DRA752_TEMP_SENSOR_GPU_OFFSET 0x150 |
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| 70 | #define DRA752_BANDGAP_THRESHOLD_GPU_OFFSET 0x1a8 |
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| 71 | #define DRA752_DTEMP_GPU_1_OFFSET 0x1f8 |
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| 72 | #define DRA752_DTEMP_GPU_2_OFFSET 0x1fc |
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| 73 | |
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| 74 | /** |
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| 75 | * Register bitfields for DRA752 |
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| 76 | * |
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| 77 | * All the macros bellow define the required bits for |
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| 78 | * controlling temperature on DRA752. Bit defines are |
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| 79 | * grouped by register. |
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| 80 | */ |
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| 81 | |
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| 82 | /* DRA752.BANDGAP_STATUS_1 */ |
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| 83 | #define DRA752_BANDGAP_STATUS_1_HOT_CORE_MASK BIT(5) |
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| 84 | #define DRA752_BANDGAP_STATUS_1_COLD_CORE_MASK BIT(4) |
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| 85 | #define DRA752_BANDGAP_STATUS_1_HOT_GPU_MASK BIT(3) |
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| 86 | #define DRA752_BANDGAP_STATUS_1_COLD_GPU_MASK BIT(2) |
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| 87 | #define DRA752_BANDGAP_STATUS_1_HOT_MPU_MASK BIT(1) |
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| 88 | #define DRA752_BANDGAP_STATUS_1_COLD_MPU_MASK BIT(0) |
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| 89 | |
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| 90 | /* DRA752.BANDGAP_CTRL_2 */ |
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| 91 | #define DRA752_BANDGAP_CTRL_2_FREEZE_IVA_MASK BIT(22) |
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| 92 | #define DRA752_BANDGAP_CTRL_2_FREEZE_DSPEVE_MASK BIT(21) |
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| 93 | #define DRA752_BANDGAP_CTRL_2_MASK_HOT_IVA_MASK BIT(3) |
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| 94 | #define DRA752_BANDGAP_CTRL_2_MASK_COLD_IVA_MASK BIT(2) |
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| 95 | #define DRA752_BANDGAP_CTRL_2_MASK_HOT_DSPEVE_MASK BIT(1) |
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| 96 | #define DRA752_BANDGAP_CTRL_2_MASK_COLD_DSPEVE_MASK BIT(0) |
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| 97 | |
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| 98 | /* DRA752.BANDGAP_STATUS_2 */ |
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| 99 | #define DRA752_BANDGAP_STATUS_2_HOT_IVA_MASK BIT(3) |
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| 100 | #define DRA752_BANDGAP_STATUS_2_COLD_IVA_MASK BIT(2) |
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| 101 | #define DRA752_BANDGAP_STATUS_2_HOT_DSPEVE_MASK BIT(1) |
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| 102 | #define DRA752_BANDGAP_STATUS_2_COLD_DSPEVE_MASK BIT(0) |
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| 103 | |
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| 104 | /* DRA752.BANDGAP_CTRL_1 */ |
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| 105 | #define DRA752_BANDGAP_CTRL_1_COUNTER_DELAY_MASK (0x7 << 27) |
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| 106 | #define DRA752_BANDGAP_CTRL_1_FREEZE_CORE_MASK BIT(23) |
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| 107 | #define DRA752_BANDGAP_CTRL_1_FREEZE_GPU_MASK BIT(22) |
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| 108 | #define DRA752_BANDGAP_CTRL_1_FREEZE_MPU_MASK BIT(21) |
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| 109 | #define DRA752_BANDGAP_CTRL_1_MASK_HOT_CORE_MASK BIT(5) |
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| 110 | #define DRA752_BANDGAP_CTRL_1_MASK_COLD_CORE_MASK BIT(4) |
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| 111 | #define DRA752_BANDGAP_CTRL_1_MASK_HOT_GPU_MASK BIT(3) |
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| 112 | #define DRA752_BANDGAP_CTRL_1_MASK_COLD_GPU_MASK BIT(2) |
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| 113 | #define DRA752_BANDGAP_CTRL_1_MASK_HOT_MPU_MASK BIT(1) |
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| 114 | #define DRA752_BANDGAP_CTRL_1_MASK_COLD_MPU_MASK BIT(0) |
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| 115 | |
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| 116 | /* DRA752.TEMP_SENSOR */ |
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| 117 | #define DRA752_TEMP_SENSOR_TMPSOFF_MASK BIT(11) |
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| 118 | #define DRA752_TEMP_SENSOR_EOCZ_MASK BIT(10) |
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| 119 | #define DRA752_TEMP_SENSOR_DTEMP_MASK (0x3ff << 0) |
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| 120 | |
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| 121 | /* DRA752.BANDGAP_THRESHOLD */ |
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| 122 | #define DRA752_BANDGAP_THRESHOLD_HOT_MASK (0x3ff << 16) |
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| 123 | #define DRA752_BANDGAP_THRESHOLD_COLD_MASK (0x3ff << 0) |
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| 124 | |
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| 125 | /** |
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| 126 | * Temperature limits and thresholds for DRA752 |
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| 127 | * |
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| 128 | * All the macros bellow are definitions for handling the |
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| 129 | * ADC conversions and representation of temperature limits |
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| 130 | * and thresholds for DRA752. Definitions are grouped |
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| 131 | * by temperature domain. |
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| 132 | */ |
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| 133 | |
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| 134 | /* DRA752.common temperature definitions */ |
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| 135 | /* ADC conversion table limits */ |
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| 136 | #define DRA752_ADC_START_VALUE 540 |
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| 137 | #define DRA752_ADC_END_VALUE 945 |
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| 138 | |
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| 139 | /* DRA752.GPU temperature definitions */ |
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| 140 | /* bandgap clock limits */ |
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| 141 | #define DRA752_GPU_MAX_FREQ 1500000 |
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| 142 | #define DRA752_GPU_MIN_FREQ 1000000 |
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| 143 | /* interrupts thresholds */ |
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| 144 | #define DRA752_GPU_T_HOT 800 |
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| 145 | #define DRA752_GPU_T_COLD 795 |
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| 146 | |
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| 147 | /* DRA752.MPU temperature definitions */ |
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| 148 | /* bandgap clock limits */ |
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| 149 | #define DRA752_MPU_MAX_FREQ 1500000 |
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| 150 | #define DRA752_MPU_MIN_FREQ 1000000 |
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| 151 | /* interrupts thresholds */ |
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| 152 | #define DRA752_MPU_T_HOT 800 |
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| 153 | #define DRA752_MPU_T_COLD 795 |
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| 154 | |
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| 155 | /* DRA752.CORE temperature definitions */ |
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| 156 | /* bandgap clock limits */ |
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| 157 | #define DRA752_CORE_MAX_FREQ 1500000 |
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| 158 | #define DRA752_CORE_MIN_FREQ 1000000 |
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| 159 | /* interrupts thresholds */ |
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| 160 | #define DRA752_CORE_T_HOT 800 |
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| 161 | #define DRA752_CORE_T_COLD 795 |
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| 162 | |
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| 163 | /* DRA752.DSPEVE temperature definitions */ |
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| 164 | /* bandgap clock limits */ |
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| 165 | #define DRA752_DSPEVE_MAX_FREQ 1500000 |
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| 166 | #define DRA752_DSPEVE_MIN_FREQ 1000000 |
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| 167 | /* interrupts thresholds */ |
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| 168 | #define DRA752_DSPEVE_T_HOT 800 |
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| 169 | #define DRA752_DSPEVE_T_COLD 795 |
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| 170 | |
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| 171 | /* DRA752.IVA temperature definitions */ |
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| 172 | /* bandgap clock limits */ |
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| 173 | #define DRA752_IVA_MAX_FREQ 1500000 |
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| 174 | #define DRA752_IVA_MIN_FREQ 1000000 |
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| 175 | /* interrupts thresholds */ |
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| 176 | #define DRA752_IVA_T_HOT 800 |
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| 177 | #define DRA752_IVA_T_COLD 795 |
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| 178 | |
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| 179 | #endif /* __DRA752_BANDGAP_H */ |
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| 180 | |
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