1 | // SPDX-License-Identifier: GPL-2.0-only |
2 | /* |
3 | * DRA752 thermal data. |
4 | * |
5 | * Copyright (C) 2013 Texas Instruments Inc. |
6 | * Contact: |
7 | * Eduardo Valentin <eduardo.valentin@ti.com> |
8 | * Tero Kristo <t-kristo@ti.com> |
9 | * |
10 | * This file is partially autogenerated. |
11 | */ |
12 | |
13 | #include "ti-thermal.h" |
14 | #include "ti-bandgap.h" |
15 | #include "dra752-bandgap.h" |
16 | |
17 | /* |
18 | * DRA752 has five instances of thermal sensor: MPU, GPU, CORE, |
19 | * IVA and DSPEVE need to describe the individual registers and |
20 | * bit fields. |
21 | */ |
22 | |
23 | /* |
24 | * DRA752 CORE thermal sensor register offsets and bit-fields |
25 | */ |
26 | static struct temp_sensor_registers |
27 | dra752_core_temp_sensor_registers = { |
28 | .temp_sensor_ctrl = DRA752_TEMP_SENSOR_CORE_OFFSET, |
29 | .bgap_tempsoff_mask = DRA752_TEMP_SENSOR_TMPSOFF_MASK, |
30 | .bgap_eocz_mask = DRA752_TEMP_SENSOR_EOCZ_MASK, |
31 | .bgap_dtemp_mask = DRA752_TEMP_SENSOR_DTEMP_MASK, |
32 | .bgap_mask_ctrl = DRA752_BANDGAP_CTRL_1_OFFSET, |
33 | .mask_hot_mask = DRA752_BANDGAP_CTRL_1_MASK_HOT_CORE_MASK, |
34 | .mask_cold_mask = DRA752_BANDGAP_CTRL_1_MASK_COLD_CORE_MASK, |
35 | .mask_counter_delay_mask = DRA752_BANDGAP_CTRL_1_COUNTER_DELAY_MASK, |
36 | .mask_freeze_mask = DRA752_BANDGAP_CTRL_1_FREEZE_CORE_MASK, |
37 | .bgap_threshold = DRA752_BANDGAP_THRESHOLD_CORE_OFFSET, |
38 | .threshold_thot_mask = DRA752_BANDGAP_THRESHOLD_HOT_MASK, |
39 | .threshold_tcold_mask = DRA752_BANDGAP_THRESHOLD_COLD_MASK, |
40 | .bgap_status = DRA752_BANDGAP_STATUS_1_OFFSET, |
41 | .status_hot_mask = DRA752_BANDGAP_STATUS_1_HOT_CORE_MASK, |
42 | .status_cold_mask = DRA752_BANDGAP_STATUS_1_COLD_CORE_MASK, |
43 | .ctrl_dtemp_1 = DRA752_DTEMP_CORE_1_OFFSET, |
44 | .ctrl_dtemp_2 = DRA752_DTEMP_CORE_2_OFFSET, |
45 | .bgap_efuse = DRA752_STD_FUSE_OPP_BGAP_CORE_OFFSET, |
46 | }; |
47 | |
48 | /* |
49 | * DRA752 IVA thermal sensor register offsets and bit-fields |
50 | */ |
51 | static struct temp_sensor_registers |
52 | dra752_iva_temp_sensor_registers = { |
53 | .temp_sensor_ctrl = DRA752_TEMP_SENSOR_IVA_OFFSET, |
54 | .bgap_tempsoff_mask = DRA752_TEMP_SENSOR_TMPSOFF_MASK, |
55 | .bgap_eocz_mask = DRA752_TEMP_SENSOR_EOCZ_MASK, |
56 | .bgap_dtemp_mask = DRA752_TEMP_SENSOR_DTEMP_MASK, |
57 | .bgap_mask_ctrl = DRA752_BANDGAP_CTRL_2_OFFSET, |
58 | .mask_hot_mask = DRA752_BANDGAP_CTRL_2_MASK_HOT_IVA_MASK, |
59 | .mask_cold_mask = DRA752_BANDGAP_CTRL_2_MASK_COLD_IVA_MASK, |
60 | .mask_counter_delay_mask = DRA752_BANDGAP_CTRL_1_COUNTER_DELAY_MASK, |
61 | .mask_freeze_mask = DRA752_BANDGAP_CTRL_2_FREEZE_IVA_MASK, |
62 | .bgap_threshold = DRA752_BANDGAP_THRESHOLD_IVA_OFFSET, |
63 | .threshold_thot_mask = DRA752_BANDGAP_THRESHOLD_HOT_MASK, |
64 | .threshold_tcold_mask = DRA752_BANDGAP_THRESHOLD_COLD_MASK, |
65 | .bgap_status = DRA752_BANDGAP_STATUS_2_OFFSET, |
66 | .status_hot_mask = DRA752_BANDGAP_STATUS_2_HOT_IVA_MASK, |
67 | .status_cold_mask = DRA752_BANDGAP_STATUS_2_COLD_IVA_MASK, |
68 | .ctrl_dtemp_1 = DRA752_DTEMP_IVA_1_OFFSET, |
69 | .ctrl_dtemp_2 = DRA752_DTEMP_IVA_2_OFFSET, |
70 | .bgap_efuse = DRA752_STD_FUSE_OPP_BGAP_IVA_OFFSET, |
71 | }; |
72 | |
73 | /* |
74 | * DRA752 MPU thermal sensor register offsets and bit-fields |
75 | */ |
76 | static struct temp_sensor_registers |
77 | dra752_mpu_temp_sensor_registers = { |
78 | .temp_sensor_ctrl = DRA752_TEMP_SENSOR_MPU_OFFSET, |
79 | .bgap_tempsoff_mask = DRA752_TEMP_SENSOR_TMPSOFF_MASK, |
80 | .bgap_eocz_mask = DRA752_TEMP_SENSOR_EOCZ_MASK, |
81 | .bgap_dtemp_mask = DRA752_TEMP_SENSOR_DTEMP_MASK, |
82 | .bgap_mask_ctrl = DRA752_BANDGAP_CTRL_1_OFFSET, |
83 | .mask_hot_mask = DRA752_BANDGAP_CTRL_1_MASK_HOT_MPU_MASK, |
84 | .mask_cold_mask = DRA752_BANDGAP_CTRL_1_MASK_COLD_MPU_MASK, |
85 | .mask_counter_delay_mask = DRA752_BANDGAP_CTRL_1_COUNTER_DELAY_MASK, |
86 | .mask_freeze_mask = DRA752_BANDGAP_CTRL_1_FREEZE_MPU_MASK, |
87 | .bgap_threshold = DRA752_BANDGAP_THRESHOLD_MPU_OFFSET, |
88 | .threshold_thot_mask = DRA752_BANDGAP_THRESHOLD_HOT_MASK, |
89 | .threshold_tcold_mask = DRA752_BANDGAP_THRESHOLD_COLD_MASK, |
90 | .bgap_status = DRA752_BANDGAP_STATUS_1_OFFSET, |
91 | .status_hot_mask = DRA752_BANDGAP_STATUS_1_HOT_MPU_MASK, |
92 | .status_cold_mask = DRA752_BANDGAP_STATUS_1_COLD_MPU_MASK, |
93 | .ctrl_dtemp_1 = DRA752_DTEMP_MPU_1_OFFSET, |
94 | .ctrl_dtemp_2 = DRA752_DTEMP_MPU_2_OFFSET, |
95 | .bgap_efuse = DRA752_STD_FUSE_OPP_BGAP_MPU_OFFSET, |
96 | }; |
97 | |
98 | /* |
99 | * DRA752 DSPEVE thermal sensor register offsets and bit-fields |
100 | */ |
101 | static struct temp_sensor_registers |
102 | dra752_dspeve_temp_sensor_registers = { |
103 | .temp_sensor_ctrl = DRA752_TEMP_SENSOR_DSPEVE_OFFSET, |
104 | .bgap_tempsoff_mask = DRA752_TEMP_SENSOR_TMPSOFF_MASK, |
105 | .bgap_eocz_mask = DRA752_TEMP_SENSOR_EOCZ_MASK, |
106 | .bgap_dtemp_mask = DRA752_TEMP_SENSOR_DTEMP_MASK, |
107 | .bgap_mask_ctrl = DRA752_BANDGAP_CTRL_2_OFFSET, |
108 | .mask_hot_mask = DRA752_BANDGAP_CTRL_2_MASK_HOT_DSPEVE_MASK, |
109 | .mask_cold_mask = DRA752_BANDGAP_CTRL_2_MASK_COLD_DSPEVE_MASK, |
110 | .mask_counter_delay_mask = DRA752_BANDGAP_CTRL_1_COUNTER_DELAY_MASK, |
111 | .mask_freeze_mask = DRA752_BANDGAP_CTRL_2_FREEZE_DSPEVE_MASK, |
112 | .bgap_threshold = DRA752_BANDGAP_THRESHOLD_DSPEVE_OFFSET, |
113 | .threshold_thot_mask = DRA752_BANDGAP_THRESHOLD_HOT_MASK, |
114 | .threshold_tcold_mask = DRA752_BANDGAP_THRESHOLD_COLD_MASK, |
115 | .bgap_status = DRA752_BANDGAP_STATUS_2_OFFSET, |
116 | .status_hot_mask = DRA752_BANDGAP_STATUS_2_HOT_DSPEVE_MASK, |
117 | .status_cold_mask = DRA752_BANDGAP_STATUS_2_COLD_DSPEVE_MASK, |
118 | .ctrl_dtemp_1 = DRA752_DTEMP_DSPEVE_1_OFFSET, |
119 | .ctrl_dtemp_2 = DRA752_DTEMP_DSPEVE_2_OFFSET, |
120 | .bgap_efuse = DRA752_STD_FUSE_OPP_BGAP_DSPEVE_OFFSET, |
121 | }; |
122 | |
123 | /* |
124 | * DRA752 GPU thermal sensor register offsets and bit-fields |
125 | */ |
126 | static struct temp_sensor_registers |
127 | dra752_gpu_temp_sensor_registers = { |
128 | .temp_sensor_ctrl = DRA752_TEMP_SENSOR_GPU_OFFSET, |
129 | .bgap_tempsoff_mask = DRA752_TEMP_SENSOR_TMPSOFF_MASK, |
130 | .bgap_eocz_mask = DRA752_TEMP_SENSOR_EOCZ_MASK, |
131 | .bgap_dtemp_mask = DRA752_TEMP_SENSOR_DTEMP_MASK, |
132 | .bgap_mask_ctrl = DRA752_BANDGAP_CTRL_1_OFFSET, |
133 | .mask_hot_mask = DRA752_BANDGAP_CTRL_1_MASK_HOT_GPU_MASK, |
134 | .mask_cold_mask = DRA752_BANDGAP_CTRL_1_MASK_COLD_GPU_MASK, |
135 | .mask_counter_delay_mask = DRA752_BANDGAP_CTRL_1_COUNTER_DELAY_MASK, |
136 | .mask_freeze_mask = DRA752_BANDGAP_CTRL_1_FREEZE_GPU_MASK, |
137 | .bgap_threshold = DRA752_BANDGAP_THRESHOLD_GPU_OFFSET, |
138 | .threshold_thot_mask = DRA752_BANDGAP_THRESHOLD_HOT_MASK, |
139 | .threshold_tcold_mask = DRA752_BANDGAP_THRESHOLD_COLD_MASK, |
140 | .bgap_status = DRA752_BANDGAP_STATUS_1_OFFSET, |
141 | .status_hot_mask = DRA752_BANDGAP_STATUS_1_HOT_GPU_MASK, |
142 | .status_cold_mask = DRA752_BANDGAP_STATUS_1_COLD_GPU_MASK, |
143 | .ctrl_dtemp_1 = DRA752_DTEMP_GPU_1_OFFSET, |
144 | .ctrl_dtemp_2 = DRA752_DTEMP_GPU_2_OFFSET, |
145 | .bgap_efuse = DRA752_STD_FUSE_OPP_BGAP_GPU_OFFSET, |
146 | }; |
147 | |
148 | /* Thresholds and limits for DRA752 MPU temperature sensor */ |
149 | static struct temp_sensor_data dra752_mpu_temp_sensor_data = { |
150 | .t_hot = DRA752_MPU_T_HOT, |
151 | .t_cold = DRA752_MPU_T_COLD, |
152 | .min_freq = DRA752_MPU_MIN_FREQ, |
153 | .max_freq = DRA752_MPU_MAX_FREQ, |
154 | }; |
155 | |
156 | /* Thresholds and limits for DRA752 GPU temperature sensor */ |
157 | static struct temp_sensor_data dra752_gpu_temp_sensor_data = { |
158 | .t_hot = DRA752_GPU_T_HOT, |
159 | .t_cold = DRA752_GPU_T_COLD, |
160 | .min_freq = DRA752_GPU_MIN_FREQ, |
161 | .max_freq = DRA752_GPU_MAX_FREQ, |
162 | }; |
163 | |
164 | /* Thresholds and limits for DRA752 CORE temperature sensor */ |
165 | static struct temp_sensor_data dra752_core_temp_sensor_data = { |
166 | .t_hot = DRA752_CORE_T_HOT, |
167 | .t_cold = DRA752_CORE_T_COLD, |
168 | .min_freq = DRA752_CORE_MIN_FREQ, |
169 | .max_freq = DRA752_CORE_MAX_FREQ, |
170 | }; |
171 | |
172 | /* Thresholds and limits for DRA752 DSPEVE temperature sensor */ |
173 | static struct temp_sensor_data dra752_dspeve_temp_sensor_data = { |
174 | .t_hot = DRA752_DSPEVE_T_HOT, |
175 | .t_cold = DRA752_DSPEVE_T_COLD, |
176 | .min_freq = DRA752_DSPEVE_MIN_FREQ, |
177 | .max_freq = DRA752_DSPEVE_MAX_FREQ, |
178 | }; |
179 | |
180 | /* Thresholds and limits for DRA752 IVA temperature sensor */ |
181 | static struct temp_sensor_data dra752_iva_temp_sensor_data = { |
182 | .t_hot = DRA752_IVA_T_HOT, |
183 | .t_cold = DRA752_IVA_T_COLD, |
184 | .min_freq = DRA752_IVA_MIN_FREQ, |
185 | .max_freq = DRA752_IVA_MAX_FREQ, |
186 | }; |
187 | |
188 | /* |
189 | * DRA752 : Temperature values in milli degree celsius |
190 | * ADC code values from 540 to 945 |
191 | */ |
192 | static |
193 | int dra752_adc_to_temp[DRA752_ADC_END_VALUE - DRA752_ADC_START_VALUE + 1] = { |
194 | /* Index 540 - 549 */ |
195 | -40000, -40000, -40000, -40000, -39800, -39400, -39000, -38600, -38200, |
196 | -37800, |
197 | /* Index 550 - 559 */ |
198 | -37400, -37000, -36600, -36200, -35800, -35300, -34700, -34200, -33800, |
199 | -33400, |
200 | /* Index 560 - 569 */ |
201 | -33000, -32600, -32200, -31800, -31400, -31000, -30600, -30200, -29800, |
202 | -29400, |
203 | /* Index 570 - 579 */ |
204 | -29000, -28600, -28200, -27700, -27100, -26600, -26200, -25800, -25400, |
205 | -25000, |
206 | /* Index 580 - 589 */ |
207 | -24600, -24200, -23800, -23400, -23000, -22600, -22200, -21800, -21400, |
208 | -21000, |
209 | /* Index 590 - 599 */ |
210 | -20500, -19900, -19400, -19000, -18600, -18200, -17800, -17400, -17000, |
211 | -16600, |
212 | /* Index 600 - 609 */ |
213 | -16200, -15800, -15400, -15000, -14600, -14200, -13800, -13400, -13000, |
214 | -12500, |
215 | /* Index 610 - 619 */ |
216 | -11900, -11400, -11000, -10600, -10200, -9800, -9400, -9000, -8600, |
217 | -8200, |
218 | /* Index 620 - 629 */ |
219 | -7800, -7400, -7000, -6600, -6200, -5800, -5400, -5000, -4500, |
220 | -3900, |
221 | /* Index 630 - 639 */ |
222 | -3400, -3000, -2600, -2200, -1800, -1400, -1000, -600, -200, |
223 | 200, |
224 | /* Index 640 - 649 */ |
225 | 600, 1000, 1400, 1800, 2200, 2600, 3000, 3400, 3900, |
226 | 4500, |
227 | /* Index 650 - 659 */ |
228 | 5000, 5400, 5800, 6200, 6600, 7000, 7400, 7800, 8200, |
229 | 8600, |
230 | /* Index 660 - 669 */ |
231 | 9000, 9400, 9800, 10200, 10600, 11000, 11400, 11800, 12200, |
232 | 12700, |
233 | /* Index 670 - 679 */ |
234 | 13300, 13800, 14200, 14600, 15000, 15400, 15800, 16200, 16600, |
235 | 17000, |
236 | /* Index 680 - 689 */ |
237 | 17400, 17800, 18200, 18600, 19000, 19400, 19800, 20200, 20600, |
238 | 21000, |
239 | /* Index 690 - 699 */ |
240 | 21400, 21900, 22500, 23000, 23400, 23800, 24200, 24600, 25000, |
241 | 25400, |
242 | /* Index 700 - 709 */ |
243 | 25800, 26200, 26600, 27000, 27400, 27800, 28200, 28600, 29000, |
244 | 29400, |
245 | /* Index 710 - 719 */ |
246 | 29800, 30200, 30600, 31000, 31400, 31900, 32500, 33000, 33400, |
247 | 33800, |
248 | /* Index 720 - 729 */ |
249 | 34200, 34600, 35000, 35400, 35800, 36200, 36600, 37000, 37400, |
250 | 37800, |
251 | /* Index 730 - 739 */ |
252 | 38200, 38600, 39000, 39400, 39800, 40200, 40600, 41000, 41400, |
253 | 41800, |
254 | /* Index 740 - 749 */ |
255 | 42200, 42600, 43100, 43700, 44200, 44600, 45000, 45400, 45800, |
256 | 46200, |
257 | /* Index 750 - 759 */ |
258 | 46600, 47000, 47400, 47800, 48200, 48600, 49000, 49400, 49800, |
259 | 50200, |
260 | /* Index 760 - 769 */ |
261 | 50600, 51000, 51400, 51800, 52200, 52600, 53000, 53400, 53800, |
262 | 54200, |
263 | /* Index 770 - 779 */ |
264 | 54600, 55000, 55400, 55900, 56500, 57000, 57400, 57800, 58200, |
265 | 58600, |
266 | /* Index 780 - 789 */ |
267 | 59000, 59400, 59800, 60200, 60600, 61000, 61400, 61800, 62200, |
268 | 62600, |
269 | /* Index 790 - 799 */ |
270 | 63000, 63400, 63800, 64200, 64600, 65000, 65400, 65800, 66200, |
271 | 66600, |
272 | /* Index 800 - 809 */ |
273 | 67000, 67400, 67800, 68200, 68600, 69000, 69400, 69800, 70200, |
274 | 70600, |
275 | /* Index 810 - 819 */ |
276 | 71000, 71500, 72100, 72600, 73000, 73400, 73800, 74200, 74600, |
277 | 75000, |
278 | /* Index 820 - 829 */ |
279 | 75400, 75800, 76200, 76600, 77000, 77400, 77800, 78200, 78600, |
280 | 79000, |
281 | /* Index 830 - 839 */ |
282 | 79400, 79800, 80200, 80600, 81000, 81400, 81800, 82200, 82600, |
283 | 83000, |
284 | /* Index 840 - 849 */ |
285 | 83400, 83800, 84200, 84600, 85000, 85400, 85800, 86200, 86600, |
286 | 87000, |
287 | /* Index 850 - 859 */ |
288 | 87400, 87800, 88200, 88600, 89000, 89400, 89800, 90200, 90600, |
289 | 91000, |
290 | /* Index 860 - 869 */ |
291 | 91400, 91800, 92200, 92600, 93000, 93400, 93800, 94200, 94600, |
292 | 95000, |
293 | /* Index 870 - 879 */ |
294 | 95400, 95800, 96200, 96600, 97000, 97500, 98100, 98600, 99000, |
295 | 99400, |
296 | /* Index 880 - 889 */ |
297 | 99800, 100200, 100600, 101000, 101400, 101800, 102200, 102600, 103000, |
298 | 103400, |
299 | /* Index 890 - 899 */ |
300 | 103800, 104200, 104600, 105000, 105400, 105800, 106200, 106600, 107000, |
301 | 107400, |
302 | /* Index 900 - 909 */ |
303 | 107800, 108200, 108600, 109000, 109400, 109800, 110200, 110600, 111000, |
304 | 111400, |
305 | /* Index 910 - 919 */ |
306 | 111800, 112200, 112600, 113000, 113400, 113800, 114200, 114600, 115000, |
307 | 115400, |
308 | /* Index 920 - 929 */ |
309 | 115800, 116200, 116600, 117000, 117400, 117800, 118200, 118600, 119000, |
310 | 119400, |
311 | /* Index 930 - 939 */ |
312 | 119800, 120200, 120600, 121000, 121400, 121800, 122200, 122600, 123000, |
313 | 123400, |
314 | /* Index 940 - 945 */ |
315 | 123800, 124200, 124600, 124900, 125000, 125000, |
316 | }; |
317 | |
318 | /* DRA752 data */ |
319 | const struct ti_bandgap_data dra752_data = { |
320 | .features = TI_BANDGAP_FEATURE_FREEZE_BIT | |
321 | TI_BANDGAP_FEATURE_TALERT | |
322 | TI_BANDGAP_FEATURE_COUNTER_DELAY | |
323 | TI_BANDGAP_FEATURE_HISTORY_BUFFER | |
324 | TI_BANDGAP_FEATURE_ERRATA_814, |
325 | .fclock_name = "l3instr_ts_gclk_div" , |
326 | .div_ck_name = "l3instr_ts_gclk_div" , |
327 | .conv_table = dra752_adc_to_temp, |
328 | .adc_start_val = DRA752_ADC_START_VALUE, |
329 | .adc_end_val = DRA752_ADC_END_VALUE, |
330 | .expose_sensor = ti_thermal_expose_sensor, |
331 | .remove_sensor = ti_thermal_remove_sensor, |
332 | .sensors = { |
333 | { |
334 | .registers = &dra752_mpu_temp_sensor_registers, |
335 | .ts_data = &dra752_mpu_temp_sensor_data, |
336 | .domain = "cpu" , |
337 | .register_cooling = ti_thermal_register_cpu_cooling, |
338 | .unregister_cooling = ti_thermal_unregister_cpu_cooling, |
339 | .slope_pcb = DRA752_GRADIENT_SLOPE_W_PCB, |
340 | .constant_pcb = DRA752_GRADIENT_CONST_W_PCB, |
341 | }, |
342 | { |
343 | .registers = &dra752_gpu_temp_sensor_registers, |
344 | .ts_data = &dra752_gpu_temp_sensor_data, |
345 | .domain = "gpu" , |
346 | .slope_pcb = DRA752_GRADIENT_SLOPE_W_PCB, |
347 | .constant_pcb = DRA752_GRADIENT_CONST_W_PCB, |
348 | }, |
349 | { |
350 | .registers = &dra752_core_temp_sensor_registers, |
351 | .ts_data = &dra752_core_temp_sensor_data, |
352 | .domain = "core" , |
353 | .slope_pcb = DRA752_GRADIENT_SLOPE_W_PCB, |
354 | .constant_pcb = DRA752_GRADIENT_CONST_W_PCB, |
355 | }, |
356 | { |
357 | .registers = &dra752_dspeve_temp_sensor_registers, |
358 | .ts_data = &dra752_dspeve_temp_sensor_data, |
359 | .domain = "dspeve" , |
360 | .slope_pcb = DRA752_GRADIENT_SLOPE_W_PCB, |
361 | .constant_pcb = DRA752_GRADIENT_CONST_W_PCB, |
362 | }, |
363 | { |
364 | .registers = &dra752_iva_temp_sensor_registers, |
365 | .ts_data = &dra752_iva_temp_sensor_data, |
366 | .domain = "iva" , |
367 | .slope_pcb = DRA752_GRADIENT_SLOPE_W_PCB, |
368 | .constant_pcb = DRA752_GRADIENT_CONST_W_PCB, |
369 | }, |
370 | }, |
371 | .sensor_count = 5, |
372 | }; |
373 | |