1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Serial port driver for BCM2835AUX UART
4 *
5 * Copyright (C) 2016 Martin Sperl <kernel@martin.sperl.org>
6 *
7 * Based on 8250_lpc18xx.c:
8 * Copyright (C) 2015 Joachim Eastwood <manabian@gmail.com>
9 *
10 * The bcm2835aux is capable of RTS auto flow-control, but this driver doesn't
11 * take advantage of it yet. When adding support, be sure not to enable it
12 * simultaneously to rs485.
13 */
14
15#include <linux/clk.h>
16#include <linux/io.h>
17#include <linux/module.h>
18#include <linux/of.h>
19#include <linux/platform_device.h>
20#include <linux/property.h>
21
22#include "8250.h"
23
24#define BCM2835_AUX_UART_CNTL 8
25#define BCM2835_AUX_UART_CNTL_RXEN 0x01 /* Receiver enable */
26#define BCM2835_AUX_UART_CNTL_TXEN 0x02 /* Transmitter enable */
27#define BCM2835_AUX_UART_CNTL_AUTORTS 0x04 /* RTS set by RX fill level */
28#define BCM2835_AUX_UART_CNTL_AUTOCTS 0x08 /* CTS stops transmitter */
29#define BCM2835_AUX_UART_CNTL_RTS3 0x00 /* RTS set until 3 chars left */
30#define BCM2835_AUX_UART_CNTL_RTS2 0x10 /* RTS set until 2 chars left */
31#define BCM2835_AUX_UART_CNTL_RTS1 0x20 /* RTS set until 1 chars left */
32#define BCM2835_AUX_UART_CNTL_RTS4 0x30 /* RTS set until 4 chars left */
33#define BCM2835_AUX_UART_CNTL_RTSINV 0x40 /* Invert auto RTS polarity */
34#define BCM2835_AUX_UART_CNTL_CTSINV 0x80 /* Invert auto CTS polarity */
35
36/**
37 * struct bcm2835aux_data - driver private data of BCM2835 auxiliary UART
38 * @clk: clock producer of the port's uartclk
39 * @line: index of the port's serial8250_ports[] entry
40 * @cntl: cached copy of CNTL register
41 */
42struct bcm2835aux_data {
43 struct clk *clk;
44 int line;
45 u32 cntl;
46};
47
48static void bcm2835aux_rs485_start_tx(struct uart_8250_port *up)
49{
50 if (!(up->port.rs485.flags & SER_RS485_RX_DURING_TX)) {
51 struct bcm2835aux_data *data = dev_get_drvdata(dev: up->port.dev);
52
53 data->cntl &= ~BCM2835_AUX_UART_CNTL_RXEN;
54 serial_out(up, BCM2835_AUX_UART_CNTL, value: data->cntl);
55 }
56
57 /*
58 * On the bcm2835aux, the MCR register contains no other
59 * flags besides RTS. So no need for a read-modify-write.
60 */
61 if (up->port.rs485.flags & SER_RS485_RTS_ON_SEND)
62 serial8250_out_MCR(up, value: 0);
63 else
64 serial8250_out_MCR(up, UART_MCR_RTS);
65}
66
67static void bcm2835aux_rs485_stop_tx(struct uart_8250_port *up)
68{
69 if (up->port.rs485.flags & SER_RS485_RTS_AFTER_SEND)
70 serial8250_out_MCR(up, value: 0);
71 else
72 serial8250_out_MCR(up, UART_MCR_RTS);
73
74 if (!(up->port.rs485.flags & SER_RS485_RX_DURING_TX)) {
75 struct bcm2835aux_data *data = dev_get_drvdata(dev: up->port.dev);
76
77 data->cntl |= BCM2835_AUX_UART_CNTL_RXEN;
78 serial_out(up, BCM2835_AUX_UART_CNTL, value: data->cntl);
79 }
80}
81
82static int bcm2835aux_serial_probe(struct platform_device *pdev)
83{
84 const struct software_node *bcm2835_swnode;
85 struct uart_8250_port up = { };
86 struct bcm2835aux_data *data;
87 struct resource *res;
88 unsigned int uartclk;
89 int ret;
90
91 /* allocate the custom structure */
92 data = devm_kzalloc(dev: &pdev->dev, size: sizeof(*data), GFP_KERNEL);
93 if (!data)
94 return -ENOMEM;
95
96 /* initialize data */
97 up.capabilities = UART_CAP_FIFO | UART_CAP_MINI;
98 up.port.dev = &pdev->dev;
99 up.port.type = PORT_16550;
100 up.port.flags = UPF_FIXED_PORT | UPF_FIXED_TYPE | UPF_SKIP_TEST | UPF_IOREMAP;
101 up.port.rs485_config = serial8250_em485_config;
102 up.port.rs485_supported = serial8250_em485_supported;
103 up.rs485_start_tx = bcm2835aux_rs485_start_tx;
104 up.rs485_stop_tx = bcm2835aux_rs485_stop_tx;
105
106 /* initialize cached copy with power-on reset value */
107 data->cntl = BCM2835_AUX_UART_CNTL_RXEN | BCM2835_AUX_UART_CNTL_TXEN;
108
109 platform_set_drvdata(pdev, data);
110
111 /* get the clock - this also enables the HW */
112 data->clk = devm_clk_get_optional(dev: &pdev->dev, NULL);
113 if (IS_ERR(ptr: data->clk))
114 return dev_err_probe(dev: &pdev->dev, err: PTR_ERR(ptr: data->clk), fmt: "could not get clk\n");
115
116 /* map the main registers */
117 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
118 if (!res) {
119 dev_err(&pdev->dev, "memory resource not found");
120 return -EINVAL;
121 }
122
123 up.port.mapbase = res->start;
124 up.port.mapsize = resource_size(res);
125
126 bcm2835_swnode = device_get_match_data(dev: &pdev->dev);
127 if (bcm2835_swnode) {
128 ret = device_add_software_node(dev: &pdev->dev, node: bcm2835_swnode);
129 if (ret)
130 return ret;
131 }
132
133 ret = uart_read_port_properties(port: &up.port);
134 if (ret)
135 goto rm_swnode;
136
137 up.port.regshift = 2;
138 up.port.fifosize = 8;
139
140 /* enable the clock as a last step */
141 ret = clk_prepare_enable(clk: data->clk);
142 if (ret) {
143 dev_err_probe(dev: &pdev->dev, err: ret, fmt: "unable to enable uart clock\n");
144 goto rm_swnode;
145 }
146
147 uartclk = clk_get_rate(clk: data->clk);
148 if (uartclk)
149 up.port.uartclk = uartclk;
150
151 /* the HW-clock divider for bcm2835aux is 8,
152 * but 8250 expects a divider of 16,
153 * so we have to multiply the actual clock by 2
154 * to get identical baudrates.
155 */
156 up.port.uartclk *= 2;
157
158 /* register the port */
159 ret = serial8250_register_8250_port(&up);
160 if (ret < 0) {
161 dev_err_probe(dev: &pdev->dev, err: ret, fmt: "unable to register 8250 port\n");
162 goto dis_clk;
163 }
164 data->line = ret;
165
166 return 0;
167
168dis_clk:
169 clk_disable_unprepare(clk: data->clk);
170rm_swnode:
171 device_remove_software_node(dev: &pdev->dev);
172 return ret;
173}
174
175static void bcm2835aux_serial_remove(struct platform_device *pdev)
176{
177 struct bcm2835aux_data *data = platform_get_drvdata(pdev);
178
179 serial8250_unregister_port(line: data->line);
180 clk_disable_unprepare(clk: data->clk);
181 device_remove_software_node(dev: &pdev->dev);
182}
183
184/*
185 * Some UEFI implementations (e.g. tianocore/edk2 for the Raspberry Pi)
186 * describe the miniuart with a base address that encompasses the auxiliary
187 * registers shared between the miniuart and spi.
188 *
189 * This is due to historical reasons, see discussion here:
190 * https://edk2.groups.io/g/devel/topic/87501357#84349
191 *
192 * We need to add the offset between the miniuart and auxiliary registers
193 * to get the real miniuart base address.
194 */
195static const struct property_entry bcm2835_acpi_properties[] = {
196 PROPERTY_ENTRY_U32("reg-offset", 0x40),
197 { }
198};
199
200static const struct software_node bcm2835_acpi_node = {
201 .properties = bcm2835_acpi_properties,
202};
203
204static const struct of_device_id bcm2835aux_serial_match[] = {
205 { .compatible = "brcm,bcm2835-aux-uart" },
206 { },
207};
208MODULE_DEVICE_TABLE(of, bcm2835aux_serial_match);
209
210static const struct acpi_device_id bcm2835aux_serial_acpi_match[] = {
211 { "BCM2836", (kernel_ulong_t)&bcm2835_acpi_node },
212 { }
213};
214MODULE_DEVICE_TABLE(acpi, bcm2835aux_serial_acpi_match);
215
216static struct platform_driver bcm2835aux_serial_driver = {
217 .driver = {
218 .name = "bcm2835-aux-uart",
219 .of_match_table = bcm2835aux_serial_match,
220 .acpi_match_table = bcm2835aux_serial_acpi_match,
221 },
222 .probe = bcm2835aux_serial_probe,
223 .remove_new = bcm2835aux_serial_remove,
224};
225module_platform_driver(bcm2835aux_serial_driver);
226
227#ifdef CONFIG_SERIAL_8250_CONSOLE
228
229static int __init early_bcm2835aux_setup(struct earlycon_device *device,
230 const char *options)
231{
232 if (!device->port.membase)
233 return -ENODEV;
234
235 device->port.iotype = UPIO_MEM32;
236 device->port.regshift = 2;
237
238 return early_serial8250_setup(device, NULL);
239}
240
241OF_EARLYCON_DECLARE(bcm2835aux, "brcm,bcm2835-aux-uart",
242 early_bcm2835aux_setup);
243#endif
244
245MODULE_DESCRIPTION("BCM2835 auxiliar UART driver");
246MODULE_AUTHOR("Martin Sperl <kernel@martin.sperl.org>");
247MODULE_LICENSE("GPL v2");
248

source code of linux/drivers/tty/serial/8250/8250_bcm2835aux.c