1	// SPDX-License-Identifier: GPL-2.0+
2	/*
3	* Base port operations for 8250/16550-type serial ports
4	*
5	* Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
6	* Split from 8250_core.c, Copyright (C) 2001 Russell King.
7	*
8	* A note about mapbase / membase
9	*
10	* mapbase is the physical address of the IO port.
11	* membase is an 'ioremapped' cookie.
12	*/
13
14	#include <linux/module.h>
15	#include <linux/moduleparam.h>
16	#include <linux/ioport.h>
17	#include <linux/init.h>
18	#include <linux/irq.h>
19	#include <linux/console.h>
20	#include <linux/gpio/consumer.h>
21	#include <linux/sysrq.h>
22	#include <linux/delay.h>
23	#include <linux/platform_device.h>
24	#include <linux/tty.h>
25	#include <linux/ratelimit.h>
26	#include <linux/tty_flip.h>
27	#include <linux/serial.h>
28	#include <linux/serial_8250.h>
29	#include <linux/nmi.h>
30	#include <linux/mutex.h>
31	#include <linux/slab.h>
32	#include <linux/uaccess.h>
33	#include <linux/pm_runtime.h>
34	#include <linux/ktime.h>
35
36	#include <asm/io.h>
37	#include <asm/irq.h>
38
39	#include "8250.h"
40
41	/*
42	* Debugging.
43	*/
44	#if 0
45	#define DEBUG_AUTOCONF(fmt...) printk(fmt)
46	#else
47	#define DEBUG_AUTOCONF(fmt...) do { } while (0)
48	#endif
49
50	/*
51	* Here we define the default xmit fifo size used for each type of UART.
52	*/
53	static const struct serial8250_config uart_config[] = {
54	[PORT_UNKNOWN] = {
55	.name = "unknown",
56	.fifo_size = 1,
57	.tx_loadsz = 1,
58	},
59	[PORT_8250] = {
60	.name = "8250",
61	.fifo_size = 1,
62	.tx_loadsz = 1,
63	},
64	[PORT_16450] = {
65	.name = "16450",
66	.fifo_size = 1,
67	.tx_loadsz = 1,
68	},
69	[PORT_16550] = {
70	.name = "16550",
71	.fifo_size = 1,
72	.tx_loadsz = 1,
73	},
74	[PORT_16550A] = {
75	.name = "16550A",
76	.fifo_size = 16,
77	.tx_loadsz = 16,
78	.fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
79	.rxtrig_bytes = {1, 4, 8, 14},
80	.flags = UART_CAP_FIFO,
81	},
82	[PORT_CIRRUS] = {
83	.name = "Cirrus",
84	.fifo_size = 1,
85	.tx_loadsz = 1,
86	},
87	[PORT_16650] = {
88	.name = "ST16650",
89	.fifo_size = 1,
90	.tx_loadsz = 1,
91	.flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
92	},
93	[PORT_16650V2] = {
94	.name = "ST16650V2",
95	.fifo_size = 32,
96	.tx_loadsz = 16,
97	.fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
98	UART_FCR_T_TRIG_00,
99	.rxtrig_bytes = {8, 16, 24, 28},
100	.flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
101	},
102	[PORT_16750] = {
103	.name = "TI16750",
104	.fifo_size = 64,
105	.tx_loadsz = 64,
106	.fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10 |
107	UART_FCR7_64BYTE,
108	.rxtrig_bytes = {1, 16, 32, 56},
109	.flags = UART_CAP_FIFO | UART_CAP_SLEEP | UART_CAP_AFE,
110	},
111	[PORT_STARTECH] = {
112	.name = "Startech",
113	.fifo_size = 1,
114	.tx_loadsz = 1,
115	},
116	[PORT_16C950] = {
117	.name = "16C950/954",
118	.fifo_size = 128,
119	.tx_loadsz = 128,
120	.fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01,
121	.rxtrig_bytes = {16, 32, 112, 120},
122	/* UART_CAP_EFR breaks billionon CF bluetooth card. */
123	.flags = UART_CAP_FIFO | UART_CAP_SLEEP,
124	},
125	[PORT_16654] = {
126	.name = "ST16654",
127	.fifo_size = 64,
128	.tx_loadsz = 32,
129	.fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
130	UART_FCR_T_TRIG_10,
131	.rxtrig_bytes = {8, 16, 56, 60},
132	.flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
133	},
134	[PORT_16850] = {
135	.name = "XR16850",
136	.fifo_size = 128,
137	.tx_loadsz = 128,
138	.fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
139	.flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
140	},
141	[PORT_RSA] = {
142	.name = "RSA",
143	.fifo_size = 2048,
144	.tx_loadsz = 2048,
145	.fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_11,
146	.flags = UART_CAP_FIFO,
147	},
148	[PORT_NS16550A] = {
149	.name = "NS16550A",
150	.fifo_size = 16,
151	.tx_loadsz = 16,
152	.fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
153	.flags = UART_CAP_FIFO | UART_NATSEMI,
154	},
155	[PORT_XSCALE] = {
156	.name = "XScale",
157	.fifo_size = 32,
158	.tx_loadsz = 32,
159	.fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
160	.flags = UART_CAP_FIFO | UART_CAP_UUE | UART_CAP_RTOIE,
161	},
162	[PORT_OCTEON] = {
163	.name = "OCTEON",
164	.fifo_size = 64,
165	.tx_loadsz = 64,
166	.fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
167	.flags = UART_CAP_FIFO,
168	},
169	[PORT_U6_16550A] = {
170	.name = "U6_16550A",
171	.fifo_size = 64,
172	.tx_loadsz = 64,
173	.fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
174	.flags = UART_CAP_FIFO | UART_CAP_AFE,
175	},
176	[PORT_TEGRA] = {
177	.name = "Tegra",
178	.fifo_size = 32,
179	.tx_loadsz = 8,
180	.fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
181	UART_FCR_T_TRIG_01,
182	.rxtrig_bytes = {1, 4, 8, 14},
183	.flags = UART_CAP_FIFO | UART_CAP_RTOIE,
184	},
185	[PORT_XR17D15X] = {
186	.name = "XR17D15X",
187	.fifo_size = 64,
188	.tx_loadsz = 64,
189	.fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
190	.flags = UART_CAP_FIFO | UART_CAP_AFE | UART_CAP_EFR |
191	UART_CAP_SLEEP,
192	},
193	[PORT_XR17V35X] = {
194	.name = "XR17V35X",
195	.fifo_size = 256,
196	.tx_loadsz = 256,
197	.fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_11 |
198	UART_FCR_T_TRIG_11,
199	.flags = UART_CAP_FIFO | UART_CAP_AFE | UART_CAP_EFR |
200	UART_CAP_SLEEP,
201	},
202	[PORT_LPC3220] = {
203	.name = "LPC3220",
204	.fifo_size = 64,
205	.tx_loadsz = 32,
206	.fcr = UART_FCR_DMA_SELECT | UART_FCR_ENABLE_FIFO |
207	UART_FCR_R_TRIG_00 | UART_FCR_T_TRIG_00,
208	.flags = UART_CAP_FIFO,
209	},
210	[PORT_BRCM_TRUMANAGE] = {
211	.name = "TruManage",
212	.fifo_size = 1,
213	.tx_loadsz = 1024,
214	.flags = UART_CAP_HFIFO,
215	},
216	[PORT_8250_CIR] = {
217	.name = "CIR port"
218	},
219	[PORT_ALTR_16550_F32] = {
220	.name = "Altera 16550 FIFO32",
221	.fifo_size = 32,
222	.tx_loadsz = 32,
223	.fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
224	.rxtrig_bytes = {1, 8, 16, 30},
225	.flags = UART_CAP_FIFO | UART_CAP_AFE,
226	},
227	[PORT_ALTR_16550_F64] = {
228	.name = "Altera 16550 FIFO64",
229	.fifo_size = 64,
230	.tx_loadsz = 64,
231	.fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
232	.rxtrig_bytes = {1, 16, 32, 62},
233	.flags = UART_CAP_FIFO | UART_CAP_AFE,
234	},
235	[PORT_ALTR_16550_F128] = {
236	.name = "Altera 16550 FIFO128",
237	.fifo_size = 128,
238	.tx_loadsz = 128,
239	.fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
240	.rxtrig_bytes = {1, 32, 64, 126},
241	.flags = UART_CAP_FIFO | UART_CAP_AFE,
242	},
243	/*
244	* tx_loadsz is set to 63-bytes instead of 64-bytes to implement
245	* workaround of errata A-008006 which states that tx_loadsz should
246	* be configured less than Maximum supported fifo bytes.
247	*/
248	[PORT_16550A_FSL64] = {
249	.name = "16550A_FSL64",
250	.fifo_size = 64,
251	.tx_loadsz = 63,
252	.fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10 |
253	UART_FCR7_64BYTE,
254	.flags = UART_CAP_FIFO | UART_CAP_NOTEMT,
255	},
256	[PORT_RT2880] = {
257	.name = "Palmchip BK-3103",
258	.fifo_size = 16,
259	.tx_loadsz = 16,
260	.fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
261	.rxtrig_bytes = {1, 4, 8, 14},
262	.flags = UART_CAP_FIFO,
263	},
264	[PORT_DA830] = {
265	.name = "TI DA8xx/66AK2x",
266	.fifo_size = 16,
267	.tx_loadsz = 16,
268	.fcr = UART_FCR_DMA_SELECT | UART_FCR_ENABLE_FIFO |
269	UART_FCR_R_TRIG_10,
270	.rxtrig_bytes = {1, 4, 8, 14},
271	.flags = UART_CAP_FIFO | UART_CAP_AFE,
272	},
273	[PORT_MTK_BTIF] = {
274	.name = "MediaTek BTIF",
275	.fifo_size = 16,
276	.tx_loadsz = 16,
277	.fcr = UART_FCR_ENABLE_FIFO |
278	UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT,
279	.flags = UART_CAP_FIFO,
280	},
281	[PORT_NPCM] = {
282	.name = "Nuvoton 16550",
283	.fifo_size = 16,
284	.tx_loadsz = 16,
285	.fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10 |
286	UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT,
287	.rxtrig_bytes = {1, 4, 8, 14},
288	.flags = UART_CAP_FIFO,
289	},
290	[PORT_SUNIX] = {
291	.name = "Sunix",
292	.fifo_size = 128,
293	.tx_loadsz = 128,
294	.fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
295	.rxtrig_bytes = {1, 32, 64, 112},
296	.flags = UART_CAP_FIFO | UART_CAP_SLEEP,
297	},
298	[PORT_ASPEED_VUART] = {
299	.name = "ASPEED VUART",
300	.fifo_size = 16,
301	.tx_loadsz = 16,
302	.fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_00,
303	.rxtrig_bytes = {1, 4, 8, 14},
304	.flags = UART_CAP_FIFO,
305	},
306	[PORT_MCHP16550A] = {
307	.name = "MCHP16550A",
308	.fifo_size = 256,
309	.tx_loadsz = 256,
310	.fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01,
311	.rxtrig_bytes = {2, 66, 130, 194},
312	.flags = UART_CAP_FIFO,
313	},
314	[PORT_BCM7271] = {
315	.name = "Broadcom BCM7271 UART",
316	.fifo_size = 32,
317	.tx_loadsz = 32,
318	.fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01,
319	.rxtrig_bytes = {1, 8, 16, 30},
320	.flags = UART_CAP_FIFO | UART_CAP_AFE,
321	},
322	};
323
324	/* Uart divisor latch read */
325	static u32 default_serial_dl_read(struct uart_8250_port *up)
326	{
327	/* Assign these in pieces to truncate any bits above 7. */
328	unsigned char dll = serial_in(up, UART_DLL);
329	unsigned char dlm = serial_in(up, UART_DLM);
330
331	return dll | dlm << 8;
332	}
333
334	/* Uart divisor latch write */
335	static void default_serial_dl_write(struct uart_8250_port *up, u32 value)
336	{
337	serial_out(up, UART_DLL, value: value & 0xff);
338	serial_out(up, UART_DLM, value: value >> 8 & 0xff);
339	}
340
341	static unsigned int hub6_serial_in(struct uart_port *p, int offset)
342	{
343	offset = offset << p->regshift;
344	outb(value: p->hub6 - 1 + offset, port: p->iobase);
345	return inb(port: p->iobase + 1);
346	}
347
348	static void hub6_serial_out(struct uart_port *p, int offset, int value)
349	{
350	offset = offset << p->regshift;
351	outb(value: p->hub6 - 1 + offset, port: p->iobase);
352	outb(value, port: p->iobase + 1);
353	}
354
355	static unsigned int mem_serial_in(struct uart_port *p, int offset)
356	{
357	offset = offset << p->regshift;
358	return readb(addr: p->membase + offset);
359	}
360
361	static void mem_serial_out(struct uart_port *p, int offset, int value)
362	{
363	offset = offset << p->regshift;
364	writeb(val: value, addr: p->membase + offset);
365	}
366
367	static void mem16_serial_out(struct uart_port *p, int offset, int value)
368	{
369	offset = offset << p->regshift;
370	writew(val: value, addr: p->membase + offset);
371	}
372
373	static unsigned int mem16_serial_in(struct uart_port *p, int offset)
374	{
375	offset = offset << p->regshift;
376	return readw(addr: p->membase + offset);
377	}
378
379	static void mem32_serial_out(struct uart_port *p, int offset, int value)
380	{
381	offset = offset << p->regshift;
382	writel(val: value, addr: p->membase + offset);
383	}
384
385	static unsigned int mem32_serial_in(struct uart_port *p, int offset)
386	{
387	offset = offset << p->regshift;
388	return readl(addr: p->membase + offset);
389	}
390
391	static void mem32be_serial_out(struct uart_port *p, int offset, int value)
392	{
393	offset = offset << p->regshift;
394	iowrite32be(value, p->membase + offset);
395	}
396
397	static unsigned int mem32be_serial_in(struct uart_port *p, int offset)
398	{
399	offset = offset << p->regshift;
400	return ioread32be(p->membase + offset);
401	}
402
403	static unsigned int io_serial_in(struct uart_port *p, int offset)
404	{
405	offset = offset << p->regshift;
406	return inb(port: p->iobase + offset);
407	}
408
409	static void io_serial_out(struct uart_port *p, int offset, int value)
410	{
411	offset = offset << p->regshift;
412	outb(value, port: p->iobase + offset);
413	}
414
415	static int serial8250_default_handle_irq(struct uart_port *port);
416
417	static void set_io_from_upio(struct uart_port *p)
418	{
419	struct uart_8250_port *up = up_to_u8250p(up: p);
420
421	up->dl_read = default_serial_dl_read;
422	up->dl_write = default_serial_dl_write;
423
424	switch (p->iotype) {
425	case UPIO_HUB6:
426	p->serial_in = hub6_serial_in;
427	p->serial_out = hub6_serial_out;
428	break;
429
430	case UPIO_MEM:
431	p->serial_in = mem_serial_in;
432	p->serial_out = mem_serial_out;
433	break;
434
435	case UPIO_MEM16:
436	p->serial_in = mem16_serial_in;
437	p->serial_out = mem16_serial_out;
438	break;
439
440	case UPIO_MEM32:
441	p->serial_in = mem32_serial_in;
442	p->serial_out = mem32_serial_out;
443	break;
444
445	case UPIO_MEM32BE:
446	p->serial_in = mem32be_serial_in;
447	p->serial_out = mem32be_serial_out;
448	break;
449
450	default:
451	p->serial_in = io_serial_in;
452	p->serial_out = io_serial_out;
453	break;
454	}
455	/* Remember loaded iotype */
456	up->cur_iotype = p->iotype;
457	p->handle_irq = serial8250_default_handle_irq;
458	}
459
460	static void
461	serial_port_out_sync(struct uart_port *p, int offset, int value)
462	{
463	switch (p->iotype) {
464	case UPIO_MEM:
465	case UPIO_MEM16:
466	case UPIO_MEM32:
467	case UPIO_MEM32BE:
468	case UPIO_AU:
469	p->serial_out(p, offset, value);
470	p->serial_in(p, UART_LCR); /* safe, no side-effects */
471	break;
472	default:
473	p->serial_out(p, offset, value);
474	}
475	}
476
477	/*
478	* FIFO support.
479	*/
480	static void serial8250_clear_fifos(struct uart_8250_port *p)
481	{
482	if (p->capabilities & UART_CAP_FIFO) {
483	serial_out(up: p, UART_FCR, UART_FCR_ENABLE_FIFO);
484	serial_out(up: p, UART_FCR, UART_FCR_ENABLE_FIFO |
485	UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
486	serial_out(up: p, UART_FCR, value: 0);
487	}
488	}
489
490	static enum hrtimer_restart serial8250_em485_handle_start_tx(struct hrtimer *t);
491	static enum hrtimer_restart serial8250_em485_handle_stop_tx(struct hrtimer *t);
492
493	void serial8250_clear_and_reinit_fifos(struct uart_8250_port *p)
494	{
495	serial8250_clear_fifos(p);
496	serial_out(up: p, UART_FCR, value: p->fcr);
497	}
498	EXPORT_SYMBOL_GPL(serial8250_clear_and_reinit_fifos);
499
500	void serial8250_rpm_get(struct uart_8250_port *p)
501	{
502	if (!(p->capabilities & UART_CAP_RPM))
503	return;
504	pm_runtime_get_sync(dev: p->port.dev);
505	}
506	EXPORT_SYMBOL_GPL(serial8250_rpm_get);
507
508	void serial8250_rpm_put(struct uart_8250_port *p)
509	{
510	if (!(p->capabilities & UART_CAP_RPM))
511	return;
512	pm_runtime_mark_last_busy(dev: p->port.dev);
513	pm_runtime_put_autosuspend(dev: p->port.dev);
514	}
515	EXPORT_SYMBOL_GPL(serial8250_rpm_put);
516
517	/**
518	* serial8250_em485_init() - put uart_8250_port into rs485 emulating
519	* @p: uart_8250_port port instance
520	*
521	* The function is used to start rs485 software emulating on the
522	* &struct uart_8250_port* @p. Namely, RTS is switched before/after
523	* transmission. The function is idempotent, so it is safe to call it
524	* multiple times.
525	*
526	* The caller MUST enable interrupt on empty shift register before
527	* calling serial8250_em485_init(). This interrupt is not a part of
528	* 8250 standard, but implementation defined.
529	*
530	* The function is supposed to be called from .rs485_config callback
531	* or from any other callback protected with p->port.lock spinlock.
532	*
533	* See also serial8250_em485_destroy()
534	*
535	* Return 0 - success, -errno - otherwise
536	*/
537	static int serial8250_em485_init(struct uart_8250_port *p)
538	{
539	/* Port locked to synchronize UART_IER access against the console. */
540	lockdep_assert_held_once(&p->port.lock);
541
542	if (p->em485)
543	goto deassert_rts;
544
545	p->em485 = kmalloc(size: sizeof(struct uart_8250_em485), GFP_ATOMIC);
546	if (!p->em485)
547	return -ENOMEM;
548
549	hrtimer_init(timer: &p->em485->stop_tx_timer, CLOCK_MONOTONIC,
550	mode: HRTIMER_MODE_REL);
551	hrtimer_init(timer: &p->em485->start_tx_timer, CLOCK_MONOTONIC,
552	mode: HRTIMER_MODE_REL);
553	p->em485->stop_tx_timer.function = &serial8250_em485_handle_stop_tx;
554	p->em485->start_tx_timer.function = &serial8250_em485_handle_start_tx;
555	p->em485->port = p;
556	p->em485->active_timer = NULL;
557	p->em485->tx_stopped = true;
558
559	deassert_rts:
560	if (p->em485->tx_stopped)
561	p->rs485_stop_tx(p);
562
563	return 0;
564	}
565
566	/**
567	* serial8250_em485_destroy() - put uart_8250_port into normal state
568	* @p: uart_8250_port port instance
569	*
570	* The function is used to stop rs485 software emulating on the
571	* &struct uart_8250_port* @p. The function is idempotent, so it is safe to
572	* call it multiple times.
573	*
574	* The function is supposed to be called from .rs485_config callback
575	* or from any other callback protected with p->port.lock spinlock.
576	*
577	* See also serial8250_em485_init()
578	*/
579	void serial8250_em485_destroy(struct uart_8250_port *p)
580	{
581	if (!p->em485)
582	return;
583
584	hrtimer_cancel(timer: &p->em485->start_tx_timer);
585	hrtimer_cancel(timer: &p->em485->stop_tx_timer);
586
587	kfree(objp: p->em485);
588	p->em485 = NULL;
589	}
590	EXPORT_SYMBOL_GPL(serial8250_em485_destroy);
591
592	struct serial_rs485 serial8250_em485_supported = {
593	.flags = SER_RS485_ENABLED | SER_RS485_RTS_ON_SEND | SER_RS485_RTS_AFTER_SEND |
594	SER_RS485_TERMINATE_BUS | SER_RS485_RX_DURING_TX,
595	.delay_rts_before_send = 1,
596	.delay_rts_after_send = 1,
597	};
598	EXPORT_SYMBOL_GPL(serial8250_em485_supported);
599
600	/**
601	* serial8250_em485_config() - generic ->rs485_config() callback
602	* @port: uart port
603	* @termios: termios structure
604	* @rs485: rs485 settings
605	*
606	* Generic callback usable by 8250 uart drivers to activate rs485 settings
607	* if the uart is incapable of driving RTS as a Transmit Enable signal in
608	* hardware, relying on software emulation instead.
609	*/
610	int serial8250_em485_config(struct uart_port *port, struct ktermios *termios,
611	struct serial_rs485 *rs485)
612	{
613	struct uart_8250_port *up = up_to_u8250p(up: port);
614
615	/* pick sane settings if the user hasn't */
616	if (!!(rs485->flags & SER_RS485_RTS_ON_SEND) ==
617	!!(rs485->flags & SER_RS485_RTS_AFTER_SEND)) {
618	rs485->flags |= SER_RS485_RTS_ON_SEND;
619	rs485->flags &= ~SER_RS485_RTS_AFTER_SEND;
620	}
621
622	/*
623	* Both serial8250_em485_init() and serial8250_em485_destroy()
624	* are idempotent.
625	*/
626	if (rs485->flags & SER_RS485_ENABLED)
627	return serial8250_em485_init(p: up);
628
629	serial8250_em485_destroy(up);
630	return 0;
631	}
632	EXPORT_SYMBOL_GPL(serial8250_em485_config);
633
634	/*
635	* These two wrappers ensure that enable_runtime_pm_tx() can be called more than
636	* once and disable_runtime_pm_tx() will still disable RPM because the fifo is
637	* empty and the HW can idle again.
638	*/
639	void serial8250_rpm_get_tx(struct uart_8250_port *p)
640	{
641	unsigned char rpm_active;
642
643	if (!(p->capabilities & UART_CAP_RPM))
644	return;
645
646	rpm_active = xchg(&p->rpm_tx_active, 1);
647	if (rpm_active)
648	return;
649	pm_runtime_get_sync(dev: p->port.dev);
650	}
651	EXPORT_SYMBOL_GPL(serial8250_rpm_get_tx);
652
653	void serial8250_rpm_put_tx(struct uart_8250_port *p)
654	{
655	unsigned char rpm_active;
656
657	if (!(p->capabilities & UART_CAP_RPM))
658	return;
659
660	rpm_active = xchg(&p->rpm_tx_active, 0);
661	if (!rpm_active)
662	return;
663	pm_runtime_mark_last_busy(dev: p->port.dev);
664	pm_runtime_put_autosuspend(dev: p->port.dev);
665	}
666	EXPORT_SYMBOL_GPL(serial8250_rpm_put_tx);
667
668	/*
669	* IER sleep support. UARTs which have EFRs need the "extended
670	* capability" bit enabled. Note that on XR16C850s, we need to
671	* reset LCR to write to IER.
672	*/
673	static void serial8250_set_sleep(struct uart_8250_port *p, int sleep)
674	{
675	unsigned char lcr = 0, efr = 0;
676
677	serial8250_rpm_get(p);
678
679	if (p->capabilities & UART_CAP_SLEEP) {
680	/* Synchronize UART_IER access against the console. */
681	uart_port_lock_irq(up: &p->port);
682	if (p->capabilities & UART_CAP_EFR) {
683	lcr = serial_in(up: p, UART_LCR);
684	efr = serial_in(up: p, UART_EFR);
685	serial_out(up: p, UART_LCR, UART_LCR_CONF_MODE_B);
686	serial_out(up: p, UART_EFR, UART_EFR_ECB);
687	serial_out(up: p, UART_LCR, value: 0);
688	}
689	serial_out(up: p, UART_IER, value: sleep ? UART_IERX_SLEEP : 0);
690	if (p->capabilities & UART_CAP_EFR) {
691	serial_out(up: p, UART_LCR, UART_LCR_CONF_MODE_B);
692	serial_out(up: p, UART_EFR, value: efr);
693	serial_out(up: p, UART_LCR, value: lcr);
694	}
695	uart_port_unlock_irq(up: &p->port);
696	}
697
698	serial8250_rpm_put(p);
699	}
700
701	static void serial8250_clear_IER(struct uart_8250_port *up)
702	{
703	if (up->capabilities & UART_CAP_UUE)
704	serial_out(up, UART_IER, UART_IER_UUE);
705	else
706	serial_out(up, UART_IER, value: 0);
707	}
708
709	#ifdef CONFIG_SERIAL_8250_RSA
710	/*
711	* Attempts to turn on the RSA FIFO. Returns zero on failure.
712	* We set the port uart clock rate if we succeed.
713	*/
714	static int __enable_rsa(struct uart_8250_port *up)
715	{
716	unsigned char mode;
717	int result;
718
719	mode = serial_in(up, UART_RSA_MSR);
720	result = mode & UART_RSA_MSR_FIFO;
721
722	if (!result) {
723	serial_out(up, UART_RSA_MSR, value: mode | UART_RSA_MSR_FIFO);
724	mode = serial_in(up, UART_RSA_MSR);
725	result = mode & UART_RSA_MSR_FIFO;
726	}
727
728	if (result)
729	up->port.uartclk = SERIAL_RSA_BAUD_BASE * 16;
730
731	return result;
732	}
733
734	static void enable_rsa(struct uart_8250_port *up)
735	{
736	if (up->port.type == PORT_RSA) {
737	if (up->port.uartclk != SERIAL_RSA_BAUD_BASE * 16) {
738	uart_port_lock_irq(up: &up->port);
739	__enable_rsa(up);
740	uart_port_unlock_irq(up: &up->port);
741	}
742	if (up->port.uartclk == SERIAL_RSA_BAUD_BASE * 16)
743	serial_out(up, UART_RSA_FRR, value: 0);
744	}
745	}
746
747	/*
748	* Attempts to turn off the RSA FIFO. Returns zero on failure.
749	* It is unknown why interrupts were disabled in here. However,
750	* the caller is expected to preserve this behaviour by grabbing
751	* the spinlock before calling this function.
752	*/
753	static void disable_rsa(struct uart_8250_port *up)
754	{
755	unsigned char mode;
756	int result;
757
758	if (up->port.type == PORT_RSA &&
759	up->port.uartclk == SERIAL_RSA_BAUD_BASE * 16) {
760	uart_port_lock_irq(up: &up->port);
761
762	mode = serial_in(up, UART_RSA_MSR);
763	result = !(mode & UART_RSA_MSR_FIFO);
764
765	if (!result) {
766	serial_out(up, UART_RSA_MSR, value: mode & ~UART_RSA_MSR_FIFO);
767	mode = serial_in(up, UART_RSA_MSR);
768	result = !(mode & UART_RSA_MSR_FIFO);
769	}
770
771	if (result)
772	up->port.uartclk = SERIAL_RSA_BAUD_BASE_LO * 16;
773	uart_port_unlock_irq(up: &up->port);
774	}
775	}
776	#endif /* CONFIG_SERIAL_8250_RSA */
777
778	/*
779	* This is a quickie test to see how big the FIFO is.
780	* It doesn't work at all the time, more's the pity.
781	*/
782	static int size_fifo(struct uart_8250_port *up)
783	{
784	unsigned char old_fcr, old_mcr, old_lcr;
785	u32 old_dl;
786	int count;
787
788	old_lcr = serial_in(up, UART_LCR);
789	serial_out(up, UART_LCR, value: 0);
790	old_fcr = serial_in(up, UART_FCR);
791	old_mcr = serial8250_in_MCR(up);
792	serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO |
793	UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
794	serial8250_out_MCR(up, UART_MCR_LOOP);
795	serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
796	old_dl = serial_dl_read(up);
797	serial_dl_write(up, value: 0x0001);
798	serial_out(up, UART_LCR, UART_LCR_WLEN8);
799	for (count = 0; count < 256; count++)
800	serial_out(up, UART_TX, value: count);
801	mdelay(20);/* FIXME - schedule_timeout */
802	for (count = 0; (serial_in(up, UART_LSR) & UART_LSR_DR) &&
803	(count < 256); count++)
804	serial_in(up, UART_RX);
805	serial_out(up, UART_FCR, value: old_fcr);
806	serial8250_out_MCR(up, value: old_mcr);
807	serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
808	serial_dl_write(up, value: old_dl);
809	serial_out(up, UART_LCR, value: old_lcr);
810
811	return count;
812	}
813
814	/*
815	* Read UART ID using the divisor method - set DLL and DLM to zero
816	* and the revision will be in DLL and device type in DLM. We
817	* preserve the device state across this.
818	*/
819	static unsigned int autoconfig_read_divisor_id(struct uart_8250_port *p)
820	{
821	unsigned char old_lcr;
822	unsigned int id, old_dl;
823
824	old_lcr = serial_in(up: p, UART_LCR);
825	serial_out(up: p, UART_LCR, UART_LCR_CONF_MODE_A);
826	old_dl = serial_dl_read(up: p);
827	serial_dl_write(up: p, value: 0);
828	id = serial_dl_read(up: p);
829	serial_dl_write(up: p, value: old_dl);
830
831	serial_out(up: p, UART_LCR, value: old_lcr);
832
833	return id;
834	}
835
836	/*
837	* This is a helper routine to autodetect StarTech/Exar/Oxsemi UART's.
838	* When this function is called we know it is at least a StarTech
839	* 16650 V2, but it might be one of several StarTech UARTs, or one of
840	* its clones. (We treat the broken original StarTech 16650 V1 as a
841	* 16550, and why not? Startech doesn't seem to even acknowledge its
842	* existence.)
843	*
844	* What evil have men's minds wrought...
845	*/
846	static void autoconfig_has_efr(struct uart_8250_port *up)
847	{
848	unsigned int id1, id2, id3, rev;
849
850	/*
851	* Everything with an EFR has SLEEP
852	*/
853	up->capabilities |= UART_CAP_EFR | UART_CAP_SLEEP;
854
855	/*
856	* First we check to see if it's an Oxford Semiconductor UART.
857	*
858	* If we have to do this here because some non-National
859	* Semiconductor clone chips lock up if you try writing to the
860	* LSR register (which serial_icr_read does)
861	*/
862
863	/*
864	* Check for Oxford Semiconductor 16C950.
865	*
866	* EFR [4] must be set else this test fails.
867	*
868	* This shouldn't be necessary, but Mike Hudson (Exoray@isys.ca)
869	* claims that it's needed for 952 dual UART's (which are not
870	* recommended for new designs).
871	*/
872	up->acr = 0;
873	serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
874	serial_out(up, UART_EFR, UART_EFR_ECB);
875	serial_out(up, UART_LCR, value: 0x00);
876	id1 = serial_icr_read(up, UART_ID1);
877	id2 = serial_icr_read(up, UART_ID2);
878	id3 = serial_icr_read(up, UART_ID3);
879	rev = serial_icr_read(up, UART_REV);
880
881	DEBUG_AUTOCONF("950id=%02x:%02x:%02x:%02x ", id1, id2, id3, rev);
882
883	if (id1 == 0x16 && id2 == 0xC9 &&
884	(id3 == 0x50 || id3 == 0x52 || id3 == 0x54)) {
885	up->port.type = PORT_16C950;
886
887	/*
888	* Enable work around for the Oxford Semiconductor 952 rev B
889	* chip which causes it to seriously miscalculate baud rates
890	* when DLL is 0.
891	*/
892	if (id3 == 0x52 && rev == 0x01)
893	up->bugs |= UART_BUG_QUOT;
894	return;
895	}
896
897	/*
898	* We check for a XR16C850 by setting DLL and DLM to 0, and then
899	* reading back DLL and DLM. The chip type depends on the DLM
900	* value read back:
901	* 0x10 - XR16C850 and the DLL contains the chip revision.
902	* 0x12 - XR16C2850.
903	* 0x14 - XR16C854.
904	*/
905	id1 = autoconfig_read_divisor_id(p: up);
906	DEBUG_AUTOCONF("850id=%04x ", id1);
907
908	id2 = id1 >> 8;
909	if (id2 == 0x10 || id2 == 0x12 || id2 == 0x14) {
910	up->port.type = PORT_16850;
911	return;
912	}
913
914	/*
915	* It wasn't an XR16C850.
916	*
917	* We distinguish between the '654 and the '650 by counting
918	* how many bytes are in the FIFO. I'm using this for now,
919	* since that's the technique that was sent to me in the
920	* serial driver update, but I'm not convinced this works.
921	* I've had problems doing this in the past. -TYT
922	*/
923	if (size_fifo(up) == 64)
924	up->port.type = PORT_16654;
925	else
926	up->port.type = PORT_16650V2;
927	}
928
929	/*
930	* We detected a chip without a FIFO. Only two fall into
931	* this category - the original 8250 and the 16450. The
932	* 16450 has a scratch register (accessible with LCR=0)
933	*/
934	static void autoconfig_8250(struct uart_8250_port *up)
935	{
936	unsigned char scratch, status1, status2;
937
938	up->port.type = PORT_8250;
939
940	scratch = serial_in(up, UART_SCR);
941	serial_out(up, UART_SCR, value: 0xa5);
942	status1 = serial_in(up, UART_SCR);
943	serial_out(up, UART_SCR, value: 0x5a);
944	status2 = serial_in(up, UART_SCR);
945	serial_out(up, UART_SCR, value: scratch);
946
947	if (status1 == 0xa5 && status2 == 0x5a)
948	up->port.type = PORT_16450;
949	}
950
951	static int broken_efr(struct uart_8250_port *up)
952	{
953	/*
954	* Exar ST16C2550 "A2" devices incorrectly detect as
955	* having an EFR, and report an ID of 0x0201. See
956	* http://linux.derkeiler.com/Mailing-Lists/Kernel/2004-11/4812.html
957	*/
958	if (autoconfig_read_divisor_id(p: up) == 0x0201 && size_fifo(up) == 16)
959	return 1;
960
961	return 0;
962	}
963
964	/*
965	* We know that the chip has FIFOs. Does it have an EFR? The
966	* EFR is located in the same register position as the IIR and
967	* we know the top two bits of the IIR are currently set. The
968	* EFR should contain zero. Try to read the EFR.
969	*/
970	static void autoconfig_16550a(struct uart_8250_port *up)
971	{
972	unsigned char status1, status2;
973	unsigned int iersave;
974
975	/* Port locked to synchronize UART_IER access against the console. */
976	lockdep_assert_held_once(&up->port.lock);
977
978	up->port.type = PORT_16550A;
979	up->capabilities |= UART_CAP_FIFO;
980
981	if (!IS_ENABLED(CONFIG_SERIAL_8250_16550A_VARIANTS) &&
982	!(up->port.flags & UPF_FULL_PROBE))
983	return;
984
985	/*
986	* Check for presence of the EFR when DLAB is set.
987	* Only ST16C650V1 UARTs pass this test.
988	*/
989	serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
990	if (serial_in(up, UART_EFR) == 0) {
991	serial_out(up, UART_EFR, value: 0xA8);
992	if (serial_in(up, UART_EFR) != 0) {
993	DEBUG_AUTOCONF("EFRv1 ");
994	up->port.type = PORT_16650;
995	up->capabilities |= UART_CAP_EFR | UART_CAP_SLEEP;
996	} else {
997	serial_out(up, UART_LCR, value: 0);
998	serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO |
999	UART_FCR7_64BYTE);
1000	status1 = serial_in(up, UART_IIR) & UART_IIR_FIFO_ENABLED_16750;
1001	serial_out(up, UART_FCR, value: 0);
1002	serial_out(up, UART_LCR, value: 0);
1003
1004	if (status1 == UART_IIR_FIFO_ENABLED_16750)
1005	up->port.type = PORT_16550A_FSL64;
1006	else
1007	DEBUG_AUTOCONF("Motorola 8xxx DUART ");
1008	}
1009	serial_out(up, UART_EFR, value: 0);
1010	return;
1011	}
1012
1013	/*
1014	* Maybe it requires 0xbf to be written to the LCR.
1015	* (other ST16C650V2 UARTs, TI16C752A, etc)
1016	*/
1017	serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
1018	if (serial_in(up, UART_EFR) == 0 && !broken_efr(up)) {
1019	DEBUG_AUTOCONF("EFRv2 ");
1020	autoconfig_has_efr(up);
1021	return;
1022	}
1023
1024	/*
1025	* Check for a National Semiconductor SuperIO chip.
1026	* Attempt to switch to bank 2, read the value of the LOOP bit
1027	* from EXCR1. Switch back to bank 0, change it in MCR. Then
1028	* switch back to bank 2, read it from EXCR1 again and check
1029	* it's changed. If so, set baud_base in EXCR2 to 921600. -- dwmw2
1030	*/
1031	serial_out(up, UART_LCR, value: 0);
1032	status1 = serial8250_in_MCR(up);
1033	serial_out(up, UART_LCR, value: 0xE0);
1034	status2 = serial_in(up, offset: 0x02); /* EXCR1 */
1035
1036	if (!((status2 ^ status1) & UART_MCR_LOOP)) {
1037	serial_out(up, UART_LCR, value: 0);
1038	serial8250_out_MCR(up, value: status1 ^ UART_MCR_LOOP);
1039	serial_out(up, UART_LCR, value: 0xE0);
1040	status2 = serial_in(up, offset: 0x02); /* EXCR1 */
1041	serial_out(up, UART_LCR, value: 0);
1042	serial8250_out_MCR(up, value: status1);
1043
1044	if ((status2 ^ status1) & UART_MCR_LOOP) {
1045	unsigned short quot;
1046
1047	serial_out(up, UART_LCR, value: 0xE0);
1048
1049	quot = serial_dl_read(up);
1050	quot <<= 3;
1051
1052	if (ns16550a_goto_highspeed(up))
1053	serial_dl_write(up, value: quot);
1054
1055	serial_out(up, UART_LCR, value: 0);
1056
1057	up->port.uartclk = 921600*16;
1058	up->port.type = PORT_NS16550A;
1059	up->capabilities |= UART_NATSEMI;
1060	return;
1061	}
1062	}
1063
1064	/*
1065	* No EFR. Try to detect a TI16750, which only sets bit 5 of
1066	* the IIR when 64 byte FIFO mode is enabled when DLAB is set.
1067	* Try setting it with and without DLAB set. Cheap clones
1068	* set bit 5 without DLAB set.
1069	*/
1070	serial_out(up, UART_LCR, value: 0);
1071	serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO | UART_FCR7_64BYTE);
1072	status1 = serial_in(up, UART_IIR) & UART_IIR_FIFO_ENABLED_16750;
1073	serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO);
1074
1075	serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
1076	serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO | UART_FCR7_64BYTE);
1077	status2 = serial_in(up, UART_IIR) & UART_IIR_FIFO_ENABLED_16750;
1078	serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO);
1079
1080	serial_out(up, UART_LCR, value: 0);
1081
1082	DEBUG_AUTOCONF("iir1=%d iir2=%d ", status1, status2);
1083
1084	if (status1 == UART_IIR_FIFO_ENABLED_16550A &&
1085	status2 == UART_IIR_FIFO_ENABLED_16750) {
1086	up->port.type = PORT_16750;
1087	up->capabilities |= UART_CAP_AFE | UART_CAP_SLEEP;
1088	return;
1089	}
1090
1091	/*
1092	* Try writing and reading the UART_IER_UUE bit (b6).
1093	* If it works, this is probably one of the Xscale platform's
1094	* internal UARTs.
1095	* We're going to explicitly set the UUE bit to 0 before
1096	* trying to write and read a 1 just to make sure it's not
1097	* already a 1 and maybe locked there before we even start.
1098	*/
1099	iersave = serial_in(up, UART_IER);
1100	serial_out(up, UART_IER, value: iersave & ~UART_IER_UUE);
1101	if (!(serial_in(up, UART_IER) & UART_IER_UUE)) {
1102	/*
1103	* OK it's in a known zero state, try writing and reading
1104	* without disturbing the current state of the other bits.
1105	*/
1106	serial_out(up, UART_IER, value: iersave | UART_IER_UUE);
1107	if (serial_in(up, UART_IER) & UART_IER_UUE) {
1108	/*
1109	* It's an Xscale.
1110	* We'll leave the UART_IER_UUE bit set to 1 (enabled).
1111	*/
1112	DEBUG_AUTOCONF("Xscale ");
1113	up->port.type = PORT_XSCALE;
1114	up->capabilities |= UART_CAP_UUE | UART_CAP_RTOIE;
1115	return;
1116	}
1117	} else {
1118	/*
1119	* If we got here we couldn't force the IER_UUE bit to 0.
1120	* Log it and continue.
1121	*/
1122	DEBUG_AUTOCONF("Couldn't force IER_UUE to 0 ");
1123	}
1124	serial_out(up, UART_IER, value: iersave);
1125
1126	/*
1127	* We distinguish between 16550A and U6 16550A by counting
1128	* how many bytes are in the FIFO.
1129	*/
1130	if (up->port.type == PORT_16550A && size_fifo(up) == 64) {
1131	up->port.type = PORT_U6_16550A;
1132	up->capabilities |= UART_CAP_AFE;
1133	}
1134	}
1135
1136	/*
1137	* This routine is called by rs_init() to initialize a specific serial
1138	* port. It determines what type of UART chip this serial port is
1139	* using: 8250, 16450, 16550, 16550A. The important question is
1140	* whether or not this UART is a 16550A or not, since this will
1141	* determine whether or not we can use its FIFO features or not.
1142	*/
1143	static void autoconfig(struct uart_8250_port *up)
1144	{
1145	unsigned char status1, scratch, scratch2, scratch3;
1146	unsigned char save_lcr, save_mcr;
1147	struct uart_port *port = &up->port;
1148	unsigned long flags;
1149	unsigned int old_capabilities;
1150
1151	if (!port->iobase && !port->mapbase && !port->membase)
1152	return;
1153
1154	DEBUG_AUTOCONF("%s: autoconf (0x%04lx, 0x%p): ",
1155	port->name, port->iobase, port->membase);
1156
1157	/*
1158	* We really do need global IRQs disabled here - we're going to
1159	* be frobbing the chips IRQ enable register to see if it exists.
1160	*
1161	* Synchronize UART_IER access against the console.
1162	*/
1163	uart_port_lock_irqsave(up: port, flags: &flags);
1164
1165	up->capabilities = 0;
1166	up->bugs = 0;
1167
1168	if (!(port->flags & UPF_BUGGY_UART)) {
1169	/*
1170	* Do a simple existence test first; if we fail this,
1171	* there's no point trying anything else.
1172	*
1173	* 0x80 is used as a nonsense port to prevent against
1174	* false positives due to ISA bus float. The
1175	* assumption is that 0x80 is a non-existent port;
1176	* which should be safe since include/asm/io.h also
1177	* makes this assumption.
1178	*
1179	* Note: this is safe as long as MCR bit 4 is clear
1180	* and the device is in "PC" mode.
1181	*/
1182	scratch = serial_in(up, UART_IER);
1183	serial_out(up, UART_IER, value: 0);
1184	#ifdef __i386__
1185	outb(0xff, 0x080);
1186	#endif
1187	/*
1188	* Mask out IER[7:4] bits for test as some UARTs (e.g. TL
1189	* 16C754B) allow only to modify them if an EFR bit is set.
1190	*/
1191	scratch2 = serial_in(up, UART_IER) & UART_IER_ALL_INTR;
1192	serial_out(up, UART_IER, UART_IER_ALL_INTR);
1193	#ifdef __i386__
1194	outb(0, 0x080);
1195	#endif
1196	scratch3 = serial_in(up, UART_IER) & UART_IER_ALL_INTR;
1197	serial_out(up, UART_IER, value: scratch);
1198	if (scratch2 != 0 || scratch3 != UART_IER_ALL_INTR) {
1199	/*
1200	* We failed; there's nothing here
1201	*/
1202	uart_port_unlock_irqrestore(up: port, flags);
1203	DEBUG_AUTOCONF("IER test failed (%02x, %02x) ",
1204	scratch2, scratch3);
1205	goto out;
1206	}
1207	}
1208
1209	save_mcr = serial8250_in_MCR(up);
1210	save_lcr = serial_in(up, UART_LCR);
1211
1212	/*
1213	* Check to see if a UART is really there. Certain broken
1214	* internal modems based on the Rockwell chipset fail this
1215	* test, because they apparently don't implement the loopback
1216	* test mode. So this test is skipped on the COM 1 through
1217	* COM 4 ports. This *should* be safe, since no board
1218	* manufacturer would be stupid enough to design a board
1219	* that conflicts with COM 1-4 --- we hope!
1220	*/
1221	if (!(port->flags & UPF_SKIP_TEST)) {
1222	serial8250_out_MCR(up, UART_MCR_LOOP | UART_MCR_OUT2 | UART_MCR_RTS);
1223	status1 = serial_in(up, UART_MSR) & UART_MSR_STATUS_BITS;
1224	serial8250_out_MCR(up, value: save_mcr);
1225	if (status1 != (UART_MSR_DCD | UART_MSR_CTS)) {
1226	uart_port_unlock_irqrestore(up: port, flags);
1227	DEBUG_AUTOCONF("LOOP test failed (%02x) ",
1228	status1);
1229	goto out;
1230	}
1231	}
1232
1233	/*
1234	* We're pretty sure there's a port here. Lets find out what
1235	* type of port it is. The IIR top two bits allows us to find
1236	* out if it's 8250 or 16450, 16550, 16550A or later. This
1237	* determines what we test for next.
1238	*
1239	* We also initialise the EFR (if any) to zero for later. The
1240	* EFR occupies the same register location as the FCR and IIR.
1241	*/
1242	serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
1243	serial_out(up, UART_EFR, value: 0);
1244	serial_out(up, UART_LCR, value: 0);
1245
1246	serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO);
1247
1248	switch (serial_in(up, UART_IIR) & UART_IIR_FIFO_ENABLED) {
1249	case UART_IIR_FIFO_ENABLED_8250:
1250	autoconfig_8250(up);
1251	break;
1252	case UART_IIR_FIFO_ENABLED_16550:
1253	port->type = PORT_16550;
1254	break;
1255	case UART_IIR_FIFO_ENABLED_16550A:
1256	autoconfig_16550a(up);
1257	break;
1258	default:
1259	port->type = PORT_UNKNOWN;
1260	break;
1261	}
1262
1263	#ifdef CONFIG_SERIAL_8250_RSA
1264	/*
1265	* Only probe for RSA ports if we got the region.
1266	*/
1267	if (port->type == PORT_16550A && up->probe & UART_PROBE_RSA &&
1268	__enable_rsa(up))
1269	port->type = PORT_RSA;
1270	#endif
1271
1272	serial_out(up, UART_LCR, value: save_lcr);
1273
1274	port->fifosize = uart_config[up->port.type].fifo_size;
1275	old_capabilities = up->capabilities;
1276	up->capabilities = uart_config[port->type].flags;
1277	up->tx_loadsz = uart_config[port->type].tx_loadsz;
1278
1279	if (port->type == PORT_UNKNOWN)
1280	goto out_unlock;
1281
1282	/*
1283	* Reset the UART.
1284	*/
1285	#ifdef CONFIG_SERIAL_8250_RSA
1286	if (port->type == PORT_RSA)
1287	serial_out(up, UART_RSA_FRR, value: 0);
1288	#endif
1289	serial8250_out_MCR(up, value: save_mcr);
1290	serial8250_clear_fifos(p: up);
1291	serial_in(up, UART_RX);
1292	serial8250_clear_IER(up);
1293
1294	out_unlock:
1295	uart_port_unlock_irqrestore(up: port, flags);
1296
1297	/*
1298	* Check if the device is a Fintek F81216A
1299	*/
1300	if (port->type == PORT_16550A && port->iotype == UPIO_PORT)
1301	fintek_8250_probe(uart: up);
1302
1303	if (up->capabilities != old_capabilities) {
1304	dev_warn(port->dev, "detected caps %08x should be %08x\n",
1305	old_capabilities, up->capabilities);
1306	}
1307	out:
1308	DEBUG_AUTOCONF("iir=%d ", scratch);
1309	DEBUG_AUTOCONF("type=%s\n", uart_config[port->type].name);
1310	}
1311
1312	static void autoconfig_irq(struct uart_8250_port *up)
1313	{
1314	struct uart_port *port = &up->port;
1315	unsigned char save_mcr, save_ier;
1316	unsigned char save_ICP = 0;
1317	unsigned int ICP = 0;
1318	unsigned long irqs;
1319	int irq;
1320
1321	if (port->flags & UPF_FOURPORT) {
1322	ICP = (port->iobase & 0xfe0) | 0x1f;
1323	save_ICP = inb_p(port: ICP);
1324	outb_p(value: 0x80, port: ICP);
1325	inb_p(port: ICP);
1326	}
1327
1328	/* forget possible initially masked and pending IRQ */
1329	probe_irq_off(probe_irq_on());
1330	save_mcr = serial8250_in_MCR(up);
1331	/* Synchronize UART_IER access against the console. */
1332	uart_port_lock_irq(up: port);
1333	save_ier = serial_in(up, UART_IER);
1334	uart_port_unlock_irq(up: port);
1335	serial8250_out_MCR(up, UART_MCR_OUT1 | UART_MCR_OUT2);
1336
1337	irqs = probe_irq_on();
1338	serial8250_out_MCR(up, value: 0);
1339	udelay(10);
1340	if (port->flags & UPF_FOURPORT) {
1341	serial8250_out_MCR(up, UART_MCR_DTR | UART_MCR_RTS);
1342	} else {
1343	serial8250_out_MCR(up,
1344	UART_MCR_DTR | UART_MCR_RTS | UART_MCR_OUT2);
1345	}
1346	/* Synchronize UART_IER access against the console. */
1347	uart_port_lock_irq(up: port);
1348	serial_out(up, UART_IER, UART_IER_ALL_INTR);
1349	uart_port_unlock_irq(up: port);
1350	serial_in(up, UART_LSR);
1351	serial_in(up, UART_RX);
1352	serial_in(up, UART_IIR);
1353	serial_in(up, UART_MSR);
1354	serial_out(up, UART_TX, value: 0xFF);
1355	udelay(20);
1356	irq = probe_irq_off(irqs);
1357
1358	serial8250_out_MCR(up, value: save_mcr);
1359	/* Synchronize UART_IER access against the console. */
1360	uart_port_lock_irq(up: port);
1361	serial_out(up, UART_IER, value: save_ier);
1362	uart_port_unlock_irq(up: port);
1363
1364	if (port->flags & UPF_FOURPORT)
1365	outb_p(value: save_ICP, port: ICP);
1366
1367	port->irq = (irq > 0) ? irq : 0;
1368	}
1369
1370	static void serial8250_stop_rx(struct uart_port *port)
1371	{
1372	struct uart_8250_port *up = up_to_u8250p(up: port);
1373
1374	/* Port locked to synchronize UART_IER access against the console. */
1375	lockdep_assert_held_once(&port->lock);
1376
1377	serial8250_rpm_get(up);
1378
1379	up->ier &= ~(UART_IER_RLSI | UART_IER_RDI);
1380	up->port.read_status_mask &= ~UART_LSR_DR;
1381	serial_port_out(up: port, UART_IER, value: up->ier);
1382
1383	serial8250_rpm_put(up);
1384	}
1385
1386	/**
1387	* serial8250_em485_stop_tx() - generic ->rs485_stop_tx() callback
1388	* @p: uart 8250 port
1389	*
1390	* Generic callback usable by 8250 uart drivers to stop rs485 transmission.
1391	*/
1392	void serial8250_em485_stop_tx(struct uart_8250_port *p)
1393	{
1394	unsigned char mcr = serial8250_in_MCR(up: p);
1395
1396	/* Port locked to synchronize UART_IER access against the console. */
1397	lockdep_assert_held_once(&p->port.lock);
1398
1399	if (p->port.rs485.flags & SER_RS485_RTS_AFTER_SEND)
1400	mcr |= UART_MCR_RTS;
1401	else
1402	mcr &= ~UART_MCR_RTS;
1403	serial8250_out_MCR(up: p, value: mcr);
1404
1405	/*
1406	* Empty the RX FIFO, we are not interested in anything
1407	* received during the half-duplex transmission.
1408	* Enable previously disabled RX interrupts.
1409	*/
1410	if (!(p->port.rs485.flags & SER_RS485_RX_DURING_TX)) {
1411	serial8250_clear_and_reinit_fifos(p);
1412
1413	p->ier |= UART_IER_RLSI | UART_IER_RDI;
1414	serial_port_out(up: &p->port, UART_IER, value: p->ier);
1415	}
1416	}
1417	EXPORT_SYMBOL_GPL(serial8250_em485_stop_tx);
1418
1419	static enum hrtimer_restart serial8250_em485_handle_stop_tx(struct hrtimer *t)
1420	{
1421	struct uart_8250_em485 *em485 = container_of(t, struct uart_8250_em485,
1422	stop_tx_timer);
1423	struct uart_8250_port *p = em485->port;
1424	unsigned long flags;
1425
1426	serial8250_rpm_get(p);
1427	uart_port_lock_irqsave(up: &p->port, flags: &flags);
1428	if (em485->active_timer == &em485->stop_tx_timer) {
1429	p->rs485_stop_tx(p);
1430	em485->active_timer = NULL;
1431	em485->tx_stopped = true;
1432	}
1433	uart_port_unlock_irqrestore(up: &p->port, flags);
1434	serial8250_rpm_put(p);
1435
1436	return HRTIMER_NORESTART;
1437	}
1438
1439	static void start_hrtimer_ms(struct hrtimer *hrt, unsigned long msec)
1440	{
1441	hrtimer_start(timer: hrt, tim: ms_to_ktime(ms: msec), mode: HRTIMER_MODE_REL);
1442	}
1443
1444	static void __stop_tx_rs485(struct uart_8250_port *p, u64 stop_delay)
1445	{
1446	struct uart_8250_em485 *em485 = p->em485;
1447
1448	/* Port locked to synchronize UART_IER access against the console. */
1449	lockdep_assert_held_once(&p->port.lock);
1450
1451	stop_delay += (u64)p->port.rs485.delay_rts_after_send * NSEC_PER_MSEC;
1452
1453	/*
1454	* rs485_stop_tx() is going to set RTS according to config
1455	* AND flush RX FIFO if required.
1456	*/
1457	if (stop_delay > 0) {
1458	em485->active_timer = &em485->stop_tx_timer;
1459	hrtimer_start(timer: &em485->stop_tx_timer, tim: ns_to_ktime(ns: stop_delay), mode: HRTIMER_MODE_REL);
1460	} else {
1461	p->rs485_stop_tx(p);
1462	em485->active_timer = NULL;
1463	em485->tx_stopped = true;
1464	}
1465	}
1466
1467	static inline void __stop_tx(struct uart_8250_port *p)
1468	{
1469	struct uart_8250_em485 *em485 = p->em485;
1470
1471	if (em485) {
1472	u16 lsr = serial_lsr_in(up: p);
1473	u64 stop_delay = 0;
1474
1475	if (!(lsr & UART_LSR_THRE))
1476	return;
1477	/*
1478	* To provide required timing and allow FIFO transfer,
1479	* __stop_tx_rs485() must be called only when both FIFO and
1480	* shift register are empty. The device driver should either
1481	* enable interrupt on TEMT or set UART_CAP_NOTEMT that will
1482	* enlarge stop_tx_timer by the tx time of one frame to cover
1483	* for emptying of the shift register.
1484	*/
1485	if (!(lsr & UART_LSR_TEMT)) {
1486	if (!(p->capabilities & UART_CAP_NOTEMT))
1487	return;
1488	/*
1489	* RTS might get deasserted too early with the normal
1490	* frame timing formula. It seems to suggest THRE might
1491	* get asserted already during tx of the stop bit
1492	* rather than after it is fully sent.
1493	* Roughly estimate 1 extra bit here with / 7.
1494	*/
1495	stop_delay = p->port.frame_time + DIV_ROUND_UP(p->port.frame_time, 7);
1496	}
1497
1498	__stop_tx_rs485(p, stop_delay);
1499	}
1500
1501	if (serial8250_clear_THRI(up: p))
1502	serial8250_rpm_put_tx(p);
1503	}
1504
1505	static void serial8250_stop_tx(struct uart_port *port)
1506	{
1507	struct uart_8250_port *up = up_to_u8250p(up: port);
1508
1509	serial8250_rpm_get(up);
1510	__stop_tx(p: up);
1511
1512	/*
1513	* We really want to stop the transmitter from sending.
1514	*/
1515	if (port->type == PORT_16C950) {
1516	up->acr |= UART_ACR_TXDIS;
1517	serial_icr_write(up, UART_ACR, value: up->acr);
1518	}
1519	serial8250_rpm_put(up);
1520	}
1521
1522	static inline void __start_tx(struct uart_port *port)
1523	{
1524	struct uart_8250_port *up = up_to_u8250p(up: port);
1525
1526	if (up->dma && !up->dma->tx_dma(up))
1527	return;
1528
1529	if (serial8250_set_THRI(up)) {
1530	if (up->bugs & UART_BUG_TXEN) {
1531	u16 lsr = serial_lsr_in(up);
1532
1533	if (lsr & UART_LSR_THRE)
1534	serial8250_tx_chars(up);
1535	}
1536	}
1537
1538	/*
1539	* Re-enable the transmitter if we disabled it.
1540	*/
1541	if (port->type == PORT_16C950 && up->acr & UART_ACR_TXDIS) {
1542	up->acr &= ~UART_ACR_TXDIS;
1543	serial_icr_write(up, UART_ACR, value: up->acr);
1544	}
1545	}
1546
1547	/**
1548	* serial8250_em485_start_tx() - generic ->rs485_start_tx() callback
1549	* @up: uart 8250 port
1550	*
1551	* Generic callback usable by 8250 uart drivers to start rs485 transmission.
1552	* Assumes that setting the RTS bit in the MCR register means RTS is high.
1553	* (Some chips use inverse semantics.) Further assumes that reception is
1554	* stoppable by disabling the UART_IER_RDI interrupt. (Some chips set the
1555	* UART_LSR_DR bit even when UART_IER_RDI is disabled, foiling this approach.)
1556	*/
1557	void serial8250_em485_start_tx(struct uart_8250_port *up)
1558	{
1559	unsigned char mcr = serial8250_in_MCR(up);
1560
1561	if (!(up->port.rs485.flags & SER_RS485_RX_DURING_TX))
1562	serial8250_stop_rx(port: &up->port);
1563
1564	if (up->port.rs485.flags & SER_RS485_RTS_ON_SEND)
1565	mcr |= UART_MCR_RTS;
1566	else
1567	mcr &= ~UART_MCR_RTS;
1568	serial8250_out_MCR(up, value: mcr);
1569	}
1570	EXPORT_SYMBOL_GPL(serial8250_em485_start_tx);
1571
1572	/* Returns false, if start_tx_timer was setup to defer TX start */
1573	static bool start_tx_rs485(struct uart_port *port)
1574	{
1575	struct uart_8250_port *up = up_to_u8250p(up: port);
1576	struct uart_8250_em485 *em485 = up->em485;
1577
1578	/*
1579	* While serial8250_em485_handle_stop_tx() is a noop if
1580	* em485->active_timer != &em485->stop_tx_timer, it might happen that
1581	* the timer is still armed and triggers only after the current bunch of
1582	* chars is send and em485->active_timer == &em485->stop_tx_timer again.
1583	* So cancel the timer. There is still a theoretical race condition if
1584	* the timer is already running and only comes around to check for
1585	* em485->active_timer when &em485->stop_tx_timer is armed again.
1586	*/
1587	if (em485->active_timer == &em485->stop_tx_timer)
1588	hrtimer_try_to_cancel(timer: &em485->stop_tx_timer);
1589
1590	em485->active_timer = NULL;
1591
1592	if (em485->tx_stopped) {
1593	em485->tx_stopped = false;
1594
1595	up->rs485_start_tx(up);
1596
1597	if (up->port.rs485.delay_rts_before_send > 0) {
1598	em485->active_timer = &em485->start_tx_timer;
1599	start_hrtimer_ms(hrt: &em485->start_tx_timer,
1600	msec: up->port.rs485.delay_rts_before_send);
1601	return false;
1602	}
1603	}
1604
1605	return true;
1606	}
1607
1608	static enum hrtimer_restart serial8250_em485_handle_start_tx(struct hrtimer *t)
1609	{
1610	struct uart_8250_em485 *em485 = container_of(t, struct uart_8250_em485,
1611	start_tx_timer);
1612	struct uart_8250_port *p = em485->port;
1613	unsigned long flags;
1614
1615	uart_port_lock_irqsave(up: &p->port, flags: &flags);
1616	if (em485->active_timer == &em485->start_tx_timer) {
1617	__start_tx(port: &p->port);
1618	em485->active_timer = NULL;
1619	}
1620	uart_port_unlock_irqrestore(up: &p->port, flags);
1621
1622	return HRTIMER_NORESTART;
1623	}
1624
1625	static void serial8250_start_tx(struct uart_port *port)
1626	{
1627	struct uart_8250_port *up = up_to_u8250p(up: port);
1628	struct uart_8250_em485 *em485 = up->em485;
1629
1630	/* Port locked to synchronize UART_IER access against the console. */
1631	lockdep_assert_held_once(&port->lock);
1632
1633	if (!port->x_char && uart_circ_empty(&port->state->xmit))
1634	return;
1635
1636	serial8250_rpm_get_tx(up);
1637
1638	if (em485) {
1639	if ((em485->active_timer == &em485->start_tx_timer) ||
1640	!start_tx_rs485(port))
1641	return;
1642	}
1643	__start_tx(port);
1644	}
1645
1646	static void serial8250_throttle(struct uart_port *port)
1647	{
1648	port->throttle(port);
1649	}
1650
1651	static void serial8250_unthrottle(struct uart_port *port)
1652	{
1653	port->unthrottle(port);
1654	}
1655
1656	static void serial8250_disable_ms(struct uart_port *port)
1657	{
1658	struct uart_8250_port *up = up_to_u8250p(up: port);
1659
1660	/* Port locked to synchronize UART_IER access against the console. */
1661	lockdep_assert_held_once(&port->lock);
1662
1663	/* no MSR capabilities */
1664	if (up->bugs & UART_BUG_NOMSR)
1665	return;
1666
1667	mctrl_gpio_disable_ms(gpios: up->gpios);
1668
1669	up->ier &= ~UART_IER_MSI;
1670	serial_port_out(up: port, UART_IER, value: up->ier);
1671	}
1672
1673	static void serial8250_enable_ms(struct uart_port *port)
1674	{
1675	struct uart_8250_port *up = up_to_u8250p(up: port);
1676
1677	/* Port locked to synchronize UART_IER access against the console. */
1678	lockdep_assert_held_once(&port->lock);
1679
1680	/* no MSR capabilities */
1681	if (up->bugs & UART_BUG_NOMSR)
1682	return;
1683
1684	mctrl_gpio_enable_ms(gpios: up->gpios);
1685
1686	up->ier |= UART_IER_MSI;
1687
1688	serial8250_rpm_get(up);
1689	serial_port_out(up: port, UART_IER, value: up->ier);
1690	serial8250_rpm_put(up);
1691	}
1692
1693	void serial8250_read_char(struct uart_8250_port *up, u16 lsr)
1694	{
1695	struct uart_port *port = &up->port;
1696	u8 ch, flag = TTY_NORMAL;
1697
1698	if (likely(lsr & UART_LSR_DR))
1699	ch = serial_in(up, UART_RX);
1700	else
1701	/*
1702	* Intel 82571 has a Serial Over Lan device that will
1703	* set UART_LSR_BI without setting UART_LSR_DR when
1704	* it receives a break. To avoid reading from the
1705	* receive buffer without UART_LSR_DR bit set, we
1706	* just force the read character to be 0
1707	*/
1708	ch = 0;
1709
1710	port->icount.rx++;
1711
1712	lsr |= up->lsr_saved_flags;
1713	up->lsr_saved_flags = 0;
1714
1715	if (unlikely(lsr & UART_LSR_BRK_ERROR_BITS)) {
1716	if (lsr & UART_LSR_BI) {
1717	lsr &= ~(UART_LSR_FE | UART_LSR_PE);
1718	port->icount.brk++;
1719	/*
1720	* We do the SysRQ and SAK checking
1721	* here because otherwise the break
1722	* may get masked by ignore_status_mask
1723	* or read_status_mask.
1724	*/
1725	if (uart_handle_break(port))
1726	return;
1727	} else if (lsr & UART_LSR_PE)
1728	port->icount.parity++;
1729	else if (lsr & UART_LSR_FE)
1730	port->icount.frame++;
1731	if (lsr & UART_LSR_OE)
1732	port->icount.overrun++;
1733
1734	/*
1735	* Mask off conditions which should be ignored.
1736	*/
1737	lsr &= port->read_status_mask;
1738
1739	if (lsr & UART_LSR_BI) {
1740	dev_dbg(port->dev, "handling break\n");
1741	flag = TTY_BREAK;
1742	} else if (lsr & UART_LSR_PE)
1743	flag = TTY_PARITY;
1744	else if (lsr & UART_LSR_FE)
1745	flag = TTY_FRAME;
1746	}
1747	if (uart_prepare_sysrq_char(port, ch))
1748	return;
1749
1750	uart_insert_char(port, status: lsr, UART_LSR_OE, ch, flag);
1751	}
1752	EXPORT_SYMBOL_GPL(serial8250_read_char);
1753
1754	/*
1755	* serial8250_rx_chars - Read characters. The first LSR value must be passed in.
1756	*
1757	* Returns LSR bits. The caller should rely only on non-Rx related LSR bits
1758	* (such as THRE) because the LSR value might come from an already consumed
1759	* character.
1760	*/
1761	u16 serial8250_rx_chars(struct uart_8250_port *up, u16 lsr)
1762	{
1763	struct uart_port *port = &up->port;
1764	int max_count = 256;
1765
1766	do {
1767	serial8250_read_char(up, lsr);
1768	if (--max_count == 0)
1769	break;
1770	lsr = serial_in(up, UART_LSR);
1771	} while (lsr & (UART_LSR_DR | UART_LSR_BI));
1772
1773	tty_flip_buffer_push(port: &port->state->port);
1774	return lsr;
1775	}
1776	EXPORT_SYMBOL_GPL(serial8250_rx_chars);
1777
1778	void serial8250_tx_chars(struct uart_8250_port *up)
1779	{
1780	struct uart_port *port = &up->port;
1781	struct circ_buf *xmit = &port->state->xmit;
1782	int count;
1783
1784	if (port->x_char) {
1785	uart_xchar_out(uport: port, UART_TX);
1786	return;
1787	}
1788	if (uart_tx_stopped(port)) {
1789	serial8250_stop_tx(port);
1790	return;
1791	}
1792	if (uart_circ_empty(xmit)) {
1793	__stop_tx(p: up);
1794	return;
1795	}
1796
1797	count = up->tx_loadsz;
1798	do {
1799	serial_out(up, UART_TX, value: xmit->buf[xmit->tail]);
1800	if (up->bugs & UART_BUG_TXRACE) {
1801	/*
1802	* The Aspeed BMC virtual UARTs have a bug where data
1803	* may get stuck in the BMC's Tx FIFO from bursts of
1804	* writes on the APB interface.
1805	*
1806	* Delay back-to-back writes by a read cycle to avoid
1807	* stalling the VUART. Read a register that won't have
1808	* side-effects and discard the result.
1809	*/
1810	serial_in(up, UART_SCR);
1811	}
1812	uart_xmit_advance(up: port, chars: 1);
1813	if (uart_circ_empty(xmit))
1814	break;
1815	if ((up->capabilities & UART_CAP_HFIFO) &&
1816	!uart_lsr_tx_empty(lsr: serial_in(up, UART_LSR)))
1817	break;
1818	/* The BCM2835 MINI UART THRE bit is really a not-full bit. */
1819	if ((up->capabilities & UART_CAP_MINI) &&
1820	!(serial_in(up, UART_LSR) & UART_LSR_THRE))
1821	break;
1822	} while (--count > 0);
1823
1824	if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1825	uart_write_wakeup(port);
1826
1827	/*
1828	* With RPM enabled, we have to wait until the FIFO is empty before the
1829	* HW can go idle. So we get here once again with empty FIFO and disable
1830	* the interrupt and RPM in __stop_tx()
1831	*/
1832	if (uart_circ_empty(xmit) && !(up->capabilities & UART_CAP_RPM))
1833	__stop_tx(p: up);
1834	}
1835	EXPORT_SYMBOL_GPL(serial8250_tx_chars);
1836
1837	/* Caller holds uart port lock */
1838	unsigned int serial8250_modem_status(struct uart_8250_port *up)
1839	{
1840	struct uart_port *port = &up->port;
1841	unsigned int status = serial_in(up, UART_MSR);
1842
1843	status |= up->msr_saved_flags;
1844	up->msr_saved_flags = 0;
1845	if (status & UART_MSR_ANY_DELTA && up->ier & UART_IER_MSI &&
1846	port->state != NULL) {
1847	if (status & UART_MSR_TERI)
1848	port->icount.rng++;
1849	if (status & UART_MSR_DDSR)
1850	port->icount.dsr++;
1851	if (status & UART_MSR_DDCD)
1852	uart_handle_dcd_change(uport: port, active: status & UART_MSR_DCD);
1853	if (status & UART_MSR_DCTS)
1854	uart_handle_cts_change(uport: port, active: status & UART_MSR_CTS);
1855
1856	wake_up_interruptible(&port->state->port.delta_msr_wait);
1857	}
1858
1859	return status;
1860	}
1861	EXPORT_SYMBOL_GPL(serial8250_modem_status);
1862
1863	static bool handle_rx_dma(struct uart_8250_port *up, unsigned int iir)
1864	{
1865	switch (iir & 0x3f) {
1866	case UART_IIR_THRI:
1867	/*
1868	* Postpone DMA or not decision to IIR_RDI or IIR_RX_TIMEOUT
1869	* because it's impossible to do an informed decision about
1870	* that with IIR_THRI.
1871	*
1872	* This also fixes one known DMA Rx corruption issue where
1873	* DR is asserted but DMA Rx only gets a corrupted zero byte
1874	* (too early DR?).
1875	*/
1876	return false;
1877	case UART_IIR_RDI:
1878	if (!up->dma->rx_running)
1879	break;
1880	fallthrough;
1881	case UART_IIR_RLSI:
1882	case UART_IIR_RX_TIMEOUT:
1883	serial8250_rx_dma_flush(up);
1884	return true;
1885	}
1886	return up->dma->rx_dma(up);
1887	}
1888
1889	/*
1890	* This handles the interrupt from one port.
1891	*/
1892	int serial8250_handle_irq(struct uart_port *port, unsigned int iir)
1893	{
1894	struct uart_8250_port *up = up_to_u8250p(up: port);
1895	struct tty_port *tport = &port->state->port;
1896	bool skip_rx = false;
1897	unsigned long flags;
1898	u16 status;
1899
1900	if (iir & UART_IIR_NO_INT)
1901	return 0;
1902
1903	uart_port_lock_irqsave(up: port, flags: &flags);
1904
1905	status = serial_lsr_in(up);
1906
1907	/*
1908	* If port is stopped and there are no error conditions in the
1909	* FIFO, then don't drain the FIFO, as this may lead to TTY buffer
1910	* overflow. Not servicing, RX FIFO would trigger auto HW flow
1911	* control when FIFO occupancy reaches preset threshold, thus
1912	* halting RX. This only works when auto HW flow control is
1913	* available.
1914	*/
1915	if (!(status & (UART_LSR_FIFOE | UART_LSR_BRK_ERROR_BITS)) &&
1916	(port->status & (UPSTAT_AUTOCTS | UPSTAT_AUTORTS)) &&
1917	!(port->read_status_mask & UART_LSR_DR))
1918	skip_rx = true;
1919
1920	if (status & (UART_LSR_DR | UART_LSR_BI) && !skip_rx) {
1921	struct irq_data *d;
1922
1923	d = irq_get_irq_data(irq: port->irq);
1924	if (d && irqd_is_wakeup_set(d))
1925	pm_wakeup_event(dev: tport->tty->dev, msec: 0);
1926	if (!up->dma || handle_rx_dma(up, iir))
1927	status = serial8250_rx_chars(up, status);
1928	}
1929	serial8250_modem_status(up);
1930	if ((status & UART_LSR_THRE) && (up->ier & UART_IER_THRI)) {
1931	if (!up->dma || up->dma->tx_err)
1932	serial8250_tx_chars(up);
1933	else if (!up->dma->tx_running)
1934	__stop_tx(p: up);
1935	}
1936
1937	uart_unlock_and_check_sysrq_irqrestore(port, flags);
1938
1939	return 1;
1940	}
1941	EXPORT_SYMBOL_GPL(serial8250_handle_irq);
1942
1943	static int serial8250_default_handle_irq(struct uart_port *port)
1944	{
1945	struct uart_8250_port *up = up_to_u8250p(up: port);
1946	unsigned int iir;
1947	int ret;
1948
1949	serial8250_rpm_get(up);
1950
1951	iir = serial_port_in(up: port, UART_IIR);
1952	ret = serial8250_handle_irq(port, iir);
1953
1954	serial8250_rpm_put(up);
1955	return ret;
1956	}
1957
1958	/*
1959	* Newer 16550 compatible parts such as the SC16C650 & Altera 16550 Soft IP
1960	* have a programmable TX threshold that triggers the THRE interrupt in
1961	* the IIR register. In this case, the THRE interrupt indicates the FIFO
1962	* has space available. Load it up with tx_loadsz bytes.
1963	*/
1964	static int serial8250_tx_threshold_handle_irq(struct uart_port *port)
1965	{
1966	unsigned long flags;
1967	unsigned int iir = serial_port_in(up: port, UART_IIR);
1968
1969	/* TX Threshold IRQ triggered so load up FIFO */
1970	if ((iir & UART_IIR_ID) == UART_IIR_THRI) {
1971	struct uart_8250_port *up = up_to_u8250p(up: port);
1972
1973	uart_port_lock_irqsave(up: port, flags: &flags);
1974	serial8250_tx_chars(up);
1975	uart_port_unlock_irqrestore(up: port, flags);
1976	}
1977
1978	iir = serial_port_in(up: port, UART_IIR);
1979	return serial8250_handle_irq(port, iir);
1980	}
1981
1982	static unsigned int serial8250_tx_empty(struct uart_port *port)
1983	{
1984	struct uart_8250_port *up = up_to_u8250p(up: port);
1985	unsigned int result = 0;
1986	unsigned long flags;
1987
1988	serial8250_rpm_get(up);
1989
1990	uart_port_lock_irqsave(up: port, flags: &flags);
1991	if (!serial8250_tx_dma_running(p: up) && uart_lsr_tx_empty(lsr: serial_lsr_in(up)))
1992	result = TIOCSER_TEMT;
1993	uart_port_unlock_irqrestore(up: port, flags);
1994
1995	serial8250_rpm_put(up);
1996
1997	return result;
1998	}
1999
2000	unsigned int serial8250_do_get_mctrl(struct uart_port *port)
2001	{
2002	struct uart_8250_port *up = up_to_u8250p(up: port);
2003	unsigned int status;
2004	unsigned int val;
2005
2006	serial8250_rpm_get(up);
2007	status = serial8250_modem_status(up);
2008	serial8250_rpm_put(up);
2009
2010	val = serial8250_MSR_to_TIOCM(msr: status);
2011	if (up->gpios)
2012	return mctrl_gpio_get(gpios: up->gpios, mctrl: &val);
2013
2014	return val;
2015	}
2016	EXPORT_SYMBOL_GPL(serial8250_do_get_mctrl);
2017
2018	static unsigned int serial8250_get_mctrl(struct uart_port *port)
2019	{
2020	if (port->get_mctrl)
2021	return port->get_mctrl(port);
2022	return serial8250_do_get_mctrl(port);
2023	}
2024
2025	void serial8250_do_set_mctrl(struct uart_port *port, unsigned int mctrl)
2026	{
2027	struct uart_8250_port *up = up_to_u8250p(up: port);
2028	unsigned char mcr;
2029
2030	mcr = serial8250_TIOCM_to_MCR(tiocm: mctrl);
2031
2032	mcr |= up->mcr;
2033
2034	serial8250_out_MCR(up, value: mcr);
2035	}
2036	EXPORT_SYMBOL_GPL(serial8250_do_set_mctrl);
2037
2038	static void serial8250_set_mctrl(struct uart_port *port, unsigned int mctrl)
2039	{
2040	if (port->rs485.flags & SER_RS485_ENABLED)
2041	return;
2042
2043	if (port->set_mctrl)
2044	port->set_mctrl(port, mctrl);
2045	else
2046	serial8250_do_set_mctrl(port, mctrl);
2047	}
2048
2049	static void serial8250_break_ctl(struct uart_port *port, int break_state)
2050	{
2051	struct uart_8250_port *up = up_to_u8250p(up: port);
2052	unsigned long flags;
2053
2054	serial8250_rpm_get(up);
2055	uart_port_lock_irqsave(up: port, flags: &flags);
2056	if (break_state == -1)
2057	up->lcr |= UART_LCR_SBC;
2058	else
2059	up->lcr &= ~UART_LCR_SBC;
2060	serial_port_out(up: port, UART_LCR, value: up->lcr);
2061	uart_port_unlock_irqrestore(up: port, flags);
2062	serial8250_rpm_put(up);
2063	}
2064
2065	static void wait_for_lsr(struct uart_8250_port *up, int bits)
2066	{
2067	unsigned int status, tmout = 10000;
2068
2069	/* Wait up to 10ms for the character(s) to be sent. */
2070	for (;;) {
2071	status = serial_lsr_in(up);
2072
2073	if ((status & bits) == bits)
2074	break;
2075	if (--tmout == 0)
2076	break;
2077	udelay(1);
2078	touch_nmi_watchdog();
2079	}
2080	}
2081
2082	/*
2083	* Wait for transmitter & holding register to empty
2084	*/
2085	static void wait_for_xmitr(struct uart_8250_port *up, int bits)
2086	{
2087	unsigned int tmout;
2088
2089	wait_for_lsr(up, bits);
2090
2091	/* Wait up to 1s for flow control if necessary */
2092	if (up->port.flags & UPF_CONS_FLOW) {
2093	for (tmout = 1000000; tmout; tmout--) {
2094	unsigned int msr = serial_in(up, UART_MSR);
2095	up->msr_saved_flags |= msr & MSR_SAVE_FLAGS;
2096	if (msr & UART_MSR_CTS)
2097	break;
2098	udelay(1);
2099	touch_nmi_watchdog();
2100	}
2101	}
2102	}
2103
2104	#ifdef CONFIG_CONSOLE_POLL
2105	/*
2106	* Console polling routines for writing and reading from the uart while
2107	* in an interrupt or debug context.
2108	*/
2109
2110	static int serial8250_get_poll_char(struct uart_port *port)
2111	{
2112	struct uart_8250_port *up = up_to_u8250p(up: port);
2113	int status;
2114	u16 lsr;
2115
2116	serial8250_rpm_get(up);
2117
2118	lsr = serial_port_in(up: port, UART_LSR);
2119
2120	if (!(lsr & UART_LSR_DR)) {
2121	status = NO_POLL_CHAR;
2122	goto out;
2123	}
2124
2125	status = serial_port_in(up: port, UART_RX);
2126	out:
2127	serial8250_rpm_put(up);
2128	return status;
2129	}
2130
2131
2132	static void serial8250_put_poll_char(struct uart_port *port,
2133	unsigned char c)
2134	{
2135	unsigned int ier;
2136	struct uart_8250_port *up = up_to_u8250p(up: port);
2137
2138	/*
2139	* Normally the port is locked to synchronize UART_IER access
2140	* against the console. However, this function is only used by
2141	* KDB/KGDB, where it may not be possible to acquire the port
2142	* lock because all other CPUs are quiesced. The quiescence
2143	* should allow safe lockless usage here.
2144	*/
2145
2146	serial8250_rpm_get(up);
2147	/*
2148	* First save the IER then disable the interrupts
2149	*/
2150	ier = serial_port_in(up: port, UART_IER);
2151	serial8250_clear_IER(up);
2152
2153	wait_for_xmitr(up, UART_LSR_BOTH_EMPTY);
2154	/*
2155	* Send the character out.
2156	*/
2157	serial_port_out(up: port, UART_TX, value: c);
2158
2159	/*
2160	* Finally, wait for transmitter to become empty
2161	* and restore the IER
2162	*/
2163	wait_for_xmitr(up, UART_LSR_BOTH_EMPTY);
2164	serial_port_out(up: port, UART_IER, value: ier);
2165	serial8250_rpm_put(up);
2166	}
2167
2168	#endif /* CONFIG_CONSOLE_POLL */
2169
2170	int serial8250_do_startup(struct uart_port *port)
2171	{
2172	struct uart_8250_port *up = up_to_u8250p(up: port);
2173	unsigned long flags;
2174	unsigned char iir;
2175	int retval;
2176	u16 lsr;
2177
2178	if (!port->fifosize)
2179	port->fifosize = uart_config[port->type].fifo_size;
2180	if (!up->tx_loadsz)
2181	up->tx_loadsz = uart_config[port->type].tx_loadsz;
2182	if (!up->capabilities)
2183	up->capabilities = uart_config[port->type].flags;
2184	up->mcr = 0;
2185
2186	if (port->iotype != up->cur_iotype)
2187	set_io_from_upio(port);
2188
2189	serial8250_rpm_get(up);
2190	if (port->type == PORT_16C950) {
2191	/*
2192	* Wake up and initialize UART
2193	*
2194	* Synchronize UART_IER access against the console.
2195	*/
2196	uart_port_lock_irqsave(up: port, flags: &flags);
2197	up->acr = 0;
2198	serial_port_out(up: port, UART_LCR, UART_LCR_CONF_MODE_B);
2199	serial_port_out(up: port, UART_EFR, UART_EFR_ECB);
2200	serial_port_out(up: port, UART_IER, value: 0);
2201	serial_port_out(up: port, UART_LCR, value: 0);
2202	serial_icr_write(up, UART_CSR, value: 0); /* Reset the UART */
2203	serial_port_out(up: port, UART_LCR, UART_LCR_CONF_MODE_B);
2204	serial_port_out(up: port, UART_EFR, UART_EFR_ECB);
2205	serial_port_out(up: port, UART_LCR, value: 0);
2206	uart_port_unlock_irqrestore(up: port, flags);
2207	}
2208
2209	if (port->type == PORT_DA830) {
2210	/*
2211	* Reset the port
2212	*
2213	* Synchronize UART_IER access against the console.
2214	*/
2215	uart_port_lock_irqsave(up: port, flags: &flags);
2216	serial_port_out(up: port, UART_IER, value: 0);
2217	serial_port_out(up: port, UART_DA830_PWREMU_MGMT, value: 0);
2218	uart_port_unlock_irqrestore(up: port, flags);
2219	mdelay(10);
2220
2221	/* Enable Tx, Rx and free run mode */
2222	serial_port_out(up: port, UART_DA830_PWREMU_MGMT,
2223	UART_DA830_PWREMU_MGMT_UTRST |
2224	UART_DA830_PWREMU_MGMT_URRST |
2225	UART_DA830_PWREMU_MGMT_FREE);
2226	}
2227
2228	#ifdef CONFIG_SERIAL_8250_RSA
2229	/*
2230	* If this is an RSA port, see if we can kick it up to the
2231	* higher speed clock.
2232	*/
2233	enable_rsa(up);
2234	#endif
2235
2236	/*
2237	* Clear the FIFO buffers and disable them.
2238	* (they will be reenabled in set_termios())
2239	*/
2240	serial8250_clear_fifos(p: up);
2241
2242	/*
2243	* Clear the interrupt registers.
2244	*/
2245	serial_port_in(up: port, UART_LSR);
2246	serial_port_in(up: port, UART_RX);
2247	serial_port_in(up: port, UART_IIR);
2248	serial_port_in(up: port, UART_MSR);
2249
2250	/*
2251	* At this point, there's no way the LSR could still be 0xff;
2252	* if it is, then bail out, because there's likely no UART
2253	* here.
2254	*/
2255	if (!(port->flags & UPF_BUGGY_UART) &&
2256	(serial_port_in(up: port, UART_LSR) == 0xff)) {
2257	dev_info_ratelimited(port->dev, "LSR safety check engaged!\n");
2258	retval = -ENODEV;
2259	goto out;
2260	}
2261
2262	/*
2263	* For a XR16C850, we need to set the trigger levels
2264	*/
2265	if (port->type == PORT_16850) {
2266	unsigned char fctr;
2267
2268	serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
2269
2270	fctr = serial_in(up, UART_FCTR) & ~(UART_FCTR_RX|UART_FCTR_TX);
2271	serial_port_out(up: port, UART_FCTR,
2272	value: fctr | UART_FCTR_TRGD | UART_FCTR_RX);
2273	serial_port_out(up: port, UART_TRG, UART_TRG_96);
2274	serial_port_out(up: port, UART_FCTR,
2275	value: fctr | UART_FCTR_TRGD | UART_FCTR_TX);
2276	serial_port_out(up: port, UART_TRG, UART_TRG_96);
2277
2278	serial_port_out(up: port, UART_LCR, value: 0);
2279	}
2280
2281	/*
2282	* For the Altera 16550 variants, set TX threshold trigger level.
2283	*/
2284	if (((port->type == PORT_ALTR_16550_F32) ||
2285	(port->type == PORT_ALTR_16550_F64) ||
2286	(port->type == PORT_ALTR_16550_F128)) && (port->fifosize > 1)) {
2287	/* Bounds checking of TX threshold (valid 0 to fifosize-2) */
2288	if ((up->tx_loadsz < 2) || (up->tx_loadsz > port->fifosize)) {
2289	dev_err(port->dev, "TX FIFO Threshold errors, skipping\n");
2290	} else {
2291	serial_port_out(up: port, UART_ALTR_AFR,
2292	UART_ALTR_EN_TXFIFO_LW);
2293	serial_port_out(up: port, UART_ALTR_TX_LOW,
2294	value: port->fifosize - up->tx_loadsz);
2295	port->handle_irq = serial8250_tx_threshold_handle_irq;
2296	}
2297	}
2298
2299	/* Check if we need to have shared IRQs */
2300	if (port->irq && (up->port.flags & UPF_SHARE_IRQ))
2301	up->port.irqflags |= IRQF_SHARED;
2302
2303	retval = up->ops->setup_irq(up);
2304	if (retval)
2305	goto out;
2306
2307	if (port->irq && !(up->port.flags & UPF_NO_THRE_TEST)) {
2308	unsigned char iir1;
2309
2310	if (port->irqflags & IRQF_SHARED)
2311	disable_irq_nosync(irq: port->irq);
2312
2313	/*
2314	* Test for UARTs that do not reassert THRE when the
2315	* transmitter is idle and the interrupt has already
2316	* been cleared. Real 16550s should always reassert
2317	* this interrupt whenever the transmitter is idle and
2318	* the interrupt is enabled. Delays are necessary to
2319	* allow register changes to become visible.
2320	*
2321	* Synchronize UART_IER access against the console.
2322	*/
2323	uart_port_lock_irqsave(up: port, flags: &flags);
2324
2325	wait_for_xmitr(up, UART_LSR_THRE);
2326	serial_port_out_sync(p: port, UART_IER, UART_IER_THRI);
2327	udelay(1); /* allow THRE to set */
2328	iir1 = serial_port_in(up: port, UART_IIR);
2329	serial_port_out(up: port, UART_IER, value: 0);
2330	serial_port_out_sync(p: port, UART_IER, UART_IER_THRI);
2331	udelay(1); /* allow a working UART time to re-assert THRE */
2332	iir = serial_port_in(up: port, UART_IIR);
2333	serial_port_out(up: port, UART_IER, value: 0);
2334
2335	uart_port_unlock_irqrestore(up: port, flags);
2336
2337	if (port->irqflags & IRQF_SHARED)
2338	enable_irq(irq: port->irq);
2339
2340	/*
2341	* If the interrupt is not reasserted, or we otherwise
2342	* don't trust the iir, setup a timer to kick the UART
2343	* on a regular basis.
2344	*/
2345	if ((!(iir1 & UART_IIR_NO_INT) && (iir & UART_IIR_NO_INT)) ||
2346	up->port.flags & UPF_BUG_THRE) {
2347	up->bugs |= UART_BUG_THRE;
2348	}
2349	}
2350
2351	up->ops->setup_timer(up);
2352
2353	/*
2354	* Now, initialize the UART
2355	*/
2356	serial_port_out(up: port, UART_LCR, UART_LCR_WLEN8);
2357
2358	uart_port_lock_irqsave(up: port, flags: &flags);
2359	if (up->port.flags & UPF_FOURPORT) {
2360	if (!up->port.irq)
2361	up->port.mctrl |= TIOCM_OUT1;
2362	} else
2363	/*
2364	* Most PC uarts need OUT2 raised to enable interrupts.
2365	*/
2366	if (port->irq)
2367	up->port.mctrl |= TIOCM_OUT2;
2368
2369	serial8250_set_mctrl(port, mctrl: port->mctrl);
2370
2371	/*
2372	* Serial over Lan (SoL) hack:
2373	* Intel 8257x Gigabit ethernet chips have a 16550 emulation, to be
2374	* used for Serial Over Lan. Those chips take a longer time than a
2375	* normal serial device to signalize that a transmission data was
2376	* queued. Due to that, the above test generally fails. One solution
2377	* would be to delay the reading of iir. However, this is not
2378	* reliable, since the timeout is variable. So, let's just don't
2379	* test if we receive TX irq. This way, we'll never enable
2380	* UART_BUG_TXEN.
2381	*/
2382	if (up->port.quirks & UPQ_NO_TXEN_TEST)
2383	goto dont_test_tx_en;
2384
2385	/*
2386	* Do a quick test to see if we receive an interrupt when we enable
2387	* the TX irq.
2388	*/
2389	serial_port_out(up: port, UART_IER, UART_IER_THRI);
2390	lsr = serial_port_in(up: port, UART_LSR);
2391	iir = serial_port_in(up: port, UART_IIR);
2392	serial_port_out(up: port, UART_IER, value: 0);
2393
2394	if (lsr & UART_LSR_TEMT && iir & UART_IIR_NO_INT) {
2395	if (!(up->bugs & UART_BUG_TXEN)) {
2396	up->bugs |= UART_BUG_TXEN;
2397	dev_dbg(port->dev, "enabling bad tx status workarounds\n");
2398	}
2399	} else {
2400	up->bugs &= ~UART_BUG_TXEN;
2401	}
2402
2403	dont_test_tx_en:
2404	uart_port_unlock_irqrestore(up: port, flags);
2405
2406	/*
2407	* Clear the interrupt registers again for luck, and clear the
2408	* saved flags to avoid getting false values from polling
2409	* routines or the previous session.
2410	*/
2411	serial_port_in(up: port, UART_LSR);
2412	serial_port_in(up: port, UART_RX);
2413	serial_port_in(up: port, UART_IIR);
2414	serial_port_in(up: port, UART_MSR);
2415	up->lsr_saved_flags = 0;
2416	up->msr_saved_flags = 0;
2417
2418	/*
2419	* Request DMA channels for both RX and TX.
2420	*/
2421	if (up->dma) {
2422	const char *msg = NULL;
2423
2424	if (uart_console(port))
2425	msg = "forbid DMA for kernel console";
2426	else if (serial8250_request_dma(up))
2427	msg = "failed to request DMA";
2428	if (msg) {
2429	dev_warn_ratelimited(port->dev, "%s\n", msg);
2430	up->dma = NULL;
2431	}
2432	}
2433
2434	/*
2435	* Set the IER shadow for rx interrupts but defer actual interrupt
2436	* enable until after the FIFOs are enabled; otherwise, an already-
2437	* active sender can swamp the interrupt handler with "too much work".
2438	*/
2439	up->ier = UART_IER_RLSI | UART_IER_RDI;
2440
2441	if (port->flags & UPF_FOURPORT) {
2442	unsigned int icp;
2443	/*
2444	* Enable interrupts on the AST Fourport board
2445	*/
2446	icp = (port->iobase & 0xfe0) | 0x01f;
2447	outb_p(value: 0x80, port: icp);
2448	inb_p(port: icp);
2449	}
2450	retval = 0;
2451	out:
2452	serial8250_rpm_put(up);
2453	return retval;
2454	}
2455	EXPORT_SYMBOL_GPL(serial8250_do_startup);
2456
2457	static int serial8250_startup(struct uart_port *port)
2458	{
2459	if (port->startup)
2460	return port->startup(port);
2461	return serial8250_do_startup(port);
2462	}
2463
2464	void serial8250_do_shutdown(struct uart_port *port)
2465	{
2466	struct uart_8250_port *up = up_to_u8250p(up: port);
2467	unsigned long flags;
2468
2469	serial8250_rpm_get(up);
2470	/*
2471	* Disable interrupts from this port
2472	*
2473	* Synchronize UART_IER access against the console.
2474	*/
2475	uart_port_lock_irqsave(up: port, flags: &flags);
2476	up->ier = 0;
2477	serial_port_out(up: port, UART_IER, value: 0);
2478	uart_port_unlock_irqrestore(up: port, flags);
2479
2480	synchronize_irq(irq: port->irq);
2481
2482	if (up->dma)
2483	serial8250_release_dma(up);
2484
2485	uart_port_lock_irqsave(up: port, flags: &flags);
2486	if (port->flags & UPF_FOURPORT) {
2487	/* reset interrupts on the AST Fourport board */
2488	inb(port: (port->iobase & 0xfe0) | 0x1f);
2489	port->mctrl |= TIOCM_OUT1;
2490	} else
2491	port->mctrl &= ~TIOCM_OUT2;
2492
2493	serial8250_set_mctrl(port, mctrl: port->mctrl);
2494	uart_port_unlock_irqrestore(up: port, flags);
2495
2496	/*
2497	* Disable break condition and FIFOs
2498	*/
2499	serial_port_out(up: port, UART_LCR,
2500	value: serial_port_in(up: port, UART_LCR) & ~UART_LCR_SBC);
2501	serial8250_clear_fifos(p: up);
2502
2503	#ifdef CONFIG_SERIAL_8250_RSA
2504	/*
2505	* Reset the RSA board back to 115kbps compat mode.
2506	*/
2507	disable_rsa(up);
2508	#endif
2509
2510	/*
2511	* Read data port to reset things, and then unlink from
2512	* the IRQ chain.
2513	*/
2514	serial_port_in(up: port, UART_RX);
2515	serial8250_rpm_put(up);
2516
2517	up->ops->release_irq(up);
2518	}
2519	EXPORT_SYMBOL_GPL(serial8250_do_shutdown);
2520
2521	static void serial8250_shutdown(struct uart_port *port)
2522	{
2523	if (port->shutdown)
2524	port->shutdown(port);
2525	else
2526	serial8250_do_shutdown(port);
2527	}
2528
2529	static unsigned int serial8250_do_get_divisor(struct uart_port *port,
2530	unsigned int baud,
2531	unsigned int *frac)
2532	{
2533	upf_t magic_multiplier = port->flags & UPF_MAGIC_MULTIPLIER;
2534	struct uart_8250_port *up = up_to_u8250p(up: port);
2535	unsigned int quot;
2536
2537	/*
2538	* Handle magic divisors for baud rates above baud_base on SMSC
2539	* Super I/O chips. We clamp custom rates from clk/6 and clk/12
2540	* up to clk/4 (0x8001) and clk/8 (0x8002) respectively. These
2541	* magic divisors actually reprogram the baud rate generator's
2542	* reference clock derived from chips's 14.318MHz clock input.
2543	*
2544	* Documentation claims that with these magic divisors the base
2545	* frequencies of 7.3728MHz and 3.6864MHz are used respectively
2546	* for the extra baud rates of 460800bps and 230400bps rather
2547	* than the usual base frequency of 1.8462MHz. However empirical
2548	* evidence contradicts that.
2549	*
2550	* Instead bit 7 of the DLM register (bit 15 of the divisor) is
2551	* effectively used as a clock prescaler selection bit for the
2552	* base frequency of 7.3728MHz, always used. If set to 0, then
2553	* the base frequency is divided by 4 for use by the Baud Rate
2554	* Generator, for the usual arrangement where the value of 1 of
2555	* the divisor produces the baud rate of 115200bps. Conversely,
2556	* if set to 1 and high-speed operation has been enabled with the
2557	* Serial Port Mode Register in the Device Configuration Space,
2558	* then the base frequency is supplied directly to the Baud Rate
2559	* Generator, so for the divisor values of 0x8001, 0x8002, 0x8003,
2560	* 0x8004, etc. the respective baud rates produced are 460800bps,
2561	* 230400bps, 153600bps, 115200bps, etc.
2562	*
2563	* In all cases only low 15 bits of the divisor are used to divide
2564	* the baud base and therefore 32767 is the maximum divisor value
2565	* possible, even though documentation says that the programmable
2566	* Baud Rate Generator is capable of dividing the internal PLL
2567	* clock by any divisor from 1 to 65535.
2568	*/
2569	if (magic_multiplier && baud >= port->uartclk / 6)
2570	quot = 0x8001;
2571	else if (magic_multiplier && baud >= port->uartclk / 12)
2572	quot = 0x8002;
2573	else
2574	quot = uart_get_divisor(port, baud);
2575
2576	/*
2577	* Oxford Semi 952 rev B workaround
2578	*/
2579	if (up->bugs & UART_BUG_QUOT && (quot & 0xff) == 0)
2580	quot++;
2581
2582	return quot;
2583	}
2584
2585	static unsigned int serial8250_get_divisor(struct uart_port *port,
2586	unsigned int baud,
2587	unsigned int *frac)
2588	{
2589	if (port->get_divisor)
2590	return port->get_divisor(port, baud, frac);
2591
2592	return serial8250_do_get_divisor(port, baud, frac);
2593	}
2594
2595	static unsigned char serial8250_compute_lcr(struct uart_8250_port *up,
2596	tcflag_t c_cflag)
2597	{
2598	unsigned char cval;
2599
2600	cval = UART_LCR_WLEN(tty_get_char_size(c_cflag));
2601
2602	if (c_cflag & CSTOPB)
2603	cval |= UART_LCR_STOP;
2604	if (c_cflag & PARENB)
2605	cval |= UART_LCR_PARITY;
2606	if (!(c_cflag & PARODD))
2607	cval |= UART_LCR_EPAR;
2608	if (c_cflag & CMSPAR)
2609	cval |= UART_LCR_SPAR;
2610
2611	return cval;
2612	}
2613
2614	void serial8250_do_set_divisor(struct uart_port *port, unsigned int baud,
2615	unsigned int quot, unsigned int quot_frac)
2616	{
2617	struct uart_8250_port *up = up_to_u8250p(up: port);
2618
2619	/* Workaround to enable 115200 baud on OMAP1510 internal ports */
2620	if (is_omap1510_8250(pt: up)) {
2621	if (baud == 115200) {
2622	quot = 1;
2623	serial_port_out(up: port, UART_OMAP_OSC_12M_SEL, value: 1);
2624	} else
2625	serial_port_out(up: port, UART_OMAP_OSC_12M_SEL, value: 0);
2626	}
2627
2628	/*
2629	* For NatSemi, switch to bank 2 not bank 1, to avoid resetting EXCR2,
2630	* otherwise just set DLAB
2631	*/
2632	if (up->capabilities & UART_NATSEMI)
2633	serial_port_out(up: port, UART_LCR, value: 0xe0);
2634	else
2635	serial_port_out(up: port, UART_LCR, value: up->lcr | UART_LCR_DLAB);
2636
2637	serial_dl_write(up, value: quot);
2638	}
2639	EXPORT_SYMBOL_GPL(serial8250_do_set_divisor);
2640
2641	static void serial8250_set_divisor(struct uart_port *port, unsigned int baud,
2642	unsigned int quot, unsigned int quot_frac)
2643	{
2644	if (port->set_divisor)
2645	port->set_divisor(port, baud, quot, quot_frac);
2646	else
2647	serial8250_do_set_divisor(port, baud, quot, quot_frac);
2648	}
2649
2650	static unsigned int serial8250_get_baud_rate(struct uart_port *port,
2651	struct ktermios *termios,
2652	const struct ktermios *old)
2653	{
2654	unsigned int tolerance = port->uartclk / 100;
2655	unsigned int min;
2656	unsigned int max;
2657
2658	/*
2659	* Handle magic divisors for baud rates above baud_base on SMSC
2660	* Super I/O chips. Enable custom rates of clk/4 and clk/8, but
2661	* disable divisor values beyond 32767, which are unavailable.
2662	*/
2663	if (port->flags & UPF_MAGIC_MULTIPLIER) {
2664	min = port->uartclk / 16 / UART_DIV_MAX >> 1;
2665	max = (port->uartclk + tolerance) / 4;
2666	} else {
2667	min = port->uartclk / 16 / UART_DIV_MAX;
2668	max = (port->uartclk + tolerance) / 16;
2669	}
2670
2671	/*
2672	* Ask the core to calculate the divisor for us.
2673	* Allow 1% tolerance at the upper limit so uart clks marginally
2674	* slower than nominal still match standard baud rates without
2675	* causing transmission errors.
2676	*/
2677	return uart_get_baud_rate(port, termios, old, min, max);
2678	}
2679
2680	/*
2681	* Note in order to avoid the tty port mutex deadlock don't use the next method
2682	* within the uart port callbacks. Primarily it's supposed to be utilized to
2683	* handle a sudden reference clock rate change.
2684	*/
2685	void serial8250_update_uartclk(struct uart_port *port, unsigned int uartclk)
2686	{
2687	struct tty_port *tport = &port->state->port;
2688	struct tty_struct *tty;
2689
2690	tty = tty_port_tty_get(port: tport);
2691	if (!tty) {
2692	mutex_lock(&tport->mutex);
2693	port->uartclk = uartclk;
2694	mutex_unlock(lock: &tport->mutex);
2695	return;
2696	}
2697
2698	down_write(sem: &tty->termios_rwsem);
2699	mutex_lock(&tport->mutex);
2700
2701	if (port->uartclk == uartclk)
2702	goto out_unlock;
2703
2704	port->uartclk = uartclk;
2705
2706	if (!tty_port_initialized(port: tport))
2707	goto out_unlock;
2708
2709	serial8250_do_set_termios(port, termios: &tty->termios, NULL);
2710
2711	out_unlock:
2712	mutex_unlock(lock: &tport->mutex);
2713	up_write(sem: &tty->termios_rwsem);
2714	tty_kref_put(tty);
2715	}
2716	EXPORT_SYMBOL_GPL(serial8250_update_uartclk);
2717
2718	void
2719	serial8250_do_set_termios(struct uart_port *port, struct ktermios *termios,
2720	const struct ktermios *old)
2721	{
2722	struct uart_8250_port *up = up_to_u8250p(up: port);
2723	unsigned char cval;
2724	unsigned long flags;
2725	unsigned int baud, quot, frac = 0;
2726
2727	if (up->capabilities & UART_CAP_MINI) {
2728	termios->c_cflag &= ~(CSTOPB | PARENB | PARODD | CMSPAR);
2729	if ((termios->c_cflag & CSIZE) == CS5 ||
2730	(termios->c_cflag & CSIZE) == CS6)
2731	termios->c_cflag = (termios->c_cflag & ~CSIZE) | CS7;
2732	}
2733	cval = serial8250_compute_lcr(up, c_cflag: termios->c_cflag);
2734
2735	baud = serial8250_get_baud_rate(port, termios, old);
2736	quot = serial8250_get_divisor(port, baud, frac: &frac);
2737
2738	/*
2739	* Ok, we're now changing the port state. Do it with
2740	* interrupts disabled.
2741	*
2742	* Synchronize UART_IER access against the console.
2743	*/
2744	serial8250_rpm_get(up);
2745	uart_port_lock_irqsave(up: port, flags: &flags);
2746
2747	up->lcr = cval; /* Save computed LCR */
2748
2749	if (up->capabilities & UART_CAP_FIFO && port->fifosize > 1) {
2750	if (baud < 2400 && !up->dma) {
2751	up->fcr &= ~UART_FCR_TRIGGER_MASK;
2752	up->fcr |= UART_FCR_TRIGGER_1;
2753	}
2754	}
2755
2756	/*
2757	* MCR-based auto flow control. When AFE is enabled, RTS will be
2758	* deasserted when the receive FIFO contains more characters than
2759	* the trigger, or the MCR RTS bit is cleared.
2760	*/
2761	if (up->capabilities & UART_CAP_AFE) {
2762	up->mcr &= ~UART_MCR_AFE;
2763	if (termios->c_cflag & CRTSCTS)
2764	up->mcr |= UART_MCR_AFE;
2765	}
2766
2767	/*
2768	* Update the per-port timeout.
2769	*/
2770	uart_update_timeout(port, cflag: termios->c_cflag, baud);
2771
2772	port->read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR;
2773	if (termios->c_iflag & INPCK)
2774	port->read_status_mask |= UART_LSR_FE | UART_LSR_PE;
2775	if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
2776	port->read_status_mask |= UART_LSR_BI;
2777
2778	/*
2779	* Characters to ignore
2780	*/
2781	port->ignore_status_mask = 0;
2782	if (termios->c_iflag & IGNPAR)
2783	port->ignore_status_mask |= UART_LSR_PE | UART_LSR_FE;
2784	if (termios->c_iflag & IGNBRK) {
2785	port->ignore_status_mask |= UART_LSR_BI;
2786	/*
2787	* If we're ignoring parity and break indicators,
2788	* ignore overruns too (for real raw support).
2789	*/
2790	if (termios->c_iflag & IGNPAR)
2791	port->ignore_status_mask |= UART_LSR_OE;
2792	}
2793
2794	/*
2795	* ignore all characters if CREAD is not set
2796	*/
2797	if ((termios->c_cflag & CREAD) == 0)
2798	port->ignore_status_mask |= UART_LSR_DR;
2799
2800	/*
2801	* CTS flow control flag and modem status interrupts
2802	*/
2803	up->ier &= ~UART_IER_MSI;
2804	if (!(up->bugs & UART_BUG_NOMSR) &&
2805	UART_ENABLE_MS(&up->port, termios->c_cflag))
2806	up->ier |= UART_IER_MSI;
2807	if (up->capabilities & UART_CAP_UUE)
2808	up->ier |= UART_IER_UUE;
2809	if (up->capabilities & UART_CAP_RTOIE)
2810	up->ier |= UART_IER_RTOIE;
2811
2812	serial_port_out(up: port, UART_IER, value: up->ier);
2813
2814	if (up->capabilities & UART_CAP_EFR) {
2815	unsigned char efr = 0;
2816	/*
2817	* TI16C752/Startech hardware flow control. FIXME:
2818	* - TI16C752 requires control thresholds to be set.
2819	* - UART_MCR_RTS is ineffective if auto-RTS mode is enabled.
2820	*/
2821	if (termios->c_cflag & CRTSCTS)
2822	efr |= UART_EFR_CTS;
2823
2824	serial_port_out(up: port, UART_LCR, UART_LCR_CONF_MODE_B);
2825	if (port->flags & UPF_EXAR_EFR)
2826	serial_port_out(up: port, UART_XR_EFR, value: efr);
2827	else
2828	serial_port_out(up: port, UART_EFR, value: efr);
2829	}
2830
2831	serial8250_set_divisor(port, baud, quot, quot_frac: frac);
2832
2833	/*
2834	* LCR DLAB must be set to enable 64-byte FIFO mode. If the FCR
2835	* is written without DLAB set, this mode will be disabled.
2836	*/
2837	if (port->type == PORT_16750)
2838	serial_port_out(up: port, UART_FCR, value: up->fcr);
2839
2840	serial_port_out(up: port, UART_LCR, value: up->lcr); /* reset DLAB */
2841	if (port->type != PORT_16750) {
2842	/* emulated UARTs (Lucent Venus 167x) need two steps */
2843	if (up->fcr & UART_FCR_ENABLE_FIFO)
2844	serial_port_out(up: port, UART_FCR, UART_FCR_ENABLE_FIFO);
2845	serial_port_out(up: port, UART_FCR, value: up->fcr); /* set fcr */
2846	}
2847	serial8250_set_mctrl(port, mctrl: port->mctrl);
2848	uart_port_unlock_irqrestore(up: port, flags);
2849	serial8250_rpm_put(up);
2850
2851	/* Don't rewrite B0 */
2852	if (tty_termios_baud_rate(termios))
2853	tty_termios_encode_baud_rate(termios, ibaud: baud, obaud: baud);
2854	}
2855	EXPORT_SYMBOL(serial8250_do_set_termios);
2856
2857	static void
2858	serial8250_set_termios(struct uart_port *port, struct ktermios *termios,
2859	const struct ktermios *old)
2860	{
2861	if (port->set_termios)
2862	port->set_termios(port, termios, old);
2863	else
2864	serial8250_do_set_termios(port, termios, old);
2865	}
2866
2867	void serial8250_do_set_ldisc(struct uart_port *port, struct ktermios *termios)
2868	{
2869	if (termios->c_line == N_PPS) {
2870	port->flags |= UPF_HARDPPS_CD;
2871	uart_port_lock_irq(up: port);
2872	serial8250_enable_ms(port);
2873	uart_port_unlock_irq(up: port);
2874	} else {
2875	port->flags &= ~UPF_HARDPPS_CD;
2876	if (!UART_ENABLE_MS(port, termios->c_cflag)) {
2877	uart_port_lock_irq(up: port);
2878	serial8250_disable_ms(port);
2879	uart_port_unlock_irq(up: port);
2880	}
2881	}
2882	}
2883	EXPORT_SYMBOL_GPL(serial8250_do_set_ldisc);
2884
2885	static void
2886	serial8250_set_ldisc(struct uart_port *port, struct ktermios *termios)
2887	{
2888	if (port->set_ldisc)
2889	port->set_ldisc(port, termios);
2890	else
2891	serial8250_do_set_ldisc(port, termios);
2892	}
2893
2894	void serial8250_do_pm(struct uart_port *port, unsigned int state,
2895	unsigned int oldstate)
2896	{
2897	struct uart_8250_port *p = up_to_u8250p(up: port);
2898
2899	serial8250_set_sleep(p, sleep: state != 0);
2900	}
2901	EXPORT_SYMBOL(serial8250_do_pm);
2902
2903	static void
2904	serial8250_pm(struct uart_port *port, unsigned int state,
2905	unsigned int oldstate)
2906	{
2907	if (port->pm)
2908	port->pm(port, state, oldstate);
2909	else
2910	serial8250_do_pm(port, state, oldstate);
2911	}
2912
2913	static unsigned int serial8250_port_size(struct uart_8250_port *pt)
2914	{
2915	if (pt->port.mapsize)
2916	return pt->port.mapsize;
2917	if (is_omap1_8250(pt))
2918	return 0x16 << pt->port.regshift;
2919
2920	return 8 << pt->port.regshift;
2921	}
2922
2923	/*
2924	* Resource handling.
2925	*/
2926	static int serial8250_request_std_resource(struct uart_8250_port *up)
2927	{
2928	unsigned int size = serial8250_port_size(pt: up);
2929	struct uart_port *port = &up->port;
2930	int ret = 0;
2931
2932	switch (port->iotype) {
2933	case UPIO_AU:
2934	case UPIO_TSI:
2935	case UPIO_MEM32:
2936	case UPIO_MEM32BE:
2937	case UPIO_MEM16:
2938	case UPIO_MEM:
2939	if (!port->mapbase) {
2940	ret = -EINVAL;
2941	break;
2942	}
2943
2944	if (!request_mem_region(port->mapbase, size, "serial")) {
2945	ret = -EBUSY;
2946	break;
2947	}
2948
2949	if (port->flags & UPF_IOREMAP) {
2950	port->membase = ioremap(offset: port->mapbase, size);
2951	if (!port->membase) {
2952	release_mem_region(port->mapbase, size);
2953	ret = -ENOMEM;
2954	}
2955	}
2956	break;
2957
2958	case UPIO_HUB6:
2959	case UPIO_PORT:
2960	if (!request_region(port->iobase, size, "serial"))
2961	ret = -EBUSY;
2962	break;
2963	}
2964	return ret;
2965	}
2966
2967	static void serial8250_release_std_resource(struct uart_8250_port *up)
2968	{
2969	unsigned int size = serial8250_port_size(pt: up);
2970	struct uart_port *port = &up->port;
2971
2972	switch (port->iotype) {
2973	case UPIO_AU:
2974	case UPIO_TSI:
2975	case UPIO_MEM32:
2976	case UPIO_MEM32BE:
2977	case UPIO_MEM16:
2978	case UPIO_MEM:
2979	if (!port->mapbase)
2980	break;
2981
2982	if (port->flags & UPF_IOREMAP) {
2983	iounmap(addr: port->membase);
2984	port->membase = NULL;
2985	}
2986
2987	release_mem_region(port->mapbase, size);
2988	break;
2989
2990	case UPIO_HUB6:
2991	case UPIO_PORT:
2992	release_region(port->iobase, size);
2993	break;
2994	}
2995	}
2996
2997	static void serial8250_release_port(struct uart_port *port)
2998	{
2999	struct uart_8250_port *up = up_to_u8250p(up: port);
3000
3001	serial8250_release_std_resource(up);
3002	}
3003
3004	static int serial8250_request_port(struct uart_port *port)
3005	{
3006	struct uart_8250_port *up = up_to_u8250p(up: port);
3007
3008	return serial8250_request_std_resource(up);
3009	}
3010
3011	static int fcr_get_rxtrig_bytes(struct uart_8250_port *up)
3012	{
3013	const struct serial8250_config *conf_type = &uart_config[up->port.type];
3014	unsigned char bytes;
3015
3016	bytes = conf_type->rxtrig_bytes[UART_FCR_R_TRIG_BITS(up->fcr)];
3017
3018	return bytes ? bytes : -EOPNOTSUPP;
3019	}
3020
3021	static int bytes_to_fcr_rxtrig(struct uart_8250_port *up, unsigned char bytes)
3022	{
3023	const struct serial8250_config *conf_type = &uart_config[up->port.type];
3024	int i;
3025
3026	if (!conf_type->rxtrig_bytes[UART_FCR_R_TRIG_BITS(UART_FCR_R_TRIG_00)])
3027	return -EOPNOTSUPP;
3028
3029	for (i = 1; i < UART_FCR_R_TRIG_MAX_STATE; i++) {
3030	if (bytes < conf_type->rxtrig_bytes[i])
3031	/* Use the nearest lower value */
3032	return (--i) << UART_FCR_R_TRIG_SHIFT;
3033	}
3034
3035	return UART_FCR_R_TRIG_11;
3036	}
3037
3038	static int do_get_rxtrig(struct tty_port *port)
3039	{
3040	struct uart_state *state = container_of(port, struct uart_state, port);
3041	struct uart_port *uport = state->uart_port;
3042	struct uart_8250_port *up = up_to_u8250p(up: uport);
3043
3044	if (!(up->capabilities & UART_CAP_FIFO) || uport->fifosize <= 1)
3045	return -EINVAL;
3046
3047	return fcr_get_rxtrig_bytes(up);
3048	}
3049
3050	static int do_serial8250_get_rxtrig(struct tty_port *port)
3051	{
3052	int rxtrig_bytes;
3053
3054	mutex_lock(&port->mutex);
3055	rxtrig_bytes = do_get_rxtrig(port);
3056	mutex_unlock(lock: &port->mutex);
3057
3058	return rxtrig_bytes;
3059	}
3060
3061	static ssize_t rx_trig_bytes_show(struct device *dev,
3062	struct device_attribute *attr, char *buf)
3063	{
3064	struct tty_port *port = dev_get_drvdata(dev);
3065	int rxtrig_bytes;
3066
3067	rxtrig_bytes = do_serial8250_get_rxtrig(port);
3068	if (rxtrig_bytes < 0)
3069	return rxtrig_bytes;
3070
3071	return sysfs_emit(buf, fmt: "%d\n", rxtrig_bytes);
3072	}
3073
3074	static int do_set_rxtrig(struct tty_port *port, unsigned char bytes)
3075	{
3076	struct uart_state *state = container_of(port, struct uart_state, port);
3077	struct uart_port *uport = state->uart_port;
3078	struct uart_8250_port *up = up_to_u8250p(up: uport);
3079	int rxtrig;
3080
3081	if (!(up->capabilities & UART_CAP_FIFO) || uport->fifosize <= 1)
3082	return -EINVAL;
3083
3084	rxtrig = bytes_to_fcr_rxtrig(up, bytes);
3085	if (rxtrig < 0)
3086	return rxtrig;
3087
3088	serial8250_clear_fifos(p: up);
3089	up->fcr &= ~UART_FCR_TRIGGER_MASK;
3090	up->fcr |= (unsigned char)rxtrig;
3091	serial_out(up, UART_FCR, value: up->fcr);
3092	return 0;
3093	}
3094
3095	static int do_serial8250_set_rxtrig(struct tty_port *port, unsigned char bytes)
3096	{
3097	int ret;
3098
3099	mutex_lock(&port->mutex);
3100	ret = do_set_rxtrig(port, bytes);
3101	mutex_unlock(lock: &port->mutex);
3102
3103	return ret;
3104	}
3105
3106	static ssize_t rx_trig_bytes_store(struct device *dev,
3107	struct device_attribute *attr, const char *buf, size_t count)
3108	{
3109	struct tty_port *port = dev_get_drvdata(dev);
3110	unsigned char bytes;
3111	int ret;
3112
3113	if (!count)
3114	return -EINVAL;
3115
3116	ret = kstrtou8(s: buf, base: 10, res: &bytes);
3117	if (ret < 0)
3118	return ret;
3119
3120	ret = do_serial8250_set_rxtrig(port, bytes);
3121	if (ret < 0)
3122	return ret;
3123
3124	return count;
3125	}
3126
3127	static DEVICE_ATTR_RW(rx_trig_bytes);
3128
3129	static struct attribute *serial8250_dev_attrs[] = {
3130	&dev_attr_rx_trig_bytes.attr,
3131	NULL
3132	};
3133
3134	static struct attribute_group serial8250_dev_attr_group = {
3135	.attrs = serial8250_dev_attrs,
3136	};
3137
3138	static void register_dev_spec_attr_grp(struct uart_8250_port *up)
3139	{
3140	const struct serial8250_config *conf_type = &uart_config[up->port.type];
3141
3142	if (conf_type->rxtrig_bytes[0])
3143	up->port.attr_group = &serial8250_dev_attr_group;
3144	}
3145
3146	static void serial8250_config_port(struct uart_port *port, int flags)
3147	{
3148	struct uart_8250_port *up = up_to_u8250p(up: port);
3149	int ret;
3150
3151	/*
3152	* Find the region that we can probe for. This in turn
3153	* tells us whether we can probe for the type of port.
3154	*/
3155	ret = serial8250_request_std_resource(up);
3156	if (ret < 0)
3157	return;
3158
3159	if (port->iotype != up->cur_iotype)
3160	set_io_from_upio(port);
3161
3162	if (flags & UART_CONFIG_TYPE)
3163	autoconfig(up);
3164
3165	/* HW bugs may trigger IRQ while IIR == NO_INT */
3166	if (port->type == PORT_TEGRA)
3167	up->bugs |= UART_BUG_NOMSR;
3168
3169	if (port->type != PORT_UNKNOWN && flags & UART_CONFIG_IRQ)
3170	autoconfig_irq(up);
3171
3172	if (port->type == PORT_UNKNOWN)
3173	serial8250_release_std_resource(up);
3174
3175	register_dev_spec_attr_grp(up);
3176	up->fcr = uart_config[up->port.type].fcr;
3177	}
3178
3179	static int
3180	serial8250_verify_port(struct uart_port *port, struct serial_struct *ser)
3181	{
3182	if (ser->irq >= nr_irqs || ser->irq < 0 ||
3183	ser->baud_base < 9600 || ser->type < PORT_UNKNOWN ||
3184	ser->type >= ARRAY_SIZE(uart_config) || ser->type == PORT_CIRRUS ||
3185	ser->type == PORT_STARTECH)
3186	return -EINVAL;
3187	return 0;
3188	}
3189
3190	static const char *serial8250_type(struct uart_port *port)
3191	{
3192	int type = port->type;
3193
3194	if (type >= ARRAY_SIZE(uart_config))
3195	type = 0;
3196	return uart_config[type].name;
3197	}
3198
3199	static const struct uart_ops serial8250_pops = {
3200	.tx_empty = serial8250_tx_empty,
3201	.set_mctrl = serial8250_set_mctrl,
3202	.get_mctrl = serial8250_get_mctrl,
3203	.stop_tx = serial8250_stop_tx,
3204	.start_tx = serial8250_start_tx,
3205	.throttle = serial8250_throttle,
3206	.unthrottle = serial8250_unthrottle,
3207	.stop_rx = serial8250_stop_rx,
3208	.enable_ms = serial8250_enable_ms,
3209	.break_ctl = serial8250_break_ctl,
3210	.startup = serial8250_startup,
3211	.shutdown = serial8250_shutdown,
3212	.set_termios = serial8250_set_termios,
3213	.set_ldisc = serial8250_set_ldisc,
3214	.pm = serial8250_pm,
3215	.type = serial8250_type,
3216	.release_port = serial8250_release_port,
3217	.request_port = serial8250_request_port,
3218	.config_port = serial8250_config_port,
3219	.verify_port = serial8250_verify_port,
3220	#ifdef CONFIG_CONSOLE_POLL
3221	.poll_get_char = serial8250_get_poll_char,
3222	.poll_put_char = serial8250_put_poll_char,
3223	#endif
3224	};
3225
3226	void serial8250_init_port(struct uart_8250_port *up)
3227	{
3228	struct uart_port *port = &up->port;
3229
3230	spin_lock_init(&port->lock);
3231	port->ctrl_id = 0;
3232	port->pm = NULL;
3233	port->ops = &serial8250_pops;
3234	port->has_sysrq = IS_ENABLED(CONFIG_SERIAL_8250_CONSOLE);
3235
3236	up->cur_iotype = 0xFF;
3237	}
3238	EXPORT_SYMBOL_GPL(serial8250_init_port);
3239
3240	void serial8250_set_defaults(struct uart_8250_port *up)
3241	{
3242	struct uart_port *port = &up->port;
3243
3244	if (up->port.flags & UPF_FIXED_TYPE) {
3245	unsigned int type = up->port.type;
3246
3247	if (!up->port.fifosize)
3248	up->port.fifosize = uart_config[type].fifo_size;
3249	if (!up->tx_loadsz)
3250	up->tx_loadsz = uart_config[type].tx_loadsz;
3251	if (!up->capabilities)
3252	up->capabilities = uart_config[type].flags;
3253	}
3254
3255	set_io_from_upio(port);
3256
3257	/* default dma handlers */
3258	if (up->dma) {
3259	if (!up->dma->tx_dma)
3260	up->dma->tx_dma = serial8250_tx_dma;
3261	if (!up->dma->rx_dma)
3262	up->dma->rx_dma = serial8250_rx_dma;
3263	}
3264	}
3265	EXPORT_SYMBOL_GPL(serial8250_set_defaults);
3266
3267	#ifdef CONFIG_SERIAL_8250_CONSOLE
3268
3269	static void serial8250_console_putchar(struct uart_port *port, unsigned char ch)
3270	{
3271	struct uart_8250_port *up = up_to_u8250p(up: port);
3272
3273	wait_for_xmitr(up, UART_LSR_THRE);
3274	serial_port_out(up: port, UART_TX, value: ch);
3275	}
3276
3277	/*
3278	* Restore serial console when h/w power-off detected
3279	*/
3280	static void serial8250_console_restore(struct uart_8250_port *up)
3281	{
3282	struct uart_port *port = &up->port;
3283	struct ktermios termios;
3284	unsigned int baud, quot, frac = 0;
3285
3286	termios.c_cflag = port->cons->cflag;
3287	termios.c_ispeed = port->cons->ispeed;
3288	termios.c_ospeed = port->cons->ospeed;
3289	if (port->state->port.tty && termios.c_cflag == 0) {
3290	termios.c_cflag = port->state->port.tty->termios.c_cflag;
3291	termios.c_ispeed = port->state->port.tty->termios.c_ispeed;
3292	termios.c_ospeed = port->state->port.tty->termios.c_ospeed;
3293	}
3294
3295	baud = serial8250_get_baud_rate(port, termios: &termios, NULL);
3296	quot = serial8250_get_divisor(port, baud, frac: &frac);
3297
3298	serial8250_set_divisor(port, baud, quot, quot_frac: frac);
3299	serial_port_out(up: port, UART_LCR, value: up->lcr);
3300	serial8250_out_MCR(up, value: up->mcr | UART_MCR_DTR | UART_MCR_RTS);
3301	}
3302
3303	/*
3304	* Print a string to the serial port using the device FIFO
3305	*
3306	* It sends fifosize bytes and then waits for the fifo
3307	* to get empty.
3308	*/
3309	static void serial8250_console_fifo_write(struct uart_8250_port *up,
3310	const char *s, unsigned int count)
3311	{
3312	int i;
3313	const char *end = s + count;
3314	unsigned int fifosize = up->tx_loadsz;
3315	bool cr_sent = false;
3316
3317	while (s != end) {
3318	wait_for_lsr(up, UART_LSR_THRE);
3319
3320	for (i = 0; i < fifosize && s != end; ++i) {
3321	if (*s == '\n' && !cr_sent) {
3322	serial_out(up, UART_TX, value: '\r');
3323	cr_sent = true;
3324	} else {
3325	serial_out(up, UART_TX, value: *s++);
3326	cr_sent = false;
3327	}
3328	}
3329	}
3330	}
3331
3332	/*
3333	* Print a string to the serial port trying not to disturb
3334	* any possible real use of the port...
3335	*
3336	* The console_lock must be held when we get here.
3337	*
3338	* Doing runtime PM is really a bad idea for the kernel console.
3339	* Thus, we assume the function is called when device is powered up.
3340	*/
3341	void serial8250_console_write(struct uart_8250_port *up, const char *s,
3342	unsigned int count)
3343	{
3344	struct uart_8250_em485 *em485 = up->em485;
3345	struct uart_port *port = &up->port;
3346	unsigned long flags;
3347	unsigned int ier, use_fifo;
3348	int locked = 1;
3349
3350	touch_nmi_watchdog();
3351
3352	if (oops_in_progress)
3353	locked = uart_port_trylock_irqsave(up: port, flags: &flags);
3354	else
3355	uart_port_lock_irqsave(up: port, flags: &flags);
3356
3357	/*
3358	* First save the IER then disable the interrupts
3359	*/
3360	ier = serial_port_in(up: port, UART_IER);
3361	serial8250_clear_IER(up);
3362
3363	/* check scratch reg to see if port powered off during system sleep */
3364	if (up->canary && (up->canary != serial_port_in(up: port, UART_SCR))) {
3365	serial8250_console_restore(up);
3366	up->canary = 0;
3367	}
3368
3369	if (em485) {
3370	if (em485->tx_stopped)
3371	up->rs485_start_tx(up);
3372	mdelay(port->rs485.delay_rts_before_send);
3373	}
3374
3375	use_fifo = (up->capabilities & UART_CAP_FIFO) &&
3376	/*
3377	* BCM283x requires to check the fifo
3378	* after each byte.
3379	*/
3380	!(up->capabilities & UART_CAP_MINI) &&
3381	/*
3382	* tx_loadsz contains the transmit fifo size
3383	*/
3384	up->tx_loadsz > 1 &&
3385	(up->fcr & UART_FCR_ENABLE_FIFO) &&
3386	port->state &&
3387	test_bit(TTY_PORT_INITIALIZED, &port->state->port.iflags) &&
3388	/*
3389	* After we put a data in the fifo, the controller will send
3390	* it regardless of the CTS state. Therefore, only use fifo
3391	* if we don't use control flow.
3392	*/
3393	!(up->port.flags & UPF_CONS_FLOW);
3394
3395	if (likely(use_fifo))
3396	serial8250_console_fifo_write(up, s, count);
3397	else
3398	uart_console_write(port, s, count, putchar: serial8250_console_putchar);
3399
3400	/*
3401	* Finally, wait for transmitter to become empty
3402	* and restore the IER
3403	*/
3404	wait_for_xmitr(up, UART_LSR_BOTH_EMPTY);
3405
3406	if (em485) {
3407	mdelay(port->rs485.delay_rts_after_send);
3408	if (em485->tx_stopped)
3409	up->rs485_stop_tx(up);
3410	}
3411
3412	serial_port_out(up: port, UART_IER, value: ier);
3413
3414	/*
3415	* The receive handling will happen properly because the
3416	* receive ready bit will still be set; it is not cleared
3417	* on read. However, modem control will not, we must
3418	* call it if we have saved something in the saved flags
3419	* while processing with interrupts off.
3420	*/
3421	if (up->msr_saved_flags)
3422	serial8250_modem_status(up);
3423
3424	if (locked)
3425	uart_port_unlock_irqrestore(up: port, flags);
3426	}
3427
3428	static unsigned int probe_baud(struct uart_port *port)
3429	{
3430	unsigned char lcr, dll, dlm;
3431	unsigned int quot;
3432
3433	lcr = serial_port_in(up: port, UART_LCR);
3434	serial_port_out(up: port, UART_LCR, value: lcr | UART_LCR_DLAB);
3435	dll = serial_port_in(up: port, UART_DLL);
3436	dlm = serial_port_in(up: port, UART_DLM);
3437	serial_port_out(up: port, UART_LCR, value: lcr);
3438
3439	quot = (dlm << 8) | dll;
3440	return (port->uartclk / 16) / quot;
3441	}
3442
3443	int serial8250_console_setup(struct uart_port *port, char *options, bool probe)
3444	{
3445	int baud = 9600;
3446	int bits = 8;
3447	int parity = 'n';
3448	int flow = 'n';
3449	int ret;
3450
3451	if (!port->iobase && !port->membase)
3452	return -ENODEV;
3453
3454	if (options)
3455	uart_parse_options(options, baud: &baud, parity: &parity, bits: &bits, flow: &flow);
3456	else if (probe)
3457	baud = probe_baud(port);
3458
3459	ret = uart_set_options(port, co: port->cons, baud, parity, bits, flow);
3460	if (ret)
3461	return ret;
3462
3463	if (port->dev)
3464	pm_runtime_get_sync(dev: port->dev);
3465
3466	return 0;
3467	}
3468
3469	int serial8250_console_exit(struct uart_port *port)
3470	{
3471	if (port->dev)
3472	pm_runtime_put_sync(dev: port->dev);
3473
3474	return 0;
3475	}
3476
3477	#endif /* CONFIG_SERIAL_8250_CONSOLE */
3478
3479	MODULE_LICENSE("GPL");
3480