1 | // SPDX-License-Identifier: GPL-2.0+ |
2 | /* |
3 | * SC16IS7xx tty serial driver - Copyright (C) 2014 GridPoint |
4 | * Author: Jon Ringle <jringle@gridpoint.com> |
5 | * |
6 | * Based on max310x.c, by Alexander Shiyan <shc_work@mail.ru> |
7 | */ |
8 | |
9 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
10 | |
11 | #include <linux/bitops.h> |
12 | #include <linux/clk.h> |
13 | #include <linux/delay.h> |
14 | #include <linux/device.h> |
15 | #include <linux/gpio/driver.h> |
16 | #include <linux/i2c.h> |
17 | #include <linux/mod_devicetable.h> |
18 | #include <linux/module.h> |
19 | #include <linux/property.h> |
20 | #include <linux/regmap.h> |
21 | #include <linux/serial_core.h> |
22 | #include <linux/serial.h> |
23 | #include <linux/tty.h> |
24 | #include <linux/tty_flip.h> |
25 | #include <linux/spi/spi.h> |
26 | #include <linux/uaccess.h> |
27 | #include <linux/units.h> |
28 | #include <uapi/linux/sched/types.h> |
29 | |
30 | #define SC16IS7XX_NAME "sc16is7xx" |
31 | #define SC16IS7XX_MAX_DEVS 8 |
32 | #define SC16IS7XX_MAX_PORTS 2 /* Maximum number of UART ports per IC. */ |
33 | |
34 | /* SC16IS7XX register definitions */ |
35 | #define SC16IS7XX_RHR_REG (0x00) /* RX FIFO */ |
36 | #define SC16IS7XX_THR_REG (0x00) /* TX FIFO */ |
37 | #define SC16IS7XX_IER_REG (0x01) /* Interrupt enable */ |
38 | #define SC16IS7XX_IIR_REG (0x02) /* Interrupt Identification */ |
39 | #define SC16IS7XX_FCR_REG (0x02) /* FIFO control */ |
40 | #define SC16IS7XX_LCR_REG (0x03) /* Line Control */ |
41 | #define SC16IS7XX_MCR_REG (0x04) /* Modem Control */ |
42 | #define SC16IS7XX_LSR_REG (0x05) /* Line Status */ |
43 | #define SC16IS7XX_MSR_REG (0x06) /* Modem Status */ |
44 | #define SC16IS7XX_SPR_REG (0x07) /* Scratch Pad */ |
45 | #define SC16IS7XX_TXLVL_REG (0x08) /* TX FIFO level */ |
46 | #define SC16IS7XX_RXLVL_REG (0x09) /* RX FIFO level */ |
47 | #define SC16IS7XX_IODIR_REG (0x0a) /* I/O Direction |
48 | * - only on 75x/76x |
49 | */ |
50 | #define SC16IS7XX_IOSTATE_REG (0x0b) /* I/O State |
51 | * - only on 75x/76x |
52 | */ |
53 | #define SC16IS7XX_IOINTENA_REG (0x0c) /* I/O Interrupt Enable |
54 | * - only on 75x/76x |
55 | */ |
56 | #define SC16IS7XX_IOCONTROL_REG (0x0e) /* I/O Control |
57 | * - only on 75x/76x |
58 | */ |
59 | #define SC16IS7XX_EFCR_REG (0x0f) /* Extra Features Control */ |
60 | |
61 | /* TCR/TLR Register set: Only if ((MCR[2] == 1) && (EFR[4] == 1)) */ |
62 | #define SC16IS7XX_TCR_REG (0x06) /* Transmit control */ |
63 | #define SC16IS7XX_TLR_REG (0x07) /* Trigger level */ |
64 | |
65 | /* Special Register set: Only if ((LCR[7] == 1) && (LCR != 0xBF)) */ |
66 | #define SC16IS7XX_DLL_REG (0x00) /* Divisor Latch Low */ |
67 | #define SC16IS7XX_DLH_REG (0x01) /* Divisor Latch High */ |
68 | |
69 | /* Enhanced Register set: Only if (LCR == 0xBF) */ |
70 | #define SC16IS7XX_EFR_REG (0x02) /* Enhanced Features */ |
71 | #define SC16IS7XX_XON1_REG (0x04) /* Xon1 word */ |
72 | #define SC16IS7XX_XON2_REG (0x05) /* Xon2 word */ |
73 | #define SC16IS7XX_XOFF1_REG (0x06) /* Xoff1 word */ |
74 | #define SC16IS7XX_XOFF2_REG (0x07) /* Xoff2 word */ |
75 | |
76 | /* IER register bits */ |
77 | #define SC16IS7XX_IER_RDI_BIT (1 << 0) /* Enable RX data interrupt */ |
78 | #define SC16IS7XX_IER_THRI_BIT (1 << 1) /* Enable TX holding register |
79 | * interrupt */ |
80 | #define SC16IS7XX_IER_RLSI_BIT (1 << 2) /* Enable RX line status |
81 | * interrupt */ |
82 | #define SC16IS7XX_IER_MSI_BIT (1 << 3) /* Enable Modem status |
83 | * interrupt */ |
84 | |
85 | /* IER register bits - write only if (EFR[4] == 1) */ |
86 | #define SC16IS7XX_IER_SLEEP_BIT (1 << 4) /* Enable Sleep mode */ |
87 | #define SC16IS7XX_IER_XOFFI_BIT (1 << 5) /* Enable Xoff interrupt */ |
88 | #define SC16IS7XX_IER_RTSI_BIT (1 << 6) /* Enable nRTS interrupt */ |
89 | #define SC16IS7XX_IER_CTSI_BIT (1 << 7) /* Enable nCTS interrupt */ |
90 | |
91 | /* FCR register bits */ |
92 | #define SC16IS7XX_FCR_FIFO_BIT (1 << 0) /* Enable FIFO */ |
93 | #define SC16IS7XX_FCR_RXRESET_BIT (1 << 1) /* Reset RX FIFO */ |
94 | #define SC16IS7XX_FCR_TXRESET_BIT (1 << 2) /* Reset TX FIFO */ |
95 | #define SC16IS7XX_FCR_RXLVLL_BIT (1 << 6) /* RX Trigger level LSB */ |
96 | #define SC16IS7XX_FCR_RXLVLH_BIT (1 << 7) /* RX Trigger level MSB */ |
97 | |
98 | /* FCR register bits - write only if (EFR[4] == 1) */ |
99 | #define SC16IS7XX_FCR_TXLVLL_BIT (1 << 4) /* TX Trigger level LSB */ |
100 | #define SC16IS7XX_FCR_TXLVLH_BIT (1 << 5) /* TX Trigger level MSB */ |
101 | |
102 | /* IIR register bits */ |
103 | #define SC16IS7XX_IIR_NO_INT_BIT (1 << 0) /* No interrupts pending */ |
104 | #define SC16IS7XX_IIR_ID_MASK 0x3e /* Mask for the interrupt ID */ |
105 | #define SC16IS7XX_IIR_THRI_SRC 0x02 /* TX holding register empty */ |
106 | #define SC16IS7XX_IIR_RDI_SRC 0x04 /* RX data interrupt */ |
107 | #define SC16IS7XX_IIR_RLSE_SRC 0x06 /* RX line status error */ |
108 | #define SC16IS7XX_IIR_RTOI_SRC 0x0c /* RX time-out interrupt */ |
109 | #define SC16IS7XX_IIR_MSI_SRC 0x00 /* Modem status interrupt |
110 | * - only on 75x/76x |
111 | */ |
112 | #define SC16IS7XX_IIR_INPIN_SRC 0x30 /* Input pin change of state |
113 | * - only on 75x/76x |
114 | */ |
115 | #define SC16IS7XX_IIR_XOFFI_SRC 0x10 /* Received Xoff */ |
116 | #define SC16IS7XX_IIR_CTSRTS_SRC 0x20 /* nCTS,nRTS change of state |
117 | * from active (LOW) |
118 | * to inactive (HIGH) |
119 | */ |
120 | /* LCR register bits */ |
121 | #define SC16IS7XX_LCR_LENGTH0_BIT (1 << 0) /* Word length bit 0 */ |
122 | #define SC16IS7XX_LCR_LENGTH1_BIT (1 << 1) /* Word length bit 1 |
123 | * |
124 | * Word length bits table: |
125 | * 00 -> 5 bit words |
126 | * 01 -> 6 bit words |
127 | * 10 -> 7 bit words |
128 | * 11 -> 8 bit words |
129 | */ |
130 | #define SC16IS7XX_LCR_STOPLEN_BIT (1 << 2) /* STOP length bit |
131 | * |
132 | * STOP length bit table: |
133 | * 0 -> 1 stop bit |
134 | * 1 -> 1-1.5 stop bits if |
135 | * word length is 5, |
136 | * 2 stop bits otherwise |
137 | */ |
138 | #define SC16IS7XX_LCR_PARITY_BIT (1 << 3) /* Parity bit enable */ |
139 | #define SC16IS7XX_LCR_EVENPARITY_BIT (1 << 4) /* Even parity bit enable */ |
140 | #define SC16IS7XX_LCR_FORCEPARITY_BIT (1 << 5) /* 9-bit multidrop parity */ |
141 | #define SC16IS7XX_LCR_TXBREAK_BIT (1 << 6) /* TX break enable */ |
142 | #define SC16IS7XX_LCR_DLAB_BIT (1 << 7) /* Divisor Latch enable */ |
143 | #define SC16IS7XX_LCR_WORD_LEN_5 (0x00) |
144 | #define SC16IS7XX_LCR_WORD_LEN_6 (0x01) |
145 | #define SC16IS7XX_LCR_WORD_LEN_7 (0x02) |
146 | #define SC16IS7XX_LCR_WORD_LEN_8 (0x03) |
147 | #define SC16IS7XX_LCR_CONF_MODE_A SC16IS7XX_LCR_DLAB_BIT /* Special |
148 | * reg set */ |
149 | #define SC16IS7XX_LCR_CONF_MODE_B 0xBF /* Enhanced |
150 | * reg set */ |
151 | |
152 | /* MCR register bits */ |
153 | #define SC16IS7XX_MCR_DTR_BIT (1 << 0) /* DTR complement |
154 | * - only on 75x/76x |
155 | */ |
156 | #define SC16IS7XX_MCR_RTS_BIT (1 << 1) /* RTS complement */ |
157 | #define SC16IS7XX_MCR_TCRTLR_BIT (1 << 2) /* TCR/TLR register enable */ |
158 | #define SC16IS7XX_MCR_LOOP_BIT (1 << 4) /* Enable loopback test mode */ |
159 | #define SC16IS7XX_MCR_XONANY_BIT (1 << 5) /* Enable Xon Any |
160 | * - write enabled |
161 | * if (EFR[4] == 1) |
162 | */ |
163 | #define SC16IS7XX_MCR_IRDA_BIT (1 << 6) /* Enable IrDA mode |
164 | * - write enabled |
165 | * if (EFR[4] == 1) |
166 | */ |
167 | #define SC16IS7XX_MCR_CLKSEL_BIT (1 << 7) /* Divide clock by 4 |
168 | * - write enabled |
169 | * if (EFR[4] == 1) |
170 | */ |
171 | |
172 | /* LSR register bits */ |
173 | #define SC16IS7XX_LSR_DR_BIT (1 << 0) /* Receiver data ready */ |
174 | #define SC16IS7XX_LSR_OE_BIT (1 << 1) /* Overrun Error */ |
175 | #define SC16IS7XX_LSR_PE_BIT (1 << 2) /* Parity Error */ |
176 | #define SC16IS7XX_LSR_FE_BIT (1 << 3) /* Frame Error */ |
177 | #define SC16IS7XX_LSR_BI_BIT (1 << 4) /* Break Interrupt */ |
178 | #define SC16IS7XX_LSR_BRK_ERROR_MASK 0x1E /* BI, FE, PE, OE bits */ |
179 | #define SC16IS7XX_LSR_THRE_BIT (1 << 5) /* TX holding register empty */ |
180 | #define SC16IS7XX_LSR_TEMT_BIT (1 << 6) /* Transmitter empty */ |
181 | #define SC16IS7XX_LSR_FIFOE_BIT (1 << 7) /* Fifo Error */ |
182 | |
183 | /* MSR register bits */ |
184 | #define SC16IS7XX_MSR_DCTS_BIT (1 << 0) /* Delta CTS Clear To Send */ |
185 | #define SC16IS7XX_MSR_DDSR_BIT (1 << 1) /* Delta DSR Data Set Ready |
186 | * or (IO4) |
187 | * - only on 75x/76x |
188 | */ |
189 | #define SC16IS7XX_MSR_DRI_BIT (1 << 2) /* Delta RI Ring Indicator |
190 | * or (IO7) |
191 | * - only on 75x/76x |
192 | */ |
193 | #define SC16IS7XX_MSR_DCD_BIT (1 << 3) /* Delta CD Carrier Detect |
194 | * or (IO6) |
195 | * - only on 75x/76x |
196 | */ |
197 | #define SC16IS7XX_MSR_CTS_BIT (1 << 4) /* CTS */ |
198 | #define SC16IS7XX_MSR_DSR_BIT (1 << 5) /* DSR (IO4) |
199 | * - only on 75x/76x |
200 | */ |
201 | #define SC16IS7XX_MSR_RI_BIT (1 << 6) /* RI (IO7) |
202 | * - only on 75x/76x |
203 | */ |
204 | #define SC16IS7XX_MSR_CD_BIT (1 << 7) /* CD (IO6) |
205 | * - only on 75x/76x |
206 | */ |
207 | #define SC16IS7XX_MSR_DELTA_MASK 0x0F /* Any of the delta bits! */ |
208 | |
209 | /* |
210 | * TCR register bits |
211 | * TCR trigger levels are available from 0 to 60 characters with a granularity |
212 | * of four. |
213 | * The programmer must program the TCR such that TCR[3:0] > TCR[7:4]. There is |
214 | * no built-in hardware check to make sure this condition is met. Also, the TCR |
215 | * must be programmed with this condition before auto RTS or software flow |
216 | * control is enabled to avoid spurious operation of the device. |
217 | */ |
218 | #define SC16IS7XX_TCR_RX_HALT(words) ((((words) / 4) & 0x0f) << 0) |
219 | #define SC16IS7XX_TCR_RX_RESUME(words) ((((words) / 4) & 0x0f) << 4) |
220 | |
221 | /* |
222 | * TLR register bits |
223 | * If TLR[3:0] or TLR[7:4] are logical 0, the selectable trigger levels via the |
224 | * FIFO Control Register (FCR) are used for the transmit and receive FIFO |
225 | * trigger levels. Trigger levels from 4 characters to 60 characters are |
226 | * available with a granularity of four. |
227 | * |
228 | * When the trigger level setting in TLR is zero, the SC16IS74x/75x/76x uses the |
229 | * trigger level setting defined in FCR. If TLR has non-zero trigger level value |
230 | * the trigger level defined in FCR is discarded. This applies to both transmit |
231 | * FIFO and receive FIFO trigger level setting. |
232 | * |
233 | * When TLR is used for RX trigger level control, FCR[7:6] should be left at the |
234 | * default state, that is, '00'. |
235 | */ |
236 | #define SC16IS7XX_TLR_TX_TRIGGER(words) ((((words) / 4) & 0x0f) << 0) |
237 | #define SC16IS7XX_TLR_RX_TRIGGER(words) ((((words) / 4) & 0x0f) << 4) |
238 | |
239 | /* IOControl register bits (Only 75x/76x) */ |
240 | #define SC16IS7XX_IOCONTROL_LATCH_BIT (1 << 0) /* Enable input latching */ |
241 | #define SC16IS7XX_IOCONTROL_MODEM_A_BIT (1 << 1) /* Enable GPIO[7:4] as modem A pins */ |
242 | #define SC16IS7XX_IOCONTROL_MODEM_B_BIT (1 << 2) /* Enable GPIO[3:0] as modem B pins */ |
243 | #define SC16IS7XX_IOCONTROL_SRESET_BIT (1 << 3) /* Software Reset */ |
244 | |
245 | /* EFCR register bits */ |
246 | #define SC16IS7XX_EFCR_9BIT_MODE_BIT (1 << 0) /* Enable 9-bit or Multidrop |
247 | * mode (RS485) */ |
248 | #define SC16IS7XX_EFCR_RXDISABLE_BIT (1 << 1) /* Disable receiver */ |
249 | #define SC16IS7XX_EFCR_TXDISABLE_BIT (1 << 2) /* Disable transmitter */ |
250 | #define SC16IS7XX_EFCR_AUTO_RS485_BIT (1 << 4) /* Auto RS485 RTS direction */ |
251 | #define SC16IS7XX_EFCR_RTS_INVERT_BIT (1 << 5) /* RTS output inversion */ |
252 | #define SC16IS7XX_EFCR_IRDA_MODE_BIT (1 << 7) /* IrDA mode |
253 | * 0 = rate upto 115.2 kbit/s |
254 | * - Only 75x/76x |
255 | * 1 = rate upto 1.152 Mbit/s |
256 | * - Only 76x |
257 | */ |
258 | |
259 | /* EFR register bits */ |
260 | #define SC16IS7XX_EFR_AUTORTS_BIT (1 << 6) /* Auto RTS flow ctrl enable */ |
261 | #define SC16IS7XX_EFR_AUTOCTS_BIT (1 << 7) /* Auto CTS flow ctrl enable */ |
262 | #define SC16IS7XX_EFR_XOFF2_DETECT_BIT (1 << 5) /* Enable Xoff2 detection */ |
263 | #define SC16IS7XX_EFR_ENABLE_BIT (1 << 4) /* Enable enhanced functions |
264 | * and writing to IER[7:4], |
265 | * FCR[5:4], MCR[7:5] |
266 | */ |
267 | #define SC16IS7XX_EFR_SWFLOW3_BIT (1 << 3) /* SWFLOW bit 3 */ |
268 | #define SC16IS7XX_EFR_SWFLOW2_BIT (1 << 2) /* SWFLOW bit 2 |
269 | * |
270 | * SWFLOW bits 3 & 2 table: |
271 | * 00 -> no transmitter flow |
272 | * control |
273 | * 01 -> transmitter generates |
274 | * XON2 and XOFF2 |
275 | * 10 -> transmitter generates |
276 | * XON1 and XOFF1 |
277 | * 11 -> transmitter generates |
278 | * XON1, XON2, XOFF1 and |
279 | * XOFF2 |
280 | */ |
281 | #define SC16IS7XX_EFR_SWFLOW1_BIT (1 << 1) /* SWFLOW bit 2 */ |
282 | #define SC16IS7XX_EFR_SWFLOW0_BIT (1 << 0) /* SWFLOW bit 3 |
283 | * |
284 | * SWFLOW bits 3 & 2 table: |
285 | * 00 -> no received flow |
286 | * control |
287 | * 01 -> receiver compares |
288 | * XON2 and XOFF2 |
289 | * 10 -> receiver compares |
290 | * XON1 and XOFF1 |
291 | * 11 -> receiver compares |
292 | * XON1, XON2, XOFF1 and |
293 | * XOFF2 |
294 | */ |
295 | #define SC16IS7XX_EFR_FLOWCTRL_BITS (SC16IS7XX_EFR_AUTORTS_BIT | \ |
296 | SC16IS7XX_EFR_AUTOCTS_BIT | \ |
297 | SC16IS7XX_EFR_XOFF2_DETECT_BIT | \ |
298 | SC16IS7XX_EFR_SWFLOW3_BIT | \ |
299 | SC16IS7XX_EFR_SWFLOW2_BIT | \ |
300 | SC16IS7XX_EFR_SWFLOW1_BIT | \ |
301 | SC16IS7XX_EFR_SWFLOW0_BIT) |
302 | |
303 | |
304 | /* Misc definitions */ |
305 | #define SC16IS7XX_SPI_READ_BIT BIT(7) |
306 | #define SC16IS7XX_FIFO_SIZE (64) |
307 | #define SC16IS7XX_GPIOS_PER_BANK 4 |
308 | |
309 | struct sc16is7xx_devtype { |
310 | char name[10]; |
311 | int nr_gpio; |
312 | int nr_uart; |
313 | }; |
314 | |
315 | #define SC16IS7XX_RECONF_MD (1 << 0) |
316 | #define SC16IS7XX_RECONF_IER (1 << 1) |
317 | #define SC16IS7XX_RECONF_RS485 (1 << 2) |
318 | |
319 | struct sc16is7xx_one_config { |
320 | unsigned int flags; |
321 | u8 ier_mask; |
322 | u8 ier_val; |
323 | }; |
324 | |
325 | struct sc16is7xx_one { |
326 | struct uart_port port; |
327 | struct regmap *regmap; |
328 | struct mutex efr_lock; /* EFR registers access */ |
329 | struct kthread_work tx_work; |
330 | struct kthread_work reg_work; |
331 | struct kthread_delayed_work ms_work; |
332 | struct sc16is7xx_one_config config; |
333 | unsigned int old_mctrl; |
334 | u8 old_lcr; /* Value before EFR access. */ |
335 | bool irda_mode; |
336 | }; |
337 | |
338 | struct sc16is7xx_port { |
339 | const struct sc16is7xx_devtype *devtype; |
340 | struct clk *clk; |
341 | #ifdef CONFIG_GPIOLIB |
342 | struct gpio_chip gpio; |
343 | unsigned long gpio_valid_mask; |
344 | #endif |
345 | u8 mctrl_mask; |
346 | unsigned char buf[SC16IS7XX_FIFO_SIZE]; |
347 | struct kthread_worker kworker; |
348 | struct task_struct *kworker_task; |
349 | struct sc16is7xx_one p[]; |
350 | }; |
351 | |
352 | static DECLARE_BITMAP(sc16is7xx_lines, SC16IS7XX_MAX_DEVS); |
353 | |
354 | static struct uart_driver sc16is7xx_uart = { |
355 | .owner = THIS_MODULE, |
356 | .driver_name = SC16IS7XX_NAME, |
357 | .dev_name = "ttySC" , |
358 | .nr = SC16IS7XX_MAX_DEVS, |
359 | }; |
360 | |
361 | #define to_sc16is7xx_one(p,e) ((container_of((p), struct sc16is7xx_one, e))) |
362 | |
363 | static u8 sc16is7xx_port_read(struct uart_port *port, u8 reg) |
364 | { |
365 | struct sc16is7xx_one *one = to_sc16is7xx_one(port, port); |
366 | unsigned int val = 0; |
367 | |
368 | regmap_read(map: one->regmap, reg, val: &val); |
369 | |
370 | return val; |
371 | } |
372 | |
373 | static void sc16is7xx_port_write(struct uart_port *port, u8 reg, u8 val) |
374 | { |
375 | struct sc16is7xx_one *one = to_sc16is7xx_one(port, port); |
376 | |
377 | regmap_write(map: one->regmap, reg, val); |
378 | } |
379 | |
380 | static void sc16is7xx_fifo_read(struct uart_port *port, u8 *rxbuf, unsigned int rxlen) |
381 | { |
382 | struct sc16is7xx_one *one = to_sc16is7xx_one(port, port); |
383 | |
384 | regmap_noinc_read(map: one->regmap, SC16IS7XX_RHR_REG, val: rxbuf, val_len: rxlen); |
385 | } |
386 | |
387 | static void sc16is7xx_fifo_write(struct uart_port *port, u8 *txbuf, u8 to_send) |
388 | { |
389 | struct sc16is7xx_one *one = to_sc16is7xx_one(port, port); |
390 | |
391 | /* |
392 | * Don't send zero-length data, at least on SPI it confuses the chip |
393 | * delivering wrong TXLVL data. |
394 | */ |
395 | if (unlikely(!to_send)) |
396 | return; |
397 | |
398 | regmap_noinc_write(map: one->regmap, SC16IS7XX_THR_REG, val: txbuf, val_len: to_send); |
399 | } |
400 | |
401 | static void sc16is7xx_port_update(struct uart_port *port, u8 reg, |
402 | u8 mask, u8 val) |
403 | { |
404 | struct sc16is7xx_one *one = to_sc16is7xx_one(port, port); |
405 | |
406 | regmap_update_bits(map: one->regmap, reg, mask, val); |
407 | } |
408 | |
409 | static void sc16is7xx_power(struct uart_port *port, int on) |
410 | { |
411 | sc16is7xx_port_update(port, SC16IS7XX_IER_REG, |
412 | SC16IS7XX_IER_SLEEP_BIT, |
413 | val: on ? 0 : SC16IS7XX_IER_SLEEP_BIT); |
414 | } |
415 | |
416 | /* |
417 | * In an amazing feat of design, the Enhanced Features Register (EFR) |
418 | * shares the address of the Interrupt Identification Register (IIR). |
419 | * Access to EFR is switched on by writing a magic value (0xbf) to the |
420 | * Line Control Register (LCR). Any interrupt firing during this time will |
421 | * see the EFR where it expects the IIR to be, leading to |
422 | * "Unexpected interrupt" messages. |
423 | * |
424 | * Prevent this possibility by claiming a mutex while accessing the EFR, |
425 | * and claiming the same mutex from within the interrupt handler. This is |
426 | * similar to disabling the interrupt, but that doesn't work because the |
427 | * bulk of the interrupt processing is run as a workqueue job in thread |
428 | * context. |
429 | */ |
430 | static void sc16is7xx_efr_lock(struct uart_port *port) |
431 | { |
432 | struct sc16is7xx_one *one = to_sc16is7xx_one(port, port); |
433 | |
434 | mutex_lock(&one->efr_lock); |
435 | |
436 | /* Backup content of LCR. */ |
437 | one->old_lcr = sc16is7xx_port_read(port, SC16IS7XX_LCR_REG); |
438 | |
439 | /* Enable access to Enhanced register set */ |
440 | sc16is7xx_port_write(port, SC16IS7XX_LCR_REG, SC16IS7XX_LCR_CONF_MODE_B); |
441 | |
442 | /* Disable cache updates when writing to EFR registers */ |
443 | regcache_cache_bypass(map: one->regmap, enable: true); |
444 | } |
445 | |
446 | static void sc16is7xx_efr_unlock(struct uart_port *port) |
447 | { |
448 | struct sc16is7xx_one *one = to_sc16is7xx_one(port, port); |
449 | |
450 | /* Re-enable cache updates when writing to normal registers */ |
451 | regcache_cache_bypass(map: one->regmap, enable: false); |
452 | |
453 | /* Restore original content of LCR */ |
454 | sc16is7xx_port_write(port, SC16IS7XX_LCR_REG, val: one->old_lcr); |
455 | |
456 | mutex_unlock(lock: &one->efr_lock); |
457 | } |
458 | |
459 | static void sc16is7xx_ier_clear(struct uart_port *port, u8 bit) |
460 | { |
461 | struct sc16is7xx_port *s = dev_get_drvdata(dev: port->dev); |
462 | struct sc16is7xx_one *one = to_sc16is7xx_one(port, port); |
463 | |
464 | lockdep_assert_held_once(&port->lock); |
465 | |
466 | one->config.flags |= SC16IS7XX_RECONF_IER; |
467 | one->config.ier_mask |= bit; |
468 | one->config.ier_val &= ~bit; |
469 | kthread_queue_work(worker: &s->kworker, work: &one->reg_work); |
470 | } |
471 | |
472 | static void sc16is7xx_ier_set(struct uart_port *port, u8 bit) |
473 | { |
474 | struct sc16is7xx_port *s = dev_get_drvdata(dev: port->dev); |
475 | struct sc16is7xx_one *one = to_sc16is7xx_one(port, port); |
476 | |
477 | lockdep_assert_held_once(&port->lock); |
478 | |
479 | one->config.flags |= SC16IS7XX_RECONF_IER; |
480 | one->config.ier_mask |= bit; |
481 | one->config.ier_val |= bit; |
482 | kthread_queue_work(worker: &s->kworker, work: &one->reg_work); |
483 | } |
484 | |
485 | static void sc16is7xx_stop_tx(struct uart_port *port) |
486 | { |
487 | sc16is7xx_ier_clear(port, SC16IS7XX_IER_THRI_BIT); |
488 | } |
489 | |
490 | static void sc16is7xx_stop_rx(struct uart_port *port) |
491 | { |
492 | sc16is7xx_ier_clear(port, SC16IS7XX_IER_RDI_BIT); |
493 | } |
494 | |
495 | static const struct sc16is7xx_devtype sc16is74x_devtype = { |
496 | .name = "SC16IS74X" , |
497 | .nr_gpio = 0, |
498 | .nr_uart = 1, |
499 | }; |
500 | |
501 | static const struct sc16is7xx_devtype sc16is750_devtype = { |
502 | .name = "SC16IS750" , |
503 | .nr_gpio = 8, |
504 | .nr_uart = 1, |
505 | }; |
506 | |
507 | static const struct sc16is7xx_devtype sc16is752_devtype = { |
508 | .name = "SC16IS752" , |
509 | .nr_gpio = 8, |
510 | .nr_uart = 2, |
511 | }; |
512 | |
513 | static const struct sc16is7xx_devtype sc16is760_devtype = { |
514 | .name = "SC16IS760" , |
515 | .nr_gpio = 8, |
516 | .nr_uart = 1, |
517 | }; |
518 | |
519 | static const struct sc16is7xx_devtype sc16is762_devtype = { |
520 | .name = "SC16IS762" , |
521 | .nr_gpio = 8, |
522 | .nr_uart = 2, |
523 | }; |
524 | |
525 | static bool sc16is7xx_regmap_volatile(struct device *dev, unsigned int reg) |
526 | { |
527 | switch (reg) { |
528 | case SC16IS7XX_RHR_REG: |
529 | case SC16IS7XX_IIR_REG: |
530 | case SC16IS7XX_LSR_REG: |
531 | case SC16IS7XX_MSR_REG: |
532 | case SC16IS7XX_TXLVL_REG: |
533 | case SC16IS7XX_RXLVL_REG: |
534 | case SC16IS7XX_IOSTATE_REG: |
535 | case SC16IS7XX_IOCONTROL_REG: |
536 | return true; |
537 | default: |
538 | return false; |
539 | } |
540 | } |
541 | |
542 | static bool sc16is7xx_regmap_precious(struct device *dev, unsigned int reg) |
543 | { |
544 | switch (reg) { |
545 | case SC16IS7XX_RHR_REG: |
546 | return true; |
547 | default: |
548 | return false; |
549 | } |
550 | } |
551 | |
552 | static bool sc16is7xx_regmap_noinc(struct device *dev, unsigned int reg) |
553 | { |
554 | return reg == SC16IS7XX_RHR_REG; |
555 | } |
556 | |
557 | static int sc16is7xx_set_baud(struct uart_port *port, int baud) |
558 | { |
559 | struct sc16is7xx_one *one = to_sc16is7xx_one(port, port); |
560 | u8 lcr; |
561 | u8 prescaler = 0; |
562 | unsigned long clk = port->uartclk, div = clk / 16 / baud; |
563 | |
564 | if (div >= BIT(16)) { |
565 | prescaler = SC16IS7XX_MCR_CLKSEL_BIT; |
566 | div /= 4; |
567 | } |
568 | |
569 | /* Enable enhanced features */ |
570 | sc16is7xx_efr_lock(port); |
571 | sc16is7xx_port_update(port, SC16IS7XX_EFR_REG, |
572 | SC16IS7XX_EFR_ENABLE_BIT, |
573 | SC16IS7XX_EFR_ENABLE_BIT); |
574 | sc16is7xx_efr_unlock(port); |
575 | |
576 | sc16is7xx_port_update(port, SC16IS7XX_MCR_REG, |
577 | SC16IS7XX_MCR_CLKSEL_BIT, |
578 | val: prescaler); |
579 | |
580 | /* Backup LCR and access special register set (DLL/DLH) */ |
581 | lcr = sc16is7xx_port_read(port, SC16IS7XX_LCR_REG); |
582 | sc16is7xx_port_write(port, SC16IS7XX_LCR_REG, |
583 | SC16IS7XX_LCR_CONF_MODE_A); |
584 | |
585 | /* Write the new divisor */ |
586 | regcache_cache_bypass(map: one->regmap, enable: true); |
587 | sc16is7xx_port_write(port, SC16IS7XX_DLH_REG, val: div / 256); |
588 | sc16is7xx_port_write(port, SC16IS7XX_DLL_REG, val: div % 256); |
589 | regcache_cache_bypass(map: one->regmap, enable: false); |
590 | |
591 | /* Restore LCR and access to general register set */ |
592 | sc16is7xx_port_write(port, SC16IS7XX_LCR_REG, val: lcr); |
593 | |
594 | return DIV_ROUND_CLOSEST(clk / 16, div); |
595 | } |
596 | |
597 | static void sc16is7xx_handle_rx(struct uart_port *port, unsigned int rxlen, |
598 | unsigned int iir) |
599 | { |
600 | struct sc16is7xx_port *s = dev_get_drvdata(dev: port->dev); |
601 | unsigned int lsr = 0, bytes_read, i; |
602 | bool read_lsr = (iir == SC16IS7XX_IIR_RLSE_SRC) ? true : false; |
603 | u8 ch, flag; |
604 | |
605 | if (unlikely(rxlen >= sizeof(s->buf))) { |
606 | dev_warn_ratelimited(port->dev, |
607 | "ttySC%i: Possible RX FIFO overrun: %d\n" , |
608 | port->line, rxlen); |
609 | port->icount.buf_overrun++; |
610 | /* Ensure sanity of RX level */ |
611 | rxlen = sizeof(s->buf); |
612 | } |
613 | |
614 | while (rxlen) { |
615 | /* Only read lsr if there are possible errors in FIFO */ |
616 | if (read_lsr) { |
617 | lsr = sc16is7xx_port_read(port, SC16IS7XX_LSR_REG); |
618 | if (!(lsr & SC16IS7XX_LSR_FIFOE_BIT)) |
619 | read_lsr = false; /* No errors left in FIFO */ |
620 | } else |
621 | lsr = 0; |
622 | |
623 | if (read_lsr) { |
624 | s->buf[0] = sc16is7xx_port_read(port, SC16IS7XX_RHR_REG); |
625 | bytes_read = 1; |
626 | } else { |
627 | sc16is7xx_fifo_read(port, rxbuf: s->buf, rxlen); |
628 | bytes_read = rxlen; |
629 | } |
630 | |
631 | lsr &= SC16IS7XX_LSR_BRK_ERROR_MASK; |
632 | |
633 | port->icount.rx++; |
634 | flag = TTY_NORMAL; |
635 | |
636 | if (unlikely(lsr)) { |
637 | if (lsr & SC16IS7XX_LSR_BI_BIT) { |
638 | port->icount.brk++; |
639 | if (uart_handle_break(port)) |
640 | continue; |
641 | } else if (lsr & SC16IS7XX_LSR_PE_BIT) |
642 | port->icount.parity++; |
643 | else if (lsr & SC16IS7XX_LSR_FE_BIT) |
644 | port->icount.frame++; |
645 | else if (lsr & SC16IS7XX_LSR_OE_BIT) |
646 | port->icount.overrun++; |
647 | |
648 | lsr &= port->read_status_mask; |
649 | if (lsr & SC16IS7XX_LSR_BI_BIT) |
650 | flag = TTY_BREAK; |
651 | else if (lsr & SC16IS7XX_LSR_PE_BIT) |
652 | flag = TTY_PARITY; |
653 | else if (lsr & SC16IS7XX_LSR_FE_BIT) |
654 | flag = TTY_FRAME; |
655 | else if (lsr & SC16IS7XX_LSR_OE_BIT) |
656 | flag = TTY_OVERRUN; |
657 | } |
658 | |
659 | for (i = 0; i < bytes_read; ++i) { |
660 | ch = s->buf[i]; |
661 | if (uart_handle_sysrq_char(port, ch)) |
662 | continue; |
663 | |
664 | if (lsr & port->ignore_status_mask) |
665 | continue; |
666 | |
667 | uart_insert_char(port, status: lsr, SC16IS7XX_LSR_OE_BIT, ch, |
668 | flag); |
669 | } |
670 | rxlen -= bytes_read; |
671 | } |
672 | |
673 | tty_flip_buffer_push(port: &port->state->port); |
674 | } |
675 | |
676 | static void sc16is7xx_handle_tx(struct uart_port *port) |
677 | { |
678 | struct sc16is7xx_port *s = dev_get_drvdata(dev: port->dev); |
679 | struct circ_buf *xmit = &port->state->xmit; |
680 | unsigned int txlen, to_send, i; |
681 | unsigned long flags; |
682 | |
683 | if (unlikely(port->x_char)) { |
684 | sc16is7xx_port_write(port, SC16IS7XX_THR_REG, val: port->x_char); |
685 | port->icount.tx++; |
686 | port->x_char = 0; |
687 | return; |
688 | } |
689 | |
690 | if (uart_circ_empty(xmit) || uart_tx_stopped(port)) { |
691 | uart_port_lock_irqsave(up: port, flags: &flags); |
692 | sc16is7xx_stop_tx(port); |
693 | uart_port_unlock_irqrestore(up: port, flags); |
694 | return; |
695 | } |
696 | |
697 | /* Get length of data pending in circular buffer */ |
698 | to_send = uart_circ_chars_pending(xmit); |
699 | if (likely(to_send)) { |
700 | /* Limit to space available in TX FIFO */ |
701 | txlen = sc16is7xx_port_read(port, SC16IS7XX_TXLVL_REG); |
702 | if (txlen > SC16IS7XX_FIFO_SIZE) { |
703 | dev_err_ratelimited(port->dev, |
704 | "chip reports %d free bytes in TX fifo, but it only has %d" , |
705 | txlen, SC16IS7XX_FIFO_SIZE); |
706 | txlen = 0; |
707 | } |
708 | to_send = (to_send > txlen) ? txlen : to_send; |
709 | |
710 | /* Convert to linear buffer */ |
711 | for (i = 0; i < to_send; ++i) { |
712 | s->buf[i] = xmit->buf[xmit->tail]; |
713 | uart_xmit_advance(up: port, chars: 1); |
714 | } |
715 | |
716 | sc16is7xx_fifo_write(port, txbuf: s->buf, to_send); |
717 | } |
718 | |
719 | uart_port_lock_irqsave(up: port, flags: &flags); |
720 | if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) |
721 | uart_write_wakeup(port); |
722 | |
723 | if (uart_circ_empty(xmit)) |
724 | sc16is7xx_stop_tx(port); |
725 | else |
726 | sc16is7xx_ier_set(port, SC16IS7XX_IER_THRI_BIT); |
727 | uart_port_unlock_irqrestore(up: port, flags); |
728 | } |
729 | |
730 | static unsigned int sc16is7xx_get_hwmctrl(struct uart_port *port) |
731 | { |
732 | u8 msr = sc16is7xx_port_read(port, SC16IS7XX_MSR_REG); |
733 | unsigned int mctrl = 0; |
734 | |
735 | mctrl |= (msr & SC16IS7XX_MSR_CTS_BIT) ? TIOCM_CTS : 0; |
736 | mctrl |= (msr & SC16IS7XX_MSR_DSR_BIT) ? TIOCM_DSR : 0; |
737 | mctrl |= (msr & SC16IS7XX_MSR_CD_BIT) ? TIOCM_CAR : 0; |
738 | mctrl |= (msr & SC16IS7XX_MSR_RI_BIT) ? TIOCM_RNG : 0; |
739 | return mctrl; |
740 | } |
741 | |
742 | static void sc16is7xx_update_mlines(struct sc16is7xx_one *one) |
743 | { |
744 | struct uart_port *port = &one->port; |
745 | unsigned long flags; |
746 | unsigned int status, changed; |
747 | |
748 | lockdep_assert_held_once(&one->efr_lock); |
749 | |
750 | status = sc16is7xx_get_hwmctrl(port); |
751 | changed = status ^ one->old_mctrl; |
752 | |
753 | if (changed == 0) |
754 | return; |
755 | |
756 | one->old_mctrl = status; |
757 | |
758 | uart_port_lock_irqsave(up: port, flags: &flags); |
759 | if ((changed & TIOCM_RNG) && (status & TIOCM_RNG)) |
760 | port->icount.rng++; |
761 | if (changed & TIOCM_DSR) |
762 | port->icount.dsr++; |
763 | if (changed & TIOCM_CAR) |
764 | uart_handle_dcd_change(uport: port, active: status & TIOCM_CAR); |
765 | if (changed & TIOCM_CTS) |
766 | uart_handle_cts_change(uport: port, active: status & TIOCM_CTS); |
767 | |
768 | wake_up_interruptible(&port->state->port.delta_msr_wait); |
769 | uart_port_unlock_irqrestore(up: port, flags); |
770 | } |
771 | |
772 | static bool sc16is7xx_port_irq(struct sc16is7xx_port *s, int portno) |
773 | { |
774 | bool rc = true; |
775 | unsigned int iir, rxlen; |
776 | struct uart_port *port = &s->p[portno].port; |
777 | struct sc16is7xx_one *one = to_sc16is7xx_one(port, port); |
778 | |
779 | mutex_lock(&one->efr_lock); |
780 | |
781 | iir = sc16is7xx_port_read(port, SC16IS7XX_IIR_REG); |
782 | if (iir & SC16IS7XX_IIR_NO_INT_BIT) { |
783 | rc = false; |
784 | goto out_port_irq; |
785 | } |
786 | |
787 | iir &= SC16IS7XX_IIR_ID_MASK; |
788 | |
789 | switch (iir) { |
790 | case SC16IS7XX_IIR_RDI_SRC: |
791 | case SC16IS7XX_IIR_RLSE_SRC: |
792 | case SC16IS7XX_IIR_RTOI_SRC: |
793 | case SC16IS7XX_IIR_XOFFI_SRC: |
794 | rxlen = sc16is7xx_port_read(port, SC16IS7XX_RXLVL_REG); |
795 | |
796 | /* |
797 | * There is a silicon bug that makes the chip report a |
798 | * time-out interrupt but no data in the FIFO. This is |
799 | * described in errata section 18.1.4. |
800 | * |
801 | * When this happens, read one byte from the FIFO to |
802 | * clear the interrupt. |
803 | */ |
804 | if (iir == SC16IS7XX_IIR_RTOI_SRC && !rxlen) |
805 | rxlen = 1; |
806 | |
807 | if (rxlen) |
808 | sc16is7xx_handle_rx(port, rxlen, iir); |
809 | break; |
810 | /* CTSRTS interrupt comes only when CTS goes inactive */ |
811 | case SC16IS7XX_IIR_CTSRTS_SRC: |
812 | case SC16IS7XX_IIR_MSI_SRC: |
813 | sc16is7xx_update_mlines(one); |
814 | break; |
815 | case SC16IS7XX_IIR_THRI_SRC: |
816 | sc16is7xx_handle_tx(port); |
817 | break; |
818 | default: |
819 | dev_err_ratelimited(port->dev, |
820 | "ttySC%i: Unexpected interrupt: %x" , |
821 | port->line, iir); |
822 | break; |
823 | } |
824 | |
825 | out_port_irq: |
826 | mutex_unlock(lock: &one->efr_lock); |
827 | |
828 | return rc; |
829 | } |
830 | |
831 | static irqreturn_t sc16is7xx_irq(int irq, void *dev_id) |
832 | { |
833 | bool keep_polling; |
834 | |
835 | struct sc16is7xx_port *s = (struct sc16is7xx_port *)dev_id; |
836 | |
837 | do { |
838 | int i; |
839 | |
840 | keep_polling = false; |
841 | |
842 | for (i = 0; i < s->devtype->nr_uart; ++i) |
843 | keep_polling |= sc16is7xx_port_irq(s, portno: i); |
844 | } while (keep_polling); |
845 | |
846 | return IRQ_HANDLED; |
847 | } |
848 | |
849 | static void sc16is7xx_tx_proc(struct kthread_work *ws) |
850 | { |
851 | struct uart_port *port = &(to_sc16is7xx_one(ws, tx_work)->port); |
852 | struct sc16is7xx_one *one = to_sc16is7xx_one(port, port); |
853 | |
854 | if ((port->rs485.flags & SER_RS485_ENABLED) && |
855 | (port->rs485.delay_rts_before_send > 0)) |
856 | msleep(msecs: port->rs485.delay_rts_before_send); |
857 | |
858 | mutex_lock(&one->efr_lock); |
859 | sc16is7xx_handle_tx(port); |
860 | mutex_unlock(lock: &one->efr_lock); |
861 | } |
862 | |
863 | static void sc16is7xx_reconf_rs485(struct uart_port *port) |
864 | { |
865 | const u32 mask = SC16IS7XX_EFCR_AUTO_RS485_BIT | |
866 | SC16IS7XX_EFCR_RTS_INVERT_BIT; |
867 | u32 efcr = 0; |
868 | struct serial_rs485 *rs485 = &port->rs485; |
869 | unsigned long irqflags; |
870 | |
871 | uart_port_lock_irqsave(up: port, flags: &irqflags); |
872 | if (rs485->flags & SER_RS485_ENABLED) { |
873 | efcr |= SC16IS7XX_EFCR_AUTO_RS485_BIT; |
874 | |
875 | if (rs485->flags & SER_RS485_RTS_AFTER_SEND) |
876 | efcr |= SC16IS7XX_EFCR_RTS_INVERT_BIT; |
877 | } |
878 | uart_port_unlock_irqrestore(up: port, flags: irqflags); |
879 | |
880 | sc16is7xx_port_update(port, SC16IS7XX_EFCR_REG, mask, val: efcr); |
881 | } |
882 | |
883 | static void sc16is7xx_reg_proc(struct kthread_work *ws) |
884 | { |
885 | struct sc16is7xx_one *one = to_sc16is7xx_one(ws, reg_work); |
886 | struct sc16is7xx_one_config config; |
887 | unsigned long irqflags; |
888 | |
889 | uart_port_lock_irqsave(up: &one->port, flags: &irqflags); |
890 | config = one->config; |
891 | memset(&one->config, 0, sizeof(one->config)); |
892 | uart_port_unlock_irqrestore(up: &one->port, flags: irqflags); |
893 | |
894 | if (config.flags & SC16IS7XX_RECONF_MD) { |
895 | u8 mcr = 0; |
896 | |
897 | /* Device ignores RTS setting when hardware flow is enabled */ |
898 | if (one->port.mctrl & TIOCM_RTS) |
899 | mcr |= SC16IS7XX_MCR_RTS_BIT; |
900 | |
901 | if (one->port.mctrl & TIOCM_DTR) |
902 | mcr |= SC16IS7XX_MCR_DTR_BIT; |
903 | |
904 | if (one->port.mctrl & TIOCM_LOOP) |
905 | mcr |= SC16IS7XX_MCR_LOOP_BIT; |
906 | sc16is7xx_port_update(port: &one->port, SC16IS7XX_MCR_REG, |
907 | SC16IS7XX_MCR_RTS_BIT | |
908 | SC16IS7XX_MCR_DTR_BIT | |
909 | SC16IS7XX_MCR_LOOP_BIT, |
910 | val: mcr); |
911 | } |
912 | |
913 | if (config.flags & SC16IS7XX_RECONF_IER) |
914 | sc16is7xx_port_update(port: &one->port, SC16IS7XX_IER_REG, |
915 | mask: config.ier_mask, val: config.ier_val); |
916 | |
917 | if (config.flags & SC16IS7XX_RECONF_RS485) |
918 | sc16is7xx_reconf_rs485(port: &one->port); |
919 | } |
920 | |
921 | static void sc16is7xx_ms_proc(struct kthread_work *ws) |
922 | { |
923 | struct sc16is7xx_one *one = to_sc16is7xx_one(ws, ms_work.work); |
924 | struct sc16is7xx_port *s = dev_get_drvdata(dev: one->port.dev); |
925 | |
926 | if (one->port.state) { |
927 | mutex_lock(&one->efr_lock); |
928 | sc16is7xx_update_mlines(one); |
929 | mutex_unlock(lock: &one->efr_lock); |
930 | |
931 | kthread_queue_delayed_work(worker: &s->kworker, dwork: &one->ms_work, HZ); |
932 | } |
933 | } |
934 | |
935 | static void sc16is7xx_enable_ms(struct uart_port *port) |
936 | { |
937 | struct sc16is7xx_one *one = to_sc16is7xx_one(port, port); |
938 | struct sc16is7xx_port *s = dev_get_drvdata(dev: port->dev); |
939 | |
940 | lockdep_assert_held_once(&port->lock); |
941 | |
942 | kthread_queue_delayed_work(worker: &s->kworker, dwork: &one->ms_work, delay: 0); |
943 | } |
944 | |
945 | static void sc16is7xx_start_tx(struct uart_port *port) |
946 | { |
947 | struct sc16is7xx_port *s = dev_get_drvdata(dev: port->dev); |
948 | struct sc16is7xx_one *one = to_sc16is7xx_one(port, port); |
949 | |
950 | kthread_queue_work(worker: &s->kworker, work: &one->tx_work); |
951 | } |
952 | |
953 | static void sc16is7xx_throttle(struct uart_port *port) |
954 | { |
955 | unsigned long flags; |
956 | |
957 | /* |
958 | * Hardware flow control is enabled and thus the device ignores RTS |
959 | * value set in MCR register. Stop reading data from RX FIFO so the |
960 | * AutoRTS feature will de-activate RTS output. |
961 | */ |
962 | uart_port_lock_irqsave(up: port, flags: &flags); |
963 | sc16is7xx_ier_clear(port, SC16IS7XX_IER_RDI_BIT); |
964 | uart_port_unlock_irqrestore(up: port, flags); |
965 | } |
966 | |
967 | static void sc16is7xx_unthrottle(struct uart_port *port) |
968 | { |
969 | unsigned long flags; |
970 | |
971 | uart_port_lock_irqsave(up: port, flags: &flags); |
972 | sc16is7xx_ier_set(port, SC16IS7XX_IER_RDI_BIT); |
973 | uart_port_unlock_irqrestore(up: port, flags); |
974 | } |
975 | |
976 | static unsigned int sc16is7xx_tx_empty(struct uart_port *port) |
977 | { |
978 | unsigned int lsr; |
979 | |
980 | lsr = sc16is7xx_port_read(port, SC16IS7XX_LSR_REG); |
981 | |
982 | return (lsr & SC16IS7XX_LSR_TEMT_BIT) ? TIOCSER_TEMT : 0; |
983 | } |
984 | |
985 | static unsigned int sc16is7xx_get_mctrl(struct uart_port *port) |
986 | { |
987 | struct sc16is7xx_one *one = to_sc16is7xx_one(port, port); |
988 | |
989 | /* Called with port lock taken so we can only return cached value */ |
990 | return one->old_mctrl; |
991 | } |
992 | |
993 | static void sc16is7xx_set_mctrl(struct uart_port *port, unsigned int mctrl) |
994 | { |
995 | struct sc16is7xx_port *s = dev_get_drvdata(dev: port->dev); |
996 | struct sc16is7xx_one *one = to_sc16is7xx_one(port, port); |
997 | |
998 | one->config.flags |= SC16IS7XX_RECONF_MD; |
999 | kthread_queue_work(worker: &s->kworker, work: &one->reg_work); |
1000 | } |
1001 | |
1002 | static void sc16is7xx_break_ctl(struct uart_port *port, int break_state) |
1003 | { |
1004 | sc16is7xx_port_update(port, SC16IS7XX_LCR_REG, |
1005 | SC16IS7XX_LCR_TXBREAK_BIT, |
1006 | val: break_state ? SC16IS7XX_LCR_TXBREAK_BIT : 0); |
1007 | } |
1008 | |
1009 | static void sc16is7xx_set_termios(struct uart_port *port, |
1010 | struct ktermios *termios, |
1011 | const struct ktermios *old) |
1012 | { |
1013 | struct sc16is7xx_one *one = to_sc16is7xx_one(port, port); |
1014 | unsigned int lcr, flow = 0; |
1015 | int baud; |
1016 | unsigned long flags; |
1017 | |
1018 | kthread_cancel_delayed_work_sync(work: &one->ms_work); |
1019 | |
1020 | /* Mask termios capabilities we don't support */ |
1021 | termios->c_cflag &= ~CMSPAR; |
1022 | |
1023 | /* Word size */ |
1024 | switch (termios->c_cflag & CSIZE) { |
1025 | case CS5: |
1026 | lcr = SC16IS7XX_LCR_WORD_LEN_5; |
1027 | break; |
1028 | case CS6: |
1029 | lcr = SC16IS7XX_LCR_WORD_LEN_6; |
1030 | break; |
1031 | case CS7: |
1032 | lcr = SC16IS7XX_LCR_WORD_LEN_7; |
1033 | break; |
1034 | case CS8: |
1035 | lcr = SC16IS7XX_LCR_WORD_LEN_8; |
1036 | break; |
1037 | default: |
1038 | lcr = SC16IS7XX_LCR_WORD_LEN_8; |
1039 | termios->c_cflag &= ~CSIZE; |
1040 | termios->c_cflag |= CS8; |
1041 | break; |
1042 | } |
1043 | |
1044 | /* Parity */ |
1045 | if (termios->c_cflag & PARENB) { |
1046 | lcr |= SC16IS7XX_LCR_PARITY_BIT; |
1047 | if (!(termios->c_cflag & PARODD)) |
1048 | lcr |= SC16IS7XX_LCR_EVENPARITY_BIT; |
1049 | } |
1050 | |
1051 | /* Stop bits */ |
1052 | if (termios->c_cflag & CSTOPB) |
1053 | lcr |= SC16IS7XX_LCR_STOPLEN_BIT; /* 2 stops */ |
1054 | |
1055 | /* Set read status mask */ |
1056 | port->read_status_mask = SC16IS7XX_LSR_OE_BIT; |
1057 | if (termios->c_iflag & INPCK) |
1058 | port->read_status_mask |= SC16IS7XX_LSR_PE_BIT | |
1059 | SC16IS7XX_LSR_FE_BIT; |
1060 | if (termios->c_iflag & (BRKINT | PARMRK)) |
1061 | port->read_status_mask |= SC16IS7XX_LSR_BI_BIT; |
1062 | |
1063 | /* Set status ignore mask */ |
1064 | port->ignore_status_mask = 0; |
1065 | if (termios->c_iflag & IGNBRK) |
1066 | port->ignore_status_mask |= SC16IS7XX_LSR_BI_BIT; |
1067 | if (!(termios->c_cflag & CREAD)) |
1068 | port->ignore_status_mask |= SC16IS7XX_LSR_BRK_ERROR_MASK; |
1069 | |
1070 | /* Configure flow control */ |
1071 | port->status &= ~(UPSTAT_AUTOCTS | UPSTAT_AUTORTS); |
1072 | if (termios->c_cflag & CRTSCTS) { |
1073 | flow |= SC16IS7XX_EFR_AUTOCTS_BIT | |
1074 | SC16IS7XX_EFR_AUTORTS_BIT; |
1075 | port->status |= UPSTAT_AUTOCTS | UPSTAT_AUTORTS; |
1076 | } |
1077 | if (termios->c_iflag & IXON) |
1078 | flow |= SC16IS7XX_EFR_SWFLOW3_BIT; |
1079 | if (termios->c_iflag & IXOFF) |
1080 | flow |= SC16IS7XX_EFR_SWFLOW1_BIT; |
1081 | |
1082 | /* Update LCR register */ |
1083 | sc16is7xx_port_write(port, SC16IS7XX_LCR_REG, val: lcr); |
1084 | |
1085 | /* Update EFR registers */ |
1086 | sc16is7xx_efr_lock(port); |
1087 | sc16is7xx_port_write(port, SC16IS7XX_XON1_REG, val: termios->c_cc[VSTART]); |
1088 | sc16is7xx_port_write(port, SC16IS7XX_XOFF1_REG, val: termios->c_cc[VSTOP]); |
1089 | sc16is7xx_port_update(port, SC16IS7XX_EFR_REG, |
1090 | SC16IS7XX_EFR_FLOWCTRL_BITS, val: flow); |
1091 | sc16is7xx_efr_unlock(port); |
1092 | |
1093 | /* Get baud rate generator configuration */ |
1094 | baud = uart_get_baud_rate(port, termios, old, |
1095 | min: port->uartclk / 16 / 4 / 0xffff, |
1096 | max: port->uartclk / 16); |
1097 | |
1098 | /* Setup baudrate generator */ |
1099 | baud = sc16is7xx_set_baud(port, baud); |
1100 | |
1101 | uart_port_lock_irqsave(up: port, flags: &flags); |
1102 | |
1103 | /* Update timeout according to new baud rate */ |
1104 | uart_update_timeout(port, cflag: termios->c_cflag, baud); |
1105 | |
1106 | if (UART_ENABLE_MS(port, termios->c_cflag)) |
1107 | sc16is7xx_enable_ms(port); |
1108 | |
1109 | uart_port_unlock_irqrestore(up: port, flags); |
1110 | } |
1111 | |
1112 | static int sc16is7xx_config_rs485(struct uart_port *port, struct ktermios *termios, |
1113 | struct serial_rs485 *rs485) |
1114 | { |
1115 | struct sc16is7xx_port *s = dev_get_drvdata(dev: port->dev); |
1116 | struct sc16is7xx_one *one = to_sc16is7xx_one(port, port); |
1117 | |
1118 | if (rs485->flags & SER_RS485_ENABLED) { |
1119 | /* |
1120 | * RTS signal is handled by HW, it's timing can't be influenced. |
1121 | * However, it's sometimes useful to delay TX even without RTS |
1122 | * control therefore we try to handle .delay_rts_before_send. |
1123 | */ |
1124 | if (rs485->delay_rts_after_send) |
1125 | return -EINVAL; |
1126 | } |
1127 | |
1128 | one->config.flags |= SC16IS7XX_RECONF_RS485; |
1129 | kthread_queue_work(worker: &s->kworker, work: &one->reg_work); |
1130 | |
1131 | return 0; |
1132 | } |
1133 | |
1134 | static int sc16is7xx_startup(struct uart_port *port) |
1135 | { |
1136 | struct sc16is7xx_one *one = to_sc16is7xx_one(port, port); |
1137 | unsigned int val; |
1138 | unsigned long flags; |
1139 | |
1140 | sc16is7xx_power(port, on: 1); |
1141 | |
1142 | /* Reset FIFOs*/ |
1143 | val = SC16IS7XX_FCR_RXRESET_BIT | SC16IS7XX_FCR_TXRESET_BIT; |
1144 | sc16is7xx_port_write(port, SC16IS7XX_FCR_REG, val); |
1145 | udelay(5); |
1146 | sc16is7xx_port_write(port, SC16IS7XX_FCR_REG, |
1147 | SC16IS7XX_FCR_FIFO_BIT); |
1148 | |
1149 | /* Enable EFR */ |
1150 | sc16is7xx_port_write(port, SC16IS7XX_LCR_REG, |
1151 | SC16IS7XX_LCR_CONF_MODE_B); |
1152 | |
1153 | regcache_cache_bypass(map: one->regmap, enable: true); |
1154 | |
1155 | /* Enable write access to enhanced features and internal clock div */ |
1156 | sc16is7xx_port_update(port, SC16IS7XX_EFR_REG, |
1157 | SC16IS7XX_EFR_ENABLE_BIT, |
1158 | SC16IS7XX_EFR_ENABLE_BIT); |
1159 | |
1160 | /* Enable TCR/TLR */ |
1161 | sc16is7xx_port_update(port, SC16IS7XX_MCR_REG, |
1162 | SC16IS7XX_MCR_TCRTLR_BIT, |
1163 | SC16IS7XX_MCR_TCRTLR_BIT); |
1164 | |
1165 | /* Configure flow control levels */ |
1166 | /* Flow control halt level 48, resume level 24 */ |
1167 | sc16is7xx_port_write(port, SC16IS7XX_TCR_REG, |
1168 | SC16IS7XX_TCR_RX_RESUME(24) | |
1169 | SC16IS7XX_TCR_RX_HALT(48)); |
1170 | |
1171 | regcache_cache_bypass(map: one->regmap, enable: false); |
1172 | |
1173 | /* Now, initialize the UART */ |
1174 | sc16is7xx_port_write(port, SC16IS7XX_LCR_REG, SC16IS7XX_LCR_WORD_LEN_8); |
1175 | |
1176 | /* Enable IrDA mode if requested in DT */ |
1177 | /* This bit must be written with LCR[7] = 0 */ |
1178 | sc16is7xx_port_update(port, SC16IS7XX_MCR_REG, |
1179 | SC16IS7XX_MCR_IRDA_BIT, |
1180 | val: one->irda_mode ? |
1181 | SC16IS7XX_MCR_IRDA_BIT : 0); |
1182 | |
1183 | /* Enable the Rx and Tx FIFO */ |
1184 | sc16is7xx_port_update(port, SC16IS7XX_EFCR_REG, |
1185 | SC16IS7XX_EFCR_RXDISABLE_BIT | |
1186 | SC16IS7XX_EFCR_TXDISABLE_BIT, |
1187 | val: 0); |
1188 | |
1189 | /* Enable RX, CTS change and modem lines interrupts */ |
1190 | val = SC16IS7XX_IER_RDI_BIT | SC16IS7XX_IER_CTSI_BIT | |
1191 | SC16IS7XX_IER_MSI_BIT; |
1192 | sc16is7xx_port_write(port, SC16IS7XX_IER_REG, val); |
1193 | |
1194 | /* Enable modem status polling */ |
1195 | uart_port_lock_irqsave(up: port, flags: &flags); |
1196 | sc16is7xx_enable_ms(port); |
1197 | uart_port_unlock_irqrestore(up: port, flags); |
1198 | |
1199 | return 0; |
1200 | } |
1201 | |
1202 | static void sc16is7xx_shutdown(struct uart_port *port) |
1203 | { |
1204 | struct sc16is7xx_port *s = dev_get_drvdata(dev: port->dev); |
1205 | struct sc16is7xx_one *one = to_sc16is7xx_one(port, port); |
1206 | |
1207 | kthread_cancel_delayed_work_sync(work: &one->ms_work); |
1208 | |
1209 | /* Disable all interrupts */ |
1210 | sc16is7xx_port_write(port, SC16IS7XX_IER_REG, val: 0); |
1211 | /* Disable TX/RX */ |
1212 | sc16is7xx_port_update(port, SC16IS7XX_EFCR_REG, |
1213 | SC16IS7XX_EFCR_RXDISABLE_BIT | |
1214 | SC16IS7XX_EFCR_TXDISABLE_BIT, |
1215 | SC16IS7XX_EFCR_RXDISABLE_BIT | |
1216 | SC16IS7XX_EFCR_TXDISABLE_BIT); |
1217 | |
1218 | sc16is7xx_power(port, on: 0); |
1219 | |
1220 | kthread_flush_worker(worker: &s->kworker); |
1221 | } |
1222 | |
1223 | static const char *sc16is7xx_type(struct uart_port *port) |
1224 | { |
1225 | struct sc16is7xx_port *s = dev_get_drvdata(dev: port->dev); |
1226 | |
1227 | return (port->type == PORT_SC16IS7XX) ? s->devtype->name : NULL; |
1228 | } |
1229 | |
1230 | static int sc16is7xx_request_port(struct uart_port *port) |
1231 | { |
1232 | /* Do nothing */ |
1233 | return 0; |
1234 | } |
1235 | |
1236 | static void sc16is7xx_config_port(struct uart_port *port, int flags) |
1237 | { |
1238 | if (flags & UART_CONFIG_TYPE) |
1239 | port->type = PORT_SC16IS7XX; |
1240 | } |
1241 | |
1242 | static int sc16is7xx_verify_port(struct uart_port *port, |
1243 | struct serial_struct *s) |
1244 | { |
1245 | if ((s->type != PORT_UNKNOWN) && (s->type != PORT_SC16IS7XX)) |
1246 | return -EINVAL; |
1247 | if (s->irq != port->irq) |
1248 | return -EINVAL; |
1249 | |
1250 | return 0; |
1251 | } |
1252 | |
1253 | static void sc16is7xx_pm(struct uart_port *port, unsigned int state, |
1254 | unsigned int oldstate) |
1255 | { |
1256 | sc16is7xx_power(port, on: (state == UART_PM_STATE_ON) ? 1 : 0); |
1257 | } |
1258 | |
1259 | static void sc16is7xx_null_void(struct uart_port *port) |
1260 | { |
1261 | /* Do nothing */ |
1262 | } |
1263 | |
1264 | static const struct uart_ops sc16is7xx_ops = { |
1265 | .tx_empty = sc16is7xx_tx_empty, |
1266 | .set_mctrl = sc16is7xx_set_mctrl, |
1267 | .get_mctrl = sc16is7xx_get_mctrl, |
1268 | .stop_tx = sc16is7xx_stop_tx, |
1269 | .start_tx = sc16is7xx_start_tx, |
1270 | .throttle = sc16is7xx_throttle, |
1271 | .unthrottle = sc16is7xx_unthrottle, |
1272 | .stop_rx = sc16is7xx_stop_rx, |
1273 | .enable_ms = sc16is7xx_enable_ms, |
1274 | .break_ctl = sc16is7xx_break_ctl, |
1275 | .startup = sc16is7xx_startup, |
1276 | .shutdown = sc16is7xx_shutdown, |
1277 | .set_termios = sc16is7xx_set_termios, |
1278 | .type = sc16is7xx_type, |
1279 | .request_port = sc16is7xx_request_port, |
1280 | .release_port = sc16is7xx_null_void, |
1281 | .config_port = sc16is7xx_config_port, |
1282 | .verify_port = sc16is7xx_verify_port, |
1283 | .pm = sc16is7xx_pm, |
1284 | }; |
1285 | |
1286 | #ifdef CONFIG_GPIOLIB |
1287 | static int sc16is7xx_gpio_get(struct gpio_chip *chip, unsigned offset) |
1288 | { |
1289 | unsigned int val; |
1290 | struct sc16is7xx_port *s = gpiochip_get_data(gc: chip); |
1291 | struct uart_port *port = &s->p[0].port; |
1292 | |
1293 | val = sc16is7xx_port_read(port, SC16IS7XX_IOSTATE_REG); |
1294 | |
1295 | return !!(val & BIT(offset)); |
1296 | } |
1297 | |
1298 | static void sc16is7xx_gpio_set(struct gpio_chip *chip, unsigned offset, int val) |
1299 | { |
1300 | struct sc16is7xx_port *s = gpiochip_get_data(gc: chip); |
1301 | struct uart_port *port = &s->p[0].port; |
1302 | |
1303 | sc16is7xx_port_update(port, SC16IS7XX_IOSTATE_REG, BIT(offset), |
1304 | val: val ? BIT(offset) : 0); |
1305 | } |
1306 | |
1307 | static int sc16is7xx_gpio_direction_input(struct gpio_chip *chip, |
1308 | unsigned offset) |
1309 | { |
1310 | struct sc16is7xx_port *s = gpiochip_get_data(gc: chip); |
1311 | struct uart_port *port = &s->p[0].port; |
1312 | |
1313 | sc16is7xx_port_update(port, SC16IS7XX_IODIR_REG, BIT(offset), val: 0); |
1314 | |
1315 | return 0; |
1316 | } |
1317 | |
1318 | static int sc16is7xx_gpio_direction_output(struct gpio_chip *chip, |
1319 | unsigned offset, int val) |
1320 | { |
1321 | struct sc16is7xx_port *s = gpiochip_get_data(gc: chip); |
1322 | struct uart_port *port = &s->p[0].port; |
1323 | u8 state = sc16is7xx_port_read(port, SC16IS7XX_IOSTATE_REG); |
1324 | |
1325 | if (val) |
1326 | state |= BIT(offset); |
1327 | else |
1328 | state &= ~BIT(offset); |
1329 | |
1330 | /* |
1331 | * If we write IOSTATE first, and then IODIR, the output value is not |
1332 | * transferred to the corresponding I/O pin. |
1333 | * The datasheet states that each register bit will be transferred to |
1334 | * the corresponding I/O pin programmed as output when writing to |
1335 | * IOSTATE. Therefore, configure direction first with IODIR, and then |
1336 | * set value after with IOSTATE. |
1337 | */ |
1338 | sc16is7xx_port_update(port, SC16IS7XX_IODIR_REG, BIT(offset), |
1339 | BIT(offset)); |
1340 | sc16is7xx_port_write(port, SC16IS7XX_IOSTATE_REG, val: state); |
1341 | |
1342 | return 0; |
1343 | } |
1344 | |
1345 | static int sc16is7xx_gpio_init_valid_mask(struct gpio_chip *chip, |
1346 | unsigned long *valid_mask, |
1347 | unsigned int ngpios) |
1348 | { |
1349 | struct sc16is7xx_port *s = gpiochip_get_data(gc: chip); |
1350 | |
1351 | *valid_mask = s->gpio_valid_mask; |
1352 | |
1353 | return 0; |
1354 | } |
1355 | |
1356 | static int sc16is7xx_setup_gpio_chip(struct sc16is7xx_port *s) |
1357 | { |
1358 | struct device *dev = s->p[0].port.dev; |
1359 | |
1360 | if (!s->devtype->nr_gpio) |
1361 | return 0; |
1362 | |
1363 | switch (s->mctrl_mask) { |
1364 | case 0: |
1365 | s->gpio_valid_mask = GENMASK(7, 0); |
1366 | break; |
1367 | case SC16IS7XX_IOCONTROL_MODEM_A_BIT: |
1368 | s->gpio_valid_mask = GENMASK(3, 0); |
1369 | break; |
1370 | case SC16IS7XX_IOCONTROL_MODEM_B_BIT: |
1371 | s->gpio_valid_mask = GENMASK(7, 4); |
1372 | break; |
1373 | default: |
1374 | break; |
1375 | } |
1376 | |
1377 | if (s->gpio_valid_mask == 0) |
1378 | return 0; |
1379 | |
1380 | s->gpio.owner = THIS_MODULE; |
1381 | s->gpio.parent = dev; |
1382 | s->gpio.label = dev_name(dev); |
1383 | s->gpio.init_valid_mask = sc16is7xx_gpio_init_valid_mask; |
1384 | s->gpio.direction_input = sc16is7xx_gpio_direction_input; |
1385 | s->gpio.get = sc16is7xx_gpio_get; |
1386 | s->gpio.direction_output = sc16is7xx_gpio_direction_output; |
1387 | s->gpio.set = sc16is7xx_gpio_set; |
1388 | s->gpio.base = -1; |
1389 | s->gpio.ngpio = s->devtype->nr_gpio; |
1390 | s->gpio.can_sleep = 1; |
1391 | |
1392 | return gpiochip_add_data(&s->gpio, s); |
1393 | } |
1394 | #endif |
1395 | |
1396 | static void sc16is7xx_setup_irda_ports(struct sc16is7xx_port *s) |
1397 | { |
1398 | int i; |
1399 | int ret; |
1400 | int count; |
1401 | u32 irda_port[SC16IS7XX_MAX_PORTS]; |
1402 | struct device *dev = s->p[0].port.dev; |
1403 | |
1404 | count = device_property_count_u32(dev, propname: "irda-mode-ports" ); |
1405 | if (count < 0 || count > ARRAY_SIZE(irda_port)) |
1406 | return; |
1407 | |
1408 | ret = device_property_read_u32_array(dev, propname: "irda-mode-ports" , |
1409 | val: irda_port, nval: count); |
1410 | if (ret) |
1411 | return; |
1412 | |
1413 | for (i = 0; i < count; i++) { |
1414 | if (irda_port[i] < s->devtype->nr_uart) |
1415 | s->p[irda_port[i]].irda_mode = true; |
1416 | } |
1417 | } |
1418 | |
1419 | /* |
1420 | * Configure ports designated to operate as modem control lines. |
1421 | */ |
1422 | static int sc16is7xx_setup_mctrl_ports(struct sc16is7xx_port *s, |
1423 | struct regmap *regmap) |
1424 | { |
1425 | int i; |
1426 | int ret; |
1427 | int count; |
1428 | u32 mctrl_port[SC16IS7XX_MAX_PORTS]; |
1429 | struct device *dev = s->p[0].port.dev; |
1430 | |
1431 | count = device_property_count_u32(dev, propname: "nxp,modem-control-line-ports" ); |
1432 | if (count < 0 || count > ARRAY_SIZE(mctrl_port)) |
1433 | return 0; |
1434 | |
1435 | ret = device_property_read_u32_array(dev, propname: "nxp,modem-control-line-ports" , |
1436 | val: mctrl_port, nval: count); |
1437 | if (ret) |
1438 | return ret; |
1439 | |
1440 | s->mctrl_mask = 0; |
1441 | |
1442 | for (i = 0; i < count; i++) { |
1443 | /* Use GPIO lines as modem control lines */ |
1444 | if (mctrl_port[i] == 0) |
1445 | s->mctrl_mask |= SC16IS7XX_IOCONTROL_MODEM_A_BIT; |
1446 | else if (mctrl_port[i] == 1) |
1447 | s->mctrl_mask |= SC16IS7XX_IOCONTROL_MODEM_B_BIT; |
1448 | } |
1449 | |
1450 | if (s->mctrl_mask) |
1451 | regmap_update_bits( |
1452 | map: regmap, |
1453 | SC16IS7XX_IOCONTROL_REG, |
1454 | SC16IS7XX_IOCONTROL_MODEM_A_BIT | |
1455 | SC16IS7XX_IOCONTROL_MODEM_B_BIT, val: s->mctrl_mask); |
1456 | |
1457 | return 0; |
1458 | } |
1459 | |
1460 | static const struct serial_rs485 sc16is7xx_rs485_supported = { |
1461 | .flags = SER_RS485_ENABLED | SER_RS485_RTS_AFTER_SEND, |
1462 | .delay_rts_before_send = 1, |
1463 | .delay_rts_after_send = 1, /* Not supported but keep returning -EINVAL */ |
1464 | }; |
1465 | |
1466 | static int sc16is7xx_probe(struct device *dev, |
1467 | const struct sc16is7xx_devtype *devtype, |
1468 | struct regmap *regmaps[], int irq) |
1469 | { |
1470 | unsigned long freq = 0, *pfreq = dev_get_platdata(dev); |
1471 | unsigned int val; |
1472 | u32 uartclk = 0; |
1473 | int i, ret; |
1474 | struct sc16is7xx_port *s; |
1475 | |
1476 | for (i = 0; i < devtype->nr_uart; i++) |
1477 | if (IS_ERR(ptr: regmaps[i])) |
1478 | return PTR_ERR(ptr: regmaps[i]); |
1479 | |
1480 | /* |
1481 | * This device does not have an identification register that would |
1482 | * tell us if we are really connected to the correct device. |
1483 | * The best we can do is to check if communication is at all possible. |
1484 | * |
1485 | * Note: regmap[0] is used in the probe function to access registers |
1486 | * common to all channels/ports, as it is guaranteed to be present on |
1487 | * all variants. |
1488 | */ |
1489 | ret = regmap_read(map: regmaps[0], SC16IS7XX_LSR_REG, val: &val); |
1490 | if (ret < 0) |
1491 | return -EPROBE_DEFER; |
1492 | |
1493 | /* Alloc port structure */ |
1494 | s = devm_kzalloc(dev, struct_size(s, p, devtype->nr_uart), GFP_KERNEL); |
1495 | if (!s) { |
1496 | dev_err(dev, "Error allocating port structure\n" ); |
1497 | return -ENOMEM; |
1498 | } |
1499 | |
1500 | /* Always ask for fixed clock rate from a property. */ |
1501 | device_property_read_u32(dev, propname: "clock-frequency" , val: &uartclk); |
1502 | |
1503 | s->clk = devm_clk_get_optional(dev, NULL); |
1504 | if (IS_ERR(ptr: s->clk)) |
1505 | return PTR_ERR(ptr: s->clk); |
1506 | |
1507 | ret = clk_prepare_enable(clk: s->clk); |
1508 | if (ret) |
1509 | return ret; |
1510 | |
1511 | freq = clk_get_rate(clk: s->clk); |
1512 | if (freq == 0) { |
1513 | if (uartclk) |
1514 | freq = uartclk; |
1515 | if (pfreq) |
1516 | freq = *pfreq; |
1517 | if (freq) |
1518 | dev_dbg(dev, "Clock frequency: %luHz\n" , freq); |
1519 | else |
1520 | return -EINVAL; |
1521 | } |
1522 | |
1523 | s->devtype = devtype; |
1524 | dev_set_drvdata(dev, data: s); |
1525 | |
1526 | kthread_init_worker(&s->kworker); |
1527 | s->kworker_task = kthread_run(kthread_worker_fn, &s->kworker, |
1528 | "sc16is7xx" ); |
1529 | if (IS_ERR(ptr: s->kworker_task)) { |
1530 | ret = PTR_ERR(ptr: s->kworker_task); |
1531 | goto out_clk; |
1532 | } |
1533 | sched_set_fifo(p: s->kworker_task); |
1534 | |
1535 | /* reset device, purging any pending irq / data */ |
1536 | regmap_write(map: regmaps[0], SC16IS7XX_IOCONTROL_REG, |
1537 | SC16IS7XX_IOCONTROL_SRESET_BIT); |
1538 | |
1539 | for (i = 0; i < devtype->nr_uart; ++i) { |
1540 | s->p[i].port.line = find_first_zero_bit(addr: sc16is7xx_lines, |
1541 | SC16IS7XX_MAX_DEVS); |
1542 | if (s->p[i].port.line >= SC16IS7XX_MAX_DEVS) { |
1543 | ret = -ERANGE; |
1544 | goto out_ports; |
1545 | } |
1546 | |
1547 | /* Initialize port data */ |
1548 | s->p[i].port.dev = dev; |
1549 | s->p[i].port.irq = irq; |
1550 | s->p[i].port.type = PORT_SC16IS7XX; |
1551 | s->p[i].port.fifosize = SC16IS7XX_FIFO_SIZE; |
1552 | s->p[i].port.flags = UPF_FIXED_TYPE | UPF_LOW_LATENCY; |
1553 | s->p[i].port.iobase = i; |
1554 | /* |
1555 | * Use all ones as membase to make sure uart_configure_port() in |
1556 | * serial_core.c does not abort for SPI/I2C devices where the |
1557 | * membase address is not applicable. |
1558 | */ |
1559 | s->p[i].port.membase = (void __iomem *)~0; |
1560 | s->p[i].port.iotype = UPIO_PORT; |
1561 | s->p[i].port.uartclk = freq; |
1562 | s->p[i].port.rs485_config = sc16is7xx_config_rs485; |
1563 | s->p[i].port.rs485_supported = sc16is7xx_rs485_supported; |
1564 | s->p[i].port.ops = &sc16is7xx_ops; |
1565 | s->p[i].old_mctrl = 0; |
1566 | s->p[i].regmap = regmaps[i]; |
1567 | |
1568 | mutex_init(&s->p[i].efr_lock); |
1569 | |
1570 | ret = uart_get_rs485_mode(port: &s->p[i].port); |
1571 | if (ret) |
1572 | goto out_ports; |
1573 | |
1574 | /* Disable all interrupts */ |
1575 | sc16is7xx_port_write(port: &s->p[i].port, SC16IS7XX_IER_REG, val: 0); |
1576 | /* Disable TX/RX */ |
1577 | sc16is7xx_port_write(port: &s->p[i].port, SC16IS7XX_EFCR_REG, |
1578 | SC16IS7XX_EFCR_RXDISABLE_BIT | |
1579 | SC16IS7XX_EFCR_TXDISABLE_BIT); |
1580 | |
1581 | /* Initialize kthread work structs */ |
1582 | kthread_init_work(&s->p[i].tx_work, sc16is7xx_tx_proc); |
1583 | kthread_init_work(&s->p[i].reg_work, sc16is7xx_reg_proc); |
1584 | kthread_init_delayed_work(&s->p[i].ms_work, sc16is7xx_ms_proc); |
1585 | |
1586 | /* Register port */ |
1587 | ret = uart_add_one_port(reg: &sc16is7xx_uart, port: &s->p[i].port); |
1588 | if (ret) |
1589 | goto out_ports; |
1590 | |
1591 | set_bit(nr: s->p[i].port.line, addr: sc16is7xx_lines); |
1592 | |
1593 | /* Enable EFR */ |
1594 | sc16is7xx_port_write(port: &s->p[i].port, SC16IS7XX_LCR_REG, |
1595 | SC16IS7XX_LCR_CONF_MODE_B); |
1596 | |
1597 | regcache_cache_bypass(map: regmaps[i], enable: true); |
1598 | |
1599 | /* Enable write access to enhanced features */ |
1600 | sc16is7xx_port_write(port: &s->p[i].port, SC16IS7XX_EFR_REG, |
1601 | SC16IS7XX_EFR_ENABLE_BIT); |
1602 | |
1603 | regcache_cache_bypass(map: regmaps[i], enable: false); |
1604 | |
1605 | /* Restore access to general registers */ |
1606 | sc16is7xx_port_write(port: &s->p[i].port, SC16IS7XX_LCR_REG, val: 0x00); |
1607 | |
1608 | /* Go to suspend mode */ |
1609 | sc16is7xx_power(port: &s->p[i].port, on: 0); |
1610 | } |
1611 | |
1612 | sc16is7xx_setup_irda_ports(s); |
1613 | |
1614 | ret = sc16is7xx_setup_mctrl_ports(s, regmap: regmaps[0]); |
1615 | if (ret) |
1616 | goto out_ports; |
1617 | |
1618 | #ifdef CONFIG_GPIOLIB |
1619 | ret = sc16is7xx_setup_gpio_chip(s); |
1620 | if (ret) |
1621 | goto out_ports; |
1622 | #endif |
1623 | |
1624 | /* |
1625 | * Setup interrupt. We first try to acquire the IRQ line as level IRQ. |
1626 | * If that succeeds, we can allow sharing the interrupt as well. |
1627 | * In case the interrupt controller doesn't support that, we fall |
1628 | * back to a non-shared falling-edge trigger. |
1629 | */ |
1630 | ret = devm_request_threaded_irq(dev, irq, NULL, thread_fn: sc16is7xx_irq, |
1631 | IRQF_TRIGGER_LOW | IRQF_SHARED | |
1632 | IRQF_ONESHOT, |
1633 | devname: dev_name(dev), dev_id: s); |
1634 | if (!ret) |
1635 | return 0; |
1636 | |
1637 | ret = devm_request_threaded_irq(dev, irq, NULL, thread_fn: sc16is7xx_irq, |
1638 | IRQF_TRIGGER_FALLING | IRQF_ONESHOT, |
1639 | devname: dev_name(dev), dev_id: s); |
1640 | if (!ret) |
1641 | return 0; |
1642 | |
1643 | #ifdef CONFIG_GPIOLIB |
1644 | if (s->gpio_valid_mask) |
1645 | gpiochip_remove(gc: &s->gpio); |
1646 | #endif |
1647 | |
1648 | out_ports: |
1649 | for (i = 0; i < devtype->nr_uart; i++) |
1650 | if (test_and_clear_bit(nr: s->p[i].port.line, addr: sc16is7xx_lines)) |
1651 | uart_remove_one_port(reg: &sc16is7xx_uart, port: &s->p[i].port); |
1652 | |
1653 | kthread_stop(k: s->kworker_task); |
1654 | |
1655 | out_clk: |
1656 | clk_disable_unprepare(clk: s->clk); |
1657 | |
1658 | return ret; |
1659 | } |
1660 | |
1661 | static void sc16is7xx_remove(struct device *dev) |
1662 | { |
1663 | struct sc16is7xx_port *s = dev_get_drvdata(dev); |
1664 | int i; |
1665 | |
1666 | #ifdef CONFIG_GPIOLIB |
1667 | if (s->gpio_valid_mask) |
1668 | gpiochip_remove(gc: &s->gpio); |
1669 | #endif |
1670 | |
1671 | for (i = 0; i < s->devtype->nr_uart; i++) { |
1672 | kthread_cancel_delayed_work_sync(work: &s->p[i].ms_work); |
1673 | if (test_and_clear_bit(nr: s->p[i].port.line, addr: sc16is7xx_lines)) |
1674 | uart_remove_one_port(reg: &sc16is7xx_uart, port: &s->p[i].port); |
1675 | sc16is7xx_power(port: &s->p[i].port, on: 0); |
1676 | } |
1677 | |
1678 | kthread_flush_worker(worker: &s->kworker); |
1679 | kthread_stop(k: s->kworker_task); |
1680 | |
1681 | clk_disable_unprepare(clk: s->clk); |
1682 | } |
1683 | |
1684 | static const struct of_device_id __maybe_unused sc16is7xx_dt_ids[] = { |
1685 | { .compatible = "nxp,sc16is740" , .data = &sc16is74x_devtype, }, |
1686 | { .compatible = "nxp,sc16is741" , .data = &sc16is74x_devtype, }, |
1687 | { .compatible = "nxp,sc16is750" , .data = &sc16is750_devtype, }, |
1688 | { .compatible = "nxp,sc16is752" , .data = &sc16is752_devtype, }, |
1689 | { .compatible = "nxp,sc16is760" , .data = &sc16is760_devtype, }, |
1690 | { .compatible = "nxp,sc16is762" , .data = &sc16is762_devtype, }, |
1691 | { } |
1692 | }; |
1693 | MODULE_DEVICE_TABLE(of, sc16is7xx_dt_ids); |
1694 | |
1695 | static struct regmap_config regcfg = { |
1696 | .reg_bits = 5, |
1697 | .pad_bits = 3, |
1698 | .val_bits = 8, |
1699 | .cache_type = REGCACHE_RBTREE, |
1700 | .volatile_reg = sc16is7xx_regmap_volatile, |
1701 | .precious_reg = sc16is7xx_regmap_precious, |
1702 | .writeable_noinc_reg = sc16is7xx_regmap_noinc, |
1703 | .readable_noinc_reg = sc16is7xx_regmap_noinc, |
1704 | .max_raw_read = SC16IS7XX_FIFO_SIZE, |
1705 | .max_raw_write = SC16IS7XX_FIFO_SIZE, |
1706 | .max_register = SC16IS7XX_EFCR_REG, |
1707 | }; |
1708 | |
1709 | static const char *sc16is7xx_regmap_name(u8 port_id) |
1710 | { |
1711 | switch (port_id) { |
1712 | case 0: return "port0" ; |
1713 | case 1: return "port1" ; |
1714 | default: |
1715 | WARN_ON(true); |
1716 | return NULL; |
1717 | } |
1718 | } |
1719 | |
1720 | static unsigned int sc16is7xx_regmap_port_mask(unsigned int port_id) |
1721 | { |
1722 | /* CH1,CH0 are at bits 2:1. */ |
1723 | return port_id << 1; |
1724 | } |
1725 | |
1726 | #ifdef CONFIG_SERIAL_SC16IS7XX_SPI |
1727 | static int sc16is7xx_spi_probe(struct spi_device *spi) |
1728 | { |
1729 | const struct sc16is7xx_devtype *devtype; |
1730 | struct regmap *regmaps[SC16IS7XX_MAX_PORTS]; |
1731 | unsigned int i; |
1732 | int ret; |
1733 | |
1734 | /* Setup SPI bus */ |
1735 | spi->bits_per_word = 8; |
1736 | /* For all variants, only mode 0 is supported */ |
1737 | if ((spi->mode & SPI_MODE_X_MASK) != SPI_MODE_0) |
1738 | return dev_err_probe(dev: &spi->dev, err: -EINVAL, fmt: "Unsupported SPI mode\n" ); |
1739 | |
1740 | spi->mode = spi->mode ? : SPI_MODE_0; |
1741 | spi->max_speed_hz = spi->max_speed_hz ? : 4 * HZ_PER_MHZ; |
1742 | ret = spi_setup(spi); |
1743 | if (ret) |
1744 | return ret; |
1745 | |
1746 | devtype = spi_get_device_match_data(sdev: spi); |
1747 | if (!devtype) |
1748 | return dev_err_probe(dev: &spi->dev, err: -ENODEV, fmt: "Failed to match device\n" ); |
1749 | |
1750 | for (i = 0; i < devtype->nr_uart; i++) { |
1751 | regcfg.name = sc16is7xx_regmap_name(port_id: i); |
1752 | /* |
1753 | * If read_flag_mask is 0, the regmap code sets it to a default |
1754 | * of 0x80. Since we specify our own mask, we must add the READ |
1755 | * bit ourselves: |
1756 | */ |
1757 | regcfg.read_flag_mask = sc16is7xx_regmap_port_mask(port_id: i) | |
1758 | SC16IS7XX_SPI_READ_BIT; |
1759 | regcfg.write_flag_mask = sc16is7xx_regmap_port_mask(port_id: i); |
1760 | regmaps[i] = devm_regmap_init_spi(spi, ®cfg); |
1761 | } |
1762 | |
1763 | return sc16is7xx_probe(dev: &spi->dev, devtype, regmaps, irq: spi->irq); |
1764 | } |
1765 | |
1766 | static void sc16is7xx_spi_remove(struct spi_device *spi) |
1767 | { |
1768 | sc16is7xx_remove(dev: &spi->dev); |
1769 | } |
1770 | |
1771 | static const struct spi_device_id sc16is7xx_spi_id_table[] = { |
1772 | { "sc16is74x" , (kernel_ulong_t)&sc16is74x_devtype, }, |
1773 | { "sc16is740" , (kernel_ulong_t)&sc16is74x_devtype, }, |
1774 | { "sc16is741" , (kernel_ulong_t)&sc16is74x_devtype, }, |
1775 | { "sc16is750" , (kernel_ulong_t)&sc16is750_devtype, }, |
1776 | { "sc16is752" , (kernel_ulong_t)&sc16is752_devtype, }, |
1777 | { "sc16is760" , (kernel_ulong_t)&sc16is760_devtype, }, |
1778 | { "sc16is762" , (kernel_ulong_t)&sc16is762_devtype, }, |
1779 | { } |
1780 | }; |
1781 | |
1782 | MODULE_DEVICE_TABLE(spi, sc16is7xx_spi_id_table); |
1783 | |
1784 | static struct spi_driver sc16is7xx_spi_uart_driver = { |
1785 | .driver = { |
1786 | .name = SC16IS7XX_NAME, |
1787 | .of_match_table = sc16is7xx_dt_ids, |
1788 | }, |
1789 | .probe = sc16is7xx_spi_probe, |
1790 | .remove = sc16is7xx_spi_remove, |
1791 | .id_table = sc16is7xx_spi_id_table, |
1792 | }; |
1793 | #endif |
1794 | |
1795 | #ifdef CONFIG_SERIAL_SC16IS7XX_I2C |
1796 | static int sc16is7xx_i2c_probe(struct i2c_client *i2c) |
1797 | { |
1798 | const struct sc16is7xx_devtype *devtype; |
1799 | struct regmap *regmaps[SC16IS7XX_MAX_PORTS]; |
1800 | unsigned int i; |
1801 | |
1802 | devtype = i2c_get_match_data(client: i2c); |
1803 | if (!devtype) |
1804 | return dev_err_probe(dev: &i2c->dev, err: -ENODEV, fmt: "Failed to match device\n" ); |
1805 | |
1806 | for (i = 0; i < devtype->nr_uart; i++) { |
1807 | regcfg.name = sc16is7xx_regmap_name(port_id: i); |
1808 | regcfg.read_flag_mask = sc16is7xx_regmap_port_mask(port_id: i); |
1809 | regcfg.write_flag_mask = sc16is7xx_regmap_port_mask(port_id: i); |
1810 | regmaps[i] = devm_regmap_init_i2c(i2c, ®cfg); |
1811 | } |
1812 | |
1813 | return sc16is7xx_probe(dev: &i2c->dev, devtype, regmaps, irq: i2c->irq); |
1814 | } |
1815 | |
1816 | static void sc16is7xx_i2c_remove(struct i2c_client *client) |
1817 | { |
1818 | sc16is7xx_remove(dev: &client->dev); |
1819 | } |
1820 | |
1821 | static const struct i2c_device_id sc16is7xx_i2c_id_table[] = { |
1822 | { "sc16is74x" , (kernel_ulong_t)&sc16is74x_devtype, }, |
1823 | { "sc16is740" , (kernel_ulong_t)&sc16is74x_devtype, }, |
1824 | { "sc16is741" , (kernel_ulong_t)&sc16is74x_devtype, }, |
1825 | { "sc16is750" , (kernel_ulong_t)&sc16is750_devtype, }, |
1826 | { "sc16is752" , (kernel_ulong_t)&sc16is752_devtype, }, |
1827 | { "sc16is760" , (kernel_ulong_t)&sc16is760_devtype, }, |
1828 | { "sc16is762" , (kernel_ulong_t)&sc16is762_devtype, }, |
1829 | { } |
1830 | }; |
1831 | MODULE_DEVICE_TABLE(i2c, sc16is7xx_i2c_id_table); |
1832 | |
1833 | static struct i2c_driver sc16is7xx_i2c_uart_driver = { |
1834 | .driver = { |
1835 | .name = SC16IS7XX_NAME, |
1836 | .of_match_table = sc16is7xx_dt_ids, |
1837 | }, |
1838 | .probe = sc16is7xx_i2c_probe, |
1839 | .remove = sc16is7xx_i2c_remove, |
1840 | .id_table = sc16is7xx_i2c_id_table, |
1841 | }; |
1842 | |
1843 | #endif |
1844 | |
1845 | static int __init sc16is7xx_init(void) |
1846 | { |
1847 | int ret; |
1848 | |
1849 | ret = uart_register_driver(uart: &sc16is7xx_uart); |
1850 | if (ret) { |
1851 | pr_err("Registering UART driver failed\n" ); |
1852 | return ret; |
1853 | } |
1854 | |
1855 | #ifdef CONFIG_SERIAL_SC16IS7XX_I2C |
1856 | ret = i2c_add_driver(&sc16is7xx_i2c_uart_driver); |
1857 | if (ret < 0) { |
1858 | pr_err("failed to init sc16is7xx i2c --> %d\n" , ret); |
1859 | goto err_i2c; |
1860 | } |
1861 | #endif |
1862 | |
1863 | #ifdef CONFIG_SERIAL_SC16IS7XX_SPI |
1864 | ret = spi_register_driver(&sc16is7xx_spi_uart_driver); |
1865 | if (ret < 0) { |
1866 | pr_err("failed to init sc16is7xx spi --> %d\n" , ret); |
1867 | goto err_spi; |
1868 | } |
1869 | #endif |
1870 | return ret; |
1871 | |
1872 | #ifdef CONFIG_SERIAL_SC16IS7XX_SPI |
1873 | err_spi: |
1874 | #endif |
1875 | #ifdef CONFIG_SERIAL_SC16IS7XX_I2C |
1876 | i2c_del_driver(driver: &sc16is7xx_i2c_uart_driver); |
1877 | err_i2c: |
1878 | #endif |
1879 | uart_unregister_driver(uart: &sc16is7xx_uart); |
1880 | return ret; |
1881 | } |
1882 | module_init(sc16is7xx_init); |
1883 | |
1884 | static void __exit sc16is7xx_exit(void) |
1885 | { |
1886 | #ifdef CONFIG_SERIAL_SC16IS7XX_I2C |
1887 | i2c_del_driver(driver: &sc16is7xx_i2c_uart_driver); |
1888 | #endif |
1889 | |
1890 | #ifdef CONFIG_SERIAL_SC16IS7XX_SPI |
1891 | spi_unregister_driver(sdrv: &sc16is7xx_spi_uart_driver); |
1892 | #endif |
1893 | uart_unregister_driver(uart: &sc16is7xx_uart); |
1894 | } |
1895 | module_exit(sc16is7xx_exit); |
1896 | |
1897 | MODULE_LICENSE("GPL" ); |
1898 | MODULE_AUTHOR("Jon Ringle <jringle@gridpoint.com>" ); |
1899 | MODULE_DESCRIPTION("SC16IS7XX serial driver" ); |
1900 | |