| 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
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| 2 | /* |
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| 3 | * bits.h - register bits of the ChipIdea USB IP core |
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| 4 | * |
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| 5 | * Copyright (C) 2008 Chipidea - MIPS Technologies, Inc. All rights reserved. |
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| 6 | * |
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| 7 | * Author: David Lopo |
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| 8 | */ |
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| 9 | |
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| 10 | #ifndef __DRIVERS_USB_CHIPIDEA_BITS_H |
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| 11 | #define __DRIVERS_USB_CHIPIDEA_BITS_H |
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| 12 | |
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| 13 | #include <linux/usb/ehci_def.h> |
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| 14 | |
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| 15 | /* |
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| 16 | * ID |
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| 17 | * For 1.x revision, bit24 - bit31 are reserved |
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| 18 | * For 2.x revision, bit25 - bit28 are 0x2 |
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| 19 | */ |
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| 20 | #define TAG (0x1F << 16) |
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| 21 | #define REVISION (0xF << 21) |
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| 22 | #define VERSION (0xF << 25) |
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| 23 | #define CIVERSION (0x7 << 29) |
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| 24 | |
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| 25 | /* SBUSCFG */ |
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| 26 | #define AHBBRST_MASK 0x7 |
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| 27 | |
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| 28 | /* HCCPARAMS */ |
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| 29 | #define HCCPARAMS_LEN BIT(17) |
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| 30 | |
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| 31 | /* DCCPARAMS */ |
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| 32 | #define DCCPARAMS_DEN (0x1F << 0) |
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| 33 | #define DCCPARAMS_DC BIT(7) |
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| 34 | #define DCCPARAMS_HC BIT(8) |
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| 35 | |
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| 36 | /* TESTMODE */ |
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| 37 | #define TESTMODE_FORCE BIT(0) |
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| 38 | |
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| 39 | /* USBCMD */ |
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| 40 | #define USBCMD_RS BIT(0) |
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| 41 | #define USBCMD_RST BIT(1) |
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| 42 | #define USBCMD_SUTW BIT(13) |
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| 43 | #define USBCMD_ATDTW BIT(14) |
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| 44 | |
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| 45 | /* USBSTS & USBINTR */ |
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| 46 | #define USBi_UI BIT(0) |
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| 47 | #define USBi_UEI BIT(1) |
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| 48 | #define USBi_PCI BIT(2) |
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| 49 | #define USBi_URI BIT(6) |
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| 50 | #define USBi_SLI BIT(8) |
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| 51 | |
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| 52 | /* DEVICEADDR */ |
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| 53 | #define DEVICEADDR_USBADRA BIT(24) |
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| 54 | #define DEVICEADDR_USBADR (0x7FUL << 25) |
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| 55 | |
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| 56 | /* TTCTRL */ |
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| 57 | #define TTCTRL_TTHA_MASK (0x7fUL << 24) |
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| 58 | /* Set non-zero value for internal TT Hub address representation */ |
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| 59 | #define TTCTRL_TTHA (0x7fUL << 24) |
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| 60 | |
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| 61 | /* BURSTSIZE */ |
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| 62 | #define RX_BURST_MASK 0xff |
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| 63 | #define TX_BURST_MASK 0xff00 |
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| 64 | |
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| 65 | /* PORTSC */ |
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| 66 | #define PORTSC_CCS BIT(0) |
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| 67 | #define PORTSC_CSC BIT(1) |
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| 68 | #define PORTSC_PEC BIT(3) |
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| 69 | #define PORTSC_OCC BIT(5) |
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| 70 | #define PORTSC_FPR BIT(6) |
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| 71 | #define PORTSC_SUSP BIT(7) |
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| 72 | #define PORTSC_HSP BIT(9) |
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| 73 | #define PORTSC_PP BIT(12) |
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| 74 | #define PORTSC_PTC (0x0FUL << 16) |
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| 75 | #define PORTSC_WKCN BIT(20) |
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| 76 | #define PORTSC_PHCD(d) ((d) ? BIT(22) : BIT(23)) |
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| 77 | /* PTS and PTW for non lpm version only */ |
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| 78 | #define PORTSC_PFSC BIT(24) |
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| 79 | #define PORTSC_PTS(d) \ |
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| 80 | (u32)((((d) & 0x3) << 30) | (((d) & 0x4) ? BIT(25) : 0)) |
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| 81 | #define PORTSC_PTW BIT(28) |
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| 82 | #define PORTSC_STS BIT(29) |
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| 83 | |
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| 84 | #define PORTSC_W1C_BITS \ |
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| 85 | (PORTSC_CSC | PORTSC_PEC | PORTSC_OCC) |
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| 86 | |
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| 87 | /* DEVLC */ |
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| 88 | #define DEVLC_PFSC BIT(23) |
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| 89 | #define DEVLC_PSPD (0x03UL << 25) |
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| 90 | #define DEVLC_PSPD_HS (0x02UL << 25) |
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| 91 | #define DEVLC_PTW BIT(27) |
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| 92 | #define DEVLC_STS BIT(28) |
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| 93 | #define DEVLC_PTS(d) (u32)(((d) & 0x7) << 29) |
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| 94 | |
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| 95 | /* Encoding for DEVLC_PTS and PORTSC_PTS */ |
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| 96 | #define PTS_UTMI 0 |
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| 97 | #define PTS_ULPI 2 |
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| 98 | #define PTS_SERIAL 3 |
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| 99 | #define PTS_HSIC 4 |
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| 100 | |
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| 101 | /* OTGSC */ |
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| 102 | #define OTGSC_IDPU BIT(5) |
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| 103 | #define OTGSC_HADP BIT(6) |
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| 104 | #define OTGSC_HABA BIT(7) |
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| 105 | #define OTGSC_ID BIT(8) |
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| 106 | #define OTGSC_AVV BIT(9) |
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| 107 | #define OTGSC_ASV BIT(10) |
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| 108 | #define OTGSC_BSV BIT(11) |
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| 109 | #define OTGSC_BSE BIT(12) |
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| 110 | #define OTGSC_IDIS BIT(16) |
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| 111 | #define OTGSC_AVVIS BIT(17) |
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| 112 | #define OTGSC_ASVIS BIT(18) |
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| 113 | #define OTGSC_BSVIS BIT(19) |
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| 114 | #define OTGSC_BSEIS BIT(20) |
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| 115 | #define OTGSC_1MSIS BIT(21) |
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| 116 | #define OTGSC_DPIS BIT(22) |
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| 117 | #define OTGSC_IDIE BIT(24) |
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| 118 | #define OTGSC_AVVIE BIT(25) |
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| 119 | #define OTGSC_ASVIE BIT(26) |
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| 120 | #define OTGSC_BSVIE BIT(27) |
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| 121 | #define OTGSC_BSEIE BIT(28) |
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| 122 | #define OTGSC_1MSIE BIT(29) |
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| 123 | #define OTGSC_DPIE BIT(30) |
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| 124 | #define OTGSC_INT_EN_BITS (OTGSC_IDIE | OTGSC_AVVIE | OTGSC_ASVIE \ |
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| 125 | | OTGSC_BSVIE | OTGSC_BSEIE | OTGSC_1MSIE \ |
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| 126 | | OTGSC_DPIE) |
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| 127 | #define OTGSC_INT_STATUS_BITS (OTGSC_IDIS | OTGSC_AVVIS | OTGSC_ASVIS \ |
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| 128 | | OTGSC_BSVIS | OTGSC_BSEIS | OTGSC_1MSIS \ |
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| 129 | | OTGSC_DPIS) |
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| 130 | |
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| 131 | /* USBMODE */ |
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| 132 | #define USBMODE_CM (0x03UL << 0) |
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| 133 | #define USBMODE_CM_DC (0x02UL << 0) |
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| 134 | #define USBMODE_SLOM BIT(3) |
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| 135 | #define USBMODE_CI_SDIS BIT(4) |
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| 136 | |
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| 137 | /* ENDPTCTRL */ |
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| 138 | #define ENDPTCTRL_RXS BIT(0) |
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| 139 | #define ENDPTCTRL_RXT (0x03UL << 2) |
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| 140 | #define ENDPTCTRL_RXR BIT(6) /* reserved for port 0 */ |
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| 141 | #define ENDPTCTRL_RXE BIT(7) |
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| 142 | #define ENDPTCTRL_TXS BIT(16) |
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| 143 | #define ENDPTCTRL_TXT (0x03UL << 18) |
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| 144 | #define ENDPTCTRL_TXR BIT(22) /* reserved for port 0 */ |
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| 145 | #define ENDPTCTRL_TXE BIT(23) |
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| 146 | |
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| 147 | #endif /* __DRIVERS_USB_CHIPIDEA_BITS_H */ |
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| 148 | |
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