1	// SPDX-License-Identifier: GPL-2.0
2	/*
3	* core.c - ChipIdea USB IP core family device controller
4	*
5	* Copyright (C) 2008 Chipidea - MIPS Technologies, Inc. All rights reserved.
6	* Copyright (C) 2020 NXP
7	*
8	* Author: David Lopo
9	* Peter Chen <peter.chen@nxp.com>
10	*
11	* Main Features:
12	* - Four transfers are supported, usbtest is passed
13	* - USB Certification for gadget: CH9 and Mass Storage are passed
14	* - Low power mode
15	* - USB wakeup
16	*/
17	#include <linux/delay.h>
18	#include <linux/device.h>
19	#include <linux/dma-mapping.h>
20	#include <linux/extcon.h>
21	#include <linux/phy/phy.h>
22	#include <linux/platform_device.h>
23	#include <linux/module.h>
24	#include <linux/idr.h>
25	#include <linux/interrupt.h>
26	#include <linux/io.h>
27	#include <linux/kernel.h>
28	#include <linux/slab.h>
29	#include <linux/pm_runtime.h>
30	#include <linux/pinctrl/consumer.h>
31	#include <linux/usb/ch9.h>
32	#include <linux/usb/gadget.h>
33	#include <linux/usb/otg.h>
34	#include <linux/usb/chipidea.h>
35	#include <linux/usb/of.h>
36	#include <linux/of.h>
37	#include <linux/regulator/consumer.h>
38	#include <linux/usb/ehci_def.h>
39
40	#include "ci.h"
41	#include "udc.h"
42	#include "bits.h"
43	#include "host.h"
44	#include "otg.h"
45	#include "otg_fsm.h"
46
47	/* Controller register map */
48	static const u8 ci_regs_nolpm[] = {
49	[CAP_CAPLENGTH] = 0x00U,
50	[CAP_HCCPARAMS] = 0x08U,
51	[CAP_DCCPARAMS] = 0x24U,
52	[CAP_TESTMODE] = 0x38U,
53	[OP_USBCMD] = 0x00U,
54	[OP_USBSTS] = 0x04U,
55	[OP_USBINTR] = 0x08U,
56	[OP_FRINDEX] = 0x0CU,
57	[OP_DEVICEADDR] = 0x14U,
58	[OP_ENDPTLISTADDR] = 0x18U,
59	[OP_TTCTRL] = 0x1CU,
60	[OP_BURSTSIZE] = 0x20U,
61	[OP_ULPI_VIEWPORT] = 0x30U,
62	[OP_PORTSC] = 0x44U,
63	[OP_DEVLC] = 0x84U,
64	[OP_OTGSC] = 0x64U,
65	[OP_USBMODE] = 0x68U,
66	[OP_ENDPTSETUPSTAT] = 0x6CU,
67	[OP_ENDPTPRIME] = 0x70U,
68	[OP_ENDPTFLUSH] = 0x74U,
69	[OP_ENDPTSTAT] = 0x78U,
70	[OP_ENDPTCOMPLETE] = 0x7CU,
71	[OP_ENDPTCTRL] = 0x80U,
72	};
73
74	static const u8 ci_regs_lpm[] = {
75	[CAP_CAPLENGTH] = 0x00U,
76	[CAP_HCCPARAMS] = 0x08U,
77	[CAP_DCCPARAMS] = 0x24U,
78	[CAP_TESTMODE] = 0xFCU,
79	[OP_USBCMD] = 0x00U,
80	[OP_USBSTS] = 0x04U,
81	[OP_USBINTR] = 0x08U,
82	[OP_FRINDEX] = 0x0CU,
83	[OP_DEVICEADDR] = 0x14U,
84	[OP_ENDPTLISTADDR] = 0x18U,
85	[OP_TTCTRL] = 0x1CU,
86	[OP_BURSTSIZE] = 0x20U,
87	[OP_ULPI_VIEWPORT] = 0x30U,
88	[OP_PORTSC] = 0x44U,
89	[OP_DEVLC] = 0x84U,
90	[OP_OTGSC] = 0xC4U,
91	[OP_USBMODE] = 0xC8U,
92	[OP_ENDPTSETUPSTAT] = 0xD8U,
93	[OP_ENDPTPRIME] = 0xDCU,
94	[OP_ENDPTFLUSH] = 0xE0U,
95	[OP_ENDPTSTAT] = 0xE4U,
96	[OP_ENDPTCOMPLETE] = 0xE8U,
97	[OP_ENDPTCTRL] = 0xECU,
98	};
99
100	static void hw_alloc_regmap(struct ci_hdrc *ci, bool is_lpm)
101	{
102	int i;
103
104	for (i = 0; i < OP_ENDPTCTRL; i++)
105	ci->hw_bank.regmap[i] =
106	(i <= CAP_LAST ? ci->hw_bank.cap : ci->hw_bank.op) +
107	(is_lpm ? ci_regs_lpm[i] : ci_regs_nolpm[i]);
108
109	for (; i <= OP_LAST; i++)
110	ci->hw_bank.regmap[i] = ci->hw_bank.op +
111	4 * (i - OP_ENDPTCTRL) +
112	(is_lpm
113	? ci_regs_lpm[OP_ENDPTCTRL]
114	: ci_regs_nolpm[OP_ENDPTCTRL]);
115
116	}
117
118	static enum ci_revision ci_get_revision(struct ci_hdrc *ci)
119	{
120	int ver = hw_read_id_reg(ci, ID_ID, VERSION) >> __ffs(VERSION);
121	enum ci_revision rev = CI_REVISION_UNKNOWN;
122
123	if (ver == 0x2) {
124	rev = hw_read_id_reg(ci, ID_ID, REVISION)
125	>> __ffs(REVISION);
126	rev += CI_REVISION_20;
127	} else if (ver == 0x0) {
128	rev = CI_REVISION_1X;
129	}
130
131	return rev;
132	}
133
134	/**
135	* hw_read_intr_enable: returns interrupt enable register
136	*
137	* @ci: the controller
138	*
139	* This function returns register data
140	*/
141	u32 hw_read_intr_enable(struct ci_hdrc *ci)
142	{
143	return hw_read(ci, reg: OP_USBINTR, mask: ~0);
144	}
145
146	/**
147	* hw_read_intr_status: returns interrupt status register
148	*
149	* @ci: the controller
150	*
151	* This function returns register data
152	*/
153	u32 hw_read_intr_status(struct ci_hdrc *ci)
154	{
155	return hw_read(ci, reg: OP_USBSTS, mask: ~0);
156	}
157
158	/**
159	* hw_port_test_set: writes port test mode (execute without interruption)
160	* @ci: the controller
161	* @mode: new value
162	*
163	* This function returns an error code
164	*/
165	int hw_port_test_set(struct ci_hdrc *ci, u8 mode)
166	{
167	const u8 TEST_MODE_MAX = 7;
168
169	if (mode > TEST_MODE_MAX)
170	return -EINVAL;
171
172	hw_write(ci, reg: OP_PORTSC, PORTSC_PTC, data: mode << __ffs(PORTSC_PTC));
173	return 0;
174	}
175
176	/**
177	* hw_port_test_get: reads port test mode value
178	*
179	* @ci: the controller
180	*
181	* This function returns port test mode value
182	*/
183	u8 hw_port_test_get(struct ci_hdrc *ci)
184	{
185	return hw_read(ci, reg: OP_PORTSC, PORTSC_PTC) >> __ffs(PORTSC_PTC);
186	}
187
188	static void hw_wait_phy_stable(void)
189	{
190	/*
191	* The phy needs some delay to output the stable status from low
192	* power mode. And for OTGSC, the status inputs are debounced
193	* using a 1 ms time constant, so, delay 2ms for controller to get
194	* the stable status, like vbus and id when the phy leaves low power.
195	*/
196	usleep_range(min: 2000, max: 2500);
197	}
198
199	/* The PHY enters/leaves low power mode */
200	static void ci_hdrc_enter_lpm_common(struct ci_hdrc *ci, bool enable)
201	{
202	enum ci_hw_regs reg = ci->hw_bank.lpm ? OP_DEVLC : OP_PORTSC;
203	bool lpm = !!(hw_read(ci, reg, PORTSC_PHCD(ci->hw_bank.lpm)));
204
205	if (enable && !lpm)
206	hw_write(ci, reg, PORTSC_PHCD(ci->hw_bank.lpm),
207	PORTSC_PHCD(ci->hw_bank.lpm));
208	else if (!enable && lpm)
209	hw_write(ci, reg, PORTSC_PHCD(ci->hw_bank.lpm),
210	data: 0);
211	}
212
213	static void ci_hdrc_enter_lpm(struct ci_hdrc *ci, bool enable)
214	{
215	return ci->platdata->enter_lpm(ci, enable);
216	}
217
218	static int hw_device_init(struct ci_hdrc *ci, void __iomem *base)
219	{
220	u32 reg;
221
222	/* bank is a module variable */
223	ci->hw_bank.abs = base;
224
225	ci->hw_bank.cap = ci->hw_bank.abs;
226	ci->hw_bank.cap += ci->platdata->capoffset;
227	ci->hw_bank.op = ci->hw_bank.cap + (ioread32(ci->hw_bank.cap) & 0xff);
228
229	hw_alloc_regmap(ci, is_lpm: false);
230	reg = hw_read(ci, reg: CAP_HCCPARAMS, HCCPARAMS_LEN) >>
231	__ffs(HCCPARAMS_LEN);
232	ci->hw_bank.lpm = reg;
233	if (reg)
234	hw_alloc_regmap(ci, is_lpm: !!reg);
235	ci->hw_bank.size = ci->hw_bank.op - ci->hw_bank.abs;
236	ci->hw_bank.size += OP_LAST;
237	ci->hw_bank.size /= sizeof(u32);
238
239	reg = hw_read(ci, reg: CAP_DCCPARAMS, DCCPARAMS_DEN) >>
240	__ffs(DCCPARAMS_DEN);
241	ci->hw_ep_max = reg * 2; /* cache hw ENDPT_MAX */
242
243	if (ci->hw_ep_max > ENDPT_MAX)
244	return -ENODEV;
245
246	ci_hdrc_enter_lpm(ci, enable: false);
247
248	/* Disable all interrupts bits */
249	hw_write(ci, reg: OP_USBINTR, mask: 0xffffffff, data: 0);
250
251	/* Clear all interrupts status bits*/
252	hw_write(ci, reg: OP_USBSTS, mask: 0xffffffff, data: 0xffffffff);
253
254	ci->rev = ci_get_revision(ci);
255
256	dev_dbg(ci->dev,
257	"revision: %d, lpm: %d; cap: %px op: %px\n",
258	ci->rev, ci->hw_bank.lpm, ci->hw_bank.cap, ci->hw_bank.op);
259
260	/* setup lock mode ? */
261
262	/* ENDPTSETUPSTAT is '0' by default */
263
264	/* HCSPARAMS.bf.ppc SHOULD BE zero for device */
265
266	return 0;
267	}
268
269	void hw_phymode_configure(struct ci_hdrc *ci)
270	{
271	u32 portsc, lpm, sts = 0;
272
273	switch (ci->platdata->phy_mode) {
274	case USBPHY_INTERFACE_MODE_UTMI:
275	portsc = PORTSC_PTS(PTS_UTMI);
276	lpm = DEVLC_PTS(PTS_UTMI);
277	break;
278	case USBPHY_INTERFACE_MODE_UTMIW:
279	portsc = PORTSC_PTS(PTS_UTMI) | PORTSC_PTW;
280	lpm = DEVLC_PTS(PTS_UTMI) | DEVLC_PTW;
281	break;
282	case USBPHY_INTERFACE_MODE_ULPI:
283	portsc = PORTSC_PTS(PTS_ULPI);
284	lpm = DEVLC_PTS(PTS_ULPI);
285	break;
286	case USBPHY_INTERFACE_MODE_SERIAL:
287	portsc = PORTSC_PTS(PTS_SERIAL);
288	lpm = DEVLC_PTS(PTS_SERIAL);
289	sts = 1;
290	break;
291	case USBPHY_INTERFACE_MODE_HSIC:
292	portsc = PORTSC_PTS(PTS_HSIC);
293	lpm = DEVLC_PTS(PTS_HSIC);
294	break;
295	default:
296	return;
297	}
298
299	if (ci->hw_bank.lpm) {
300	hw_write(ci, reg: OP_DEVLC, DEVLC_PTS(7) | DEVLC_PTW, data: lpm);
301	if (sts)
302	hw_write(ci, reg: OP_DEVLC, DEVLC_STS, DEVLC_STS);
303	} else {
304	hw_write(ci, reg: OP_PORTSC, PORTSC_PTS(7) | PORTSC_PTW, data: portsc);
305	if (sts)
306	hw_write(ci, reg: OP_PORTSC, PORTSC_STS, PORTSC_STS);
307	}
308	}
309	EXPORT_SYMBOL_GPL(hw_phymode_configure);
310
311	/**
312	* _ci_usb_phy_init: initialize phy taking in account both phy and usb_phy
313	* interfaces
314	* @ci: the controller
315	*
316	* This function returns an error code if the phy failed to init
317	*/
318	static int _ci_usb_phy_init(struct ci_hdrc *ci)
319	{
320	int ret;
321
322	if (ci->phy) {
323	ret = phy_init(phy: ci->phy);
324	if (ret)
325	return ret;
326
327	ret = phy_power_on(phy: ci->phy);
328	if (ret) {
329	phy_exit(phy: ci->phy);
330	return ret;
331	}
332	} else {
333	ret = usb_phy_init(x: ci->usb_phy);
334	}
335
336	return ret;
337	}
338
339	/**
340	* ci_usb_phy_exit: deinitialize phy taking in account both phy and usb_phy
341	* interfaces
342	* @ci: the controller
343	*/
344	static void ci_usb_phy_exit(struct ci_hdrc *ci)
345	{
346	if (ci->platdata->flags & CI_HDRC_OVERRIDE_PHY_CONTROL)
347	return;
348
349	if (ci->phy) {
350	phy_power_off(phy: ci->phy);
351	phy_exit(phy: ci->phy);
352	} else {
353	usb_phy_shutdown(x: ci->usb_phy);
354	}
355	}
356
357	/**
358	* ci_usb_phy_init: initialize phy according to different phy type
359	* @ci: the controller
360	*
361	* This function returns an error code if usb_phy_init has failed
362	*/
363	static int ci_usb_phy_init(struct ci_hdrc *ci)
364	{
365	int ret;
366
367	if (ci->platdata->flags & CI_HDRC_OVERRIDE_PHY_CONTROL)
368	return 0;
369
370	switch (ci->platdata->phy_mode) {
371	case USBPHY_INTERFACE_MODE_UTMI:
372	case USBPHY_INTERFACE_MODE_UTMIW:
373	case USBPHY_INTERFACE_MODE_HSIC:
374	ret = _ci_usb_phy_init(ci);
375	if (!ret)
376	hw_wait_phy_stable();
377	else
378	return ret;
379	hw_phymode_configure(ci);
380	break;
381	case USBPHY_INTERFACE_MODE_ULPI:
382	case USBPHY_INTERFACE_MODE_SERIAL:
383	hw_phymode_configure(ci);
384	ret = _ci_usb_phy_init(ci);
385	if (ret)
386	return ret;
387	break;
388	default:
389	ret = _ci_usb_phy_init(ci);
390	if (!ret)
391	hw_wait_phy_stable();
392	}
393
394	return ret;
395	}
396
397
398	/**
399	* ci_platform_configure: do controller configure
400	* @ci: the controller
401	*
402	*/
403	void ci_platform_configure(struct ci_hdrc *ci)
404	{
405	bool is_device_mode, is_host_mode;
406
407	is_device_mode = hw_read(ci, reg: OP_USBMODE, USBMODE_CM) == USBMODE_CM_DC;
408	is_host_mode = hw_read(ci, reg: OP_USBMODE, USBMODE_CM) == USBMODE_CM_HC;
409
410	if (is_device_mode) {
411	phy_set_mode(ci->phy, PHY_MODE_USB_DEVICE);
412
413	if (ci->platdata->flags & CI_HDRC_DISABLE_DEVICE_STREAMING)
414	hw_write(ci, reg: OP_USBMODE, USBMODE_CI_SDIS,
415	USBMODE_CI_SDIS);
416	}
417
418	if (is_host_mode) {
419	phy_set_mode(ci->phy, PHY_MODE_USB_HOST);
420
421	if (ci->platdata->flags & CI_HDRC_DISABLE_HOST_STREAMING)
422	hw_write(ci, reg: OP_USBMODE, USBMODE_CI_SDIS,
423	USBMODE_CI_SDIS);
424	}
425
426	if (ci->platdata->flags & CI_HDRC_FORCE_FULLSPEED) {
427	if (ci->hw_bank.lpm)
428	hw_write(ci, reg: OP_DEVLC, DEVLC_PFSC, DEVLC_PFSC);
429	else
430	hw_write(ci, reg: OP_PORTSC, PORTSC_PFSC, PORTSC_PFSC);
431	}
432
433	if (ci->platdata->flags & CI_HDRC_SET_NON_ZERO_TTHA)
434	hw_write(ci, reg: OP_TTCTRL, TTCTRL_TTHA_MASK, TTCTRL_TTHA);
435
436	hw_write(ci, reg: OP_USBCMD, mask: 0xff0000, data: ci->platdata->itc_setting << 16);
437
438	if (ci->platdata->flags & CI_HDRC_OVERRIDE_AHB_BURST)
439	hw_write_id_reg(ci, ID_SBUSCFG, AHBBRST_MASK,
440	data: ci->platdata->ahb_burst_config);
441
442	/* override burst size, take effect only when ahb_burst_config is 0 */
443	if (!hw_read_id_reg(ci, ID_SBUSCFG, AHBBRST_MASK)) {
444	if (ci->platdata->flags & CI_HDRC_OVERRIDE_TX_BURST)
445	hw_write(ci, reg: OP_BURSTSIZE, TX_BURST_MASK,
446	data: ci->platdata->tx_burst_size << __ffs(TX_BURST_MASK));
447
448	if (ci->platdata->flags & CI_HDRC_OVERRIDE_RX_BURST)
449	hw_write(ci, reg: OP_BURSTSIZE, RX_BURST_MASK,
450	data: ci->platdata->rx_burst_size);
451	}
452	}
453
454	/**
455	* hw_controller_reset: do controller reset
456	* @ci: the controller
457	*
458	* This function returns an error code
459	*/
460	static int hw_controller_reset(struct ci_hdrc *ci)
461	{
462	int count = 0;
463
464	hw_write(ci, reg: OP_USBCMD, USBCMD_RST, USBCMD_RST);
465	while (hw_read(ci, reg: OP_USBCMD, USBCMD_RST)) {
466	udelay(10);
467	if (count++ > 1000)
468	return -ETIMEDOUT;
469	}
470
471	return 0;
472	}
473
474	/**
475	* hw_device_reset: resets chip (execute without interruption)
476	* @ci: the controller
477	*
478	* This function returns an error code
479	*/
480	int hw_device_reset(struct ci_hdrc *ci)
481	{
482	int ret;
483
484	/* should flush & stop before reset */
485	hw_write(ci, reg: OP_ENDPTFLUSH, mask: ~0, data: ~0);
486	hw_write(ci, reg: OP_USBCMD, USBCMD_RS, data: 0);
487
488	ret = hw_controller_reset(ci);
489	if (ret) {
490	dev_err(ci->dev, "error resetting controller, ret=%d\n", ret);
491	return ret;
492	}
493
494	if (ci->platdata->notify_event) {
495	ret = ci->platdata->notify_event(ci,
496	CI_HDRC_CONTROLLER_RESET_EVENT);
497	if (ret)
498	return ret;
499	}
500
501	/* USBMODE should be configured step by step */
502	hw_write(ci, reg: OP_USBMODE, USBMODE_CM, USBMODE_CM_IDLE);
503	hw_write(ci, reg: OP_USBMODE, USBMODE_CM, USBMODE_CM_DC);
504	/* HW >= 2.3 */
505	hw_write(ci, reg: OP_USBMODE, USBMODE_SLOM, USBMODE_SLOM);
506
507	if (hw_read(ci, reg: OP_USBMODE, USBMODE_CM) != USBMODE_CM_DC) {
508	dev_err(ci->dev, "cannot enter in %s device mode\n",
509	ci_role(ci)->name);
510	dev_err(ci->dev, "lpm = %i\n", ci->hw_bank.lpm);
511	return -ENODEV;
512	}
513
514	ci_platform_configure(ci);
515
516	return 0;
517	}
518
519	static irqreturn_t ci_irq_handler(int irq, void *data)
520	{
521	struct ci_hdrc *ci = data;
522	irqreturn_t ret = IRQ_NONE;
523	u32 otgsc = 0;
524
525	if (ci->in_lpm) {
526	disable_irq_nosync(irq);
527	ci->wakeup_int = true;
528	pm_runtime_get(dev: ci->dev);
529	return IRQ_HANDLED;
530	}
531
532	if (ci->is_otg) {
533	otgsc = hw_read_otgsc(ci, mask: ~0);
534	if (ci_otg_is_fsm_mode(ci)) {
535	ret = ci_otg_fsm_irq(ci);
536	if (ret == IRQ_HANDLED)
537	return ret;
538	}
539	}
540
541	/*
542	* Handle id change interrupt, it indicates device/host function
543	* switch.
544	*/
545	if (ci->is_otg && (otgsc & OTGSC_IDIE) && (otgsc & OTGSC_IDIS)) {
546	ci->id_event = true;
547	/* Clear ID change irq status */
548	hw_write_otgsc(ci, OTGSC_IDIS, OTGSC_IDIS);
549	ci_otg_queue_work(ci);
550	return IRQ_HANDLED;
551	}
552
553	/*
554	* Handle vbus change interrupt, it indicates device connection
555	* and disconnection events.
556	*/
557	if (ci->is_otg && (otgsc & OTGSC_BSVIE) && (otgsc & OTGSC_BSVIS)) {
558	ci->b_sess_valid_event = true;
559	/* Clear BSV irq */
560	hw_write_otgsc(ci, OTGSC_BSVIS, OTGSC_BSVIS);
561	ci_otg_queue_work(ci);
562	return IRQ_HANDLED;
563	}
564
565	/* Handle device/host interrupt */
566	if (ci->role != CI_ROLE_END)
567	ret = ci_role(ci)->irq(ci);
568
569	return ret;
570	}
571
572	static void ci_irq(struct ci_hdrc *ci)
573	{
574	unsigned long flags;
575
576	local_irq_save(flags);
577	ci_irq_handler(irq: ci->irq, data: ci);
578	local_irq_restore(flags);
579	}
580
581	static int ci_cable_notifier(struct notifier_block *nb, unsigned long event,
582	void *ptr)
583	{
584	struct ci_hdrc_cable *cbl = container_of(nb, struct ci_hdrc_cable, nb);
585	struct ci_hdrc *ci = cbl->ci;
586
587	cbl->connected = event;
588	cbl->changed = true;
589
590	ci_irq(ci);
591	return NOTIFY_DONE;
592	}
593
594	static enum usb_role ci_usb_role_switch_get(struct usb_role_switch *sw)
595	{
596	struct ci_hdrc *ci = usb_role_switch_get_drvdata(sw);
597	enum usb_role role;
598	unsigned long flags;
599
600	spin_lock_irqsave(&ci->lock, flags);
601	role = ci_role_to_usb_role(ci);
602	spin_unlock_irqrestore(lock: &ci->lock, flags);
603
604	return role;
605	}
606
607	static int ci_usb_role_switch_set(struct usb_role_switch *sw,
608	enum usb_role role)
609	{
610	struct ci_hdrc *ci = usb_role_switch_get_drvdata(sw);
611	struct ci_hdrc_cable *cable;
612
613	if (role == USB_ROLE_HOST) {
614	cable = &ci->platdata->id_extcon;
615	cable->changed = true;
616	cable->connected = true;
617	cable = &ci->platdata->vbus_extcon;
618	cable->changed = true;
619	cable->connected = false;
620	} else if (role == USB_ROLE_DEVICE) {
621	cable = &ci->platdata->id_extcon;
622	cable->changed = true;
623	cable->connected = false;
624	cable = &ci->platdata->vbus_extcon;
625	cable->changed = true;
626	cable->connected = true;
627	} else {
628	cable = &ci->platdata->id_extcon;
629	cable->changed = true;
630	cable->connected = false;
631	cable = &ci->platdata->vbus_extcon;
632	cable->changed = true;
633	cable->connected = false;
634	}
635
636	ci_irq(ci);
637	return 0;
638	}
639
640	static enum ci_role ci_get_role(struct ci_hdrc *ci)
641	{
642	enum ci_role role;
643
644	if (ci->roles[CI_ROLE_HOST] && ci->roles[CI_ROLE_GADGET]) {
645	if (ci->is_otg) {
646	role = ci_otg_role(ci);
647	hw_write_otgsc(ci, OTGSC_IDIE, OTGSC_IDIE);
648	} else {
649	/*
650	* If the controller is not OTG capable, but support
651	* role switch, the defalt role is gadget, and the
652	* user can switch it through debugfs.
653	*/
654	role = CI_ROLE_GADGET;
655	}
656	} else {
657	role = ci->roles[CI_ROLE_HOST] ? CI_ROLE_HOST
658	: CI_ROLE_GADGET;
659	}
660
661	return role;
662	}
663
664	static struct usb_role_switch_desc ci_role_switch = {
665	.set = ci_usb_role_switch_set,
666	.get = ci_usb_role_switch_get,
667	.allow_userspace_control = true,
668	};
669
670	static int ci_get_platdata(struct device *dev,
671	struct ci_hdrc_platform_data *platdata)
672	{
673	struct extcon_dev *ext_vbus, *ext_id;
674	struct ci_hdrc_cable *cable;
675	int ret;
676
677	if (!platdata->phy_mode)
678	platdata->phy_mode = of_usb_get_phy_mode(np: dev->of_node);
679
680	if (!platdata->dr_mode)
681	platdata->dr_mode = usb_get_dr_mode(dev);
682
683	if (platdata->dr_mode == USB_DR_MODE_UNKNOWN)
684	platdata->dr_mode = USB_DR_MODE_OTG;
685
686	if (platdata->dr_mode != USB_DR_MODE_PERIPHERAL) {
687	/* Get the vbus regulator */
688	platdata->reg_vbus = devm_regulator_get_optional(dev, id: "vbus");
689	if (PTR_ERR(ptr: platdata->reg_vbus) == -EPROBE_DEFER) {
690	return -EPROBE_DEFER;
691	} else if (PTR_ERR(ptr: platdata->reg_vbus) == -ENODEV) {
692	/* no vbus regulator is needed */
693	platdata->reg_vbus = NULL;
694	} else if (IS_ERR(ptr: platdata->reg_vbus)) {
695	dev_err(dev, "Getting regulator error: %ld\n",
696	PTR_ERR(platdata->reg_vbus));
697	return PTR_ERR(ptr: platdata->reg_vbus);
698	}
699	/* Get TPL support */
700	if (!platdata->tpl_support)
701	platdata->tpl_support =
702	of_usb_host_tpl_support(np: dev->of_node);
703	}
704
705	if (platdata->dr_mode == USB_DR_MODE_OTG) {
706	/* We can support HNP and SRP of OTG 2.0 */
707	platdata->ci_otg_caps.otg_rev = 0x0200;
708	platdata->ci_otg_caps.hnp_support = true;
709	platdata->ci_otg_caps.srp_support = true;
710
711	/* Update otg capabilities by DT properties */
712	ret = of_usb_update_otg_caps(np: dev->of_node,
713	otg_caps: &platdata->ci_otg_caps);
714	if (ret)
715	return ret;
716	}
717
718	if (usb_get_maximum_speed(dev) == USB_SPEED_FULL)
719	platdata->flags |= CI_HDRC_FORCE_FULLSPEED;
720
721	of_property_read_u32(np: dev->of_node, propname: "phy-clkgate-delay-us",
722	out_value: &platdata->phy_clkgate_delay_us);
723
724	platdata->itc_setting = 1;
725
726	of_property_read_u32(np: dev->of_node, propname: "itc-setting",
727	out_value: &platdata->itc_setting);
728
729	ret = of_property_read_u32(np: dev->of_node, propname: "ahb-burst-config",
730	out_value: &platdata->ahb_burst_config);
731	if (!ret) {
732	platdata->flags |= CI_HDRC_OVERRIDE_AHB_BURST;
733	} else if (ret != -EINVAL) {
734	dev_err(dev, "failed to get ahb-burst-config\n");
735	return ret;
736	}
737
738	ret = of_property_read_u32(np: dev->of_node, propname: "tx-burst-size-dword",
739	out_value: &platdata->tx_burst_size);
740	if (!ret) {
741	platdata->flags |= CI_HDRC_OVERRIDE_TX_BURST;
742	} else if (ret != -EINVAL) {
743	dev_err(dev, "failed to get tx-burst-size-dword\n");
744	return ret;
745	}
746
747	ret = of_property_read_u32(np: dev->of_node, propname: "rx-burst-size-dword",
748	out_value: &platdata->rx_burst_size);
749	if (!ret) {
750	platdata->flags |= CI_HDRC_OVERRIDE_RX_BURST;
751	} else if (ret != -EINVAL) {
752	dev_err(dev, "failed to get rx-burst-size-dword\n");
753	return ret;
754	}
755
756	if (of_property_read_bool(np: dev->of_node, propname: "non-zero-ttctrl-ttha"))
757	platdata->flags |= CI_HDRC_SET_NON_ZERO_TTHA;
758
759	ext_id = ERR_PTR(error: -ENODEV);
760	ext_vbus = ERR_PTR(error: -ENODEV);
761	if (of_property_read_bool(np: dev->of_node, propname: "extcon")) {
762	/* Each one of them is not mandatory */
763	ext_vbus = extcon_get_edev_by_phandle(dev, index: 0);
764	if (IS_ERR(ptr: ext_vbus) && PTR_ERR(ptr: ext_vbus) != -ENODEV)
765	return PTR_ERR(ptr: ext_vbus);
766
767	ext_id = extcon_get_edev_by_phandle(dev, index: 1);
768	if (IS_ERR(ptr: ext_id) && PTR_ERR(ptr: ext_id) != -ENODEV)
769	return PTR_ERR(ptr: ext_id);
770	}
771
772	cable = &platdata->vbus_extcon;
773	cable->nb.notifier_call = ci_cable_notifier;
774	cable->edev = ext_vbus;
775
776	if (!IS_ERR(ptr: ext_vbus)) {
777	ret = extcon_get_state(edev: cable->edev, EXTCON_USB);
778	if (ret)
779	cable->connected = true;
780	else
781	cable->connected = false;
782	}
783
784	cable = &platdata->id_extcon;
785	cable->nb.notifier_call = ci_cable_notifier;
786	cable->edev = ext_id;
787
788	if (!IS_ERR(ptr: ext_id)) {
789	ret = extcon_get_state(edev: cable->edev, EXTCON_USB_HOST);
790	if (ret)
791	cable->connected = true;
792	else
793	cable->connected = false;
794	}
795
796	if (device_property_read_bool(dev, propname: "usb-role-switch"))
797	ci_role_switch.fwnode = dev->fwnode;
798
799	platdata->pctl = devm_pinctrl_get(dev);
800	if (!IS_ERR(ptr: platdata->pctl)) {
801	struct pinctrl_state *p;
802
803	p = pinctrl_lookup_state(p: platdata->pctl, name: "default");
804	if (!IS_ERR(ptr: p))
805	platdata->pins_default = p;
806
807	p = pinctrl_lookup_state(p: platdata->pctl, name: "host");
808	if (!IS_ERR(ptr: p))
809	platdata->pins_host = p;
810
811	p = pinctrl_lookup_state(p: platdata->pctl, name: "device");
812	if (!IS_ERR(ptr: p))
813	platdata->pins_device = p;
814	}
815
816	if (!platdata->enter_lpm)
817	platdata->enter_lpm = ci_hdrc_enter_lpm_common;
818
819	return 0;
820	}
821
822	static int ci_extcon_register(struct ci_hdrc *ci)
823	{
824	struct ci_hdrc_cable *id, *vbus;
825	int ret;
826
827	id = &ci->platdata->id_extcon;
828	id->ci = ci;
829	if (!IS_ERR_OR_NULL(ptr: id->edev)) {
830	ret = devm_extcon_register_notifier(dev: ci->dev, edev: id->edev,
831	EXTCON_USB_HOST, nb: &id->nb);
832	if (ret < 0) {
833	dev_err(ci->dev, "register ID failed\n");
834	return ret;
835	}
836	}
837
838	vbus = &ci->platdata->vbus_extcon;
839	vbus->ci = ci;
840	if (!IS_ERR_OR_NULL(ptr: vbus->edev)) {
841	ret = devm_extcon_register_notifier(dev: ci->dev, edev: vbus->edev,
842	EXTCON_USB, nb: &vbus->nb);
843	if (ret < 0) {
844	dev_err(ci->dev, "register VBUS failed\n");
845	return ret;
846	}
847	}
848
849	return 0;
850	}
851
852	static DEFINE_IDA(ci_ida);
853
854	struct platform_device *ci_hdrc_add_device(struct device *dev,
855	struct resource *res, int nres,
856	struct ci_hdrc_platform_data *platdata)
857	{
858	struct platform_device *pdev;
859	int id, ret;
860
861	ret = ci_get_platdata(dev, platdata);
862	if (ret)
863	return ERR_PTR(error: ret);
864
865	id = ida_simple_get(&ci_ida, 0, 0, GFP_KERNEL);
866	if (id < 0)
867	return ERR_PTR(error: id);
868
869	pdev = platform_device_alloc(name: "ci_hdrc", id);
870	if (!pdev) {
871	ret = -ENOMEM;
872	goto put_id;
873	}
874
875	pdev->dev.parent = dev;
876	device_set_of_node_from_dev(dev: &pdev->dev, dev2: dev);
877
878	ret = platform_device_add_resources(pdev, res, num: nres);
879	if (ret)
880	goto err;
881
882	ret = platform_device_add_data(pdev, data: platdata, size: sizeof(*platdata));
883	if (ret)
884	goto err;
885
886	ret = platform_device_add(pdev);
887	if (ret)
888	goto err;
889
890	return pdev;
891
892	err:
893	platform_device_put(pdev);
894	put_id:
895	ida_simple_remove(&ci_ida, id);
896	return ERR_PTR(error: ret);
897	}
898	EXPORT_SYMBOL_GPL(ci_hdrc_add_device);
899
900	void ci_hdrc_remove_device(struct platform_device *pdev)
901	{
902	int id = pdev->id;
903	platform_device_unregister(pdev);
904	ida_simple_remove(&ci_ida, id);
905	}
906	EXPORT_SYMBOL_GPL(ci_hdrc_remove_device);
907
908	/**
909	* ci_hdrc_query_available_role: get runtime available operation mode
910	*
911	* The glue layer can get current operation mode (host/peripheral/otg)
912	* This function should be called after ci core device has created.
913	*
914	* @pdev: the platform device of ci core.
915	*
916	* Return runtime usb_dr_mode.
917	*/
918	enum usb_dr_mode ci_hdrc_query_available_role(struct platform_device *pdev)
919	{
920	struct ci_hdrc *ci = platform_get_drvdata(pdev);
921
922	if (!ci)
923	return USB_DR_MODE_UNKNOWN;
924	if (ci->roles[CI_ROLE_HOST] && ci->roles[CI_ROLE_GADGET])
925	return USB_DR_MODE_OTG;
926	else if (ci->roles[CI_ROLE_HOST])
927	return USB_DR_MODE_HOST;
928	else if (ci->roles[CI_ROLE_GADGET])
929	return USB_DR_MODE_PERIPHERAL;
930	else
931	return USB_DR_MODE_UNKNOWN;
932	}
933	EXPORT_SYMBOL_GPL(ci_hdrc_query_available_role);
934
935	static inline void ci_role_destroy(struct ci_hdrc *ci)
936	{
937	ci_hdrc_gadget_destroy(ci);
938	ci_hdrc_host_destroy(ci);
939	if (ci->is_otg && ci->roles[CI_ROLE_GADGET])
940	ci_hdrc_otg_destroy(ci);
941	}
942
943	static void ci_get_otg_capable(struct ci_hdrc *ci)
944	{
945	if (ci->platdata->flags & CI_HDRC_DUAL_ROLE_NOT_OTG)
946	ci->is_otg = false;
947	else
948	ci->is_otg = (hw_read(ci, reg: CAP_DCCPARAMS,
949	DCCPARAMS_DC | DCCPARAMS_HC)
950	== (DCCPARAMS_DC | DCCPARAMS_HC));
951	if (ci->is_otg) {
952	dev_dbg(ci->dev, "It is OTG capable controller\n");
953	/* Disable and clear all OTG irq */
954	hw_write_otgsc(ci, OTGSC_INT_EN_BITS | OTGSC_INT_STATUS_BITS,
955	OTGSC_INT_STATUS_BITS);
956	}
957	}
958
959	static ssize_t role_show(struct device *dev, struct device_attribute *attr,
960	char *buf)
961	{
962	struct ci_hdrc *ci = dev_get_drvdata(dev);
963
964	if (ci->role != CI_ROLE_END)
965	return sprintf(buf, fmt: "%s\n", ci_role(ci)->name);
966
967	return 0;
968	}
969
970	static ssize_t role_store(struct device *dev,
971	struct device_attribute *attr, const char *buf, size_t n)
972	{
973	struct ci_hdrc *ci = dev_get_drvdata(dev);
974	enum ci_role role;
975	int ret;
976
977	if (!(ci->roles[CI_ROLE_HOST] && ci->roles[CI_ROLE_GADGET])) {
978	dev_warn(dev, "Current configuration is not dual-role, quit\n");
979	return -EPERM;
980	}
981
982	for (role = CI_ROLE_HOST; role < CI_ROLE_END; role++)
983	if (!strncmp(buf, ci->roles[role]->name,
984	strlen(ci->roles[role]->name)))
985	break;
986
987	if (role == CI_ROLE_END)
988	return -EINVAL;
989
990	mutex_lock(&ci->mutex);
991
992	if (role == ci->role) {
993	mutex_unlock(lock: &ci->mutex);
994	return n;
995	}
996
997	pm_runtime_get_sync(dev);
998	disable_irq(irq: ci->irq);
999	ci_role_stop(ci);
1000	ret = ci_role_start(ci, role);
1001	if (!ret && ci->role == CI_ROLE_GADGET)
1002	ci_handle_vbus_change(ci);
1003	enable_irq(irq: ci->irq);
1004	pm_runtime_put_sync(dev);
1005	mutex_unlock(lock: &ci->mutex);
1006
1007	return (ret == 0) ? n : ret;
1008	}
1009	static DEVICE_ATTR_RW(role);
1010
1011	static struct attribute *ci_attrs[] = {
1012	&dev_attr_role.attr,
1013	NULL,
1014	};
1015	ATTRIBUTE_GROUPS(ci);
1016
1017	static int ci_hdrc_probe(struct platform_device *pdev)
1018	{
1019	struct device *dev = &pdev->dev;
1020	struct ci_hdrc *ci;
1021	struct resource *res;
1022	void __iomem *base;
1023	int ret;
1024	enum usb_dr_mode dr_mode;
1025
1026	if (!dev_get_platdata(dev)) {
1027	dev_err(dev, "platform data missing\n");
1028	return -ENODEV;
1029	}
1030
1031	base = devm_platform_get_and_ioremap_resource(pdev, index: 0, res: &res);
1032	if (IS_ERR(ptr: base))
1033	return PTR_ERR(ptr: base);
1034
1035	ci = devm_kzalloc(dev, size: sizeof(*ci), GFP_KERNEL);
1036	if (!ci)
1037	return -ENOMEM;
1038
1039	spin_lock_init(&ci->lock);
1040	mutex_init(&ci->mutex);
1041	ci->dev = dev;
1042	ci->platdata = dev_get_platdata(dev);
1043	ci->imx28_write_fix = !!(ci->platdata->flags &
1044	CI_HDRC_IMX28_WRITE_FIX);
1045	ci->supports_runtime_pm = !!(ci->platdata->flags &
1046	CI_HDRC_SUPPORTS_RUNTIME_PM);
1047	ci->has_portsc_pec_bug = !!(ci->platdata->flags &
1048	CI_HDRC_HAS_PORTSC_PEC_MISSED);
1049	platform_set_drvdata(pdev, data: ci);
1050
1051	ret = hw_device_init(ci, base);
1052	if (ret < 0) {
1053	dev_err(dev, "can't initialize hardware\n");
1054	return -ENODEV;
1055	}
1056
1057	ret = ci_ulpi_init(ci);
1058	if (ret)
1059	return ret;
1060
1061	if (ci->platdata->phy) {
1062	ci->phy = ci->platdata->phy;
1063	} else if (ci->platdata->usb_phy) {
1064	ci->usb_phy = ci->platdata->usb_phy;
1065	} else {
1066	/* Look for a generic PHY first */
1067	ci->phy = devm_phy_get(dev: dev->parent, string: "usb-phy");
1068
1069	if (PTR_ERR(ptr: ci->phy) == -EPROBE_DEFER) {
1070	ret = -EPROBE_DEFER;
1071	goto ulpi_exit;
1072	} else if (IS_ERR(ptr: ci->phy)) {
1073	ci->phy = NULL;
1074	}
1075
1076	/* Look for a legacy USB PHY from device-tree next */
1077	if (!ci->phy) {
1078	ci->usb_phy = devm_usb_get_phy_by_phandle(dev: dev->parent,
1079	phandle: "phys", index: 0);
1080
1081	if (PTR_ERR(ptr: ci->usb_phy) == -EPROBE_DEFER) {
1082	ret = -EPROBE_DEFER;
1083	goto ulpi_exit;
1084	} else if (IS_ERR(ptr: ci->usb_phy)) {
1085	ci->usb_phy = NULL;
1086	}
1087	}
1088
1089	/* Look for any registered legacy USB PHY as last resort */
1090	if (!ci->phy && !ci->usb_phy) {
1091	ci->usb_phy = devm_usb_get_phy(dev: dev->parent,
1092	type: USB_PHY_TYPE_USB2);
1093
1094	if (PTR_ERR(ptr: ci->usb_phy) == -EPROBE_DEFER) {
1095	ret = -EPROBE_DEFER;
1096	goto ulpi_exit;
1097	} else if (IS_ERR(ptr: ci->usb_phy)) {
1098	ci->usb_phy = NULL;
1099	}
1100	}
1101
1102	/* No USB PHY was found in the end */
1103	if (!ci->phy && !ci->usb_phy) {
1104	ret = -ENXIO;
1105	goto ulpi_exit;
1106	}
1107	}
1108
1109	ret = ci_usb_phy_init(ci);
1110	if (ret) {
1111	dev_err(dev, "unable to init phy: %d\n", ret);
1112	goto ulpi_exit;
1113	}
1114
1115	ci->hw_bank.phys = res->start;
1116
1117	ci->irq = platform_get_irq(pdev, 0);
1118	if (ci->irq < 0) {
1119	ret = ci->irq;
1120	goto deinit_phy;
1121	}
1122
1123	ci_get_otg_capable(ci);
1124
1125	dr_mode = ci->platdata->dr_mode;
1126	/* initialize role(s) before the interrupt is requested */
1127	if (dr_mode == USB_DR_MODE_OTG || dr_mode == USB_DR_MODE_HOST) {
1128	ret = ci_hdrc_host_init(ci);
1129	if (ret) {
1130	if (ret == -ENXIO)
1131	dev_info(dev, "doesn't support host\n");
1132	else
1133	goto deinit_phy;
1134	}
1135	}
1136
1137	if (dr_mode == USB_DR_MODE_OTG || dr_mode == USB_DR_MODE_PERIPHERAL) {
1138	ret = ci_hdrc_gadget_init(ci);
1139	if (ret) {
1140	if (ret == -ENXIO)
1141	dev_info(dev, "doesn't support gadget\n");
1142	else
1143	goto deinit_host;
1144	}
1145	}
1146
1147	if (!ci->roles[CI_ROLE_HOST] && !ci->roles[CI_ROLE_GADGET]) {
1148	dev_err(dev, "no supported roles\n");
1149	ret = -ENODEV;
1150	goto deinit_gadget;
1151	}
1152
1153	if (ci->is_otg && ci->roles[CI_ROLE_GADGET]) {
1154	ret = ci_hdrc_otg_init(ci);
1155	if (ret) {
1156	dev_err(dev, "init otg fails, ret = %d\n", ret);
1157	goto deinit_gadget;
1158	}
1159	}
1160
1161	if (ci_role_switch.fwnode) {
1162	ci_role_switch.driver_data = ci;
1163	ci->role_switch = usb_role_switch_register(parent: dev,
1164	desc: &ci_role_switch);
1165	if (IS_ERR(ptr: ci->role_switch)) {
1166	ret = PTR_ERR(ptr: ci->role_switch);
1167	goto deinit_otg;
1168	}
1169	}
1170
1171	ci->role = ci_get_role(ci);
1172	if (!ci_otg_is_fsm_mode(ci)) {
1173	/* only update vbus status for peripheral */
1174	if (ci->role == CI_ROLE_GADGET) {
1175	/* Pull down DP for possible charger detection */
1176	hw_write(ci, reg: OP_USBCMD, USBCMD_RS, data: 0);
1177	ci_handle_vbus_change(ci);
1178	}
1179
1180	ret = ci_role_start(ci, role: ci->role);
1181	if (ret) {
1182	dev_err(dev, "can't start %s role\n",
1183	ci_role(ci)->name);
1184	goto stop;
1185	}
1186	}
1187
1188	ret = devm_request_irq(dev, irq: ci->irq, handler: ci_irq_handler, IRQF_SHARED,
1189	devname: ci->platdata->name, dev_id: ci);
1190	if (ret)
1191	goto stop;
1192
1193	ret = ci_extcon_register(ci);
1194	if (ret)
1195	goto stop;
1196
1197	if (ci->supports_runtime_pm) {
1198	pm_runtime_set_active(dev: &pdev->dev);
1199	pm_runtime_enable(dev: &pdev->dev);
1200	pm_runtime_set_autosuspend_delay(dev: &pdev->dev, delay: 2000);
1201	pm_runtime_mark_last_busy(dev: ci->dev);
1202	pm_runtime_use_autosuspend(dev: &pdev->dev);
1203	}
1204
1205	if (ci_otg_is_fsm_mode(ci))
1206	ci_hdrc_otg_fsm_start(ci);
1207
1208	device_set_wakeup_capable(dev: &pdev->dev, capable: true);
1209	dbg_create_files(ci);
1210
1211	return 0;
1212
1213	stop:
1214	if (ci->role_switch)
1215	usb_role_switch_unregister(sw: ci->role_switch);
1216	deinit_otg:
1217	if (ci->is_otg && ci->roles[CI_ROLE_GADGET])
1218	ci_hdrc_otg_destroy(ci);
1219	deinit_gadget:
1220	ci_hdrc_gadget_destroy(ci);
1221	deinit_host:
1222	ci_hdrc_host_destroy(ci);
1223	deinit_phy:
1224	ci_usb_phy_exit(ci);
1225	ulpi_exit:
1226	ci_ulpi_exit(ci);
1227
1228	return ret;
1229	}
1230
1231	static void ci_hdrc_remove(struct platform_device *pdev)
1232	{
1233	struct ci_hdrc *ci = platform_get_drvdata(pdev);
1234
1235	if (ci->role_switch)
1236	usb_role_switch_unregister(sw: ci->role_switch);
1237
1238	if (ci->supports_runtime_pm) {
1239	pm_runtime_get_sync(dev: &pdev->dev);
1240	pm_runtime_disable(dev: &pdev->dev);
1241	pm_runtime_put_noidle(dev: &pdev->dev);
1242	}
1243
1244	dbg_remove_files(ci);
1245	ci_role_destroy(ci);
1246	ci_hdrc_enter_lpm(ci, enable: true);
1247	ci_usb_phy_exit(ci);
1248	ci_ulpi_exit(ci);
1249	}
1250
1251	#ifdef CONFIG_PM
1252	/* Prepare wakeup by SRP before suspend */
1253	static void ci_otg_fsm_suspend_for_srp(struct ci_hdrc *ci)
1254	{
1255	if ((ci->fsm.otg->state == OTG_STATE_A_IDLE) &&
1256	!hw_read_otgsc(ci, OTGSC_ID)) {
1257	hw_write(ci, reg: OP_PORTSC, PORTSC_W1C_BITS | PORTSC_PP,
1258	PORTSC_PP);
1259	hw_write(ci, reg: OP_PORTSC, PORTSC_W1C_BITS | PORTSC_WKCN,
1260	PORTSC_WKCN);
1261	}
1262	}
1263
1264	/* Handle SRP when wakeup by data pulse */
1265	static void ci_otg_fsm_wakeup_by_srp(struct ci_hdrc *ci)
1266	{
1267	if ((ci->fsm.otg->state == OTG_STATE_A_IDLE) &&
1268	(ci->fsm.a_bus_drop == 1) && (ci->fsm.a_bus_req == 0)) {
1269	if (!hw_read_otgsc(ci, OTGSC_ID)) {
1270	ci->fsm.a_srp_det = 1;
1271	ci->fsm.a_bus_drop = 0;
1272	} else {
1273	ci->fsm.id = 1;
1274	}
1275	ci_otg_queue_work(ci);
1276	}
1277	}
1278
1279	static void ci_controller_suspend(struct ci_hdrc *ci)
1280	{
1281	disable_irq(irq: ci->irq);
1282	ci_hdrc_enter_lpm(ci, enable: true);
1283	if (ci->platdata->phy_clkgate_delay_us)
1284	usleep_range(min: ci->platdata->phy_clkgate_delay_us,
1285	max: ci->platdata->phy_clkgate_delay_us + 50);
1286	usb_phy_set_suspend(x: ci->usb_phy, suspend: 1);
1287	ci->in_lpm = true;
1288	enable_irq(irq: ci->irq);
1289	}
1290
1291	/*
1292	* Handle the wakeup interrupt triggered by extcon connector
1293	* We need to call ci_irq again for extcon since the first
1294	* interrupt (wakeup int) only let the controller be out of
1295	* low power mode, but not handle any interrupts.
1296	*/
1297	static void ci_extcon_wakeup_int(struct ci_hdrc *ci)
1298	{
1299	struct ci_hdrc_cable *cable_id, *cable_vbus;
1300	u32 otgsc = hw_read_otgsc(ci, mask: ~0);
1301
1302	cable_id = &ci->platdata->id_extcon;
1303	cable_vbus = &ci->platdata->vbus_extcon;
1304
1305	if ((!IS_ERR(ptr: cable_id->edev) || ci->role_switch)
1306	&& ci->is_otg &&
1307	(otgsc & OTGSC_IDIE) && (otgsc & OTGSC_IDIS))
1308	ci_irq(ci);
1309
1310	if ((!IS_ERR(ptr: cable_vbus->edev) || ci->role_switch)
1311	&& ci->is_otg &&
1312	(otgsc & OTGSC_BSVIE) && (otgsc & OTGSC_BSVIS))
1313	ci_irq(ci);
1314	}
1315
1316	static int ci_controller_resume(struct device *dev)
1317	{
1318	struct ci_hdrc *ci = dev_get_drvdata(dev);
1319	int ret;
1320
1321	dev_dbg(dev, "at %s\n", __func__);
1322
1323	if (!ci->in_lpm) {
1324	WARN_ON(1);
1325	return 0;
1326	}
1327
1328	ci_hdrc_enter_lpm(ci, enable: false);
1329
1330	ret = ci_ulpi_resume(ci);
1331	if (ret)
1332	return ret;
1333
1334	if (ci->usb_phy) {
1335	usb_phy_set_suspend(x: ci->usb_phy, suspend: 0);
1336	usb_phy_set_wakeup(x: ci->usb_phy, enabled: false);
1337	hw_wait_phy_stable();
1338	}
1339
1340	ci->in_lpm = false;
1341	if (ci->wakeup_int) {
1342	ci->wakeup_int = false;
1343	pm_runtime_mark_last_busy(dev: ci->dev);
1344	pm_runtime_put_autosuspend(dev: ci->dev);
1345	enable_irq(irq: ci->irq);
1346	if (ci_otg_is_fsm_mode(ci))
1347	ci_otg_fsm_wakeup_by_srp(ci);
1348	ci_extcon_wakeup_int(ci);
1349	}
1350
1351	return 0;
1352	}
1353
1354	#ifdef CONFIG_PM_SLEEP
1355	static int ci_suspend(struct device *dev)
1356	{
1357	struct ci_hdrc *ci = dev_get_drvdata(dev);
1358
1359	if (ci->wq)
1360	flush_workqueue(ci->wq);
1361	/*
1362	* Controller needs to be active during suspend, otherwise the core
1363	* may run resume when the parent is at suspend if other driver's
1364	* suspend fails, it occurs before parent's suspend has not started,
1365	* but the core suspend has finished.
1366	*/
1367	if (ci->in_lpm)
1368	pm_runtime_resume(dev);
1369
1370	if (ci->in_lpm) {
1371	WARN_ON(1);
1372	return 0;
1373	}
1374
1375	/* Extra routine per role before system suspend */
1376	if (ci->role != CI_ROLE_END && ci_role(ci)->suspend)
1377	ci_role(ci)->suspend(ci);
1378
1379	if (device_may_wakeup(dev)) {
1380	if (ci_otg_is_fsm_mode(ci))
1381	ci_otg_fsm_suspend_for_srp(ci);
1382
1383	usb_phy_set_wakeup(x: ci->usb_phy, enabled: true);
1384	enable_irq_wake(irq: ci->irq);
1385	}
1386
1387	ci_controller_suspend(ci);
1388
1389	return 0;
1390	}
1391
1392	static void ci_handle_power_lost(struct ci_hdrc *ci)
1393	{
1394	enum ci_role role;
1395
1396	disable_irq_nosync(irq: ci->irq);
1397	if (!ci_otg_is_fsm_mode(ci)) {
1398	role = ci_get_role(ci);
1399
1400	if (ci->role != role) {
1401	ci_handle_id_switch(ci);
1402	} else if (role == CI_ROLE_GADGET) {
1403	if (ci->is_otg && hw_read_otgsc(ci, OTGSC_BSV))
1404	usb_gadget_vbus_connect(gadget: &ci->gadget);
1405	}
1406	}
1407
1408	enable_irq(irq: ci->irq);
1409	}
1410
1411	static int ci_resume(struct device *dev)
1412	{
1413	struct ci_hdrc *ci = dev_get_drvdata(dev);
1414	bool power_lost;
1415	int ret;
1416
1417	/* Since ASYNCLISTADDR (host mode) and ENDPTLISTADDR (device
1418	* mode) share the same register address. We can check if
1419	* controller resume from power lost based on this address
1420	* due to this register will be reset after power lost.
1421	*/
1422	power_lost = !hw_read(ci, reg: OP_ENDPTLISTADDR, mask: ~0);
1423
1424	if (device_may_wakeup(dev))
1425	disable_irq_wake(irq: ci->irq);
1426
1427	ret = ci_controller_resume(dev);
1428	if (ret)
1429	return ret;
1430
1431	if (power_lost) {
1432	/* shutdown and re-init for phy */
1433	ci_usb_phy_exit(ci);
1434	ci_usb_phy_init(ci);
1435	}
1436
1437	/* Extra routine per role after system resume */
1438	if (ci->role != CI_ROLE_END && ci_role(ci)->resume)
1439	ci_role(ci)->resume(ci, power_lost);
1440
1441	if (power_lost)
1442	ci_handle_power_lost(ci);
1443
1444	if (ci->supports_runtime_pm) {
1445	pm_runtime_disable(dev);
1446	pm_runtime_set_active(dev);
1447	pm_runtime_enable(dev);
1448	}
1449
1450	return ret;
1451	}
1452	#endif /* CONFIG_PM_SLEEP */
1453
1454	static int ci_runtime_suspend(struct device *dev)
1455	{
1456	struct ci_hdrc *ci = dev_get_drvdata(dev);
1457
1458	dev_dbg(dev, "at %s\n", __func__);
1459
1460	if (ci->in_lpm) {
1461	WARN_ON(1);
1462	return 0;
1463	}
1464
1465	if (ci_otg_is_fsm_mode(ci))
1466	ci_otg_fsm_suspend_for_srp(ci);
1467
1468	usb_phy_set_wakeup(x: ci->usb_phy, enabled: true);
1469	ci_controller_suspend(ci);
1470
1471	return 0;
1472	}
1473
1474	static int ci_runtime_resume(struct device *dev)
1475	{
1476	return ci_controller_resume(dev);
1477	}
1478
1479	#endif /* CONFIG_PM */
1480	static const struct dev_pm_ops ci_pm_ops = {
1481	SET_SYSTEM_SLEEP_PM_OPS(ci_suspend, ci_resume)
1482	SET_RUNTIME_PM_OPS(ci_runtime_suspend, ci_runtime_resume, NULL)
1483	};
1484
1485	static struct platform_driver ci_hdrc_driver = {
1486	.probe = ci_hdrc_probe,
1487	.remove_new = ci_hdrc_remove,
1488	.driver = {
1489	.name = "ci_hdrc",
1490	.pm = &ci_pm_ops,
1491	.dev_groups = ci_groups,
1492	},
1493	};
1494
1495	static int __init ci_hdrc_platform_register(void)
1496	{
1497	ci_hdrc_host_driver_init();
1498	return platform_driver_register(&ci_hdrc_driver);
1499	}
1500	module_init(ci_hdrc_platform_register);
1501
1502	static void __exit ci_hdrc_platform_unregister(void)
1503	{
1504	platform_driver_unregister(&ci_hdrc_driver);
1505	}
1506	module_exit(ci_hdrc_platform_unregister);
1507
1508	MODULE_ALIAS("platform:ci_hdrc");
1509	MODULE_LICENSE("GPL v2");
1510	MODULE_AUTHOR("David Lopo <dlopo@chipidea.mips.com>");
1511	MODULE_DESCRIPTION("ChipIdea HDRC Driver");
1512