1	// SPDX-License-Identifier: GPL-2.0+
2	/*
3	* USB Gadget driver for LPC32xx
4	*
5	* Authors:
6	* Kevin Wells <kevin.wells@nxp.com>
7	* Mike James
8	* Roland Stigge <stigge@antcom.de>
9	*
10	* Copyright (C) 2006 Philips Semiconductors
11	* Copyright (C) 2009 NXP Semiconductors
12	* Copyright (C) 2012 Roland Stigge
13	*
14	* Note: This driver is based on original work done by Mike James for
15	* the LPC3180.
16	*/
17
18	#include <linux/clk.h>
19	#include <linux/delay.h>
20	#include <linux/dma-mapping.h>
21	#include <linux/dmapool.h>
22	#include <linux/i2c.h>
23	#include <linux/interrupt.h>
24	#include <linux/module.h>
25	#include <linux/of.h>
26	#include <linux/platform_device.h>
27	#include <linux/prefetch.h>
28	#include <linux/proc_fs.h>
29	#include <linux/slab.h>
30	#include <linux/usb/ch9.h>
31	#include <linux/usb/gadget.h>
32	#include <linux/usb/isp1301.h>
33
34	#ifdef CONFIG_USB_GADGET_DEBUG_FILES
35	#include <linux/debugfs.h>
36	#include <linux/seq_file.h>
37	#endif
38
39	/*
40	* USB device configuration structure
41	*/
42	typedef void (*usc_chg_event)(int);
43	struct lpc32xx_usbd_cfg {
44	int vbus_drv_pol; /* 0=active low drive for VBUS via ISP1301 */
45	usc_chg_event conn_chgb; /* Connection change event (optional) */
46	usc_chg_event susp_chgb; /* Suspend/resume event (optional) */
47	usc_chg_event rmwk_chgb; /* Enable/disable remote wakeup */
48	};
49
50	/*
51	* controller driver data structures
52	*/
53
54	/* 16 endpoints (not to be confused with 32 hardware endpoints) */
55	#define NUM_ENDPOINTS 16
56
57	/*
58	* IRQ indices make reading the code a little easier
59	*/
60	#define IRQ_USB_LP 0
61	#define IRQ_USB_HP 1
62	#define IRQ_USB_DEVDMA 2
63	#define IRQ_USB_ATX 3
64
65	#define EP_OUT 0 /* RX (from host) */
66	#define EP_IN 1 /* TX (to host) */
67
68	/* Returns the interrupt mask for the selected hardware endpoint */
69	#define EP_MASK_SEL(ep, dir) (1 << (((ep) * 2) + dir))
70
71	#define EP_INT_TYPE 0
72	#define EP_ISO_TYPE 1
73	#define EP_BLK_TYPE 2
74	#define EP_CTL_TYPE 3
75
76	/* EP0 states */
77	#define WAIT_FOR_SETUP 0 /* Wait for setup packet */
78	#define DATA_IN 1 /* Expect dev->host transfer */
79	#define DATA_OUT 2 /* Expect host->dev transfer */
80
81	/* DD (DMA Descriptor) structure, requires word alignment, this is already
82	* defined in the LPC32XX USB device header file, but this version is slightly
83	* modified to tag some work data with each DMA descriptor. */
84	struct lpc32xx_usbd_dd_gad {
85	u32 dd_next_phy;
86	u32 dd_setup;
87	u32 dd_buffer_addr;
88	u32 dd_status;
89	u32 dd_iso_ps_mem_addr;
90	u32 this_dma;
91	u32 iso_status[6]; /* 5 spare */
92	u32 dd_next_v;
93	};
94
95	/*
96	* Logical endpoint structure
97	*/
98	struct lpc32xx_ep {
99	struct usb_ep ep;
100	struct list_head queue;
101	struct lpc32xx_udc *udc;
102
103	u32 hwep_num_base; /* Physical hardware EP */
104	u32 hwep_num; /* Maps to hardware endpoint */
105	u32 maxpacket;
106	u32 lep;
107
108	bool is_in;
109	bool req_pending;
110	u32 eptype;
111
112	u32 totalints;
113
114	bool wedge;
115	};
116
117	enum atx_type {
118	ISP1301,
119	STOTG04,
120	};
121
122	/*
123	* Common UDC structure
124	*/
125	struct lpc32xx_udc {
126	struct usb_gadget gadget;
127	struct usb_gadget_driver *driver;
128	struct platform_device *pdev;
129	struct device *dev;
130	spinlock_t lock;
131	struct i2c_client *isp1301_i2c_client;
132
133	/* Board and device specific */
134	struct lpc32xx_usbd_cfg *board;
135	void __iomem *udp_baseaddr;
136	int udp_irq[4];
137	struct clk *usb_slv_clk;
138
139	/* DMA support */
140	u32 *udca_v_base;
141	u32 udca_p_base;
142	struct dma_pool *dd_cache;
143
144	/* Common EP and control data */
145	u32 enabled_devints;
146	u32 enabled_hwepints;
147	u32 dev_status;
148	u32 realized_eps;
149
150	/* VBUS detection, pullup, and power flags */
151	u8 vbus;
152	u8 last_vbus;
153	int pullup;
154	int poweron;
155	enum atx_type atx;
156
157	/* Work queues related to I2C support */
158	struct work_struct pullup_job;
159	struct work_struct power_job;
160
161	/* USB device peripheral - various */
162	struct lpc32xx_ep ep[NUM_ENDPOINTS];
163	bool enabled;
164	bool clocked;
165	bool suspended;
166	int ep0state;
167	atomic_t enabled_ep_cnt;
168	wait_queue_head_t ep_disable_wait_queue;
169	};
170
171	/*
172	* Endpoint request
173	*/
174	struct lpc32xx_request {
175	struct usb_request req;
176	struct list_head queue;
177	struct lpc32xx_usbd_dd_gad *dd_desc_ptr;
178	bool mapped;
179	bool send_zlp;
180	};
181
182	static inline struct lpc32xx_udc *to_udc(struct usb_gadget *g)
183	{
184	return container_of(g, struct lpc32xx_udc, gadget);
185	}
186
187	#define ep_dbg(epp, fmt, arg...) \
188	dev_dbg(epp->udc->dev, "%s: " fmt, __func__, ## arg)
189	#define ep_err(epp, fmt, arg...) \
190	dev_err(epp->udc->dev, "%s: " fmt, __func__, ## arg)
191	#define ep_info(epp, fmt, arg...) \
192	dev_info(epp->udc->dev, "%s: " fmt, __func__, ## arg)
193	#define ep_warn(epp, fmt, arg...) \
194	dev_warn(epp->udc->dev, "%s:" fmt, __func__, ## arg)
195
196	#define UDCA_BUFF_SIZE (128)
197
198	/**********************************************************************
199	* USB device controller register offsets
200	**********************************************************************/
201
202	#define USBD_DEVINTST(x) ((x) + 0x200)
203	#define USBD_DEVINTEN(x) ((x) + 0x204)
204	#define USBD_DEVINTCLR(x) ((x) + 0x208)
205	#define USBD_DEVINTSET(x) ((x) + 0x20C)
206	#define USBD_CMDCODE(x) ((x) + 0x210)
207	#define USBD_CMDDATA(x) ((x) + 0x214)
208	#define USBD_RXDATA(x) ((x) + 0x218)
209	#define USBD_TXDATA(x) ((x) + 0x21C)
210	#define USBD_RXPLEN(x) ((x) + 0x220)
211	#define USBD_TXPLEN(x) ((x) + 0x224)
212	#define USBD_CTRL(x) ((x) + 0x228)
213	#define USBD_DEVINTPRI(x) ((x) + 0x22C)
214	#define USBD_EPINTST(x) ((x) + 0x230)
215	#define USBD_EPINTEN(x) ((x) + 0x234)
216	#define USBD_EPINTCLR(x) ((x) + 0x238)
217	#define USBD_EPINTSET(x) ((x) + 0x23C)
218	#define USBD_EPINTPRI(x) ((x) + 0x240)
219	#define USBD_REEP(x) ((x) + 0x244)
220	#define USBD_EPIND(x) ((x) + 0x248)
221	#define USBD_EPMAXPSIZE(x) ((x) + 0x24C)
222	/* DMA support registers only below */
223	/* Set, clear, or get enabled state of the DMA request status. If
224	* enabled, an IN or OUT token will start a DMA transfer for the EP */
225	#define USBD_DMARST(x) ((x) + 0x250)
226	#define USBD_DMARCLR(x) ((x) + 0x254)
227	#define USBD_DMARSET(x) ((x) + 0x258)
228	/* DMA UDCA head pointer */
229	#define USBD_UDCAH(x) ((x) + 0x280)
230	/* EP DMA status, enable, and disable. This is used to specifically
231	* enabled or disable DMA for a specific EP */
232	#define USBD_EPDMAST(x) ((x) + 0x284)
233	#define USBD_EPDMAEN(x) ((x) + 0x288)
234	#define USBD_EPDMADIS(x) ((x) + 0x28C)
235	/* DMA master interrupts enable and pending interrupts */
236	#define USBD_DMAINTST(x) ((x) + 0x290)
237	#define USBD_DMAINTEN(x) ((x) + 0x294)
238	/* DMA end of transfer interrupt enable, disable, status */
239	#define USBD_EOTINTST(x) ((x) + 0x2A0)
240	#define USBD_EOTINTCLR(x) ((x) + 0x2A4)
241	#define USBD_EOTINTSET(x) ((x) + 0x2A8)
242	/* New DD request interrupt enable, disable, status */
243	#define USBD_NDDRTINTST(x) ((x) + 0x2AC)
244	#define USBD_NDDRTINTCLR(x) ((x) + 0x2B0)
245	#define USBD_NDDRTINTSET(x) ((x) + 0x2B4)
246	/* DMA error interrupt enable, disable, status */
247	#define USBD_SYSERRTINTST(x) ((x) + 0x2B8)
248	#define USBD_SYSERRTINTCLR(x) ((x) + 0x2BC)
249	#define USBD_SYSERRTINTSET(x) ((x) + 0x2C0)
250
251	/**********************************************************************
252	* USBD_DEVINTST/USBD_DEVINTEN/USBD_DEVINTCLR/USBD_DEVINTSET/
253	* USBD_DEVINTPRI register definitions
254	**********************************************************************/
255	#define USBD_ERR_INT (1 << 9)
256	#define USBD_EP_RLZED (1 << 8)
257	#define USBD_TXENDPKT (1 << 7)
258	#define USBD_RXENDPKT (1 << 6)
259	#define USBD_CDFULL (1 << 5)
260	#define USBD_CCEMPTY (1 << 4)
261	#define USBD_DEV_STAT (1 << 3)
262	#define USBD_EP_SLOW (1 << 2)
263	#define USBD_EP_FAST (1 << 1)
264	#define USBD_FRAME (1 << 0)
265
266	/**********************************************************************
267	* USBD_EPINTST/USBD_EPINTEN/USBD_EPINTCLR/USBD_EPINTSET/
268	* USBD_EPINTPRI register definitions
269	**********************************************************************/
270	/* End point selection macro (RX) */
271	#define USBD_RX_EP_SEL(e) (1 << ((e) << 1))
272
273	/* End point selection macro (TX) */
274	#define USBD_TX_EP_SEL(e) (1 << (((e) << 1) + 1))
275
276	/**********************************************************************
277	* USBD_REEP/USBD_DMARST/USBD_DMARCLR/USBD_DMARSET/USBD_EPDMAST/
278	* USBD_EPDMAEN/USBD_EPDMADIS/
279	* USBD_NDDRTINTST/USBD_NDDRTINTCLR/USBD_NDDRTINTSET/
280	* USBD_EOTINTST/USBD_EOTINTCLR/USBD_EOTINTSET/
281	* USBD_SYSERRTINTST/USBD_SYSERRTINTCLR/USBD_SYSERRTINTSET
282	* register definitions
283	**********************************************************************/
284	/* Endpoint selection macro */
285	#define USBD_EP_SEL(e) (1 << (e))
286
287	/**********************************************************************
288	* SBD_DMAINTST/USBD_DMAINTEN
289	**********************************************************************/
290	#define USBD_SYS_ERR_INT (1 << 2)
291	#define USBD_NEW_DD_INT (1 << 1)
292	#define USBD_EOT_INT (1 << 0)
293
294	/**********************************************************************
295	* USBD_RXPLEN register definitions
296	**********************************************************************/
297	#define USBD_PKT_RDY (1 << 11)
298	#define USBD_DV (1 << 10)
299	#define USBD_PK_LEN_MASK 0x3FF
300
301	/**********************************************************************
302	* USBD_CTRL register definitions
303	**********************************************************************/
304	#define USBD_LOG_ENDPOINT(e) ((e) << 2)
305	#define USBD_WR_EN (1 << 1)
306	#define USBD_RD_EN (1 << 0)
307
308	/**********************************************************************
309	* USBD_CMDCODE register definitions
310	**********************************************************************/
311	#define USBD_CMD_CODE(c) ((c) << 16)
312	#define USBD_CMD_PHASE(p) ((p) << 8)
313
314	/**********************************************************************
315	* USBD_DMARST/USBD_DMARCLR/USBD_DMARSET register definitions
316	**********************************************************************/
317	#define USBD_DMAEP(e) (1 << (e))
318
319	/* DD (DMA Descriptor) structure, requires word alignment */
320	struct lpc32xx_usbd_dd {
321	u32 *dd_next;
322	u32 dd_setup;
323	u32 dd_buffer_addr;
324	u32 dd_status;
325	u32 dd_iso_ps_mem_addr;
326	};
327
328	/* dd_setup bit defines */
329	#define DD_SETUP_ATLE_DMA_MODE 0x01
330	#define DD_SETUP_NEXT_DD_VALID 0x04
331	#define DD_SETUP_ISO_EP 0x10
332	#define DD_SETUP_PACKETLEN(n) (((n) & 0x7FF) << 5)
333	#define DD_SETUP_DMALENBYTES(n) (((n) & 0xFFFF) << 16)
334
335	/* dd_status bit defines */
336	#define DD_STATUS_DD_RETIRED 0x01
337	#define DD_STATUS_STS_MASK 0x1E
338	#define DD_STATUS_STS_NS 0x00 /* Not serviced */
339	#define DD_STATUS_STS_BS 0x02 /* Being serviced */
340	#define DD_STATUS_STS_NC 0x04 /* Normal completion */
341	#define DD_STATUS_STS_DUR 0x06 /* Data underrun (short packet) */
342	#define DD_STATUS_STS_DOR 0x08 /* Data overrun */
343	#define DD_STATUS_STS_SE 0x12 /* System error */
344	#define DD_STATUS_PKT_VAL 0x20 /* Packet valid */
345	#define DD_STATUS_LSB_EX 0x40 /* LS byte extracted (ATLE) */
346	#define DD_STATUS_MSB_EX 0x80 /* MS byte extracted (ATLE) */
347	#define DD_STATUS_MLEN(n) (((n) >> 8) & 0x3F)
348	#define DD_STATUS_CURDMACNT(n) (((n) >> 16) & 0xFFFF)
349
350	/*
351	*
352	* Protocol engine bits below
353	*
354	*/
355	/* Device Interrupt Bit Definitions */
356	#define FRAME_INT 0x00000001
357	#define EP_FAST_INT 0x00000002
358	#define EP_SLOW_INT 0x00000004
359	#define DEV_STAT_INT 0x00000008
360	#define CCEMTY_INT 0x00000010
361	#define CDFULL_INT 0x00000020
362	#define RxENDPKT_INT 0x00000040
363	#define TxENDPKT_INT 0x00000080
364	#define EP_RLZED_INT 0x00000100
365	#define ERR_INT 0x00000200
366
367	/* Rx & Tx Packet Length Definitions */
368	#define PKT_LNGTH_MASK 0x000003FF
369	#define PKT_DV 0x00000400
370	#define PKT_RDY 0x00000800
371
372	/* USB Control Definitions */
373	#define CTRL_RD_EN 0x00000001
374	#define CTRL_WR_EN 0x00000002
375
376	/* Command Codes */
377	#define CMD_SET_ADDR 0x00D00500
378	#define CMD_CFG_DEV 0x00D80500
379	#define CMD_SET_MODE 0x00F30500
380	#define CMD_RD_FRAME 0x00F50500
381	#define DAT_RD_FRAME 0x00F50200
382	#define CMD_RD_TEST 0x00FD0500
383	#define DAT_RD_TEST 0x00FD0200
384	#define CMD_SET_DEV_STAT 0x00FE0500
385	#define CMD_GET_DEV_STAT 0x00FE0500
386	#define DAT_GET_DEV_STAT 0x00FE0200
387	#define CMD_GET_ERR_CODE 0x00FF0500
388	#define DAT_GET_ERR_CODE 0x00FF0200
389	#define CMD_RD_ERR_STAT 0x00FB0500
390	#define DAT_RD_ERR_STAT 0x00FB0200
391	#define DAT_WR_BYTE(x) (0x00000100 | ((x) << 16))
392	#define CMD_SEL_EP(x) (0x00000500 | ((x) << 16))
393	#define DAT_SEL_EP(x) (0x00000200 | ((x) << 16))
394	#define CMD_SEL_EP_CLRI(x) (0x00400500 | ((x) << 16))
395	#define DAT_SEL_EP_CLRI(x) (0x00400200 | ((x) << 16))
396	#define CMD_SET_EP_STAT(x) (0x00400500 | ((x) << 16))
397	#define CMD_CLR_BUF 0x00F20500
398	#define DAT_CLR_BUF 0x00F20200
399	#define CMD_VALID_BUF 0x00FA0500
400
401	/* Device Address Register Definitions */
402	#define DEV_ADDR_MASK 0x7F
403	#define DEV_EN 0x80
404
405	/* Device Configure Register Definitions */
406	#define CONF_DVICE 0x01
407
408	/* Device Mode Register Definitions */
409	#define AP_CLK 0x01
410	#define INAK_CI 0x02
411	#define INAK_CO 0x04
412	#define INAK_II 0x08
413	#define INAK_IO 0x10
414	#define INAK_BI 0x20
415	#define INAK_BO 0x40
416
417	/* Device Status Register Definitions */
418	#define DEV_CON 0x01
419	#define DEV_CON_CH 0x02
420	#define DEV_SUS 0x04
421	#define DEV_SUS_CH 0x08
422	#define DEV_RST 0x10
423
424	/* Error Code Register Definitions */
425	#define ERR_EC_MASK 0x0F
426	#define ERR_EA 0x10
427
428	/* Error Status Register Definitions */
429	#define ERR_PID 0x01
430	#define ERR_UEPKT 0x02
431	#define ERR_DCRC 0x04
432	#define ERR_TIMOUT 0x08
433	#define ERR_EOP 0x10
434	#define ERR_B_OVRN 0x20
435	#define ERR_BTSTF 0x40
436	#define ERR_TGL 0x80
437
438	/* Endpoint Select Register Definitions */
439	#define EP_SEL_F 0x01
440	#define EP_SEL_ST 0x02
441	#define EP_SEL_STP 0x04
442	#define EP_SEL_PO 0x08
443	#define EP_SEL_EPN 0x10
444	#define EP_SEL_B_1_FULL 0x20
445	#define EP_SEL_B_2_FULL 0x40
446
447	/* Endpoint Status Register Definitions */
448	#define EP_STAT_ST 0x01
449	#define EP_STAT_DA 0x20
450	#define EP_STAT_RF_MO 0x40
451	#define EP_STAT_CND_ST 0x80
452
453	/* Clear Buffer Register Definitions */
454	#define CLR_BUF_PO 0x01
455
456	/* DMA Interrupt Bit Definitions */
457	#define EOT_INT 0x01
458	#define NDD_REQ_INT 0x02
459	#define SYS_ERR_INT 0x04
460
461	#define DRIVER_VERSION "1.03"
462	static const char driver_name[] = "lpc32xx_udc";
463
464	/*
465	*
466	* proc interface support
467	*
468	*/
469	#ifdef CONFIG_USB_GADGET_DEBUG_FILES
470	static char *epnames[] = {"INT", "ISO", "BULK", "CTRL"};
471	static const char debug_filename[] = "driver/udc";
472
473	static void proc_ep_show(struct seq_file *s, struct lpc32xx_ep *ep)
474	{
475	struct lpc32xx_request *req;
476
477	seq_printf(m: s, fmt: "\n");
478	seq_printf(m: s, fmt: "%12s, maxpacket %4d %3s",
479	ep->ep.name, ep->ep.maxpacket,
480	ep->is_in ? "in" : "out");
481	seq_printf(m: s, fmt: " type %4s", epnames[ep->eptype]);
482	seq_printf(m: s, fmt: " ints: %12d", ep->totalints);
483
484	if (list_empty(head: &ep->queue))
485	seq_printf(m: s, fmt: "\t(queue empty)\n");
486	else {
487	list_for_each_entry(req, &ep->queue, queue) {
488	u32 length = req->req.actual;
489
490	seq_printf(m: s, fmt: "\treq %p len %d/%d buf %p\n",
491	&req->req, length,
492	req->req.length, req->req.buf);
493	}
494	}
495	}
496
497	static int udc_show(struct seq_file *s, void *unused)
498	{
499	struct lpc32xx_udc *udc = s->private;
500	struct lpc32xx_ep *ep;
501	unsigned long flags;
502
503	seq_printf(m: s, fmt: "%s: version %s\n", driver_name, DRIVER_VERSION);
504
505	spin_lock_irqsave(&udc->lock, flags);
506
507	seq_printf(m: s, fmt: "vbus %s, pullup %s, %s powered%s, gadget %s\n\n",
508	udc->vbus ? "present" : "off",
509	udc->enabled ? (udc->vbus ? "active" : "enabled") :
510	"disabled",
511	udc->gadget.is_selfpowered ? "self" : "VBUS",
512	udc->suspended ? ", suspended" : "",
513	udc->driver ? udc->driver->driver.name : "(none)");
514
515	if (udc->enabled && udc->vbus) {
516	proc_ep_show(s, ep: &udc->ep[0]);
517	list_for_each_entry(ep, &udc->gadget.ep_list, ep.ep_list)
518	proc_ep_show(s, ep);
519	}
520
521	spin_unlock_irqrestore(lock: &udc->lock, flags);
522
523	return 0;
524	}
525
526	DEFINE_SHOW_ATTRIBUTE(udc);
527
528	static void create_debug_file(struct lpc32xx_udc *udc)
529	{
530	debugfs_create_file(name: debug_filename, mode: 0, NULL, data: udc, fops: &udc_fops);
531	}
532
533	static void remove_debug_file(struct lpc32xx_udc *udc)
534	{
535	debugfs_lookup_and_remove(name: debug_filename, NULL);
536	}
537
538	#else
539	static inline void create_debug_file(struct lpc32xx_udc *udc) {}
540	static inline void remove_debug_file(struct lpc32xx_udc *udc) {}
541	#endif
542
543	/* Primary initialization sequence for the ISP1301 transceiver */
544	static void isp1301_udc_configure(struct lpc32xx_udc *udc)
545	{
546	u8 value;
547	s32 vendor, product;
548
549	vendor = i2c_smbus_read_word_data(client: udc->isp1301_i2c_client, command: 0x00);
550	product = i2c_smbus_read_word_data(client: udc->isp1301_i2c_client, command: 0x02);
551
552	if (vendor == 0x0483 && product == 0xa0c4)
553	udc->atx = STOTG04;
554
555	/* LPC32XX only supports DAT_SE0 USB mode */
556	/* This sequence is important */
557
558	/* Disable transparent UART mode first */
559	i2c_smbus_write_byte_data(client: udc->isp1301_i2c_client,
560	command: (ISP1301_I2C_MODE_CONTROL_1 | ISP1301_I2C_REG_CLEAR_ADDR),
561	MC1_UART_EN);
562
563	/* Set full speed and SE0 mode */
564	i2c_smbus_write_byte_data(client: udc->isp1301_i2c_client,
565	command: (ISP1301_I2C_MODE_CONTROL_1 | ISP1301_I2C_REG_CLEAR_ADDR), value: ~0);
566	i2c_smbus_write_byte_data(client: udc->isp1301_i2c_client,
567	ISP1301_I2C_MODE_CONTROL_1, value: (MC1_SPEED_REG | MC1_DAT_SE0));
568
569	/*
570	* The PSW_OE enable bit state is reversed in the ISP1301 User's Guide
571	*/
572	i2c_smbus_write_byte_data(client: udc->isp1301_i2c_client,
573	command: (ISP1301_I2C_MODE_CONTROL_2 | ISP1301_I2C_REG_CLEAR_ADDR), value: ~0);
574
575	value = MC2_BI_DI;
576	if (udc->atx != STOTG04)
577	value |= MC2_SPD_SUSP_CTRL;
578	i2c_smbus_write_byte_data(client: udc->isp1301_i2c_client,
579	ISP1301_I2C_MODE_CONTROL_2, value);
580
581	/* Driver VBUS_DRV high or low depending on board setup */
582	if (udc->board->vbus_drv_pol != 0)
583	i2c_smbus_write_byte_data(client: udc->isp1301_i2c_client,
584	ISP1301_I2C_OTG_CONTROL_1, OTG1_VBUS_DRV);
585	else
586	i2c_smbus_write_byte_data(client: udc->isp1301_i2c_client,
587	ISP1301_I2C_OTG_CONTROL_1 | ISP1301_I2C_REG_CLEAR_ADDR,
588	OTG1_VBUS_DRV);
589
590	/* Bi-directional mode with suspend control
591	* Enable both pulldowns for now - the pullup will be enable when VBUS
592	* is detected */
593	i2c_smbus_write_byte_data(client: udc->isp1301_i2c_client,
594	command: (ISP1301_I2C_OTG_CONTROL_1 | ISP1301_I2C_REG_CLEAR_ADDR), value: ~0);
595	i2c_smbus_write_byte_data(client: udc->isp1301_i2c_client,
596	ISP1301_I2C_OTG_CONTROL_1,
597	value: (0 | OTG1_DM_PULLDOWN | OTG1_DP_PULLDOWN));
598
599	/* Discharge VBUS (just in case) */
600	i2c_smbus_write_byte_data(client: udc->isp1301_i2c_client,
601	ISP1301_I2C_OTG_CONTROL_1, OTG1_VBUS_DISCHRG);
602	msleep(msecs: 1);
603	i2c_smbus_write_byte_data(client: udc->isp1301_i2c_client,
604	command: (ISP1301_I2C_OTG_CONTROL_1 | ISP1301_I2C_REG_CLEAR_ADDR),
605	OTG1_VBUS_DISCHRG);
606
607	i2c_smbus_write_byte_data(client: udc->isp1301_i2c_client,
608	ISP1301_I2C_INTERRUPT_LATCH | ISP1301_I2C_REG_CLEAR_ADDR, value: ~0);
609
610	i2c_smbus_write_byte_data(client: udc->isp1301_i2c_client,
611	ISP1301_I2C_INTERRUPT_FALLING | ISP1301_I2C_REG_CLEAR_ADDR, value: ~0);
612	i2c_smbus_write_byte_data(client: udc->isp1301_i2c_client,
613	ISP1301_I2C_INTERRUPT_RISING | ISP1301_I2C_REG_CLEAR_ADDR, value: ~0);
614
615	dev_info(udc->dev, "ISP1301 Vendor ID : 0x%04x\n", vendor);
616	dev_info(udc->dev, "ISP1301 Product ID : 0x%04x\n", product);
617	dev_info(udc->dev, "ISP1301 Version ID : 0x%04x\n",
618	i2c_smbus_read_word_data(udc->isp1301_i2c_client, 0x14));
619
620	}
621
622	/* Enables or disables the USB device pullup via the ISP1301 transceiver */
623	static void isp1301_pullup_set(struct lpc32xx_udc *udc)
624	{
625	if (udc->pullup)
626	/* Enable pullup for bus signalling */
627	i2c_smbus_write_byte_data(client: udc->isp1301_i2c_client,
628	ISP1301_I2C_OTG_CONTROL_1, OTG1_DP_PULLUP);
629	else
630	/* Enable pullup for bus signalling */
631	i2c_smbus_write_byte_data(client: udc->isp1301_i2c_client,
632	ISP1301_I2C_OTG_CONTROL_1 | ISP1301_I2C_REG_CLEAR_ADDR,
633	OTG1_DP_PULLUP);
634	}
635
636	static void pullup_work(struct work_struct *work)
637	{
638	struct lpc32xx_udc *udc =
639	container_of(work, struct lpc32xx_udc, pullup_job);
640
641	isp1301_pullup_set(udc);
642	}
643
644	static void isp1301_pullup_enable(struct lpc32xx_udc *udc, int en_pullup,
645	int block)
646	{
647	if (en_pullup == udc->pullup)
648	return;
649
650	udc->pullup = en_pullup;
651	if (block)
652	isp1301_pullup_set(udc);
653	else
654	/* defer slow i2c pull up setting */
655	schedule_work(work: &udc->pullup_job);
656	}
657
658	#ifdef CONFIG_PM
659	/* Powers up or down the ISP1301 transceiver */
660	static void isp1301_set_powerstate(struct lpc32xx_udc *udc, int enable)
661	{
662	/* There is no "global power down" register for stotg04 */
663	if (udc->atx == STOTG04)
664	return;
665
666	if (enable != 0)
667	/* Power up ISP1301 - this ISP1301 will automatically wakeup
668	when VBUS is detected */
669	i2c_smbus_write_byte_data(client: udc->isp1301_i2c_client,
670	ISP1301_I2C_MODE_CONTROL_2 | ISP1301_I2C_REG_CLEAR_ADDR,
671	MC2_GLOBAL_PWR_DN);
672	else
673	/* Power down ISP1301 */
674	i2c_smbus_write_byte_data(client: udc->isp1301_i2c_client,
675	ISP1301_I2C_MODE_CONTROL_2, MC2_GLOBAL_PWR_DN);
676	}
677
678	static void power_work(struct work_struct *work)
679	{
680	struct lpc32xx_udc *udc =
681	container_of(work, struct lpc32xx_udc, power_job);
682
683	isp1301_set_powerstate(udc, enable: udc->poweron);
684	}
685	#endif
686
687	/*
688	*
689	* USB protocol engine command/data read/write helper functions
690	*
691	*/
692	/* Issues a single command to the USB device state machine */
693	static void udc_protocol_cmd_w(struct lpc32xx_udc *udc, u32 cmd)
694	{
695	u32 pass = 0;
696	int to;
697
698	/* EP may lock on CLRI if this read isn't done */
699	u32 tmp = readl(USBD_DEVINTST(udc->udp_baseaddr));
700	(void) tmp;
701
702	while (pass == 0) {
703	writel(USBD_CCEMPTY, USBD_DEVINTCLR(udc->udp_baseaddr));
704
705	/* Write command code */
706	writel(val: cmd, USBD_CMDCODE(udc->udp_baseaddr));
707	to = 10000;
708	while (((readl(USBD_DEVINTST(udc->udp_baseaddr)) &
709	USBD_CCEMPTY) == 0) && (to > 0)) {
710	to--;
711	}
712
713	if (to > 0)
714	pass = 1;
715
716	cpu_relax();
717	}
718	}
719
720	/* Issues 2 commands (or command and data) to the USB device state machine */
721	static inline void udc_protocol_cmd_data_w(struct lpc32xx_udc *udc, u32 cmd,
722	u32 data)
723	{
724	udc_protocol_cmd_w(udc, cmd);
725	udc_protocol_cmd_w(udc, cmd: data);
726	}
727
728	/* Issues a single command to the USB device state machine and reads
729	* response data */
730	static u32 udc_protocol_cmd_r(struct lpc32xx_udc *udc, u32 cmd)
731	{
732	int to = 1000;
733
734	/* Write a command and read data from the protocol engine */
735	writel(val: (USBD_CDFULL | USBD_CCEMPTY),
736	USBD_DEVINTCLR(udc->udp_baseaddr));
737
738	/* Write command code */
739	udc_protocol_cmd_w(udc, cmd);
740
741	while ((!(readl(USBD_DEVINTST(udc->udp_baseaddr)) & USBD_CDFULL))
742	&& (to > 0))
743	to--;
744	if (!to)
745	dev_dbg(udc->dev,
746	"Protocol engine didn't receive response (CDFULL)\n");
747
748	return readl(USBD_CMDDATA(udc->udp_baseaddr));
749	}
750
751	/*
752	*
753	* USB device interrupt mask support functions
754	*
755	*/
756	/* Enable one or more USB device interrupts */
757	static inline void uda_enable_devint(struct lpc32xx_udc *udc, u32 devmask)
758	{
759	udc->enabled_devints |= devmask;
760	writel(val: udc->enabled_devints, USBD_DEVINTEN(udc->udp_baseaddr));
761	}
762
763	/* Disable one or more USB device interrupts */
764	static inline void uda_disable_devint(struct lpc32xx_udc *udc, u32 mask)
765	{
766	udc->enabled_devints &= ~mask;
767	writel(val: udc->enabled_devints, USBD_DEVINTEN(udc->udp_baseaddr));
768	}
769
770	/* Clear one or more USB device interrupts */
771	static inline void uda_clear_devint(struct lpc32xx_udc *udc, u32 mask)
772	{
773	writel(val: mask, USBD_DEVINTCLR(udc->udp_baseaddr));
774	}
775
776	/*
777	*
778	* Endpoint interrupt disable/enable functions
779	*
780	*/
781	/* Enable one or more USB endpoint interrupts */
782	static void uda_enable_hwepint(struct lpc32xx_udc *udc, u32 hwep)
783	{
784	udc->enabled_hwepints |= (1 << hwep);
785	writel(val: udc->enabled_hwepints, USBD_EPINTEN(udc->udp_baseaddr));
786	}
787
788	/* Disable one or more USB endpoint interrupts */
789	static void uda_disable_hwepint(struct lpc32xx_udc *udc, u32 hwep)
790	{
791	udc->enabled_hwepints &= ~(1 << hwep);
792	writel(val: udc->enabled_hwepints, USBD_EPINTEN(udc->udp_baseaddr));
793	}
794
795	/* Clear one or more USB endpoint interrupts */
796	static inline void uda_clear_hwepint(struct lpc32xx_udc *udc, u32 hwep)
797	{
798	writel(val: (1 << hwep), USBD_EPINTCLR(udc->udp_baseaddr));
799	}
800
801	/* Enable DMA for the HW channel */
802	static inline void udc_ep_dma_enable(struct lpc32xx_udc *udc, u32 hwep)
803	{
804	writel(val: (1 << hwep), USBD_EPDMAEN(udc->udp_baseaddr));
805	}
806
807	/* Disable DMA for the HW channel */
808	static inline void udc_ep_dma_disable(struct lpc32xx_udc *udc, u32 hwep)
809	{
810	writel(val: (1 << hwep), USBD_EPDMADIS(udc->udp_baseaddr));
811	}
812
813	/*
814	*
815	* Endpoint realize/unrealize functions
816	*
817	*/
818	/* Before an endpoint can be used, it needs to be realized
819	* in the USB protocol engine - this realizes the endpoint.
820	* The interrupt (FIFO or DMA) is not enabled with this function */
821	static void udc_realize_hwep(struct lpc32xx_udc *udc, u32 hwep,
822	u32 maxpacket)
823	{
824	int to = 1000;
825
826	writel(USBD_EP_RLZED, USBD_DEVINTCLR(udc->udp_baseaddr));
827	writel(val: hwep, USBD_EPIND(udc->udp_baseaddr));
828	udc->realized_eps |= (1 << hwep);
829	writel(val: udc->realized_eps, USBD_REEP(udc->udp_baseaddr));
830	writel(val: maxpacket, USBD_EPMAXPSIZE(udc->udp_baseaddr));
831
832	/* Wait until endpoint is realized in hardware */
833	while ((!(readl(USBD_DEVINTST(udc->udp_baseaddr)) &
834	USBD_EP_RLZED)) && (to > 0))
835	to--;
836	if (!to)
837	dev_dbg(udc->dev, "EP not correctly realized in hardware\n");
838
839	writel(USBD_EP_RLZED, USBD_DEVINTCLR(udc->udp_baseaddr));
840	}
841
842	/* Unrealize an EP */
843	static void udc_unrealize_hwep(struct lpc32xx_udc *udc, u32 hwep)
844	{
845	udc->realized_eps &= ~(1 << hwep);
846	writel(val: udc->realized_eps, USBD_REEP(udc->udp_baseaddr));
847	}
848
849	/*
850	*
851	* Endpoint support functions
852	*
853	*/
854	/* Select and clear endpoint interrupt */
855	static u32 udc_selep_clrint(struct lpc32xx_udc *udc, u32 hwep)
856	{
857	udc_protocol_cmd_w(udc, CMD_SEL_EP_CLRI(hwep));
858	return udc_protocol_cmd_r(udc, DAT_SEL_EP_CLRI(hwep));
859	}
860
861	/* Disables the endpoint in the USB protocol engine */
862	static void udc_disable_hwep(struct lpc32xx_udc *udc, u32 hwep)
863	{
864	udc_protocol_cmd_data_w(udc, CMD_SET_EP_STAT(hwep),
865	DAT_WR_BYTE(EP_STAT_DA));
866	}
867
868	/* Stalls the endpoint - endpoint will return STALL */
869	static void udc_stall_hwep(struct lpc32xx_udc *udc, u32 hwep)
870	{
871	udc_protocol_cmd_data_w(udc, CMD_SET_EP_STAT(hwep),
872	DAT_WR_BYTE(EP_STAT_ST));
873	}
874
875	/* Clear stall or reset endpoint */
876	static void udc_clrstall_hwep(struct lpc32xx_udc *udc, u32 hwep)
877	{
878	udc_protocol_cmd_data_w(udc, CMD_SET_EP_STAT(hwep),
879	DAT_WR_BYTE(0));
880	}
881
882	/* Select an endpoint for endpoint status, clear, validate */
883	static void udc_select_hwep(struct lpc32xx_udc *udc, u32 hwep)
884	{
885	udc_protocol_cmd_w(udc, CMD_SEL_EP(hwep));
886	}
887
888	/*
889	*
890	* Endpoint buffer management functions
891	*
892	*/
893	/* Clear the current endpoint's buffer */
894	static void udc_clr_buffer_hwep(struct lpc32xx_udc *udc, u32 hwep)
895	{
896	udc_select_hwep(udc, hwep);
897	udc_protocol_cmd_w(udc, CMD_CLR_BUF);
898	}
899
900	/* Validate the current endpoint's buffer */
901	static void udc_val_buffer_hwep(struct lpc32xx_udc *udc, u32 hwep)
902	{
903	udc_select_hwep(udc, hwep);
904	udc_protocol_cmd_w(udc, CMD_VALID_BUF);
905	}
906
907	static inline u32 udc_clearep_getsts(struct lpc32xx_udc *udc, u32 hwep)
908	{
909	/* Clear EP interrupt */
910	uda_clear_hwepint(udc, hwep);
911	return udc_selep_clrint(udc, hwep);
912	}
913
914	/*
915	*
916	* USB EP DMA support
917	*
918	*/
919	/* Allocate a DMA Descriptor */
920	static struct lpc32xx_usbd_dd_gad *udc_dd_alloc(struct lpc32xx_udc *udc)
921	{
922	dma_addr_t dma;
923	struct lpc32xx_usbd_dd_gad *dd;
924
925	dd = dma_pool_alloc(pool: udc->dd_cache, GFP_ATOMIC | GFP_DMA, handle: &dma);
926	if (dd)
927	dd->this_dma = dma;
928
929	return dd;
930	}
931
932	/* Free a DMA Descriptor */
933	static void udc_dd_free(struct lpc32xx_udc *udc, struct lpc32xx_usbd_dd_gad *dd)
934	{
935	dma_pool_free(pool: udc->dd_cache, vaddr: dd, addr: dd->this_dma);
936	}
937
938	/*
939	*
940	* USB setup and shutdown functions
941	*
942	*/
943	/* Enables or disables most of the USB system clocks when low power mode is
944	* needed. Clocks are typically started on a connection event, and disabled
945	* when a cable is disconnected */
946	static void udc_clk_set(struct lpc32xx_udc *udc, int enable)
947	{
948	if (enable != 0) {
949	if (udc->clocked)
950	return;
951
952	udc->clocked = 1;
953	clk_prepare_enable(clk: udc->usb_slv_clk);
954	} else {
955	if (!udc->clocked)
956	return;
957
958	udc->clocked = 0;
959	clk_disable_unprepare(clk: udc->usb_slv_clk);
960	}
961	}
962
963	/* Set/reset USB device address */
964	static void udc_set_address(struct lpc32xx_udc *udc, u32 addr)
965	{
966	/* Address will be latched at the end of the status phase, or
967	latched immediately if function is called twice */
968	udc_protocol_cmd_data_w(udc, CMD_SET_ADDR,
969	DAT_WR_BYTE(DEV_EN | addr));
970	}
971
972	/* Setup up a IN request for DMA transfer - this consists of determining the
973	* list of DMA addresses for the transfer, allocating DMA Descriptors,
974	* installing the DD into the UDCA, and then enabling the DMA for that EP */
975	static int udc_ep_in_req_dma(struct lpc32xx_udc *udc, struct lpc32xx_ep *ep)
976	{
977	struct lpc32xx_request *req;
978	u32 hwep = ep->hwep_num;
979
980	ep->req_pending = 1;
981
982	/* There will always be a request waiting here */
983	req = list_entry(ep->queue.next, struct lpc32xx_request, queue);
984
985	/* Place the DD Descriptor into the UDCA */
986	udc->udca_v_base[hwep] = req->dd_desc_ptr->this_dma;
987
988	/* Enable DMA and interrupt for the HW EP */
989	udc_ep_dma_enable(udc, hwep);
990
991	/* Clear ZLP if last packet is not of MAXP size */
992	if (req->req.length % ep->ep.maxpacket)
993	req->send_zlp = 0;
994
995	return 0;
996	}
997
998	/* Setup up a OUT request for DMA transfer - this consists of determining the
999	* list of DMA addresses for the transfer, allocating DMA Descriptors,
1000	* installing the DD into the UDCA, and then enabling the DMA for that EP */
1001	static int udc_ep_out_req_dma(struct lpc32xx_udc *udc, struct lpc32xx_ep *ep)
1002	{
1003	struct lpc32xx_request *req;
1004	u32 hwep = ep->hwep_num;
1005
1006	ep->req_pending = 1;
1007
1008	/* There will always be a request waiting here */
1009	req = list_entry(ep->queue.next, struct lpc32xx_request, queue);
1010
1011	/* Place the DD Descriptor into the UDCA */
1012	udc->udca_v_base[hwep] = req->dd_desc_ptr->this_dma;
1013
1014	/* Enable DMA and interrupt for the HW EP */
1015	udc_ep_dma_enable(udc, hwep);
1016	return 0;
1017	}
1018
1019	static void udc_disable(struct lpc32xx_udc *udc)
1020	{
1021	u32 i;
1022
1023	/* Disable device */
1024	udc_protocol_cmd_data_w(udc, CMD_CFG_DEV, DAT_WR_BYTE(0));
1025	udc_protocol_cmd_data_w(udc, CMD_SET_DEV_STAT, DAT_WR_BYTE(0));
1026
1027	/* Disable all device interrupts (including EP0) */
1028	uda_disable_devint(udc, mask: 0x3FF);
1029
1030	/* Disable and reset all endpoint interrupts */
1031	for (i = 0; i < 32; i++) {
1032	uda_disable_hwepint(udc, hwep: i);
1033	uda_clear_hwepint(udc, hwep: i);
1034	udc_disable_hwep(udc, hwep: i);
1035	udc_unrealize_hwep(udc, hwep: i);
1036	udc->udca_v_base[i] = 0;
1037
1038	/* Disable and clear all interrupts and DMA */
1039	udc_ep_dma_disable(udc, hwep: i);
1040	writel(val: (1 << i), USBD_EOTINTCLR(udc->udp_baseaddr));
1041	writel(val: (1 << i), USBD_NDDRTINTCLR(udc->udp_baseaddr));
1042	writel(val: (1 << i), USBD_SYSERRTINTCLR(udc->udp_baseaddr));
1043	writel(val: (1 << i), USBD_DMARCLR(udc->udp_baseaddr));
1044	}
1045
1046	/* Disable DMA interrupts */
1047	writel(val: 0, USBD_DMAINTEN(udc->udp_baseaddr));
1048
1049	writel(val: 0, USBD_UDCAH(udc->udp_baseaddr));
1050	}
1051
1052	static void udc_enable(struct lpc32xx_udc *udc)
1053	{
1054	u32 i;
1055	struct lpc32xx_ep *ep = &udc->ep[0];
1056
1057	/* Start with known state */
1058	udc_disable(udc);
1059
1060	/* Enable device */
1061	udc_protocol_cmd_data_w(udc, CMD_SET_DEV_STAT, DAT_WR_BYTE(DEV_CON));
1062
1063	/* EP interrupts on high priority, FRAME interrupt on low priority */
1064	writel(USBD_EP_FAST, USBD_DEVINTPRI(udc->udp_baseaddr));
1065	writel(val: 0xFFFF, USBD_EPINTPRI(udc->udp_baseaddr));
1066
1067	/* Clear any pending device interrupts */
1068	writel(val: 0x3FF, USBD_DEVINTCLR(udc->udp_baseaddr));
1069
1070	/* Setup UDCA - not yet used (DMA) */
1071	writel(val: udc->udca_p_base, USBD_UDCAH(udc->udp_baseaddr));
1072
1073	/* Only enable EP0 in and out for now, EP0 only works in FIFO mode */
1074	for (i = 0; i <= 1; i++) {
1075	udc_realize_hwep(udc, hwep: i, maxpacket: ep->ep.maxpacket);
1076	uda_enable_hwepint(udc, hwep: i);
1077	udc_select_hwep(udc, hwep: i);
1078	udc_clrstall_hwep(udc, hwep: i);
1079	udc_clr_buffer_hwep(udc, hwep: i);
1080	}
1081
1082	/* Device interrupt setup */
1083	uda_clear_devint(udc, mask: (USBD_ERR_INT | USBD_DEV_STAT | USBD_EP_SLOW |
1084	USBD_EP_FAST));
1085	uda_enable_devint(udc, devmask: (USBD_ERR_INT | USBD_DEV_STAT | USBD_EP_SLOW |
1086	USBD_EP_FAST));
1087
1088	/* Set device address to 0 - called twice to force a latch in the USB
1089	engine without the need of a setup packet status closure */
1090	udc_set_address(udc, addr: 0);
1091	udc_set_address(udc, addr: 0);
1092
1093	/* Enable master DMA interrupts */
1094	writel(val: (USBD_SYS_ERR_INT | USBD_EOT_INT),
1095	USBD_DMAINTEN(udc->udp_baseaddr));
1096
1097	udc->dev_status = 0;
1098	}
1099
1100	/*
1101	*
1102	* USB device board specific events handled via callbacks
1103	*
1104	*/
1105	/* Connection change event - notify board function of change */
1106	static void uda_power_event(struct lpc32xx_udc *udc, u32 conn)
1107	{
1108	/* Just notify of a connection change event (optional) */
1109	if (udc->board->conn_chgb != NULL)
1110	udc->board->conn_chgb(conn);
1111	}
1112
1113	/* Suspend/resume event - notify board function of change */
1114	static void uda_resm_susp_event(struct lpc32xx_udc *udc, u32 conn)
1115	{
1116	/* Just notify of a Suspend/resume change event (optional) */
1117	if (udc->board->susp_chgb != NULL)
1118	udc->board->susp_chgb(conn);
1119
1120	if (conn)
1121	udc->suspended = 0;
1122	else
1123	udc->suspended = 1;
1124	}
1125
1126	/* Remote wakeup enable/disable - notify board function of change */
1127	static void uda_remwkp_cgh(struct lpc32xx_udc *udc)
1128	{
1129	if (udc->board->rmwk_chgb != NULL)
1130	udc->board->rmwk_chgb(udc->dev_status &
1131	(1 << USB_DEVICE_REMOTE_WAKEUP));
1132	}
1133
1134	/* Reads data from FIFO, adjusts for alignment and data size */
1135	static void udc_pop_fifo(struct lpc32xx_udc *udc, u8 *data, u32 bytes)
1136	{
1137	int n, i, bl;
1138	u16 *p16;
1139	u32 *p32, tmp, cbytes;
1140
1141	/* Use optimal data transfer method based on source address and size */
1142	switch (((uintptr_t) data) & 0x3) {
1143	case 0: /* 32-bit aligned */
1144	p32 = (u32 *) data;
1145	cbytes = (bytes & ~0x3);
1146
1147	/* Copy 32-bit aligned data first */
1148	for (n = 0; n < cbytes; n += 4)
1149	*p32++ = readl(USBD_RXDATA(udc->udp_baseaddr));
1150
1151	/* Handle any remaining bytes */
1152	bl = bytes - cbytes;
1153	if (bl) {
1154	tmp = readl(USBD_RXDATA(udc->udp_baseaddr));
1155	for (n = 0; n < bl; n++)
1156	data[cbytes + n] = ((tmp >> (n * 8)) & 0xFF);
1157
1158	}
1159	break;
1160
1161	case 1: /* 8-bit aligned */
1162	case 3:
1163	/* Each byte has to be handled independently */
1164	for (n = 0; n < bytes; n += 4) {
1165	tmp = readl(USBD_RXDATA(udc->udp_baseaddr));
1166
1167	bl = bytes - n;
1168	if (bl > 4)
1169	bl = 4;
1170
1171	for (i = 0; i < bl; i++)
1172	data[n + i] = (u8) ((tmp >> (i * 8)) & 0xFF);
1173	}
1174	break;
1175
1176	case 2: /* 16-bit aligned */
1177	p16 = (u16 *) data;
1178	cbytes = (bytes & ~0x3);
1179
1180	/* Copy 32-bit sized objects first with 16-bit alignment */
1181	for (n = 0; n < cbytes; n += 4) {
1182	tmp = readl(USBD_RXDATA(udc->udp_baseaddr));
1183	*p16++ = (u16)(tmp & 0xFFFF);
1184	*p16++ = (u16)((tmp >> 16) & 0xFFFF);
1185	}
1186
1187	/* Handle any remaining bytes */
1188	bl = bytes - cbytes;
1189	if (bl) {
1190	tmp = readl(USBD_RXDATA(udc->udp_baseaddr));
1191	for (n = 0; n < bl; n++)
1192	data[cbytes + n] = ((tmp >> (n * 8)) & 0xFF);
1193	}
1194	break;
1195	}
1196	}
1197
1198	/* Read data from the FIFO for an endpoint. This function is for endpoints (such
1199	* as EP0) that don't use DMA. This function should only be called if a packet
1200	* is known to be ready to read for the endpoint. Note that the endpoint must
1201	* be selected in the protocol engine prior to this call. */
1202	static u32 udc_read_hwep(struct lpc32xx_udc *udc, u32 hwep, u32 *data,
1203	u32 bytes)
1204	{
1205	u32 tmpv;
1206	int to = 1000;
1207	u32 tmp, hwrep = ((hwep & 0x1E) << 1) | CTRL_RD_EN;
1208
1209	/* Setup read of endpoint */
1210	writel(val: hwrep, USBD_CTRL(udc->udp_baseaddr));
1211
1212	/* Wait until packet is ready */
1213	while ((((tmpv = readl(USBD_RXPLEN(udc->udp_baseaddr))) &
1214	PKT_RDY) == 0) && (to > 0))
1215	to--;
1216	if (!to)
1217	dev_dbg(udc->dev, "No packet ready on FIFO EP read\n");
1218
1219	/* Mask out count */
1220	tmp = tmpv & PKT_LNGTH_MASK;
1221	if (bytes < tmp)
1222	tmp = bytes;
1223
1224	if ((tmp > 0) && (data != NULL))
1225	udc_pop_fifo(udc, data: (u8 *) data, bytes: tmp);
1226
1227	writel(val: ((hwep & 0x1E) << 1), USBD_CTRL(udc->udp_baseaddr));
1228
1229	/* Clear the buffer */
1230	udc_clr_buffer_hwep(udc, hwep);
1231
1232	return tmp;
1233	}
1234
1235	/* Stuffs data into the FIFO, adjusts for alignment and data size */
1236	static void udc_stuff_fifo(struct lpc32xx_udc *udc, u8 *data, u32 bytes)
1237	{
1238	int n, i, bl;
1239	u16 *p16;
1240	u32 *p32, tmp, cbytes;
1241
1242	/* Use optimal data transfer method based on source address and size */
1243	switch (((uintptr_t) data) & 0x3) {
1244	case 0: /* 32-bit aligned */
1245	p32 = (u32 *) data;
1246	cbytes = (bytes & ~0x3);
1247
1248	/* Copy 32-bit aligned data first */
1249	for (n = 0; n < cbytes; n += 4)
1250	writel(val: *p32++, USBD_TXDATA(udc->udp_baseaddr));
1251
1252	/* Handle any remaining bytes */
1253	bl = bytes - cbytes;
1254	if (bl) {
1255	tmp = 0;
1256	for (n = 0; n < bl; n++)
1257	tmp |= data[cbytes + n] << (n * 8);
1258
1259	writel(val: tmp, USBD_TXDATA(udc->udp_baseaddr));
1260	}
1261	break;
1262
1263	case 1: /* 8-bit aligned */
1264	case 3:
1265	/* Each byte has to be handled independently */
1266	for (n = 0; n < bytes; n += 4) {
1267	bl = bytes - n;
1268	if (bl > 4)
1269	bl = 4;
1270
1271	tmp = 0;
1272	for (i = 0; i < bl; i++)
1273	tmp |= data[n + i] << (i * 8);
1274
1275	writel(val: tmp, USBD_TXDATA(udc->udp_baseaddr));
1276	}
1277	break;
1278
1279	case 2: /* 16-bit aligned */
1280	p16 = (u16 *) data;
1281	cbytes = (bytes & ~0x3);
1282
1283	/* Copy 32-bit aligned data first */
1284	for (n = 0; n < cbytes; n += 4) {
1285	tmp = *p16++ & 0xFFFF;
1286	tmp |= (*p16++ & 0xFFFF) << 16;
1287	writel(val: tmp, USBD_TXDATA(udc->udp_baseaddr));
1288	}
1289
1290	/* Handle any remaining bytes */
1291	bl = bytes - cbytes;
1292	if (bl) {
1293	tmp = 0;
1294	for (n = 0; n < bl; n++)
1295	tmp |= data[cbytes + n] << (n * 8);
1296
1297	writel(val: tmp, USBD_TXDATA(udc->udp_baseaddr));
1298	}
1299	break;
1300	}
1301	}
1302
1303	/* Write data to the FIFO for an endpoint. This function is for endpoints (such
1304	* as EP0) that don't use DMA. Note that the endpoint must be selected in the
1305	* protocol engine prior to this call. */
1306	static void udc_write_hwep(struct lpc32xx_udc *udc, u32 hwep, u32 *data,
1307	u32 bytes)
1308	{
1309	u32 hwwep = ((hwep & 0x1E) << 1) | CTRL_WR_EN;
1310
1311	if ((bytes > 0) && (data == NULL))
1312	return;
1313
1314	/* Setup write of endpoint */
1315	writel(val: hwwep, USBD_CTRL(udc->udp_baseaddr));
1316
1317	writel(val: bytes, USBD_TXPLEN(udc->udp_baseaddr));
1318
1319	/* Need at least 1 byte to trigger TX */
1320	if (bytes == 0)
1321	writel(val: 0, USBD_TXDATA(udc->udp_baseaddr));
1322	else
1323	udc_stuff_fifo(udc, data: (u8 *) data, bytes);
1324
1325	writel(val: ((hwep & 0x1E) << 1), USBD_CTRL(udc->udp_baseaddr));
1326
1327	udc_val_buffer_hwep(udc, hwep);
1328	}
1329
1330	/* USB device reset - resets USB to a default state with just EP0
1331	enabled */
1332	static void uda_usb_reset(struct lpc32xx_udc *udc)
1333	{
1334	u32 i = 0;
1335	/* Re-init device controller and EP0 */
1336	udc_enable(udc);
1337	udc->gadget.speed = USB_SPEED_FULL;
1338
1339	for (i = 1; i < NUM_ENDPOINTS; i++) {
1340	struct lpc32xx_ep *ep = &udc->ep[i];
1341	ep->req_pending = 0;
1342	}
1343	}
1344
1345	/* Send a ZLP on EP0 */
1346	static void udc_ep0_send_zlp(struct lpc32xx_udc *udc)
1347	{
1348	udc_write_hwep(udc, EP_IN, NULL, bytes: 0);
1349	}
1350
1351	/* Get current frame number */
1352	static u16 udc_get_current_frame(struct lpc32xx_udc *udc)
1353	{
1354	u16 flo, fhi;
1355
1356	udc_protocol_cmd_w(udc, CMD_RD_FRAME);
1357	flo = (u16) udc_protocol_cmd_r(udc, DAT_RD_FRAME);
1358	fhi = (u16) udc_protocol_cmd_r(udc, DAT_RD_FRAME);
1359
1360	return (fhi << 8) | flo;
1361	}
1362
1363	/* Set the device as configured - enables all endpoints */
1364	static inline void udc_set_device_configured(struct lpc32xx_udc *udc)
1365	{
1366	udc_protocol_cmd_data_w(udc, CMD_CFG_DEV, DAT_WR_BYTE(CONF_DVICE));
1367	}
1368
1369	/* Set the device as unconfigured - disables all endpoints */
1370	static inline void udc_set_device_unconfigured(struct lpc32xx_udc *udc)
1371	{
1372	udc_protocol_cmd_data_w(udc, CMD_CFG_DEV, DAT_WR_BYTE(0));
1373	}
1374
1375	/* reinit == restore initial software state */
1376	static void udc_reinit(struct lpc32xx_udc *udc)
1377	{
1378	u32 i;
1379
1380	INIT_LIST_HEAD(list: &udc->gadget.ep_list);
1381	INIT_LIST_HEAD(list: &udc->gadget.ep0->ep_list);
1382
1383	for (i = 0; i < NUM_ENDPOINTS; i++) {
1384	struct lpc32xx_ep *ep = &udc->ep[i];
1385
1386	if (i != 0)
1387	list_add_tail(new: &ep->ep.ep_list, head: &udc->gadget.ep_list);
1388	usb_ep_set_maxpacket_limit(ep: &ep->ep, maxpacket_limit: ep->maxpacket);
1389	INIT_LIST_HEAD(list: &ep->queue);
1390	ep->req_pending = 0;
1391	}
1392
1393	udc->ep0state = WAIT_FOR_SETUP;
1394	}
1395
1396	/* Must be called with lock */
1397	static void done(struct lpc32xx_ep *ep, struct lpc32xx_request *req, int status)
1398	{
1399	struct lpc32xx_udc *udc = ep->udc;
1400
1401	list_del_init(entry: &req->queue);
1402	if (req->req.status == -EINPROGRESS)
1403	req->req.status = status;
1404	else
1405	status = req->req.status;
1406
1407	if (ep->lep) {
1408	usb_gadget_unmap_request(gadget: &udc->gadget, req: &req->req, is_in: ep->is_in);
1409
1410	/* Free DDs */
1411	udc_dd_free(udc, dd: req->dd_desc_ptr);
1412	}
1413
1414	if (status && status != -ESHUTDOWN)
1415	ep_dbg(ep, "%s done %p, status %d\n", ep->ep.name, req, status);
1416
1417	ep->req_pending = 0;
1418	spin_unlock(lock: &udc->lock);
1419	usb_gadget_giveback_request(ep: &ep->ep, req: &req->req);
1420	spin_lock(lock: &udc->lock);
1421	}
1422
1423	/* Must be called with lock */
1424	static void nuke(struct lpc32xx_ep *ep, int status)
1425	{
1426	struct lpc32xx_request *req;
1427
1428	while (!list_empty(head: &ep->queue)) {
1429	req = list_entry(ep->queue.next, struct lpc32xx_request, queue);
1430	done(ep, req, status);
1431	}
1432
1433	if (status == -ESHUTDOWN) {
1434	uda_disable_hwepint(udc: ep->udc, hwep: ep->hwep_num);
1435	udc_disable_hwep(udc: ep->udc, hwep: ep->hwep_num);
1436	}
1437	}
1438
1439	/* IN endpoint 0 transfer */
1440	static int udc_ep0_in_req(struct lpc32xx_udc *udc)
1441	{
1442	struct lpc32xx_request *req;
1443	struct lpc32xx_ep *ep0 = &udc->ep[0];
1444	u32 tsend, ts = 0;
1445
1446	if (list_empty(head: &ep0->queue))
1447	/* Nothing to send */
1448	return 0;
1449	else
1450	req = list_entry(ep0->queue.next, struct lpc32xx_request,
1451	queue);
1452
1453	tsend = ts = req->req.length - req->req.actual;
1454	if (ts == 0) {
1455	/* Send a ZLP */
1456	udc_ep0_send_zlp(udc);
1457	done(ep: ep0, req, status: 0);
1458	return 1;
1459	} else if (ts > ep0->ep.maxpacket)
1460	ts = ep0->ep.maxpacket; /* Just send what we can */
1461
1462	/* Write data to the EP0 FIFO and start transfer */
1463	udc_write_hwep(udc, EP_IN, data: (req->req.buf + req->req.actual), bytes: ts);
1464
1465	/* Increment data pointer */
1466	req->req.actual += ts;
1467
1468	if (tsend >= ep0->ep.maxpacket)
1469	return 0; /* Stay in data transfer state */
1470
1471	/* Transfer request is complete */
1472	udc->ep0state = WAIT_FOR_SETUP;
1473	done(ep: ep0, req, status: 0);
1474	return 1;
1475	}
1476
1477	/* OUT endpoint 0 transfer */
1478	static int udc_ep0_out_req(struct lpc32xx_udc *udc)
1479	{
1480	struct lpc32xx_request *req;
1481	struct lpc32xx_ep *ep0 = &udc->ep[0];
1482	u32 tr, bufferspace;
1483
1484	if (list_empty(head: &ep0->queue))
1485	return 0;
1486	else
1487	req = list_entry(ep0->queue.next, struct lpc32xx_request,
1488	queue);
1489
1490	if (req) {
1491	if (req->req.length == 0) {
1492	/* Just dequeue request */
1493	done(ep: ep0, req, status: 0);
1494	udc->ep0state = WAIT_FOR_SETUP;
1495	return 1;
1496	}
1497
1498	/* Get data from FIFO */
1499	bufferspace = req->req.length - req->req.actual;
1500	if (bufferspace > ep0->ep.maxpacket)
1501	bufferspace = ep0->ep.maxpacket;
1502
1503	/* Copy data to buffer */
1504	prefetchw(x: req->req.buf + req->req.actual);
1505	tr = udc_read_hwep(udc, EP_OUT, data: req->req.buf + req->req.actual,
1506	bytes: bufferspace);
1507	req->req.actual += bufferspace;
1508
1509	if (tr < ep0->ep.maxpacket) {
1510	/* This is the last packet */
1511	done(ep: ep0, req, status: 0);
1512	udc->ep0state = WAIT_FOR_SETUP;
1513	return 1;
1514	}
1515	}
1516
1517	return 0;
1518	}
1519
1520	/* Must be called with lock */
1521	static void stop_activity(struct lpc32xx_udc *udc)
1522	{
1523	struct usb_gadget_driver *driver = udc->driver;
1524	int i;
1525
1526	if (udc->gadget.speed == USB_SPEED_UNKNOWN)
1527	driver = NULL;
1528
1529	udc->gadget.speed = USB_SPEED_UNKNOWN;
1530	udc->suspended = 0;
1531
1532	for (i = 0; i < NUM_ENDPOINTS; i++) {
1533	struct lpc32xx_ep *ep = &udc->ep[i];
1534	nuke(ep, status: -ESHUTDOWN);
1535	}
1536	if (driver) {
1537	spin_unlock(lock: &udc->lock);
1538	driver->disconnect(&udc->gadget);
1539	spin_lock(lock: &udc->lock);
1540	}
1541
1542	isp1301_pullup_enable(udc, en_pullup: 0, block: 0);
1543	udc_disable(udc);
1544	udc_reinit(udc);
1545	}
1546
1547	/*
1548	* Activate or kill host pullup
1549	* Can be called with or without lock
1550	*/
1551	static void pullup(struct lpc32xx_udc *udc, int is_on)
1552	{
1553	if (!udc->clocked)
1554	return;
1555
1556	if (!udc->enabled || !udc->vbus)
1557	is_on = 0;
1558
1559	if (is_on != udc->pullup)
1560	isp1301_pullup_enable(udc, en_pullup: is_on, block: 0);
1561	}
1562
1563	/* Must be called without lock */
1564	static int lpc32xx_ep_disable(struct usb_ep *_ep)
1565	{
1566	struct lpc32xx_ep *ep = container_of(_ep, struct lpc32xx_ep, ep);
1567	struct lpc32xx_udc *udc = ep->udc;
1568	unsigned long flags;
1569
1570	if ((ep->hwep_num_base == 0) || (ep->hwep_num == 0))
1571	return -EINVAL;
1572	spin_lock_irqsave(&udc->lock, flags);
1573
1574	nuke(ep, status: -ESHUTDOWN);
1575
1576	/* Clear all DMA statuses for this EP */
1577	udc_ep_dma_disable(udc, hwep: ep->hwep_num);
1578	writel(val: 1 << ep->hwep_num, USBD_EOTINTCLR(udc->udp_baseaddr));
1579	writel(val: 1 << ep->hwep_num, USBD_NDDRTINTCLR(udc->udp_baseaddr));
1580	writel(val: 1 << ep->hwep_num, USBD_SYSERRTINTCLR(udc->udp_baseaddr));
1581	writel(val: 1 << ep->hwep_num, USBD_DMARCLR(udc->udp_baseaddr));
1582
1583	/* Remove the DD pointer in the UDCA */
1584	udc->udca_v_base[ep->hwep_num] = 0;
1585
1586	/* Disable and reset endpoint and interrupt */
1587	uda_clear_hwepint(udc, hwep: ep->hwep_num);
1588	udc_unrealize_hwep(udc, hwep: ep->hwep_num);
1589
1590	ep->hwep_num = 0;
1591
1592	spin_unlock_irqrestore(lock: &udc->lock, flags);
1593
1594	atomic_dec(v: &udc->enabled_ep_cnt);
1595	wake_up(&udc->ep_disable_wait_queue);
1596
1597	return 0;
1598	}
1599
1600	/* Must be called without lock */
1601	static int lpc32xx_ep_enable(struct usb_ep *_ep,
1602	const struct usb_endpoint_descriptor *desc)
1603	{
1604	struct lpc32xx_ep *ep = container_of(_ep, struct lpc32xx_ep, ep);
1605	struct lpc32xx_udc *udc;
1606	u16 maxpacket;
1607	u32 tmp;
1608	unsigned long flags;
1609
1610	/* Verify EP data */
1611	if ((!_ep) || (!ep) || (!desc) ||
1612	(desc->bDescriptorType != USB_DT_ENDPOINT))
1613	return -EINVAL;
1614
1615	udc = ep->udc;
1616	maxpacket = usb_endpoint_maxp(epd: desc);
1617	if ((maxpacket == 0) || (maxpacket > ep->maxpacket)) {
1618	dev_dbg(udc->dev, "bad ep descriptor's packet size\n");
1619	return -EINVAL;
1620	}
1621
1622	/* Don't touch EP0 */
1623	if (ep->hwep_num_base == 0) {
1624	dev_dbg(udc->dev, "Can't re-enable EP0!!!\n");
1625	return -EINVAL;
1626	}
1627
1628	/* Is driver ready? */
1629	if ((!udc->driver) || (udc->gadget.speed == USB_SPEED_UNKNOWN)) {
1630	dev_dbg(udc->dev, "bogus device state\n");
1631	return -ESHUTDOWN;
1632	}
1633
1634	tmp = desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK;
1635	switch (tmp) {
1636	case USB_ENDPOINT_XFER_CONTROL:
1637	return -EINVAL;
1638
1639	case USB_ENDPOINT_XFER_INT:
1640	if (maxpacket > ep->maxpacket) {
1641	dev_dbg(udc->dev,
1642	"Bad INT endpoint maxpacket %d\n", maxpacket);
1643	return -EINVAL;
1644	}
1645	break;
1646
1647	case USB_ENDPOINT_XFER_BULK:
1648	switch (maxpacket) {
1649	case 8:
1650	case 16:
1651	case 32:
1652	case 64:
1653	break;
1654
1655	default:
1656	dev_dbg(udc->dev,
1657	"Bad BULK endpoint maxpacket %d\n", maxpacket);
1658	return -EINVAL;
1659	}
1660	break;
1661
1662	case USB_ENDPOINT_XFER_ISOC:
1663	break;
1664	}
1665	spin_lock_irqsave(&udc->lock, flags);
1666
1667	/* Initialize endpoint to match the selected descriptor */
1668	ep->is_in = (desc->bEndpointAddress & USB_DIR_IN) != 0;
1669	ep->ep.maxpacket = maxpacket;
1670
1671	/* Map hardware endpoint from base and direction */
1672	if (ep->is_in)
1673	/* IN endpoints are offset 1 from the OUT endpoint */
1674	ep->hwep_num = ep->hwep_num_base + EP_IN;
1675	else
1676	ep->hwep_num = ep->hwep_num_base;
1677
1678	ep_dbg(ep, "EP enabled: %s, HW:%d, MP:%d IN:%d\n", ep->ep.name,
1679	ep->hwep_num, maxpacket, (ep->is_in == 1));
1680
1681	/* Realize the endpoint, interrupt is enabled later when
1682	* buffers are queued, IN EPs will NAK until buffers are ready */
1683	udc_realize_hwep(udc, hwep: ep->hwep_num, maxpacket: ep->ep.maxpacket);
1684	udc_clr_buffer_hwep(udc, hwep: ep->hwep_num);
1685	uda_disable_hwepint(udc, hwep: ep->hwep_num);
1686	udc_clrstall_hwep(udc, hwep: ep->hwep_num);
1687
1688	/* Clear all DMA statuses for this EP */
1689	udc_ep_dma_disable(udc, hwep: ep->hwep_num);
1690	writel(val: 1 << ep->hwep_num, USBD_EOTINTCLR(udc->udp_baseaddr));
1691	writel(val: 1 << ep->hwep_num, USBD_NDDRTINTCLR(udc->udp_baseaddr));
1692	writel(val: 1 << ep->hwep_num, USBD_SYSERRTINTCLR(udc->udp_baseaddr));
1693	writel(val: 1 << ep->hwep_num, USBD_DMARCLR(udc->udp_baseaddr));
1694
1695	spin_unlock_irqrestore(lock: &udc->lock, flags);
1696
1697	atomic_inc(v: &udc->enabled_ep_cnt);
1698	return 0;
1699	}
1700
1701	/*
1702	* Allocate a USB request list
1703	* Can be called with or without lock
1704	*/
1705	static struct usb_request *lpc32xx_ep_alloc_request(struct usb_ep *_ep,
1706	gfp_t gfp_flags)
1707	{
1708	struct lpc32xx_request *req;
1709
1710	req = kzalloc(size: sizeof(struct lpc32xx_request), flags: gfp_flags);
1711	if (!req)
1712	return NULL;
1713
1714	INIT_LIST_HEAD(list: &req->queue);
1715	return &req->req;
1716	}
1717
1718	/*
1719	* De-allocate a USB request list
1720	* Can be called with or without lock
1721	*/
1722	static void lpc32xx_ep_free_request(struct usb_ep *_ep,
1723	struct usb_request *_req)
1724	{
1725	struct lpc32xx_request *req;
1726
1727	req = container_of(_req, struct lpc32xx_request, req);
1728	BUG_ON(!list_empty(&req->queue));
1729	kfree(objp: req);
1730	}
1731
1732	/* Must be called without lock */
1733	static int lpc32xx_ep_queue(struct usb_ep *_ep,
1734	struct usb_request *_req, gfp_t gfp_flags)
1735	{
1736	struct lpc32xx_request *req;
1737	struct lpc32xx_ep *ep;
1738	struct lpc32xx_udc *udc;
1739	unsigned long flags;
1740	int status = 0;
1741
1742	req = container_of(_req, struct lpc32xx_request, req);
1743	ep = container_of(_ep, struct lpc32xx_ep, ep);
1744
1745	if (!_ep || !_req || !_req->complete || !_req->buf ||
1746	!list_empty(head: &req->queue))
1747	return -EINVAL;
1748
1749	udc = ep->udc;
1750
1751	if (udc->gadget.speed == USB_SPEED_UNKNOWN)
1752	return -EPIPE;
1753
1754	if (ep->lep) {
1755	struct lpc32xx_usbd_dd_gad *dd;
1756
1757	status = usb_gadget_map_request(gadget: &udc->gadget, req: _req, is_in: ep->is_in);
1758	if (status)
1759	return status;
1760
1761	/* For the request, build a list of DDs */
1762	dd = udc_dd_alloc(udc);
1763	if (!dd) {
1764	/* Error allocating DD */
1765	return -ENOMEM;
1766	}
1767	req->dd_desc_ptr = dd;
1768
1769	/* Setup the DMA descriptor */
1770	dd->dd_next_phy = dd->dd_next_v = 0;
1771	dd->dd_buffer_addr = req->req.dma;
1772	dd->dd_status = 0;
1773
1774	/* Special handling for ISO EPs */
1775	if (ep->eptype == EP_ISO_TYPE) {
1776	dd->dd_setup = DD_SETUP_ISO_EP |
1777	DD_SETUP_PACKETLEN(0) |
1778	DD_SETUP_DMALENBYTES(1);
1779	dd->dd_iso_ps_mem_addr = dd->this_dma + 24;
1780	if (ep->is_in)
1781	dd->iso_status[0] = req->req.length;
1782	else
1783	dd->iso_status[0] = 0;
1784	} else
1785	dd->dd_setup = DD_SETUP_PACKETLEN(ep->ep.maxpacket) |
1786	DD_SETUP_DMALENBYTES(req->req.length);
1787	}
1788
1789	ep_dbg(ep, "%s queue req %p len %d buf %p (in=%d) z=%d\n", _ep->name,
1790	_req, _req->length, _req->buf, ep->is_in, _req->zero);
1791
1792	spin_lock_irqsave(&udc->lock, flags);
1793
1794	_req->status = -EINPROGRESS;
1795	_req->actual = 0;
1796	req->send_zlp = _req->zero;
1797
1798	/* Kickstart empty queues */
1799	if (list_empty(head: &ep->queue)) {
1800	list_add_tail(new: &req->queue, head: &ep->queue);
1801
1802	if (ep->hwep_num_base == 0) {
1803	/* Handle expected data direction */
1804	if (ep->is_in) {
1805	/* IN packet to host */
1806	udc->ep0state = DATA_IN;
1807	status = udc_ep0_in_req(udc);
1808	} else {
1809	/* OUT packet from host */
1810	udc->ep0state = DATA_OUT;
1811	status = udc_ep0_out_req(udc);
1812	}
1813	} else if (ep->is_in) {
1814	/* IN packet to host and kick off transfer */
1815	if (!ep->req_pending)
1816	udc_ep_in_req_dma(udc, ep);
1817	} else
1818	/* OUT packet from host and kick off list */
1819	if (!ep->req_pending)
1820	udc_ep_out_req_dma(udc, ep);
1821	} else
1822	list_add_tail(new: &req->queue, head: &ep->queue);
1823
1824	spin_unlock_irqrestore(lock: &udc->lock, flags);
1825
1826	return (status < 0) ? status : 0;
1827	}
1828
1829	/* Must be called without lock */
1830	static int lpc32xx_ep_dequeue(struct usb_ep *_ep, struct usb_request *_req)
1831	{
1832	struct lpc32xx_ep *ep;
1833	struct lpc32xx_request *req = NULL, *iter;
1834	unsigned long flags;
1835
1836	ep = container_of(_ep, struct lpc32xx_ep, ep);
1837	if (!_ep || ep->hwep_num_base == 0)
1838	return -EINVAL;
1839
1840	spin_lock_irqsave(&ep->udc->lock, flags);
1841
1842	/* make sure it's actually queued on this endpoint */
1843	list_for_each_entry(iter, &ep->queue, queue) {
1844	if (&iter->req != _req)
1845	continue;
1846	req = iter;
1847	break;
1848	}
1849	if (!req) {
1850	spin_unlock_irqrestore(lock: &ep->udc->lock, flags);
1851	return -EINVAL;
1852	}
1853
1854	done(ep, req, status: -ECONNRESET);
1855
1856	spin_unlock_irqrestore(lock: &ep->udc->lock, flags);
1857
1858	return 0;
1859	}
1860
1861	/* Must be called without lock */
1862	static int lpc32xx_ep_set_halt(struct usb_ep *_ep, int value)
1863	{
1864	struct lpc32xx_ep *ep = container_of(_ep, struct lpc32xx_ep, ep);
1865	struct lpc32xx_udc *udc;
1866	unsigned long flags;
1867
1868	if ((!ep) || (ep->hwep_num <= 1))
1869	return -EINVAL;
1870
1871	/* Don't halt an IN EP */
1872	if (ep->is_in)
1873	return -EAGAIN;
1874
1875	udc = ep->udc;
1876	spin_lock_irqsave(&udc->lock, flags);
1877
1878	if (value == 1) {
1879	/* stall */
1880	udc_protocol_cmd_data_w(udc, CMD_SET_EP_STAT(ep->hwep_num),
1881	DAT_WR_BYTE(EP_STAT_ST));
1882	} else {
1883	/* End stall */
1884	ep->wedge = 0;
1885	udc_protocol_cmd_data_w(udc, CMD_SET_EP_STAT(ep->hwep_num),
1886	DAT_WR_BYTE(0));
1887	}
1888
1889	spin_unlock_irqrestore(lock: &udc->lock, flags);
1890
1891	return 0;
1892	}
1893
1894	/* set the halt feature and ignores clear requests */
1895	static int lpc32xx_ep_set_wedge(struct usb_ep *_ep)
1896	{
1897	struct lpc32xx_ep *ep = container_of(_ep, struct lpc32xx_ep, ep);
1898
1899	if (!_ep || !ep->udc)
1900	return -EINVAL;
1901
1902	ep->wedge = 1;
1903
1904	return usb_ep_set_halt(ep: _ep);
1905	}
1906
1907	static const struct usb_ep_ops lpc32xx_ep_ops = {
1908	.enable = lpc32xx_ep_enable,
1909	.disable = lpc32xx_ep_disable,
1910	.alloc_request = lpc32xx_ep_alloc_request,
1911	.free_request = lpc32xx_ep_free_request,
1912	.queue = lpc32xx_ep_queue,
1913	.dequeue = lpc32xx_ep_dequeue,
1914	.set_halt = lpc32xx_ep_set_halt,
1915	.set_wedge = lpc32xx_ep_set_wedge,
1916	};
1917
1918	/* Send a ZLP on a non-0 IN EP */
1919	static void udc_send_in_zlp(struct lpc32xx_udc *udc, struct lpc32xx_ep *ep)
1920	{
1921	/* Clear EP status */
1922	udc_clearep_getsts(udc, hwep: ep->hwep_num);
1923
1924	/* Send ZLP via FIFO mechanism */
1925	udc_write_hwep(udc, hwep: ep->hwep_num, NULL, bytes: 0);
1926	}
1927
1928	/*
1929	* Handle EP completion for ZLP
1930	* This function will only be called when a delayed ZLP needs to be sent out
1931	* after a DMA transfer has filled both buffers.
1932	*/
1933	static void udc_handle_eps(struct lpc32xx_udc *udc, struct lpc32xx_ep *ep)
1934	{
1935	u32 epstatus;
1936	struct lpc32xx_request *req;
1937
1938	if (ep->hwep_num <= 0)
1939	return;
1940
1941	uda_clear_hwepint(udc, hwep: ep->hwep_num);
1942
1943	/* If this interrupt isn't enabled, return now */
1944	if (!(udc->enabled_hwepints & (1 << ep->hwep_num)))
1945	return;
1946
1947	/* Get endpoint status */
1948	epstatus = udc_clearep_getsts(udc, hwep: ep->hwep_num);
1949
1950	/*
1951	* This should never happen, but protect against writing to the
1952	* buffer when full.
1953	*/
1954	if (epstatus & EP_SEL_F)
1955	return;
1956
1957	if (ep->is_in) {
1958	udc_send_in_zlp(udc, ep);
1959	uda_disable_hwepint(udc, hwep: ep->hwep_num);
1960	} else
1961	return;
1962
1963	/* If there isn't a request waiting, something went wrong */
1964	req = list_entry(ep->queue.next, struct lpc32xx_request, queue);
1965	if (req) {
1966	done(ep, req, status: 0);
1967
1968	/* Start another request if ready */
1969	if (!list_empty(head: &ep->queue)) {
1970	if (ep->is_in)
1971	udc_ep_in_req_dma(udc, ep);
1972	else
1973	udc_ep_out_req_dma(udc, ep);
1974	} else
1975	ep->req_pending = 0;
1976	}
1977	}
1978
1979
1980	/* DMA end of transfer completion */
1981	static void udc_handle_dma_ep(struct lpc32xx_udc *udc, struct lpc32xx_ep *ep)
1982	{
1983	u32 status;
1984	struct lpc32xx_request *req;
1985	struct lpc32xx_usbd_dd_gad *dd;
1986
1987	#ifdef CONFIG_USB_GADGET_DEBUG_FILES
1988	ep->totalints++;
1989	#endif
1990
1991	req = list_entry(ep->queue.next, struct lpc32xx_request, queue);
1992	if (!req) {
1993	ep_err(ep, "DMA interrupt on no req!\n");
1994	return;
1995	}
1996	dd = req->dd_desc_ptr;
1997
1998	/* DMA descriptor should always be retired for this call */
1999	if (!(dd->dd_status & DD_STATUS_DD_RETIRED))
2000	ep_warn(ep, "DMA descriptor did not retire\n");
2001
2002	/* Disable DMA */
2003	udc_ep_dma_disable(udc, hwep: ep->hwep_num);
2004	writel(val: (1 << ep->hwep_num), USBD_EOTINTCLR(udc->udp_baseaddr));
2005	writel(val: (1 << ep->hwep_num), USBD_NDDRTINTCLR(udc->udp_baseaddr));
2006
2007	/* System error? */
2008	if (readl(USBD_SYSERRTINTST(udc->udp_baseaddr)) &
2009	(1 << ep->hwep_num)) {
2010	writel(val: (1 << ep->hwep_num),
2011	USBD_SYSERRTINTCLR(udc->udp_baseaddr));
2012	ep_err(ep, "AHB critical error!\n");
2013	ep->req_pending = 0;
2014
2015	/* The error could have occurred on a packet of a multipacket
2016	* transfer, so recovering the transfer is not possible. Close
2017	* the request with an error */
2018	done(ep, req, status: -ECONNABORTED);
2019	return;
2020	}
2021
2022	/* Handle the current DD's status */
2023	status = dd->dd_status;
2024	switch (status & DD_STATUS_STS_MASK) {
2025	case DD_STATUS_STS_NS:
2026	/* DD not serviced? This shouldn't happen! */
2027	ep->req_pending = 0;
2028	ep_err(ep, "DMA critical EP error: DD not serviced (0x%x)!\n",
2029	status);
2030
2031	done(ep, req, status: -ECONNABORTED);
2032	return;
2033
2034	case DD_STATUS_STS_BS:
2035	/* Interrupt only fires on EOT - This shouldn't happen! */
2036	ep->req_pending = 0;
2037	ep_err(ep, "DMA critical EP error: EOT prior to service completion (0x%x)!\n",
2038	status);
2039	done(ep, req, status: -ECONNABORTED);
2040	return;
2041
2042	case DD_STATUS_STS_NC:
2043	case DD_STATUS_STS_DUR:
2044	/* Really just a short packet, not an underrun */
2045	/* This is a good status and what we expect */
2046	break;
2047
2048	default:
2049	/* Data overrun, system error, or unknown */
2050	ep->req_pending = 0;
2051	ep_err(ep, "DMA critical EP error: System error (0x%x)!\n",
2052	status);
2053	done(ep, req, status: -ECONNABORTED);
2054	return;
2055	}
2056
2057	/* ISO endpoints are handled differently */
2058	if (ep->eptype == EP_ISO_TYPE) {
2059	if (ep->is_in)
2060	req->req.actual = req->req.length;
2061	else
2062	req->req.actual = dd->iso_status[0] & 0xFFFF;
2063	} else
2064	req->req.actual += DD_STATUS_CURDMACNT(status);
2065
2066	/* Send a ZLP if necessary. This will be done for non-int
2067	* packets which have a size that is a divisor of MAXP */
2068	if (req->send_zlp) {
2069	/*
2070	* If at least 1 buffer is available, send the ZLP now.
2071	* Otherwise, the ZLP send needs to be deferred until a
2072	* buffer is available.
2073	*/
2074	if (udc_clearep_getsts(udc, hwep: ep->hwep_num) & EP_SEL_F) {
2075	udc_clearep_getsts(udc, hwep: ep->hwep_num);
2076	uda_enable_hwepint(udc, hwep: ep->hwep_num);
2077	udc_clearep_getsts(udc, hwep: ep->hwep_num);
2078
2079	/* Let the EP interrupt handle the ZLP */
2080	return;
2081	} else
2082	udc_send_in_zlp(udc, ep);
2083	}
2084
2085	/* Transfer request is complete */
2086	done(ep, req, status: 0);
2087
2088	/* Start another request if ready */
2089	udc_clearep_getsts(udc, hwep: ep->hwep_num);
2090	if (!list_empty(head: (&ep->queue))) {
2091	if (ep->is_in)
2092	udc_ep_in_req_dma(udc, ep);
2093	else
2094	udc_ep_out_req_dma(udc, ep);
2095	} else
2096	ep->req_pending = 0;
2097
2098	}
2099
2100	/*
2101	*
2102	* Endpoint 0 functions
2103	*
2104	*/
2105	static void udc_handle_dev(struct lpc32xx_udc *udc)
2106	{
2107	u32 tmp;
2108
2109	udc_protocol_cmd_w(udc, CMD_GET_DEV_STAT);
2110	tmp = udc_protocol_cmd_r(udc, DAT_GET_DEV_STAT);
2111
2112	if (tmp & DEV_RST)
2113	uda_usb_reset(udc);
2114	else if (tmp & DEV_CON_CH)
2115	uda_power_event(udc, conn: (tmp & DEV_CON));
2116	else if (tmp & DEV_SUS_CH) {
2117	if (tmp & DEV_SUS) {
2118	if (udc->vbus == 0)
2119	stop_activity(udc);
2120	else if ((udc->gadget.speed != USB_SPEED_UNKNOWN) &&
2121	udc->driver) {
2122	/* Power down transceiver */
2123	udc->poweron = 0;
2124	schedule_work(work: &udc->pullup_job);
2125	uda_resm_susp_event(udc, conn: 1);
2126	}
2127	} else if ((udc->gadget.speed != USB_SPEED_UNKNOWN) &&
2128	udc->driver && udc->vbus) {
2129	uda_resm_susp_event(udc, conn: 0);
2130	/* Power up transceiver */
2131	udc->poweron = 1;
2132	schedule_work(work: &udc->pullup_job);
2133	}
2134	}
2135	}
2136
2137	static int udc_get_status(struct lpc32xx_udc *udc, u16 reqtype, u16 wIndex)
2138	{
2139	struct lpc32xx_ep *ep;
2140	u32 ep0buff = 0, tmp;
2141
2142	switch (reqtype & USB_RECIP_MASK) {
2143	case USB_RECIP_INTERFACE:
2144	break; /* Not supported */
2145
2146	case USB_RECIP_DEVICE:
2147	ep0buff = udc->gadget.is_selfpowered;
2148	if (udc->dev_status & (1 << USB_DEVICE_REMOTE_WAKEUP))
2149	ep0buff |= (1 << USB_DEVICE_REMOTE_WAKEUP);
2150	break;
2151
2152	case USB_RECIP_ENDPOINT:
2153	tmp = wIndex & USB_ENDPOINT_NUMBER_MASK;
2154	ep = &udc->ep[tmp];
2155	if ((tmp == 0) || (tmp >= NUM_ENDPOINTS))
2156	return -EOPNOTSUPP;
2157
2158	if (wIndex & USB_DIR_IN) {
2159	if (!ep->is_in)
2160	return -EOPNOTSUPP; /* Something's wrong */
2161	} else if (ep->is_in)
2162	return -EOPNOTSUPP; /* Not an IN endpoint */
2163
2164	/* Get status of the endpoint */
2165	udc_protocol_cmd_w(udc, CMD_SEL_EP(ep->hwep_num));
2166	tmp = udc_protocol_cmd_r(udc, DAT_SEL_EP(ep->hwep_num));
2167
2168	if (tmp & EP_SEL_ST)
2169	ep0buff = (1 << USB_ENDPOINT_HALT);
2170	else
2171	ep0buff = 0;
2172	break;
2173
2174	default:
2175	break;
2176	}
2177
2178	/* Return data */
2179	udc_write_hwep(udc, EP_IN, data: &ep0buff, bytes: 2);
2180
2181	return 0;
2182	}
2183
2184	static void udc_handle_ep0_setup(struct lpc32xx_udc *udc)
2185	{
2186	struct lpc32xx_ep *ep, *ep0 = &udc->ep[0];
2187	struct usb_ctrlrequest ctrlpkt;
2188	int i, bytes;
2189	u16 wIndex, wValue, reqtype, req, tmp;
2190
2191	/* Nuke previous transfers */
2192	nuke(ep: ep0, status: -EPROTO);
2193
2194	/* Get setup packet */
2195	bytes = udc_read_hwep(udc, EP_OUT, data: (u32 *) &ctrlpkt, bytes: 8);
2196	if (bytes != 8) {
2197	ep_warn(ep0, "Incorrectly sized setup packet (s/b 8, is %d)!\n",
2198	bytes);
2199	return;
2200	}
2201
2202	/* Native endianness */
2203	wIndex = le16_to_cpu(ctrlpkt.wIndex);
2204	wValue = le16_to_cpu(ctrlpkt.wValue);
2205	reqtype = le16_to_cpu(ctrlpkt.bRequestType);
2206
2207	/* Set direction of EP0 */
2208	if (likely(reqtype & USB_DIR_IN))
2209	ep0->is_in = 1;
2210	else
2211	ep0->is_in = 0;
2212
2213	/* Handle SETUP packet */
2214	req = le16_to_cpu(ctrlpkt.bRequest);
2215	switch (req) {
2216	case USB_REQ_CLEAR_FEATURE:
2217	case USB_REQ_SET_FEATURE:
2218	switch (reqtype) {
2219	case (USB_TYPE_STANDARD | USB_RECIP_DEVICE):
2220	if (wValue != USB_DEVICE_REMOTE_WAKEUP)
2221	goto stall; /* Nothing else handled */
2222
2223	/* Tell board about event */
2224	if (req == USB_REQ_CLEAR_FEATURE)
2225	udc->dev_status &=
2226	~(1 << USB_DEVICE_REMOTE_WAKEUP);
2227	else
2228	udc->dev_status |=
2229	(1 << USB_DEVICE_REMOTE_WAKEUP);
2230	uda_remwkp_cgh(udc);
2231	goto zlp_send;
2232
2233	case (USB_TYPE_STANDARD | USB_RECIP_ENDPOINT):
2234	tmp = wIndex & USB_ENDPOINT_NUMBER_MASK;
2235	if ((wValue != USB_ENDPOINT_HALT) ||
2236	(tmp >= NUM_ENDPOINTS))
2237	break;
2238
2239	/* Find hardware endpoint from logical endpoint */
2240	ep = &udc->ep[tmp];
2241	tmp = ep->hwep_num;
2242	if (tmp == 0)
2243	break;
2244
2245	if (req == USB_REQ_SET_FEATURE)
2246	udc_stall_hwep(udc, hwep: tmp);
2247	else if (!ep->wedge)
2248	udc_clrstall_hwep(udc, hwep: tmp);
2249
2250	goto zlp_send;
2251
2252	default:
2253	break;
2254	}
2255	break;
2256
2257	case USB_REQ_SET_ADDRESS:
2258	if (reqtype == (USB_TYPE_STANDARD | USB_RECIP_DEVICE)) {
2259	udc_set_address(udc, addr: wValue);
2260	goto zlp_send;
2261	}
2262	break;
2263
2264	case USB_REQ_GET_STATUS:
2265	udc_get_status(udc, reqtype, wIndex);
2266	return;
2267
2268	default:
2269	break; /* Let GadgetFS handle the descriptor instead */
2270	}
2271
2272	if (likely(udc->driver)) {
2273	/* device-2-host (IN) or no data setup command, process
2274	* immediately */
2275	spin_unlock(lock: &udc->lock);
2276	i = udc->driver->setup(&udc->gadget, &ctrlpkt);
2277
2278	spin_lock(lock: &udc->lock);
2279	if (req == USB_REQ_SET_CONFIGURATION) {
2280	/* Configuration is set after endpoints are realized */
2281	if (wValue) {
2282	/* Set configuration */
2283	udc_set_device_configured(udc);
2284
2285	udc_protocol_cmd_data_w(udc, CMD_SET_MODE,
2286	DAT_WR_BYTE(AP_CLK |
2287	INAK_BI | INAK_II));
2288	} else {
2289	/* Clear configuration */
2290	udc_set_device_unconfigured(udc);
2291
2292	/* Disable NAK interrupts */
2293	udc_protocol_cmd_data_w(udc, CMD_SET_MODE,
2294	DAT_WR_BYTE(AP_CLK));
2295	}
2296	}
2297
2298	if (i < 0) {
2299	/* setup processing failed, force stall */
2300	dev_dbg(udc->dev,
2301	"req %02x.%02x protocol STALL; stat %d\n",
2302	reqtype, req, i);
2303	udc->ep0state = WAIT_FOR_SETUP;
2304	goto stall;
2305	}
2306	}
2307
2308	if (!ep0->is_in)
2309	udc_ep0_send_zlp(udc); /* ZLP IN packet on data phase */
2310
2311	return;
2312
2313	stall:
2314	udc_stall_hwep(udc, EP_IN);
2315	return;
2316
2317	zlp_send:
2318	udc_ep0_send_zlp(udc);
2319	return;
2320	}
2321
2322	/* IN endpoint 0 transfer */
2323	static void udc_handle_ep0_in(struct lpc32xx_udc *udc)
2324	{
2325	struct lpc32xx_ep *ep0 = &udc->ep[0];
2326	u32 epstatus;
2327
2328	/* Clear EP interrupt */
2329	epstatus = udc_clearep_getsts(udc, EP_IN);
2330
2331	#ifdef CONFIG_USB_GADGET_DEBUG_FILES
2332	ep0->totalints++;
2333	#endif
2334
2335	/* Stalled? Clear stall and reset buffers */
2336	if (epstatus & EP_SEL_ST) {
2337	udc_clrstall_hwep(udc, EP_IN);
2338	nuke(ep: ep0, status: -ECONNABORTED);
2339	udc->ep0state = WAIT_FOR_SETUP;
2340	return;
2341	}
2342
2343	/* Is a buffer available? */
2344	if (!(epstatus & EP_SEL_F)) {
2345	/* Handle based on current state */
2346	if (udc->ep0state == DATA_IN)
2347	udc_ep0_in_req(udc);
2348	else {
2349	/* Unknown state for EP0 oe end of DATA IN phase */
2350	nuke(ep: ep0, status: -ECONNABORTED);
2351	udc->ep0state = WAIT_FOR_SETUP;
2352	}
2353	}
2354	}
2355
2356	/* OUT endpoint 0 transfer */
2357	static void udc_handle_ep0_out(struct lpc32xx_udc *udc)
2358	{
2359	struct lpc32xx_ep *ep0 = &udc->ep[0];
2360	u32 epstatus;
2361
2362	/* Clear EP interrupt */
2363	epstatus = udc_clearep_getsts(udc, EP_OUT);
2364
2365
2366	#ifdef CONFIG_USB_GADGET_DEBUG_FILES
2367	ep0->totalints++;
2368	#endif
2369
2370	/* Stalled? */
2371	if (epstatus & EP_SEL_ST) {
2372	udc_clrstall_hwep(udc, EP_OUT);
2373	nuke(ep: ep0, status: -ECONNABORTED);
2374	udc->ep0state = WAIT_FOR_SETUP;
2375	return;
2376	}
2377
2378	/* A NAK may occur if a packet couldn't be received yet */
2379	if (epstatus & EP_SEL_EPN)
2380	return;
2381	/* Setup packet incoming? */
2382	if (epstatus & EP_SEL_STP) {
2383	nuke(ep: ep0, status: 0);
2384	udc->ep0state = WAIT_FOR_SETUP;
2385	}
2386
2387	/* Data available? */
2388	if (epstatus & EP_SEL_F)
2389	/* Handle based on current state */
2390	switch (udc->ep0state) {
2391	case WAIT_FOR_SETUP:
2392	udc_handle_ep0_setup(udc);
2393	break;
2394
2395	case DATA_OUT:
2396	udc_ep0_out_req(udc);
2397	break;
2398
2399	default:
2400	/* Unknown state for EP0 */
2401	nuke(ep: ep0, status: -ECONNABORTED);
2402	udc->ep0state = WAIT_FOR_SETUP;
2403	}
2404	}
2405
2406	/* Must be called without lock */
2407	static int lpc32xx_get_frame(struct usb_gadget *gadget)
2408	{
2409	int frame;
2410	unsigned long flags;
2411	struct lpc32xx_udc *udc = to_udc(g: gadget);
2412
2413	if (!udc->clocked)
2414	return -EINVAL;
2415
2416	spin_lock_irqsave(&udc->lock, flags);
2417
2418	frame = (int) udc_get_current_frame(udc);
2419
2420	spin_unlock_irqrestore(lock: &udc->lock, flags);
2421
2422	return frame;
2423	}
2424
2425	static int lpc32xx_wakeup(struct usb_gadget *gadget)
2426	{
2427	return -ENOTSUPP;
2428	}
2429
2430	static int lpc32xx_set_selfpowered(struct usb_gadget *gadget, int is_on)
2431	{
2432	gadget->is_selfpowered = (is_on != 0);
2433
2434	return 0;
2435	}
2436
2437	/*
2438	* vbus is here! turn everything on that's ready
2439	* Must be called without lock
2440	*/
2441	static int lpc32xx_vbus_session(struct usb_gadget *gadget, int is_active)
2442	{
2443	unsigned long flags;
2444	struct lpc32xx_udc *udc = to_udc(g: gadget);
2445
2446	spin_lock_irqsave(&udc->lock, flags);
2447
2448	/* Doesn't need lock */
2449	if (udc->driver) {
2450	udc_clk_set(udc, enable: 1);
2451	udc_enable(udc);
2452	pullup(udc, is_on: is_active);
2453	} else {
2454	stop_activity(udc);
2455	pullup(udc, is_on: 0);
2456
2457	spin_unlock_irqrestore(lock: &udc->lock, flags);
2458	/*
2459	* Wait for all the endpoints to disable,
2460	* before disabling clocks. Don't wait if
2461	* endpoints are not enabled.
2462	*/
2463	if (atomic_read(v: &udc->enabled_ep_cnt))
2464	wait_event_interruptible(udc->ep_disable_wait_queue,
2465	(atomic_read(&udc->enabled_ep_cnt) == 0));
2466
2467	spin_lock_irqsave(&udc->lock, flags);
2468
2469	udc_clk_set(udc, enable: 0);
2470	}
2471
2472	spin_unlock_irqrestore(lock: &udc->lock, flags);
2473
2474	return 0;
2475	}
2476
2477	/* Can be called with or without lock */
2478	static int lpc32xx_pullup(struct usb_gadget *gadget, int is_on)
2479	{
2480	struct lpc32xx_udc *udc = to_udc(g: gadget);
2481
2482	/* Doesn't need lock */
2483	pullup(udc, is_on);
2484
2485	return 0;
2486	}
2487
2488	static int lpc32xx_start(struct usb_gadget *, struct usb_gadget_driver *);
2489	static int lpc32xx_stop(struct usb_gadget *);
2490
2491	static const struct usb_gadget_ops lpc32xx_udc_ops = {
2492	.get_frame = lpc32xx_get_frame,
2493	.wakeup = lpc32xx_wakeup,
2494	.set_selfpowered = lpc32xx_set_selfpowered,
2495	.vbus_session = lpc32xx_vbus_session,
2496	.pullup = lpc32xx_pullup,
2497	.udc_start = lpc32xx_start,
2498	.udc_stop = lpc32xx_stop,
2499	};
2500
2501	static void nop_release(struct device *dev)
2502	{
2503	/* nothing to free */
2504	}
2505
2506	static const struct lpc32xx_udc controller_template = {
2507	.gadget = {
2508	.ops = &lpc32xx_udc_ops,
2509	.name = driver_name,
2510	.dev = {
2511	.init_name = "gadget",
2512	.release = nop_release,
2513	}
2514	},
2515	.ep[0] = {
2516	.ep = {
2517	.name = "ep0",
2518	.ops = &lpc32xx_ep_ops,
2519	.caps = USB_EP_CAPS(USB_EP_CAPS_TYPE_CONTROL,
2520	USB_EP_CAPS_DIR_ALL),
2521	},
2522	.maxpacket = 64,
2523	.hwep_num_base = 0,
2524	.hwep_num = 0, /* Can be 0 or 1, has special handling */
2525	.lep = 0,
2526	.eptype = EP_CTL_TYPE,
2527	},
2528	.ep[1] = {
2529	.ep = {
2530	.name = "ep1-int",
2531	.ops = &lpc32xx_ep_ops,
2532	.caps = USB_EP_CAPS(USB_EP_CAPS_TYPE_INT,
2533	USB_EP_CAPS_DIR_ALL),
2534	},
2535	.maxpacket = 64,
2536	.hwep_num_base = 2,
2537	.hwep_num = 0, /* 2 or 3, will be set later */
2538	.lep = 1,
2539	.eptype = EP_INT_TYPE,
2540	},
2541	.ep[2] = {
2542	.ep = {
2543	.name = "ep2-bulk",
2544	.ops = &lpc32xx_ep_ops,
2545	.caps = USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK,
2546	USB_EP_CAPS_DIR_ALL),
2547	},
2548	.maxpacket = 64,
2549	.hwep_num_base = 4,
2550	.hwep_num = 0, /* 4 or 5, will be set later */
2551	.lep = 2,
2552	.eptype = EP_BLK_TYPE,
2553	},
2554	.ep[3] = {
2555	.ep = {
2556	.name = "ep3-iso",
2557	.ops = &lpc32xx_ep_ops,
2558	.caps = USB_EP_CAPS(USB_EP_CAPS_TYPE_ISO,
2559	USB_EP_CAPS_DIR_ALL),
2560	},
2561	.maxpacket = 1023,
2562	.hwep_num_base = 6,
2563	.hwep_num = 0, /* 6 or 7, will be set later */
2564	.lep = 3,
2565	.eptype = EP_ISO_TYPE,
2566	},
2567	.ep[4] = {
2568	.ep = {
2569	.name = "ep4-int",
2570	.ops = &lpc32xx_ep_ops,
2571	.caps = USB_EP_CAPS(USB_EP_CAPS_TYPE_INT,
2572	USB_EP_CAPS_DIR_ALL),
2573	},
2574	.maxpacket = 64,
2575	.hwep_num_base = 8,
2576	.hwep_num = 0, /* 8 or 9, will be set later */
2577	.lep = 4,
2578	.eptype = EP_INT_TYPE,
2579	},
2580	.ep[5] = {
2581	.ep = {
2582	.name = "ep5-bulk",
2583	.ops = &lpc32xx_ep_ops,
2584	.caps = USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK,
2585	USB_EP_CAPS_DIR_ALL),
2586	},
2587	.maxpacket = 64,
2588	.hwep_num_base = 10,
2589	.hwep_num = 0, /* 10 or 11, will be set later */
2590	.lep = 5,
2591	.eptype = EP_BLK_TYPE,
2592	},
2593	.ep[6] = {
2594	.ep = {
2595	.name = "ep6-iso",
2596	.ops = &lpc32xx_ep_ops,
2597	.caps = USB_EP_CAPS(USB_EP_CAPS_TYPE_ISO,
2598	USB_EP_CAPS_DIR_ALL),
2599	},
2600	.maxpacket = 1023,
2601	.hwep_num_base = 12,
2602	.hwep_num = 0, /* 12 or 13, will be set later */
2603	.lep = 6,
2604	.eptype = EP_ISO_TYPE,
2605	},
2606	.ep[7] = {
2607	.ep = {
2608	.name = "ep7-int",
2609	.ops = &lpc32xx_ep_ops,
2610	.caps = USB_EP_CAPS(USB_EP_CAPS_TYPE_INT,
2611	USB_EP_CAPS_DIR_ALL),
2612	},
2613	.maxpacket = 64,
2614	.hwep_num_base = 14,
2615	.hwep_num = 0,
2616	.lep = 7,
2617	.eptype = EP_INT_TYPE,
2618	},
2619	.ep[8] = {
2620	.ep = {
2621	.name = "ep8-bulk",
2622	.ops = &lpc32xx_ep_ops,
2623	.caps = USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK,
2624	USB_EP_CAPS_DIR_ALL),
2625	},
2626	.maxpacket = 64,
2627	.hwep_num_base = 16,
2628	.hwep_num = 0,
2629	.lep = 8,
2630	.eptype = EP_BLK_TYPE,
2631	},
2632	.ep[9] = {
2633	.ep = {
2634	.name = "ep9-iso",
2635	.ops = &lpc32xx_ep_ops,
2636	.caps = USB_EP_CAPS(USB_EP_CAPS_TYPE_ISO,
2637	USB_EP_CAPS_DIR_ALL),
2638	},
2639	.maxpacket = 1023,
2640	.hwep_num_base = 18,
2641	.hwep_num = 0,
2642	.lep = 9,
2643	.eptype = EP_ISO_TYPE,
2644	},
2645	.ep[10] = {
2646	.ep = {
2647	.name = "ep10-int",
2648	.ops = &lpc32xx_ep_ops,
2649	.caps = USB_EP_CAPS(USB_EP_CAPS_TYPE_INT,
2650	USB_EP_CAPS_DIR_ALL),
2651	},
2652	.maxpacket = 64,
2653	.hwep_num_base = 20,
2654	.hwep_num = 0,
2655	.lep = 10,
2656	.eptype = EP_INT_TYPE,
2657	},
2658	.ep[11] = {
2659	.ep = {
2660	.name = "ep11-bulk",
2661	.ops = &lpc32xx_ep_ops,
2662	.caps = USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK,
2663	USB_EP_CAPS_DIR_ALL),
2664	},
2665	.maxpacket = 64,
2666	.hwep_num_base = 22,
2667	.hwep_num = 0,
2668	.lep = 11,
2669	.eptype = EP_BLK_TYPE,
2670	},
2671	.ep[12] = {
2672	.ep = {
2673	.name = "ep12-iso",
2674	.ops = &lpc32xx_ep_ops,
2675	.caps = USB_EP_CAPS(USB_EP_CAPS_TYPE_ISO,
2676	USB_EP_CAPS_DIR_ALL),
2677	},
2678	.maxpacket = 1023,
2679	.hwep_num_base = 24,
2680	.hwep_num = 0,
2681	.lep = 12,
2682	.eptype = EP_ISO_TYPE,
2683	},
2684	.ep[13] = {
2685	.ep = {
2686	.name = "ep13-int",
2687	.ops = &lpc32xx_ep_ops,
2688	.caps = USB_EP_CAPS(USB_EP_CAPS_TYPE_INT,
2689	USB_EP_CAPS_DIR_ALL),
2690	},
2691	.maxpacket = 64,
2692	.hwep_num_base = 26,
2693	.hwep_num = 0,
2694	.lep = 13,
2695	.eptype = EP_INT_TYPE,
2696	},
2697	.ep[14] = {
2698	.ep = {
2699	.name = "ep14-bulk",
2700	.ops = &lpc32xx_ep_ops,
2701	.caps = USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK,
2702	USB_EP_CAPS_DIR_ALL),
2703	},
2704	.maxpacket = 64,
2705	.hwep_num_base = 28,
2706	.hwep_num = 0,
2707	.lep = 14,
2708	.eptype = EP_BLK_TYPE,
2709	},
2710	.ep[15] = {
2711	.ep = {
2712	.name = "ep15-bulk",
2713	.ops = &lpc32xx_ep_ops,
2714	.caps = USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK,
2715	USB_EP_CAPS_DIR_ALL),
2716	},
2717	.maxpacket = 1023,
2718	.hwep_num_base = 30,
2719	.hwep_num = 0,
2720	.lep = 15,
2721	.eptype = EP_BLK_TYPE,
2722	},
2723	};
2724
2725	/* ISO and status interrupts */
2726	static irqreturn_t lpc32xx_usb_lp_irq(int irq, void *_udc)
2727	{
2728	u32 tmp, devstat;
2729	struct lpc32xx_udc *udc = _udc;
2730
2731	spin_lock(lock: &udc->lock);
2732
2733	/* Read the device status register */
2734	devstat = readl(USBD_DEVINTST(udc->udp_baseaddr));
2735
2736	devstat &= ~USBD_EP_FAST;
2737	writel(val: devstat, USBD_DEVINTCLR(udc->udp_baseaddr));
2738	devstat = devstat & udc->enabled_devints;
2739
2740	/* Device specific handling needed? */
2741	if (devstat & USBD_DEV_STAT)
2742	udc_handle_dev(udc);
2743
2744	/* Start of frame? (devstat & FRAME_INT):
2745	* The frame interrupt isn't really needed for ISO support,
2746	* as the driver will queue the necessary packets */
2747
2748	/* Error? */
2749	if (devstat & ERR_INT) {
2750	/* All types of errors, from cable removal during transfer to
2751	* misc protocol and bit errors. These are mostly for just info,
2752	* as the USB hardware will work around these. If these errors
2753	* happen alot, something is wrong. */
2754	udc_protocol_cmd_w(udc, CMD_RD_ERR_STAT);
2755	tmp = udc_protocol_cmd_r(udc, DAT_RD_ERR_STAT);
2756	dev_dbg(udc->dev, "Device error (0x%x)!\n", tmp);
2757	}
2758
2759	spin_unlock(lock: &udc->lock);
2760
2761	return IRQ_HANDLED;
2762	}
2763
2764	/* EP interrupts */
2765	static irqreturn_t lpc32xx_usb_hp_irq(int irq, void *_udc)
2766	{
2767	u32 tmp;
2768	struct lpc32xx_udc *udc = _udc;
2769
2770	spin_lock(lock: &udc->lock);
2771
2772	/* Read the device status register */
2773	writel(USBD_EP_FAST, USBD_DEVINTCLR(udc->udp_baseaddr));
2774
2775	/* Endpoints */
2776	tmp = readl(USBD_EPINTST(udc->udp_baseaddr));
2777
2778	/* Special handling for EP0 */
2779	if (tmp & (EP_MASK_SEL(0, EP_OUT) | EP_MASK_SEL(0, EP_IN))) {
2780	/* Handle EP0 IN */
2781	if (tmp & (EP_MASK_SEL(0, EP_IN)))
2782	udc_handle_ep0_in(udc);
2783
2784	/* Handle EP0 OUT */
2785	if (tmp & (EP_MASK_SEL(0, EP_OUT)))
2786	udc_handle_ep0_out(udc);
2787	}
2788
2789	/* All other EPs */
2790	if (tmp & ~(EP_MASK_SEL(0, EP_OUT) | EP_MASK_SEL(0, EP_IN))) {
2791	int i;
2792
2793	/* Handle other EP interrupts */
2794	for (i = 1; i < NUM_ENDPOINTS; i++) {
2795	if (tmp & (1 << udc->ep[i].hwep_num))
2796	udc_handle_eps(udc, ep: &udc->ep[i]);
2797	}
2798	}
2799
2800	spin_unlock(lock: &udc->lock);
2801
2802	return IRQ_HANDLED;
2803	}
2804
2805	static irqreturn_t lpc32xx_usb_devdma_irq(int irq, void *_udc)
2806	{
2807	struct lpc32xx_udc *udc = _udc;
2808
2809	int i;
2810	u32 tmp;
2811
2812	spin_lock(lock: &udc->lock);
2813
2814	/* Handle EP DMA EOT interrupts */
2815	tmp = readl(USBD_EOTINTST(udc->udp_baseaddr)) |
2816	(readl(USBD_EPDMAST(udc->udp_baseaddr)) &
2817	readl(USBD_NDDRTINTST(udc->udp_baseaddr))) |
2818	readl(USBD_SYSERRTINTST(udc->udp_baseaddr));
2819	for (i = 1; i < NUM_ENDPOINTS; i++) {
2820	if (tmp & (1 << udc->ep[i].hwep_num))
2821	udc_handle_dma_ep(udc, ep: &udc->ep[i]);
2822	}
2823
2824	spin_unlock(lock: &udc->lock);
2825
2826	return IRQ_HANDLED;
2827	}
2828
2829	/*
2830	*
2831	* VBUS detection, pullup handler, and Gadget cable state notification
2832	*
2833	*/
2834	static void vbus_work(struct lpc32xx_udc *udc)
2835	{
2836	u8 value;
2837
2838	if (udc->enabled != 0) {
2839	/* Discharge VBUS real quick */
2840	i2c_smbus_write_byte_data(client: udc->isp1301_i2c_client,
2841	ISP1301_I2C_OTG_CONTROL_1, OTG1_VBUS_DISCHRG);
2842
2843	/* Give VBUS some time (100mS) to discharge */
2844	msleep(msecs: 100);
2845
2846	/* Disable VBUS discharge resistor */
2847	i2c_smbus_write_byte_data(client: udc->isp1301_i2c_client,
2848	ISP1301_I2C_OTG_CONTROL_1 | ISP1301_I2C_REG_CLEAR_ADDR,
2849	OTG1_VBUS_DISCHRG);
2850
2851	/* Clear interrupt */
2852	i2c_smbus_write_byte_data(client: udc->isp1301_i2c_client,
2853	ISP1301_I2C_INTERRUPT_LATCH |
2854	ISP1301_I2C_REG_CLEAR_ADDR, value: ~0);
2855
2856	/* Get the VBUS status from the transceiver */
2857	value = i2c_smbus_read_byte_data(client: udc->isp1301_i2c_client,
2858	ISP1301_I2C_INTERRUPT_SOURCE);
2859
2860	/* VBUS on or off? */
2861	if (value & INT_SESS_VLD)
2862	udc->vbus = 1;
2863	else
2864	udc->vbus = 0;
2865
2866	/* VBUS changed? */
2867	if (udc->last_vbus != udc->vbus) {
2868	udc->last_vbus = udc->vbus;
2869	lpc32xx_vbus_session(gadget: &udc->gadget, is_active: udc->vbus);
2870	}
2871	}
2872	}
2873
2874	static irqreturn_t lpc32xx_usb_vbus_irq(int irq, void *_udc)
2875	{
2876	struct lpc32xx_udc *udc = _udc;
2877
2878	vbus_work(udc);
2879
2880	return IRQ_HANDLED;
2881	}
2882
2883	static int lpc32xx_start(struct usb_gadget *gadget,
2884	struct usb_gadget_driver *driver)
2885	{
2886	struct lpc32xx_udc *udc = to_udc(g: gadget);
2887
2888	if (!driver || driver->max_speed < USB_SPEED_FULL || !driver->setup) {
2889	dev_err(udc->dev, "bad parameter.\n");
2890	return -EINVAL;
2891	}
2892
2893	if (udc->driver) {
2894	dev_err(udc->dev, "UDC already has a gadget driver\n");
2895	return -EBUSY;
2896	}
2897
2898	udc->driver = driver;
2899	udc->gadget.dev.of_node = udc->dev->of_node;
2900	udc->enabled = 1;
2901	udc->gadget.is_selfpowered = 1;
2902	udc->vbus = 0;
2903
2904	/* Force VBUS process once to check for cable insertion */
2905	udc->last_vbus = udc->vbus = 0;
2906	vbus_work(udc);
2907
2908	/* enable interrupts */
2909	i2c_smbus_write_byte_data(client: udc->isp1301_i2c_client,
2910	ISP1301_I2C_INTERRUPT_FALLING, INT_SESS_VLD | INT_VBUS_VLD);
2911	i2c_smbus_write_byte_data(client: udc->isp1301_i2c_client,
2912	ISP1301_I2C_INTERRUPT_RISING, INT_SESS_VLD | INT_VBUS_VLD);
2913
2914	return 0;
2915	}
2916
2917	static int lpc32xx_stop(struct usb_gadget *gadget)
2918	{
2919	struct lpc32xx_udc *udc = to_udc(g: gadget);
2920
2921	i2c_smbus_write_byte_data(client: udc->isp1301_i2c_client,
2922	ISP1301_I2C_INTERRUPT_FALLING | ISP1301_I2C_REG_CLEAR_ADDR, value: ~0);
2923	i2c_smbus_write_byte_data(client: udc->isp1301_i2c_client,
2924	ISP1301_I2C_INTERRUPT_RISING | ISP1301_I2C_REG_CLEAR_ADDR, value: ~0);
2925
2926	if (udc->clocked) {
2927	spin_lock(lock: &udc->lock);
2928	stop_activity(udc);
2929	spin_unlock(lock: &udc->lock);
2930
2931	/*
2932	* Wait for all the endpoints to disable,
2933	* before disabling clocks. Don't wait if
2934	* endpoints are not enabled.
2935	*/
2936	if (atomic_read(v: &udc->enabled_ep_cnt))
2937	wait_event_interruptible(udc->ep_disable_wait_queue,
2938	(atomic_read(&udc->enabled_ep_cnt) == 0));
2939
2940	spin_lock(lock: &udc->lock);
2941	udc_clk_set(udc, enable: 0);
2942	spin_unlock(lock: &udc->lock);
2943	}
2944
2945	udc->enabled = 0;
2946	udc->driver = NULL;
2947
2948	return 0;
2949	}
2950
2951	static void lpc32xx_udc_shutdown(struct platform_device *dev)
2952	{
2953	/* Force disconnect on reboot */
2954	struct lpc32xx_udc *udc = platform_get_drvdata(pdev: dev);
2955
2956	pullup(udc, is_on: 0);
2957	}
2958
2959	/*
2960	* Callbacks to be overridden by options passed via OF (TODO)
2961	*/
2962
2963	static void lpc32xx_usbd_conn_chg(int conn)
2964	{
2965	/* Do nothing, it might be nice to enable an LED
2966	* based on conn state being !0 */
2967	}
2968
2969	static void lpc32xx_usbd_susp_chg(int susp)
2970	{
2971	/* Device suspend if susp != 0 */
2972	}
2973
2974	static void lpc32xx_rmwkup_chg(int remote_wakup_enable)
2975	{
2976	/* Enable or disable USB remote wakeup */
2977	}
2978
2979	static struct lpc32xx_usbd_cfg lpc32xx_usbddata = {
2980	.vbus_drv_pol = 0,
2981	.conn_chgb = &lpc32xx_usbd_conn_chg,
2982	.susp_chgb = &lpc32xx_usbd_susp_chg,
2983	.rmwk_chgb = &lpc32xx_rmwkup_chg,
2984	};
2985
2986
2987	static u64 lpc32xx_usbd_dmamask = ~(u32) 0x7F;
2988
2989	static int lpc32xx_udc_probe(struct platform_device *pdev)
2990	{
2991	struct device *dev = &pdev->dev;
2992	struct lpc32xx_udc *udc;
2993	int retval, i;
2994	dma_addr_t dma_handle;
2995	struct device_node *isp1301_node;
2996
2997	udc = devm_kmemdup(dev, src: &controller_template, len: sizeof(*udc), GFP_KERNEL);
2998	if (!udc)
2999	return -ENOMEM;
3000
3001	for (i = 0; i <= 15; i++)
3002	udc->ep[i].udc = udc;
3003	udc->gadget.ep0 = &udc->ep[0].ep;
3004
3005	/* init software state */
3006	udc->gadget.dev.parent = dev;
3007	udc->pdev = pdev;
3008	udc->dev = &pdev->dev;
3009	udc->enabled = 0;
3010
3011	if (pdev->dev.of_node) {
3012	isp1301_node = of_parse_phandle(np: pdev->dev.of_node,
3013	phandle_name: "transceiver", index: 0);
3014	} else {
3015	isp1301_node = NULL;
3016	}
3017
3018	udc->isp1301_i2c_client = isp1301_get_client(node: isp1301_node);
3019	of_node_put(node: isp1301_node);
3020	if (!udc->isp1301_i2c_client) {
3021	return -EPROBE_DEFER;
3022	}
3023
3024	dev_info(udc->dev, "ISP1301 I2C device at address 0x%x\n",
3025	udc->isp1301_i2c_client->addr);
3026
3027	pdev->dev.dma_mask = &lpc32xx_usbd_dmamask;
3028	retval = dma_set_coherent_mask(dev: &pdev->dev, DMA_BIT_MASK(32));
3029	if (retval)
3030	return retval;
3031
3032	udc->board = &lpc32xx_usbddata;
3033
3034	/*
3035	* Resources are mapped as follows:
3036	* IORESOURCE_MEM, base address and size of USB space
3037	* IORESOURCE_IRQ, USB device low priority interrupt number
3038	* IORESOURCE_IRQ, USB device high priority interrupt number
3039	* IORESOURCE_IRQ, USB device interrupt number
3040	* IORESOURCE_IRQ, USB transceiver interrupt number
3041	*/
3042
3043	spin_lock_init(&udc->lock);
3044
3045	/* Get IRQs */
3046	for (i = 0; i < 4; i++) {
3047	udc->udp_irq[i] = platform_get_irq(pdev, i);
3048	if (udc->udp_irq[i] < 0)
3049	return udc->udp_irq[i];
3050	}
3051
3052	udc->udp_baseaddr = devm_platform_ioremap_resource(pdev, index: 0);
3053	if (IS_ERR(ptr: udc->udp_baseaddr)) {
3054	dev_err(udc->dev, "IO map failure\n");
3055	return PTR_ERR(ptr: udc->udp_baseaddr);
3056	}
3057
3058	/* Get USB device clock */
3059	udc->usb_slv_clk = devm_clk_get(dev: &pdev->dev, NULL);
3060	if (IS_ERR(ptr: udc->usb_slv_clk)) {
3061	dev_err(udc->dev, "failed to acquire USB device clock\n");
3062	return PTR_ERR(ptr: udc->usb_slv_clk);
3063	}
3064
3065	/* Enable USB device clock */
3066	retval = clk_prepare_enable(clk: udc->usb_slv_clk);
3067	if (retval < 0) {
3068	dev_err(udc->dev, "failed to start USB device clock\n");
3069	return retval;
3070	}
3071
3072	/* Setup deferred workqueue data */
3073	udc->poweron = udc->pullup = 0;
3074	INIT_WORK(&udc->pullup_job, pullup_work);
3075	#ifdef CONFIG_PM
3076	INIT_WORK(&udc->power_job, power_work);
3077	#endif
3078
3079	/* All clocks are now on */
3080	udc->clocked = 1;
3081
3082	isp1301_udc_configure(udc);
3083	/* Allocate memory for the UDCA */
3084	udc->udca_v_base = dma_alloc_coherent(dev: &pdev->dev, UDCA_BUFF_SIZE,
3085	dma_handle: &dma_handle,
3086	gfp: (GFP_KERNEL | GFP_DMA));
3087	if (!udc->udca_v_base) {
3088	dev_err(udc->dev, "error getting UDCA region\n");
3089	retval = -ENOMEM;
3090	goto i2c_fail;
3091	}
3092	udc->udca_p_base = dma_handle;
3093	dev_dbg(udc->dev, "DMA buffer(0x%x bytes), P:0x%08x, V:0x%p\n",
3094	UDCA_BUFF_SIZE, udc->udca_p_base, udc->udca_v_base);
3095
3096	/* Setup the DD DMA memory pool */
3097	udc->dd_cache = dma_pool_create(name: "udc_dd", dev: udc->dev,
3098	size: sizeof(struct lpc32xx_usbd_dd_gad),
3099	align: sizeof(u32), allocation: 0);
3100	if (!udc->dd_cache) {
3101	dev_err(udc->dev, "error getting DD DMA region\n");
3102	retval = -ENOMEM;
3103	goto dma_alloc_fail;
3104	}
3105
3106	/* Clear USB peripheral and initialize gadget endpoints */
3107	udc_disable(udc);
3108	udc_reinit(udc);
3109
3110	/* Request IRQs - low and high priority USB device IRQs are routed to
3111	* the same handler, while the DMA interrupt is routed elsewhere */
3112	retval = devm_request_irq(dev, irq: udc->udp_irq[IRQ_USB_LP],
3113	handler: lpc32xx_usb_lp_irq, irqflags: 0, devname: "udc_lp", dev_id: udc);
3114	if (retval < 0) {
3115	dev_err(udc->dev, "LP request irq %d failed\n",
3116	udc->udp_irq[IRQ_USB_LP]);
3117	goto irq_req_fail;
3118	}
3119	retval = devm_request_irq(dev, irq: udc->udp_irq[IRQ_USB_HP],
3120	handler: lpc32xx_usb_hp_irq, irqflags: 0, devname: "udc_hp", dev_id: udc);
3121	if (retval < 0) {
3122	dev_err(udc->dev, "HP request irq %d failed\n",
3123	udc->udp_irq[IRQ_USB_HP]);
3124	goto irq_req_fail;
3125	}
3126
3127	retval = devm_request_irq(dev, irq: udc->udp_irq[IRQ_USB_DEVDMA],
3128	handler: lpc32xx_usb_devdma_irq, irqflags: 0, devname: "udc_dma", dev_id: udc);
3129	if (retval < 0) {
3130	dev_err(udc->dev, "DEV request irq %d failed\n",
3131	udc->udp_irq[IRQ_USB_DEVDMA]);
3132	goto irq_req_fail;
3133	}
3134
3135	/* The transceiver interrupt is used for VBUS detection and will
3136	kick off the VBUS handler function */
3137	retval = devm_request_threaded_irq(dev, irq: udc->udp_irq[IRQ_USB_ATX], NULL,
3138	thread_fn: lpc32xx_usb_vbus_irq, IRQF_ONESHOT,
3139	devname: "udc_otg", dev_id: udc);
3140	if (retval < 0) {
3141	dev_err(udc->dev, "VBUS request irq %d failed\n",
3142	udc->udp_irq[IRQ_USB_ATX]);
3143	goto irq_req_fail;
3144	}
3145
3146	/* Initialize wait queue */
3147	init_waitqueue_head(&udc->ep_disable_wait_queue);
3148	atomic_set(v: &udc->enabled_ep_cnt, i: 0);
3149
3150	retval = usb_add_gadget_udc(parent: dev, gadget: &udc->gadget);
3151	if (retval < 0)
3152	goto add_gadget_fail;
3153
3154	dev_set_drvdata(dev, data: udc);
3155	device_init_wakeup(dev, enable: 1);
3156	create_debug_file(udc);
3157
3158	/* Disable clocks for now */
3159	udc_clk_set(udc, enable: 0);
3160
3161	dev_info(udc->dev, "%s version %s\n", driver_name, DRIVER_VERSION);
3162	return 0;
3163
3164	add_gadget_fail:
3165	irq_req_fail:
3166	dma_pool_destroy(pool: udc->dd_cache);
3167	dma_alloc_fail:
3168	dma_free_coherent(dev: &pdev->dev, UDCA_BUFF_SIZE,
3169	cpu_addr: udc->udca_v_base, dma_handle: udc->udca_p_base);
3170	i2c_fail:
3171	clk_disable_unprepare(clk: udc->usb_slv_clk);
3172	dev_err(udc->dev, "%s probe failed, %d\n", driver_name, retval);
3173
3174	return retval;
3175	}
3176
3177	static void lpc32xx_udc_remove(struct platform_device *pdev)
3178	{
3179	struct lpc32xx_udc *udc = platform_get_drvdata(pdev);
3180
3181	usb_del_gadget_udc(gadget: &udc->gadget);
3182	if (udc->driver) {
3183	dev_err(&pdev->dev,
3184	"Driver still in use but removing anyhow\n");
3185	return;
3186	}
3187
3188	udc_clk_set(udc, enable: 1);
3189	udc_disable(udc);
3190	pullup(udc, is_on: 0);
3191
3192	device_init_wakeup(dev: &pdev->dev, enable: 0);
3193	remove_debug_file(udc);
3194
3195	dma_pool_destroy(pool: udc->dd_cache);
3196	dma_free_coherent(dev: &pdev->dev, UDCA_BUFF_SIZE,
3197	cpu_addr: udc->udca_v_base, dma_handle: udc->udca_p_base);
3198
3199	clk_disable_unprepare(clk: udc->usb_slv_clk);
3200	}
3201
3202	#ifdef CONFIG_PM
3203	static int lpc32xx_udc_suspend(struct platform_device *pdev, pm_message_t mesg)
3204	{
3205	struct lpc32xx_udc *udc = platform_get_drvdata(pdev);
3206
3207	if (udc->clocked) {
3208	/* Power down ISP */
3209	udc->poweron = 0;
3210	isp1301_set_powerstate(udc, enable: 0);
3211
3212	/* Disable clocking */
3213	udc_clk_set(udc, enable: 0);
3214
3215	/* Keep clock flag on, so we know to re-enable clocks
3216	on resume */
3217	udc->clocked = 1;
3218
3219	/* Kill global USB clock */
3220	clk_disable_unprepare(clk: udc->usb_slv_clk);
3221	}
3222
3223	return 0;
3224	}
3225
3226	static int lpc32xx_udc_resume(struct platform_device *pdev)
3227	{
3228	struct lpc32xx_udc *udc = platform_get_drvdata(pdev);
3229
3230	if (udc->clocked) {
3231	/* Enable global USB clock */
3232	clk_prepare_enable(clk: udc->usb_slv_clk);
3233
3234	/* Enable clocking */
3235	udc_clk_set(udc, enable: 1);
3236
3237	/* ISP back to normal power mode */
3238	udc->poweron = 1;
3239	isp1301_set_powerstate(udc, enable: 1);
3240	}
3241
3242	return 0;
3243	}
3244	#else
3245	#define lpc32xx_udc_suspend NULL
3246	#define lpc32xx_udc_resume NULL
3247	#endif
3248
3249	#ifdef CONFIG_OF
3250	static const struct of_device_id lpc32xx_udc_of_match[] = {
3251	{ .compatible = "nxp,lpc3220-udc", },
3252	{ },
3253	};
3254	MODULE_DEVICE_TABLE(of, lpc32xx_udc_of_match);
3255	#endif
3256
3257	static struct platform_driver lpc32xx_udc_driver = {
3258	.probe = lpc32xx_udc_probe,
3259	.remove_new = lpc32xx_udc_remove,
3260	.shutdown = lpc32xx_udc_shutdown,
3261	.suspend = lpc32xx_udc_suspend,
3262	.resume = lpc32xx_udc_resume,
3263	.driver = {
3264	.name = driver_name,
3265	.of_match_table = of_match_ptr(lpc32xx_udc_of_match),
3266	},
3267	};
3268
3269	module_platform_driver(lpc32xx_udc_driver);
3270
3271	MODULE_DESCRIPTION("LPC32XX udc driver");
3272	MODULE_AUTHOR("Kevin Wells <kevin.wells@nxp.com>");
3273	MODULE_AUTHOR("Roland Stigge <stigge@antcom.de>");
3274	MODULE_LICENSE("GPL");
3275	MODULE_ALIAS("platform:lpc32xx_udc");
3276