1	/*
2	* linux/drivers/video/pxafb.c
3	*
4	* Copyright (C) 1999 Eric A. Thomas.
5	* Copyright (C) 2004 Jean-Frederic Clere.
6	* Copyright (C) 2004 Ian Campbell.
7	* Copyright (C) 2004 Jeff Lackey.
8	* Based on sa1100fb.c Copyright (C) 1999 Eric A. Thomas
9	* which in turn is
10	* Based on acornfb.c Copyright (C) Russell King.
11	*
12	* This file is subject to the terms and conditions of the GNU General Public
13	* License. See the file COPYING in the main directory of this archive for
14	* more details.
15	*
16	* Intel PXA250/210 LCD Controller Frame Buffer Driver
17	*
18	* Please direct your questions and comments on this driver to the following
19	* email address:
20	*
21	* linux-arm-kernel@lists.arm.linux.org.uk
22	*
23	* Add support for overlay1 and overlay2 based on pxafb_overlay.c:
24	*
25	* Copyright (C) 2004, Intel Corporation
26	*
27	* 2003/08/27: <yu.tang@intel.com>
28	* 2004/03/10: <stanley.cai@intel.com>
29	* 2004/10/28: <yan.yin@intel.com>
30	*
31	* Copyright (C) 2006-2008 Marvell International Ltd.
32	* All Rights Reserved
33	*/
34
35	#include <linux/module.h>
36	#include <linux/moduleparam.h>
37	#include <linux/kernel.h>
38	#include <linux/sched.h>
39	#include <linux/errno.h>
40	#include <linux/string.h>
41	#include <linux/interrupt.h>
42	#include <linux/slab.h>
43	#include <linux/mm.h>
44	#include <linux/fb.h>
45	#include <linux/delay.h>
46	#include <linux/init.h>
47	#include <linux/ioport.h>
48	#include <linux/cpufreq.h>
49	#include <linux/platform_device.h>
50	#include <linux/dma-mapping.h>
51	#include <linux/clk.h>
52	#include <linux/err.h>
53	#include <linux/completion.h>
54	#include <linux/mutex.h>
55	#include <linux/kthread.h>
56	#include <linux/freezer.h>
57	#include <linux/console.h>
58	#include <linux/of_graph.h>
59	#include <linux/regulator/consumer.h>
60	#include <linux/soc/pxa/cpu.h>
61	#include <video/of_display_timing.h>
62	#include <video/videomode.h>
63
64	#include <asm/io.h>
65	#include <asm/irq.h>
66	#include <asm/div64.h>
67	#include <linux/platform_data/video-pxafb.h>
68
69	/*
70	* Complain if VAR is out of range.
71	*/
72	#define DEBUG_VAR 1
73
74	#include "pxafb.h"
75	#include "pxa3xx-regs.h"
76
77	/* Bits which should not be set in machine configuration structures */
78	#define LCCR0_INVALID_CONFIG_MASK (LCCR0_OUM | LCCR0_BM | LCCR0_QDM |\
79	LCCR0_DIS | LCCR0_EFM | LCCR0_IUM |\
80	LCCR0_SFM | LCCR0_LDM | LCCR0_ENB)
81
82	#define LCCR3_INVALID_CONFIG_MASK (LCCR3_HSP | LCCR3_VSP |\
83	LCCR3_PCD | LCCR3_BPP(0xf))
84
85	static int pxafb_activate_var(struct fb_var_screeninfo *var,
86	struct pxafb_info *);
87	static void set_ctrlr_state(struct pxafb_info *fbi, u_int state);
88	static void setup_base_frame(struct pxafb_info *fbi,
89	struct fb_var_screeninfo *var, int branch);
90	static int setup_frame_dma(struct pxafb_info *fbi, int dma, int pal,
91	unsigned long offset, size_t size);
92
93	static unsigned long video_mem_size = 0;
94
95	static inline unsigned long
96	lcd_readl(struct pxafb_info *fbi, unsigned int off)
97	{
98	return __raw_readl(addr: fbi->mmio_base + off);
99	}
100
101	static inline void
102	lcd_writel(struct pxafb_info *fbi, unsigned int off, unsigned long val)
103	{
104	__raw_writel(val, addr: fbi->mmio_base + off);
105	}
106
107	static inline void pxafb_schedule_work(struct pxafb_info *fbi, u_int state)
108	{
109	unsigned long flags;
110
111	local_irq_save(flags);
112	/*
113	* We need to handle two requests being made at the same time.
114	* There are two important cases:
115	* 1. When we are changing VT (C_REENABLE) while unblanking
116	* (C_ENABLE) We must perform the unblanking, which will
117	* do our REENABLE for us.
118	* 2. When we are blanking, but immediately unblank before
119	* we have blanked. We do the "REENABLE" thing here as
120	* well, just to be sure.
121	*/
122	if (fbi->task_state == C_ENABLE && state == C_REENABLE)
123	state = (u_int) -1;
124	if (fbi->task_state == C_DISABLE && state == C_ENABLE)
125	state = C_REENABLE;
126
127	if (state != (u_int)-1) {
128	fbi->task_state = state;
129	schedule_work(work: &fbi->task);
130	}
131	local_irq_restore(flags);
132	}
133
134	static inline u_int chan_to_field(u_int chan, struct fb_bitfield *bf)
135	{
136	chan &= 0xffff;
137	chan >>= 16 - bf->length;
138	return chan << bf->offset;
139	}
140
141	static int
142	pxafb_setpalettereg(u_int regno, u_int red, u_int green, u_int blue,
143	u_int trans, struct fb_info *info)
144	{
145	struct pxafb_info *fbi = container_of(info, struct pxafb_info, fb);
146	u_int val;
147
148	if (regno >= fbi->palette_size)
149	return 1;
150
151	if (fbi->fb.var.grayscale) {
152	fbi->palette_cpu[regno] = ((blue >> 8) & 0x00ff);
153	return 0;
154	}
155
156	switch (fbi->lccr4 & LCCR4_PAL_FOR_MASK) {
157	case LCCR4_PAL_FOR_0:
158	val = ((red >> 0) & 0xf800);
159	val |= ((green >> 5) & 0x07e0);
160	val |= ((blue >> 11) & 0x001f);
161	fbi->palette_cpu[regno] = val;
162	break;
163	case LCCR4_PAL_FOR_1:
164	val = ((red << 8) & 0x00f80000);
165	val |= ((green >> 0) & 0x0000fc00);
166	val |= ((blue >> 8) & 0x000000f8);
167	((u32 *)(fbi->palette_cpu))[regno] = val;
168	break;
169	case LCCR4_PAL_FOR_2:
170	val = ((red << 8) & 0x00fc0000);
171	val |= ((green >> 0) & 0x0000fc00);
172	val |= ((blue >> 8) & 0x000000fc);
173	((u32 *)(fbi->palette_cpu))[regno] = val;
174	break;
175	case LCCR4_PAL_FOR_3:
176	val = ((red << 8) & 0x00ff0000);
177	val |= ((green >> 0) & 0x0000ff00);
178	val |= ((blue >> 8) & 0x000000ff);
179	((u32 *)(fbi->palette_cpu))[regno] = val;
180	break;
181	}
182
183	return 0;
184	}
185
186	static int
187	pxafb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
188	u_int trans, struct fb_info *info)
189	{
190	struct pxafb_info *fbi = container_of(info, struct pxafb_info, fb);
191	unsigned int val;
192	int ret = 1;
193
194	/*
195	* If inverse mode was selected, invert all the colours
196	* rather than the register number. The register number
197	* is what you poke into the framebuffer to produce the
198	* colour you requested.
199	*/
200	if (fbi->cmap_inverse) {
201	red = 0xffff - red;
202	green = 0xffff - green;
203	blue = 0xffff - blue;
204	}
205
206	/*
207	* If greyscale is true, then we convert the RGB value
208	* to greyscale no matter what visual we are using.
209	*/
210	if (fbi->fb.var.grayscale)
211	red = green = blue = (19595 * red + 38470 * green +
212	7471 * blue) >> 16;
213
214	switch (fbi->fb.fix.visual) {
215	case FB_VISUAL_TRUECOLOR:
216	/*
217	* 16-bit True Colour. We encode the RGB value
218	* according to the RGB bitfield information.
219	*/
220	if (regno < 16) {
221	u32 *pal = fbi->fb.pseudo_palette;
222
223	val = chan_to_field(chan: red, bf: &fbi->fb.var.red);
224	val |= chan_to_field(chan: green, bf: &fbi->fb.var.green);
225	val |= chan_to_field(chan: blue, bf: &fbi->fb.var.blue);
226
227	pal[regno] = val;
228	ret = 0;
229	}
230	break;
231
232	case FB_VISUAL_STATIC_PSEUDOCOLOR:
233	case FB_VISUAL_PSEUDOCOLOR:
234	ret = pxafb_setpalettereg(regno, red, green, blue, trans, info);
235	break;
236	}
237
238	return ret;
239	}
240
241	/* calculate pixel depth, transparency bit included, >=16bpp formats _only_ */
242	static inline int var_to_depth(struct fb_var_screeninfo *var)
243	{
244	return var->red.length + var->green.length +
245	var->blue.length + var->transp.length;
246	}
247
248	/* calculate 4-bit BPP value for LCCR3 and OVLxC1 */
249	static int pxafb_var_to_bpp(struct fb_var_screeninfo *var)
250	{
251	int bpp = -EINVAL;
252
253	switch (var->bits_per_pixel) {
254	case 1: bpp = 0; break;
255	case 2: bpp = 1; break;
256	case 4: bpp = 2; break;
257	case 8: bpp = 3; break;
258	case 16: bpp = 4; break;
259	case 24:
260	switch (var_to_depth(var)) {
261	case 18: bpp = 6; break; /* 18-bits/pixel packed */
262	case 19: bpp = 8; break; /* 19-bits/pixel packed */
263	case 24: bpp = 9; break;
264	}
265	break;
266	case 32:
267	switch (var_to_depth(var)) {
268	case 18: bpp = 5; break; /* 18-bits/pixel unpacked */
269	case 19: bpp = 7; break; /* 19-bits/pixel unpacked */
270	case 25: bpp = 10; break;
271	}
272	break;
273	}
274	return bpp;
275	}
276
277	/*
278	* pxafb_var_to_lccr3():
279	* Convert a bits per pixel value to the correct bit pattern for LCCR3
280	*
281	* NOTE: for PXA27x with overlays support, the LCCR3_PDFOR_x bits have an
282	* implication of the acutal use of transparency bit, which we handle it
283	* here separatedly. See PXA27x Developer's Manual, Section <<7.4.6 Pixel
284	* Formats>> for the valid combination of PDFOR, PAL_FOR for various BPP.
285	*
286	* Transparency for palette pixel formats is not supported at the moment.
287	*/
288	static uint32_t pxafb_var_to_lccr3(struct fb_var_screeninfo *var)
289	{
290	int bpp = pxafb_var_to_bpp(var);
291	uint32_t lccr3;
292
293	if (bpp < 0)
294	return 0;
295
296	lccr3 = LCCR3_BPP(bpp);
297
298	switch (var_to_depth(var)) {
299	case 16: lccr3 |= var->transp.length ? LCCR3_PDFOR_3 : 0; break;
300	case 18: lccr3 |= LCCR3_PDFOR_3; break;
301	case 24: lccr3 |= var->transp.length ? LCCR3_PDFOR_2 : LCCR3_PDFOR_3;
302	break;
303	case 19:
304	case 25: lccr3 |= LCCR3_PDFOR_0; break;
305	}
306	return lccr3;
307	}
308
309	#define SET_PIXFMT(v, r, g, b, t) \
310	({ \
311	(v)->transp.offset = (t) ? (r) + (g) + (b) : 0; \
312	(v)->transp.length = (t) ? (t) : 0; \
313	(v)->blue.length = (b); (v)->blue.offset = 0; \
314	(v)->green.length = (g); (v)->green.offset = (b); \
315	(v)->red.length = (r); (v)->red.offset = (b) + (g); \
316	})
317
318	/* set the RGBT bitfields of fb_var_screeninf according to
319	* var->bits_per_pixel and given depth
320	*/
321	static void pxafb_set_pixfmt(struct fb_var_screeninfo *var, int depth)
322	{
323	if (depth == 0)
324	depth = var->bits_per_pixel;
325
326	if (var->bits_per_pixel < 16) {
327	/* indexed pixel formats */
328	var->red.offset = 0; var->red.length = 8;
329	var->green.offset = 0; var->green.length = 8;
330	var->blue.offset = 0; var->blue.length = 8;
331	var->transp.offset = 0; var->transp.length = 8;
332	}
333
334	switch (depth) {
335	case 16: var->transp.length ?
336	SET_PIXFMT(var, 5, 5, 5, 1) : /* RGBT555 */
337	SET_PIXFMT(var, 5, 6, 5, 0); break; /* RGB565 */
338	case 18: SET_PIXFMT(var, 6, 6, 6, 0); break; /* RGB666 */
339	case 19: SET_PIXFMT(var, 6, 6, 6, 1); break; /* RGBT666 */
340	case 24: var->transp.length ?
341	SET_PIXFMT(var, 8, 8, 7, 1) : /* RGBT887 */
342	SET_PIXFMT(var, 8, 8, 8, 0); break; /* RGB888 */
343	case 25: SET_PIXFMT(var, 8, 8, 8, 1); break; /* RGBT888 */
344	}
345	}
346
347	#ifdef CONFIG_CPU_FREQ
348	/*
349	* pxafb_display_dma_period()
350	* Calculate the minimum period (in picoseconds) between two DMA
351	* requests for the LCD controller. If we hit this, it means we're
352	* doing nothing but LCD DMA.
353	*/
354	static unsigned int pxafb_display_dma_period(struct fb_var_screeninfo *var)
355	{
356	/*
357	* Period = pixclock * bits_per_byte * bytes_per_transfer
358	* / memory_bits_per_pixel;
359	*/
360	return var->pixclock * 8 * 16 / var->bits_per_pixel;
361	}
362	#endif
363
364	/*
365	* Select the smallest mode that allows the desired resolution to be
366	* displayed. If desired parameters can be rounded up.
367	*/
368	static struct pxafb_mode_info *pxafb_getmode(struct pxafb_mach_info *mach,
369	struct fb_var_screeninfo *var)
370	{
371	struct pxafb_mode_info *mode = NULL;
372	struct pxafb_mode_info *modelist = mach->modes;
373	unsigned int best_x = 0xffffffff, best_y = 0xffffffff;
374	unsigned int i;
375
376	for (i = 0; i < mach->num_modes; i++) {
377	if (modelist[i].xres >= var->xres &&
378	modelist[i].yres >= var->yres &&
379	modelist[i].xres < best_x &&
380	modelist[i].yres < best_y &&
381	modelist[i].bpp >= var->bits_per_pixel) {
382	best_x = modelist[i].xres;
383	best_y = modelist[i].yres;
384	mode = &modelist[i];
385	}
386	}
387
388	return mode;
389	}
390
391	static void pxafb_setmode(struct fb_var_screeninfo *var,
392	struct pxafb_mode_info *mode)
393	{
394	var->xres = mode->xres;
395	var->yres = mode->yres;
396	var->bits_per_pixel = mode->bpp;
397	var->pixclock = mode->pixclock;
398	var->hsync_len = mode->hsync_len;
399	var->left_margin = mode->left_margin;
400	var->right_margin = mode->right_margin;
401	var->vsync_len = mode->vsync_len;
402	var->upper_margin = mode->upper_margin;
403	var->lower_margin = mode->lower_margin;
404	var->sync = mode->sync;
405	var->grayscale = mode->cmap_greyscale;
406	var->transp.length = mode->transparency;
407
408	/* set the initial RGBA bitfields */
409	pxafb_set_pixfmt(var, depth: mode->depth);
410	}
411
412	static int pxafb_adjust_timing(struct pxafb_info *fbi,
413	struct fb_var_screeninfo *var)
414	{
415	int line_length;
416
417	var->xres = max_t(int, var->xres, MIN_XRES);
418	var->yres = max_t(int, var->yres, MIN_YRES);
419
420	if (!(fbi->lccr0 & LCCR0_LCDT)) {
421	clamp_val(var->hsync_len, 1, 64);
422	clamp_val(var->vsync_len, 1, 64);
423	clamp_val(var->left_margin, 1, 255);
424	clamp_val(var->right_margin, 1, 255);
425	clamp_val(var->upper_margin, 1, 255);
426	clamp_val(var->lower_margin, 1, 255);
427	}
428
429	/* make sure each line is aligned on word boundary */
430	line_length = var->xres * var->bits_per_pixel / 8;
431	line_length = ALIGN(line_length, 4);
432	var->xres = line_length * 8 / var->bits_per_pixel;
433
434	/* we don't support xpan, force xres_virtual to be equal to xres */
435	var->xres_virtual = var->xres;
436
437	if (var->accel_flags & FB_ACCELF_TEXT)
438	var->yres_virtual = fbi->fb.fix.smem_len / line_length;
439	else
440	var->yres_virtual = max(var->yres_virtual, var->yres);
441
442	/* check for limits */
443	if (var->xres > MAX_XRES || var->yres > MAX_YRES)
444	return -EINVAL;
445
446	if (var->yres > var->yres_virtual)
447	return -EINVAL;
448
449	return 0;
450	}
451
452	/*
453	* pxafb_check_var():
454	* Get the video params out of 'var'. If a value doesn't fit, round it up,
455	* if it's too big, return -EINVAL.
456	*
457	* Round up in the following order: bits_per_pixel, xres,
458	* yres, xres_virtual, yres_virtual, xoffset, yoffset, grayscale,
459	* bitfields, horizontal timing, vertical timing.
460	*/
461	static int pxafb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
462	{
463	struct pxafb_info *fbi = container_of(info, struct pxafb_info, fb);
464	struct pxafb_mach_info *inf = fbi->inf;
465	int err;
466
467	if (inf->fixed_modes) {
468	struct pxafb_mode_info *mode;
469
470	mode = pxafb_getmode(mach: inf, var);
471	if (!mode)
472	return -EINVAL;
473	pxafb_setmode(var, mode);
474	}
475
476	/* do a test conversion to BPP fields to check the color formats */
477	err = pxafb_var_to_bpp(var);
478	if (err < 0)
479	return err;
480
481	pxafb_set_pixfmt(var, depth: var_to_depth(var));
482
483	err = pxafb_adjust_timing(fbi, var);
484	if (err)
485	return err;
486
487	#ifdef CONFIG_CPU_FREQ
488	pr_debug("pxafb: dma period = %d ps\n",
489	pxafb_display_dma_period(var));
490	#endif
491
492	return 0;
493	}
494
495	/*
496	* pxafb_set_par():
497	* Set the user defined part of the display for the specified console
498	*/
499	static int pxafb_set_par(struct fb_info *info)
500	{
501	struct pxafb_info *fbi = container_of(info, struct pxafb_info, fb);
502	struct fb_var_screeninfo *var = &info->var;
503
504	if (var->bits_per_pixel >= 16)
505	fbi->fb.fix.visual = FB_VISUAL_TRUECOLOR;
506	else if (!fbi->cmap_static)
507	fbi->fb.fix.visual = FB_VISUAL_PSEUDOCOLOR;
508	else {
509	/*
510	* Some people have weird ideas about wanting static
511	* pseudocolor maps. I suspect their user space
512	* applications are broken.
513	*/
514	fbi->fb.fix.visual = FB_VISUAL_STATIC_PSEUDOCOLOR;
515	}
516
517	fbi->fb.fix.line_length = var->xres_virtual *
518	var->bits_per_pixel / 8;
519	if (var->bits_per_pixel >= 16)
520	fbi->palette_size = 0;
521	else
522	fbi->palette_size = var->bits_per_pixel == 1 ?
523	4 : 1 << var->bits_per_pixel;
524
525	fbi->palette_cpu = (u16 *)&fbi->dma_buff->palette[0];
526
527	if (fbi->fb.var.bits_per_pixel >= 16)
528	fb_dealloc_cmap(cmap: &fbi->fb.cmap);
529	else
530	fb_alloc_cmap(cmap: &fbi->fb.cmap, len: 1<<fbi->fb.var.bits_per_pixel, transp: 0);
531
532	pxafb_activate_var(var, fbi);
533
534	return 0;
535	}
536
537	static int pxafb_pan_display(struct fb_var_screeninfo *var,
538	struct fb_info *info)
539	{
540	struct pxafb_info *fbi = container_of(info, struct pxafb_info, fb);
541	struct fb_var_screeninfo newvar;
542	int dma = DMA_MAX + DMA_BASE;
543
544	if (fbi->state != C_ENABLE)
545	return 0;
546
547	/* Only take .xoffset, .yoffset and .vmode & FB_VMODE_YWRAP from what
548	* was passed in and copy the rest from the old screeninfo.
549	*/
550	memcpy(&newvar, &fbi->fb.var, sizeof(newvar));
551	newvar.xoffset = var->xoffset;
552	newvar.yoffset = var->yoffset;
553	newvar.vmode &= ~FB_VMODE_YWRAP;
554	newvar.vmode |= var->vmode & FB_VMODE_YWRAP;
555
556	setup_base_frame(fbi, var: &newvar, branch: 1);
557
558	if (fbi->lccr0 & LCCR0_SDS)
559	lcd_writel(fbi, FBR1, val: fbi->fdadr[dma + 1] | 0x1);
560
561	lcd_writel(fbi, FBR0, val: fbi->fdadr[dma] | 0x1);
562	return 0;
563	}
564
565	/*
566	* pxafb_blank():
567	* Blank the display by setting all palette values to zero. Note, the
568	* 16 bpp mode does not really use the palette, so this will not
569	* blank the display in all modes.
570	*/
571	static int pxafb_blank(int blank, struct fb_info *info)
572	{
573	struct pxafb_info *fbi = container_of(info, struct pxafb_info, fb);
574	int i;
575
576	switch (blank) {
577	case FB_BLANK_POWERDOWN:
578	case FB_BLANK_VSYNC_SUSPEND:
579	case FB_BLANK_HSYNC_SUSPEND:
580	case FB_BLANK_NORMAL:
581	if (fbi->fb.fix.visual == FB_VISUAL_PSEUDOCOLOR ||
582	fbi->fb.fix.visual == FB_VISUAL_STATIC_PSEUDOCOLOR)
583	for (i = 0; i < fbi->palette_size; i++)
584	pxafb_setpalettereg(regno: i, red: 0, green: 0, blue: 0, trans: 0, info);
585
586	pxafb_schedule_work(fbi, C_DISABLE);
587	/* TODO if (pxafb_blank_helper) pxafb_blank_helper(blank); */
588	break;
589
590	case FB_BLANK_UNBLANK:
591	/* TODO if (pxafb_blank_helper) pxafb_blank_helper(blank); */
592	if (fbi->fb.fix.visual == FB_VISUAL_PSEUDOCOLOR ||
593	fbi->fb.fix.visual == FB_VISUAL_STATIC_PSEUDOCOLOR)
594	fb_set_cmap(cmap: &fbi->fb.cmap, fb_info: info);
595	pxafb_schedule_work(fbi, C_ENABLE);
596	}
597	return 0;
598	}
599
600	static const struct fb_ops pxafb_ops = {
601	.owner = THIS_MODULE,
602	FB_DEFAULT_IOMEM_OPS,
603	.fb_check_var = pxafb_check_var,
604	.fb_set_par = pxafb_set_par,
605	.fb_pan_display = pxafb_pan_display,
606	.fb_setcolreg = pxafb_setcolreg,
607	.fb_blank = pxafb_blank,
608	};
609
610	#ifdef CONFIG_FB_PXA_OVERLAY
611	static void overlay1fb_setup(struct pxafb_layer *ofb)
612	{
613	int size = ofb->fb.fix.line_length * ofb->fb.var.yres_virtual;
614	unsigned long start = ofb->video_mem_phys;
615	setup_frame_dma(ofb->fbi, DMA_OV1, PAL_NONE, start, size);
616	}
617
618	/* Depending on the enable status of overlay1/2, the DMA should be
619	* updated from FDADRx (when disabled) or FBRx (when enabled).
620	*/
621	static void overlay1fb_enable(struct pxafb_layer *ofb)
622	{
623	int enabled = lcd_readl(ofb->fbi, OVL1C1) & OVLxC1_OEN;
624	uint32_t fdadr1 = ofb->fbi->fdadr[DMA_OV1] | (enabled ? 0x1 : 0);
625
626	lcd_writel(ofb->fbi, enabled ? FBR1 : FDADR1, fdadr1);
627	lcd_writel(ofb->fbi, OVL1C2, ofb->control[1]);
628	lcd_writel(ofb->fbi, OVL1C1, ofb->control[0] | OVLxC1_OEN);
629	}
630
631	static void overlay1fb_disable(struct pxafb_layer *ofb)
632	{
633	uint32_t lccr5;
634
635	if (!(lcd_readl(ofb->fbi, OVL1C1) & OVLxC1_OEN))
636	return;
637
638	lccr5 = lcd_readl(ofb->fbi, LCCR5);
639
640	lcd_writel(ofb->fbi, OVL1C1, ofb->control[0] & ~OVLxC1_OEN);
641
642	lcd_writel(ofb->fbi, LCSR1, LCSR1_BS(1));
643	lcd_writel(ofb->fbi, LCCR5, lccr5 & ~LCSR1_BS(1));
644	lcd_writel(ofb->fbi, FBR1, ofb->fbi->fdadr[DMA_OV1] | 0x3);
645
646	if (wait_for_completion_timeout(&ofb->branch_done, 1 * HZ) == 0)
647	pr_warn("%s: timeout disabling overlay1\n", __func__);
648
649	lcd_writel(ofb->fbi, LCCR5, lccr5);
650	}
651
652	static void overlay2fb_setup(struct pxafb_layer *ofb)
653	{
654	int size, div = 1, pfor = NONSTD_TO_PFOR(ofb->fb.var.nonstd);
655	unsigned long start[3] = { ofb->video_mem_phys, 0, 0 };
656
657	if (pfor == OVERLAY_FORMAT_RGB || pfor == OVERLAY_FORMAT_YUV444_PACKED) {
658	size = ofb->fb.fix.line_length * ofb->fb.var.yres_virtual;
659	setup_frame_dma(ofb->fbi, DMA_OV2_Y, -1, start[0], size);
660	} else {
661	size = ofb->fb.var.xres_virtual * ofb->fb.var.yres_virtual;
662	switch (pfor) {
663	case OVERLAY_FORMAT_YUV444_PLANAR: div = 1; break;
664	case OVERLAY_FORMAT_YUV422_PLANAR: div = 2; break;
665	case OVERLAY_FORMAT_YUV420_PLANAR: div = 4; break;
666	}
667	start[1] = start[0] + size;
668	start[2] = start[1] + size / div;
669	setup_frame_dma(ofb->fbi, DMA_OV2_Y, -1, start[0], size);
670	setup_frame_dma(ofb->fbi, DMA_OV2_Cb, -1, start[1], size / div);
671	setup_frame_dma(ofb->fbi, DMA_OV2_Cr, -1, start[2], size / div);
672	}
673	}
674
675	static void overlay2fb_enable(struct pxafb_layer *ofb)
676	{
677	int pfor = NONSTD_TO_PFOR(ofb->fb.var.nonstd);
678	int enabled = lcd_readl(ofb->fbi, OVL2C1) & OVLxC1_OEN;
679	uint32_t fdadr2 = ofb->fbi->fdadr[DMA_OV2_Y] | (enabled ? 0x1 : 0);
680	uint32_t fdadr3 = ofb->fbi->fdadr[DMA_OV2_Cb] | (enabled ? 0x1 : 0);
681	uint32_t fdadr4 = ofb->fbi->fdadr[DMA_OV2_Cr] | (enabled ? 0x1 : 0);
682
683	if (pfor == OVERLAY_FORMAT_RGB || pfor == OVERLAY_FORMAT_YUV444_PACKED)
684	lcd_writel(ofb->fbi, enabled ? FBR2 : FDADR2, fdadr2);
685	else {
686	lcd_writel(ofb->fbi, enabled ? FBR2 : FDADR2, fdadr2);
687	lcd_writel(ofb->fbi, enabled ? FBR3 : FDADR3, fdadr3);
688	lcd_writel(ofb->fbi, enabled ? FBR4 : FDADR4, fdadr4);
689	}
690	lcd_writel(ofb->fbi, OVL2C2, ofb->control[1]);
691	lcd_writel(ofb->fbi, OVL2C1, ofb->control[0] | OVLxC1_OEN);
692	}
693
694	static void overlay2fb_disable(struct pxafb_layer *ofb)
695	{
696	uint32_t lccr5;
697
698	if (!(lcd_readl(ofb->fbi, OVL2C1) & OVLxC1_OEN))
699	return;
700
701	lccr5 = lcd_readl(ofb->fbi, LCCR5);
702
703	lcd_writel(ofb->fbi, OVL2C1, ofb->control[0] & ~OVLxC1_OEN);
704
705	lcd_writel(ofb->fbi, LCSR1, LCSR1_BS(2));
706	lcd_writel(ofb->fbi, LCCR5, lccr5 & ~LCSR1_BS(2));
707	lcd_writel(ofb->fbi, FBR2, ofb->fbi->fdadr[DMA_OV2_Y] | 0x3);
708	lcd_writel(ofb->fbi, FBR3, ofb->fbi->fdadr[DMA_OV2_Cb] | 0x3);
709	lcd_writel(ofb->fbi, FBR4, ofb->fbi->fdadr[DMA_OV2_Cr] | 0x3);
710
711	if (wait_for_completion_timeout(&ofb->branch_done, 1 * HZ) == 0)
712	pr_warn("%s: timeout disabling overlay2\n", __func__);
713	}
714
715	static struct pxafb_layer_ops ofb_ops[] = {
716	[0] = {
717	.enable = overlay1fb_enable,
718	.disable = overlay1fb_disable,
719	.setup = overlay1fb_setup,
720	},
721	[1] = {
722	.enable = overlay2fb_enable,
723	.disable = overlay2fb_disable,
724	.setup = overlay2fb_setup,
725	},
726	};
727
728	static int overlayfb_open(struct fb_info *info, int user)
729	{
730	struct pxafb_layer *ofb = container_of(info, struct pxafb_layer, fb);
731
732	/* no support for framebuffer console on overlay */
733	if (user == 0)
734	return -ENODEV;
735
736	if (ofb->usage++ == 0) {
737	/* unblank the base framebuffer */
738	console_lock();
739	fb_blank(&ofb->fbi->fb, FB_BLANK_UNBLANK);
740	console_unlock();
741	}
742
743	return 0;
744	}
745
746	static int overlayfb_release(struct fb_info *info, int user)
747	{
748	struct pxafb_layer *ofb = container_of(info, struct pxafb_layer, fb);
749
750	if (ofb->usage == 1) {
751	ofb->ops->disable(ofb);
752	ofb->fb.var.height = -1;
753	ofb->fb.var.width = -1;
754	ofb->fb.var.xres = ofb->fb.var.xres_virtual = 0;
755	ofb->fb.var.yres = ofb->fb.var.yres_virtual = 0;
756
757	ofb->usage--;
758	}
759	return 0;
760	}
761
762	static int overlayfb_check_var(struct fb_var_screeninfo *var,
763	struct fb_info *info)
764	{
765	struct pxafb_layer *ofb = container_of(info, struct pxafb_layer, fb);
766	struct fb_var_screeninfo *base_var = &ofb->fbi->fb.var;
767	int xpos, ypos, pfor, bpp;
768
769	xpos = NONSTD_TO_XPOS(var->nonstd);
770	ypos = NONSTD_TO_YPOS(var->nonstd);
771	pfor = NONSTD_TO_PFOR(var->nonstd);
772
773	bpp = pxafb_var_to_bpp(var);
774	if (bpp < 0)
775	return -EINVAL;
776
777	/* no support for YUV format on overlay1 */
778	if (ofb->id == OVERLAY1 && pfor != 0)
779	return -EINVAL;
780
781	/* for YUV packed formats, bpp = 'minimum bpp of YUV components' */
782	switch (pfor) {
783	case OVERLAY_FORMAT_RGB:
784	bpp = pxafb_var_to_bpp(var);
785	if (bpp < 0)
786	return -EINVAL;
787
788	pxafb_set_pixfmt(var, var_to_depth(var));
789	break;
790	case OVERLAY_FORMAT_YUV444_PACKED: bpp = 24; break;
791	case OVERLAY_FORMAT_YUV444_PLANAR: bpp = 8; break;
792	case OVERLAY_FORMAT_YUV422_PLANAR: bpp = 4; break;
793	case OVERLAY_FORMAT_YUV420_PLANAR: bpp = 2; break;
794	default:
795	return -EINVAL;
796	}
797
798	/* each line must start at a 32-bit word boundary */
799	if ((xpos * bpp) % 32)
800	return -EINVAL;
801
802	/* xres must align on 32-bit word boundary */
803	var->xres = roundup(var->xres * bpp, 32) / bpp;
804
805	if ((xpos + var->xres > base_var->xres) ||
806	(ypos + var->yres > base_var->yres))
807	return -EINVAL;
808
809	var->xres_virtual = var->xres;
810	var->yres_virtual = max(var->yres, var->yres_virtual);
811	return 0;
812	}
813
814	static int overlayfb_check_video_memory(struct pxafb_layer *ofb)
815	{
816	struct fb_var_screeninfo *var = &ofb->fb.var;
817	int pfor = NONSTD_TO_PFOR(var->nonstd);
818	int size, bpp = 0;
819
820	switch (pfor) {
821	case OVERLAY_FORMAT_RGB: bpp = var->bits_per_pixel; break;
822	case OVERLAY_FORMAT_YUV444_PACKED: bpp = 24; break;
823	case OVERLAY_FORMAT_YUV444_PLANAR: bpp = 24; break;
824	case OVERLAY_FORMAT_YUV422_PLANAR: bpp = 16; break;
825	case OVERLAY_FORMAT_YUV420_PLANAR: bpp = 12; break;
826	}
827
828	ofb->fb.fix.line_length = var->xres_virtual * bpp / 8;
829
830	size = PAGE_ALIGN(ofb->fb.fix.line_length * var->yres_virtual);
831
832	if (ofb->video_mem) {
833	if (ofb->video_mem_size >= size)
834	return 0;
835	}
836	return -EINVAL;
837	}
838
839	static int overlayfb_set_par(struct fb_info *info)
840	{
841	struct pxafb_layer *ofb = container_of(info, struct pxafb_layer, fb);
842	struct fb_var_screeninfo *var = &info->var;
843	int xpos, ypos, pfor, bpp, ret;
844
845	ret = overlayfb_check_video_memory(ofb);
846	if (ret)
847	return ret;
848
849	bpp = pxafb_var_to_bpp(var);
850	xpos = NONSTD_TO_XPOS(var->nonstd);
851	ypos = NONSTD_TO_YPOS(var->nonstd);
852	pfor = NONSTD_TO_PFOR(var->nonstd);
853
854	ofb->control[0] = OVLxC1_PPL(var->xres) | OVLxC1_LPO(var->yres) |
855	OVLxC1_BPP(bpp);
856	ofb->control[1] = OVLxC2_XPOS(xpos) | OVLxC2_YPOS(ypos);
857
858	if (ofb->id == OVERLAY2)
859	ofb->control[1] |= OVL2C2_PFOR(pfor);
860
861	ofb->ops->setup(ofb);
862	ofb->ops->enable(ofb);
863	return 0;
864	}
865
866	static const struct fb_ops overlay_fb_ops = {
867	.owner = THIS_MODULE,
868	.fb_open = overlayfb_open,
869	.fb_release = overlayfb_release,
870	.fb_check_var = overlayfb_check_var,
871	.fb_set_par = overlayfb_set_par,
872	};
873
874	static void init_pxafb_overlay(struct pxafb_info *fbi, struct pxafb_layer *ofb,
875	int id)
876	{
877	sprintf(ofb->fb.fix.id, "overlay%d", id + 1);
878
879	ofb->fb.fix.type = FB_TYPE_PACKED_PIXELS;
880	ofb->fb.fix.xpanstep = 0;
881	ofb->fb.fix.ypanstep = 1;
882
883	ofb->fb.var.activate = FB_ACTIVATE_NOW;
884	ofb->fb.var.height = -1;
885	ofb->fb.var.width = -1;
886	ofb->fb.var.vmode = FB_VMODE_NONINTERLACED;
887
888	ofb->fb.fbops = &overlay_fb_ops;
889	ofb->fb.node = -1;
890	ofb->fb.pseudo_palette = NULL;
891
892	ofb->id = id;
893	ofb->ops = &ofb_ops[id];
894	ofb->usage = 0;
895	ofb->fbi = fbi;
896	init_completion(&ofb->branch_done);
897	}
898
899	static inline int pxafb_overlay_supported(void)
900	{
901	if (cpu_is_pxa27x() || cpu_is_pxa3xx())
902	return 1;
903
904	return 0;
905	}
906
907	static int pxafb_overlay_map_video_memory(struct pxafb_info *pxafb,
908	struct pxafb_layer *ofb)
909	{
910	/* We assume that user will use at most video_mem_size for overlay fb,
911	* anyway, it's useless to use 16bpp main plane and 24bpp overlay
912	*/
913	ofb->video_mem = alloc_pages_exact(PAGE_ALIGN(pxafb->video_mem_size),
914	GFP_KERNEL | __GFP_ZERO);
915	if (ofb->video_mem == NULL)
916	return -ENOMEM;
917
918	ofb->video_mem_phys = virt_to_phys(ofb->video_mem);
919	ofb->video_mem_size = PAGE_ALIGN(pxafb->video_mem_size);
920
921	mutex_lock(&ofb->fb.mm_lock);
922	ofb->fb.fix.smem_start = ofb->video_mem_phys;
923	ofb->fb.fix.smem_len = pxafb->video_mem_size;
924	mutex_unlock(&ofb->fb.mm_lock);
925
926	ofb->fb.screen_base = ofb->video_mem;
927
928	return 0;
929	}
930
931	static void pxafb_overlay_init(struct pxafb_info *fbi)
932	{
933	int i, ret;
934
935	if (!pxafb_overlay_supported())
936	return;
937
938	for (i = 0; i < 2; i++) {
939	struct pxafb_layer *ofb = &fbi->overlay[i];
940	init_pxafb_overlay(fbi, ofb, i);
941	ret = register_framebuffer(&ofb->fb);
942	if (ret) {
943	dev_err(fbi->dev, "failed to register overlay %d\n", i);
944	continue;
945	}
946	ret = pxafb_overlay_map_video_memory(fbi, ofb);
947	if (ret) {
948	dev_err(fbi->dev,
949	"failed to map video memory for overlay %d\n",
950	i);
951	unregister_framebuffer(&ofb->fb);
952	continue;
953	}
954	ofb->registered = 1;
955	}
956
957	/* mask all IU/BS/EOF/SOF interrupts */
958	lcd_writel(fbi, LCCR5, ~0);
959
960	pr_info("PXA Overlay driver loaded successfully!\n");
961	}
962
963	static void pxafb_overlay_exit(struct pxafb_info *fbi)
964	{
965	int i;
966
967	if (!pxafb_overlay_supported())
968	return;
969
970	for (i = 0; i < 2; i++) {
971	struct pxafb_layer *ofb = &fbi->overlay[i];
972	if (ofb->registered) {
973	if (ofb->video_mem)
974	free_pages_exact(ofb->video_mem,
975	ofb->video_mem_size);
976	unregister_framebuffer(&ofb->fb);
977	}
978	}
979	}
980	#else
981	static inline void pxafb_overlay_init(struct pxafb_info *fbi) {}
982	static inline void pxafb_overlay_exit(struct pxafb_info *fbi) {}
983	#endif /* CONFIG_FB_PXA_OVERLAY */
984
985	/*
986	* Calculate the PCD value from the clock rate (in picoseconds).
987	* We take account of the PPCR clock setting.
988	* From PXA Developer's Manual:
989	*
990	* PixelClock = LCLK
991	* -------------
992	* 2 ( PCD + 1 )
993	*
994	* PCD = LCLK
995	* ------------- - 1
996	* 2(PixelClock)
997	*
998	* Where:
999	* LCLK = LCD/Memory Clock
1000	* PCD = LCCR3[7:0]
1001	*
1002	* PixelClock here is in Hz while the pixclock argument given is the
1003	* period in picoseconds. Hence PixelClock = 1 / ( pixclock * 10^-12 )
1004	*
1005	* The function get_lclk_frequency_10khz returns LCLK in units of
1006	* 10khz. Calling the result of this function lclk gives us the
1007	* following
1008	*
1009	* PCD = (lclk * 10^4 ) * ( pixclock * 10^-12 )
1010	* -------------------------------------- - 1
1011	* 2
1012	*
1013	* Factoring the 10^4 and 10^-12 out gives 10^-8 == 1 / 100000000 as used below.
1014	*/
1015	static inline unsigned int get_pcd(struct pxafb_info *fbi,
1016	unsigned int pixclock)
1017	{
1018	unsigned long long pcd;
1019
1020	/* FIXME: Need to take into account Double Pixel Clock mode
1021	* (DPC) bit? or perhaps set it based on the various clock
1022	* speeds */
1023	pcd = (unsigned long long)(clk_get_rate(clk: fbi->clk) / 10000);
1024	pcd *= pixclock;
1025	do_div(pcd, 100000000 * 2);
1026	/* no need for this, since we should subtract 1 anyway. they cancel */
1027	/* pcd += 1; */ /* make up for integer math truncations */
1028	return (unsigned int)pcd;
1029	}
1030
1031	/*
1032	* Some touchscreens need hsync information from the video driver to
1033	* function correctly. We export it here. Note that 'hsync_time' and
1034	* the value returned from pxafb_get_hsync_time() is the *reciprocal*
1035	* of the hsync period in seconds.
1036	*/
1037	static inline void set_hsync_time(struct pxafb_info *fbi, unsigned int pcd)
1038	{
1039	unsigned long htime;
1040
1041	if ((pcd == 0) || (fbi->fb.var.hsync_len == 0)) {
1042	fbi->hsync_time = 0;
1043	return;
1044	}
1045
1046	htime = clk_get_rate(clk: fbi->clk) / (pcd * fbi->fb.var.hsync_len);
1047
1048	fbi->hsync_time = htime;
1049	}
1050
1051	unsigned long pxafb_get_hsync_time(struct device *dev)
1052	{
1053	struct pxafb_info *fbi = dev_get_drvdata(dev);
1054
1055	/* If display is blanked/suspended, hsync isn't active */
1056	if (!fbi || (fbi->state != C_ENABLE))
1057	return 0;
1058
1059	return fbi->hsync_time;
1060	}
1061	EXPORT_SYMBOL(pxafb_get_hsync_time);
1062
1063	static int setup_frame_dma(struct pxafb_info *fbi, int dma, int pal,
1064	unsigned long start, size_t size)
1065	{
1066	struct pxafb_dma_descriptor *dma_desc, *pal_desc;
1067	unsigned int dma_desc_off, pal_desc_off;
1068
1069	if (dma < 0 || dma >= DMA_MAX * 2)
1070	return -EINVAL;
1071
1072	dma_desc = &fbi->dma_buff->dma_desc[dma];
1073	dma_desc_off = offsetof(struct pxafb_dma_buff, dma_desc[dma]);
1074
1075	dma_desc->fsadr = start;
1076	dma_desc->fidr = 0;
1077	dma_desc->ldcmd = size;
1078
1079	if (pal < 0 || pal >= PAL_MAX * 2) {
1080	dma_desc->fdadr = fbi->dma_buff_phys + dma_desc_off;
1081	fbi->fdadr[dma] = fbi->dma_buff_phys + dma_desc_off;
1082	} else {
1083	pal_desc = &fbi->dma_buff->pal_desc[pal];
1084	pal_desc_off = offsetof(struct pxafb_dma_buff, pal_desc[pal]);
1085
1086	pal_desc->fsadr = fbi->dma_buff_phys + pal * PALETTE_SIZE;
1087	pal_desc->fidr = 0;
1088
1089	if ((fbi->lccr4 & LCCR4_PAL_FOR_MASK) == LCCR4_PAL_FOR_0)
1090	pal_desc->ldcmd = fbi->palette_size * sizeof(u16);
1091	else
1092	pal_desc->ldcmd = fbi->palette_size * sizeof(u32);
1093
1094	pal_desc->ldcmd |= LDCMD_PAL;
1095
1096	/* flip back and forth between palette and frame buffer */
1097	pal_desc->fdadr = fbi->dma_buff_phys + dma_desc_off;
1098	dma_desc->fdadr = fbi->dma_buff_phys + pal_desc_off;
1099	fbi->fdadr[dma] = fbi->dma_buff_phys + dma_desc_off;
1100	}
1101
1102	return 0;
1103	}
1104
1105	static void setup_base_frame(struct pxafb_info *fbi,
1106	struct fb_var_screeninfo *var,
1107	int branch)
1108	{
1109	struct fb_fix_screeninfo *fix = &fbi->fb.fix;
1110	int nbytes, dma, pal, bpp = var->bits_per_pixel;
1111	unsigned long offset;
1112
1113	dma = DMA_BASE + (branch ? DMA_MAX : 0);
1114	pal = (bpp >= 16) ? PAL_NONE : PAL_BASE + (branch ? PAL_MAX : 0);
1115
1116	nbytes = fix->line_length * var->yres;
1117	offset = fix->line_length * var->yoffset + fbi->video_mem_phys;
1118
1119	if (fbi->lccr0 & LCCR0_SDS) {
1120	nbytes = nbytes / 2;
1121	setup_frame_dma(fbi, dma: dma + 1, pal: PAL_NONE, start: offset + nbytes, size: nbytes);
1122	}
1123
1124	setup_frame_dma(fbi, dma, pal, start: offset, size: nbytes);
1125	}
1126
1127	#ifdef CONFIG_FB_PXA_SMARTPANEL
1128	static int setup_smart_dma(struct pxafb_info *fbi)
1129	{
1130	struct pxafb_dma_descriptor *dma_desc;
1131	unsigned long dma_desc_off, cmd_buff_off;
1132
1133	dma_desc = &fbi->dma_buff->dma_desc[DMA_CMD];
1134	dma_desc_off = offsetof(struct pxafb_dma_buff, dma_desc[DMA_CMD]);
1135	cmd_buff_off = offsetof(struct pxafb_dma_buff, cmd_buff);
1136
1137	dma_desc->fdadr = fbi->dma_buff_phys + dma_desc_off;
1138	dma_desc->fsadr = fbi->dma_buff_phys + cmd_buff_off;
1139	dma_desc->fidr = 0;
1140	dma_desc->ldcmd = fbi->n_smart_cmds * sizeof(uint16_t);
1141
1142	fbi->fdadr[DMA_CMD] = dma_desc->fdadr;
1143	return 0;
1144	}
1145
1146	int pxafb_smart_flush(struct fb_info *info)
1147	{
1148	struct pxafb_info *fbi = container_of(info, struct pxafb_info, fb);
1149	uint32_t prsr;
1150	int ret = 0;
1151
1152	/* disable controller until all registers are set up */
1153	lcd_writel(fbi, LCCR0, fbi->reg_lccr0 & ~LCCR0_ENB);
1154
1155	/* 1. make it an even number of commands to align on 32-bit boundary
1156	* 2. add the interrupt command to the end of the chain so we can
1157	* keep track of the end of the transfer
1158	*/
1159
1160	while (fbi->n_smart_cmds & 1)
1161	fbi->smart_cmds[fbi->n_smart_cmds++] = SMART_CMD_NOOP;
1162
1163	fbi->smart_cmds[fbi->n_smart_cmds++] = SMART_CMD_INTERRUPT;
1164	fbi->smart_cmds[fbi->n_smart_cmds++] = SMART_CMD_WAIT_FOR_VSYNC;
1165	setup_smart_dma(fbi);
1166
1167	/* continue to execute next command */
1168	prsr = lcd_readl(fbi, PRSR) | PRSR_ST_OK | PRSR_CON_NT;
1169	lcd_writel(fbi, PRSR, prsr);
1170
1171	/* stop the processor in case it executed "wait for sync" cmd */
1172	lcd_writel(fbi, CMDCR, 0x0001);
1173
1174	/* don't send interrupts for fifo underruns on channel 6 */
1175	lcd_writel(fbi, LCCR5, LCCR5_IUM(6));
1176
1177	lcd_writel(fbi, LCCR1, fbi->reg_lccr1);
1178	lcd_writel(fbi, LCCR2, fbi->reg_lccr2);
1179	lcd_writel(fbi, LCCR3, fbi->reg_lccr3);
1180	lcd_writel(fbi, LCCR4, fbi->reg_lccr4);
1181	lcd_writel(fbi, FDADR0, fbi->fdadr[0]);
1182	lcd_writel(fbi, FDADR6, fbi->fdadr[6]);
1183
1184	/* begin sending */
1185	lcd_writel(fbi, LCCR0, fbi->reg_lccr0 | LCCR0_ENB);
1186
1187	if (wait_for_completion_timeout(&fbi->command_done, HZ/2) == 0) {
1188	pr_warn("%s: timeout waiting for command done\n", __func__);
1189	ret = -ETIMEDOUT;
1190	}
1191
1192	/* quick disable */
1193	prsr = lcd_readl(fbi, PRSR) & ~(PRSR_ST_OK | PRSR_CON_NT);
1194	lcd_writel(fbi, PRSR, prsr);
1195	lcd_writel(fbi, LCCR0, fbi->reg_lccr0 & ~LCCR0_ENB);
1196	lcd_writel(fbi, FDADR6, 0);
1197	fbi->n_smart_cmds = 0;
1198	return ret;
1199	}
1200
1201	int pxafb_smart_queue(struct fb_info *info, uint16_t *cmds, int n_cmds)
1202	{
1203	int i;
1204	struct pxafb_info *fbi = container_of(info, struct pxafb_info, fb);
1205
1206	for (i = 0; i < n_cmds; i++, cmds++) {
1207	/* if it is a software delay, flush and delay */
1208	if ((*cmds & 0xff00) == SMART_CMD_DELAY) {
1209	pxafb_smart_flush(info);
1210	mdelay(*cmds & 0xff);
1211	continue;
1212	}
1213
1214	/* leave 2 commands for INTERRUPT and WAIT_FOR_SYNC */
1215	if (fbi->n_smart_cmds == CMD_BUFF_SIZE - 8)
1216	pxafb_smart_flush(info);
1217
1218	fbi->smart_cmds[fbi->n_smart_cmds++] = *cmds;
1219	}
1220
1221	return 0;
1222	}
1223
1224	static unsigned int __smart_timing(unsigned time_ns, unsigned long lcd_clk)
1225	{
1226	unsigned int t = (time_ns * (lcd_clk / 1000000) / 1000);
1227	return (t == 0) ? 1 : t;
1228	}
1229
1230	static void setup_smart_timing(struct pxafb_info *fbi,
1231	struct fb_var_screeninfo *var)
1232	{
1233	struct pxafb_mach_info *inf = fbi->inf;
1234	struct pxafb_mode_info *mode = &inf->modes[0];
1235	unsigned long lclk = clk_get_rate(fbi->clk);
1236	unsigned t1, t2, t3, t4;
1237
1238	t1 = max(mode->a0csrd_set_hld, mode->a0cswr_set_hld);
1239	t2 = max(mode->rd_pulse_width, mode->wr_pulse_width);
1240	t3 = mode->op_hold_time;
1241	t4 = mode->cmd_inh_time;
1242
1243	fbi->reg_lccr1 =
1244	LCCR1_DisWdth(var->xres) |
1245	LCCR1_BegLnDel(__smart_timing(t1, lclk)) |
1246	LCCR1_EndLnDel(__smart_timing(t2, lclk)) |
1247	LCCR1_HorSnchWdth(__smart_timing(t3, lclk));
1248
1249	fbi->reg_lccr2 = LCCR2_DisHght(var->yres);
1250	fbi->reg_lccr3 = fbi->lccr3 | LCCR3_PixClkDiv(__smart_timing(t4, lclk));
1251	fbi->reg_lccr3 |= (var->sync & FB_SYNC_HOR_HIGH_ACT) ? LCCR3_HSP : 0;
1252	fbi->reg_lccr3 |= (var->sync & FB_SYNC_VERT_HIGH_ACT) ? LCCR3_VSP : 0;
1253
1254	/* FIXME: make this configurable */
1255	fbi->reg_cmdcr = 1;
1256	}
1257
1258	static int pxafb_smart_thread(void *arg)
1259	{
1260	struct pxafb_info *fbi = arg;
1261	struct pxafb_mach_info *inf = fbi->inf;
1262
1263	if (!inf->smart_update) {
1264	pr_err("%s: not properly initialized, thread terminated\n",
1265	__func__);
1266	return -EINVAL;
1267	}
1268
1269	pr_debug("%s(): task starting\n", __func__);
1270
1271	set_freezable();
1272	while (!kthread_should_stop()) {
1273
1274	if (try_to_freeze())
1275	continue;
1276
1277	mutex_lock(&fbi->ctrlr_lock);
1278
1279	if (fbi->state == C_ENABLE) {
1280	inf->smart_update(&fbi->fb);
1281	complete(&fbi->refresh_done);
1282	}
1283
1284	mutex_unlock(&fbi->ctrlr_lock);
1285
1286	set_current_state(TASK_INTERRUPTIBLE);
1287	schedule_timeout(msecs_to_jiffies(30));
1288	}
1289
1290	pr_debug("%s(): task ending\n", __func__);
1291	return 0;
1292	}
1293
1294	static int pxafb_smart_init(struct pxafb_info *fbi)
1295	{
1296	if (!(fbi->lccr0 & LCCR0_LCDT))
1297	return 0;
1298
1299	fbi->smart_cmds = (uint16_t *) fbi->dma_buff->cmd_buff;
1300	fbi->n_smart_cmds = 0;
1301
1302	init_completion(&fbi->command_done);
1303	init_completion(&fbi->refresh_done);
1304
1305	fbi->smart_thread = kthread_run(pxafb_smart_thread, fbi,
1306	"lcd_refresh");
1307	if (IS_ERR(fbi->smart_thread)) {
1308	pr_err("%s: unable to create kernel thread\n", __func__);
1309	return PTR_ERR(fbi->smart_thread);
1310	}
1311
1312	return 0;
1313	}
1314	#else
1315	static inline int pxafb_smart_init(struct pxafb_info *fbi) { return 0; }
1316	#endif /* CONFIG_FB_PXA_SMARTPANEL */
1317
1318	static void setup_parallel_timing(struct pxafb_info *fbi,
1319	struct fb_var_screeninfo *var)
1320	{
1321	unsigned int lines_per_panel, pcd = get_pcd(fbi, pixclock: var->pixclock);
1322
1323	fbi->reg_lccr1 =
1324	LCCR1_DisWdth(var->xres) +
1325	LCCR1_HorSnchWdth(var->hsync_len) +
1326	LCCR1_BegLnDel(var->left_margin) +
1327	LCCR1_EndLnDel(var->right_margin);
1328
1329	/*
1330	* If we have a dual scan LCD, we need to halve
1331	* the YRES parameter.
1332	*/
1333	lines_per_panel = var->yres;
1334	if ((fbi->lccr0 & LCCR0_SDS) == LCCR0_Dual)
1335	lines_per_panel /= 2;
1336
1337	fbi->reg_lccr2 =
1338	LCCR2_DisHght(lines_per_panel) +
1339	LCCR2_VrtSnchWdth(var->vsync_len) +
1340	LCCR2_BegFrmDel(var->upper_margin) +
1341	LCCR2_EndFrmDel(var->lower_margin);
1342
1343	fbi->reg_lccr3 = fbi->lccr3 |
1344	(var->sync & FB_SYNC_HOR_HIGH_ACT ?
1345	LCCR3_HorSnchH : LCCR3_HorSnchL) |
1346	(var->sync & FB_SYNC_VERT_HIGH_ACT ?
1347	LCCR3_VrtSnchH : LCCR3_VrtSnchL);
1348
1349	if (pcd) {
1350	fbi->reg_lccr3 |= LCCR3_PixClkDiv(pcd);
1351	set_hsync_time(fbi, pcd);
1352	}
1353	}
1354
1355	/*
1356	* pxafb_activate_var():
1357	* Configures LCD Controller based on entries in var parameter.
1358	* Settings are only written to the controller if changes were made.
1359	*/
1360	static int pxafb_activate_var(struct fb_var_screeninfo *var,
1361	struct pxafb_info *fbi)
1362	{
1363	u_long flags;
1364
1365	/* Update shadow copy atomically */
1366	local_irq_save(flags);
1367
1368	#ifdef CONFIG_FB_PXA_SMARTPANEL
1369	if (fbi->lccr0 & LCCR0_LCDT)
1370	setup_smart_timing(fbi, var);
1371	else
1372	#endif
1373	setup_parallel_timing(fbi, var);
1374
1375	setup_base_frame(fbi, var, branch: 0);
1376
1377	fbi->reg_lccr0 = fbi->lccr0 |
1378	(LCCR0_LDM | LCCR0_SFM | LCCR0_IUM | LCCR0_EFM |
1379	LCCR0_QDM | LCCR0_BM | LCCR0_OUM);
1380
1381	fbi->reg_lccr3 |= pxafb_var_to_lccr3(var);
1382
1383	fbi->reg_lccr4 = lcd_readl(fbi, LCCR4) & ~LCCR4_PAL_FOR_MASK;
1384	fbi->reg_lccr4 |= (fbi->lccr4 & LCCR4_PAL_FOR_MASK);
1385	local_irq_restore(flags);
1386
1387	/*
1388	* Only update the registers if the controller is enabled
1389	* and something has changed.
1390	*/
1391	if ((lcd_readl(fbi, LCCR0) != fbi->reg_lccr0) ||
1392	(lcd_readl(fbi, LCCR1) != fbi->reg_lccr1) ||
1393	(lcd_readl(fbi, LCCR2) != fbi->reg_lccr2) ||
1394	(lcd_readl(fbi, LCCR3) != fbi->reg_lccr3) ||
1395	(lcd_readl(fbi, LCCR4) != fbi->reg_lccr4) ||
1396	(lcd_readl(fbi, FDADR0) != fbi->fdadr[0]) ||
1397	((fbi->lccr0 & LCCR0_SDS) &&
1398	(lcd_readl(fbi, FDADR1) != fbi->fdadr[1])))
1399	pxafb_schedule_work(fbi, C_REENABLE);
1400
1401	return 0;
1402	}
1403
1404	/*
1405	* NOTE! The following functions are purely helpers for set_ctrlr_state.
1406	* Do not call them directly; set_ctrlr_state does the correct serialisation
1407	* to ensure that things happen in the right way 100% of time time.
1408	* -- rmk
1409	*/
1410	static inline void __pxafb_backlight_power(struct pxafb_info *fbi, int on)
1411	{
1412	pr_debug("pxafb: backlight o%s\n", on ? "n" : "ff");
1413
1414	if (fbi->backlight_power)
1415	fbi->backlight_power(on);
1416	}
1417
1418	static inline void __pxafb_lcd_power(struct pxafb_info *fbi, int on)
1419	{
1420	pr_debug("pxafb: LCD power o%s\n", on ? "n" : "ff");
1421
1422	if (fbi->lcd_power)
1423	fbi->lcd_power(on, &fbi->fb.var);
1424
1425	if (fbi->lcd_supply && fbi->lcd_supply_enabled != on) {
1426	int ret;
1427
1428	if (on)
1429	ret = regulator_enable(regulator: fbi->lcd_supply);
1430	else
1431	ret = regulator_disable(regulator: fbi->lcd_supply);
1432
1433	if (ret < 0)
1434	pr_warn("Unable to %s LCD supply regulator: %d\n",
1435	on ? "enable" : "disable", ret);
1436	else
1437	fbi->lcd_supply_enabled = on;
1438	}
1439	}
1440
1441	static void pxafb_enable_controller(struct pxafb_info *fbi)
1442	{
1443	pr_debug("pxafb: Enabling LCD controller\n");
1444	pr_debug("fdadr0 0x%08x\n", (unsigned int) fbi->fdadr[0]);
1445	pr_debug("fdadr1 0x%08x\n", (unsigned int) fbi->fdadr[1]);
1446	pr_debug("reg_lccr0 0x%08x\n", (unsigned int) fbi->reg_lccr0);
1447	pr_debug("reg_lccr1 0x%08x\n", (unsigned int) fbi->reg_lccr1);
1448	pr_debug("reg_lccr2 0x%08x\n", (unsigned int) fbi->reg_lccr2);
1449	pr_debug("reg_lccr3 0x%08x\n", (unsigned int) fbi->reg_lccr3);
1450
1451	/* enable LCD controller clock */
1452	if (clk_prepare_enable(clk: fbi->clk)) {
1453	pr_err("%s: Failed to prepare clock\n", __func__);
1454	return;
1455	}
1456
1457	if (fbi->lccr0 & LCCR0_LCDT)
1458	return;
1459
1460	/* Sequence from 11.7.10 */
1461	lcd_writel(fbi, LCCR4, val: fbi->reg_lccr4);
1462	lcd_writel(fbi, LCCR3, val: fbi->reg_lccr3);
1463	lcd_writel(fbi, LCCR2, val: fbi->reg_lccr2);
1464	lcd_writel(fbi, LCCR1, val: fbi->reg_lccr1);
1465	lcd_writel(fbi, LCCR0, val: fbi->reg_lccr0 & ~LCCR0_ENB);
1466
1467	lcd_writel(fbi, FDADR0, val: fbi->fdadr[0]);
1468	if (fbi->lccr0 & LCCR0_SDS)
1469	lcd_writel(fbi, FDADR1, val: fbi->fdadr[1]);
1470	lcd_writel(fbi, LCCR0, val: fbi->reg_lccr0 | LCCR0_ENB);
1471	}
1472
1473	static void pxafb_disable_controller(struct pxafb_info *fbi)
1474	{
1475	uint32_t lccr0;
1476
1477	#ifdef CONFIG_FB_PXA_SMARTPANEL
1478	if (fbi->lccr0 & LCCR0_LCDT) {
1479	wait_for_completion_timeout(&fbi->refresh_done,
1480	msecs_to_jiffies(200));
1481	return;
1482	}
1483	#endif
1484
1485	/* Clear LCD Status Register */
1486	lcd_writel(fbi, LCSR, val: 0xffffffff);
1487
1488	lccr0 = lcd_readl(fbi, LCCR0) & ~LCCR0_LDM;
1489	lcd_writel(fbi, LCCR0, val: lccr0);
1490	lcd_writel(fbi, LCCR0, val: lccr0 | LCCR0_DIS);
1491
1492	wait_for_completion_timeout(x: &fbi->disable_done, timeout: msecs_to_jiffies(m: 200));
1493
1494	/* disable LCD controller clock */
1495	clk_disable_unprepare(clk: fbi->clk);
1496	}
1497
1498	/*
1499	* pxafb_handle_irq: Handle 'LCD DONE' interrupts.
1500	*/
1501	static irqreturn_t pxafb_handle_irq(int irq, void *dev_id)
1502	{
1503	struct pxafb_info *fbi = dev_id;
1504	unsigned int lccr0, lcsr;
1505
1506	lcsr = lcd_readl(fbi, LCSR);
1507	if (lcsr & LCSR_LDD) {
1508	lccr0 = lcd_readl(fbi, LCCR0);
1509	lcd_writel(fbi, LCCR0, val: lccr0 | LCCR0_LDM);
1510	complete(&fbi->disable_done);
1511	}
1512
1513	#ifdef CONFIG_FB_PXA_SMARTPANEL
1514	if (lcsr & LCSR_CMD_INT)
1515	complete(&fbi->command_done);
1516	#endif
1517	lcd_writel(fbi, LCSR, val: lcsr);
1518
1519	#ifdef CONFIG_FB_PXA_OVERLAY
1520	{
1521	unsigned int lcsr1 = lcd_readl(fbi, LCSR1);
1522	if (lcsr1 & LCSR1_BS(1))
1523	complete(&fbi->overlay[0].branch_done);
1524
1525	if (lcsr1 & LCSR1_BS(2))
1526	complete(&fbi->overlay[1].branch_done);
1527
1528	lcd_writel(fbi, LCSR1, lcsr1);
1529	}
1530	#endif
1531	return IRQ_HANDLED;
1532	}
1533
1534	/*
1535	* This function must be called from task context only, since it will
1536	* sleep when disabling the LCD controller, or if we get two contending
1537	* processes trying to alter state.
1538	*/
1539	static void set_ctrlr_state(struct pxafb_info *fbi, u_int state)
1540	{
1541	u_int old_state;
1542
1543	mutex_lock(&fbi->ctrlr_lock);
1544
1545	old_state = fbi->state;
1546
1547	/*
1548	* Hack around fbcon initialisation.
1549	*/
1550	if (old_state == C_STARTUP && state == C_REENABLE)
1551	state = C_ENABLE;
1552
1553	switch (state) {
1554	case C_DISABLE_CLKCHANGE:
1555	/*
1556	* Disable controller for clock change. If the
1557	* controller is already disabled, then do nothing.
1558	*/
1559	if (old_state != C_DISABLE && old_state != C_DISABLE_PM) {
1560	fbi->state = state;
1561	/* TODO __pxafb_lcd_power(fbi, 0); */
1562	pxafb_disable_controller(fbi);
1563	}
1564	break;
1565
1566	case C_DISABLE_PM:
1567	case C_DISABLE:
1568	/*
1569	* Disable controller
1570	*/
1571	if (old_state != C_DISABLE) {
1572	fbi->state = state;
1573	__pxafb_backlight_power(fbi, on: 0);
1574	__pxafb_lcd_power(fbi, on: 0);
1575	if (old_state != C_DISABLE_CLKCHANGE)
1576	pxafb_disable_controller(fbi);
1577	}
1578	break;
1579
1580	case C_ENABLE_CLKCHANGE:
1581	/*
1582	* Enable the controller after clock change. Only
1583	* do this if we were disabled for the clock change.
1584	*/
1585	if (old_state == C_DISABLE_CLKCHANGE) {
1586	fbi->state = C_ENABLE;
1587	pxafb_enable_controller(fbi);
1588	/* TODO __pxafb_lcd_power(fbi, 1); */
1589	}
1590	break;
1591
1592	case C_REENABLE:
1593	/*
1594	* Re-enable the controller only if it was already
1595	* enabled. This is so we reprogram the control
1596	* registers.
1597	*/
1598	if (old_state == C_ENABLE) {
1599	__pxafb_lcd_power(fbi, on: 0);
1600	pxafb_disable_controller(fbi);
1601	pxafb_enable_controller(fbi);
1602	__pxafb_lcd_power(fbi, on: 1);
1603	}
1604	break;
1605
1606	case C_ENABLE_PM:
1607	/*
1608	* Re-enable the controller after PM. This is not
1609	* perfect - think about the case where we were doing
1610	* a clock change, and we suspended half-way through.
1611	*/
1612	if (old_state != C_DISABLE_PM)
1613	break;
1614	fallthrough;
1615
1616	case C_ENABLE:
1617	/*
1618	* Power up the LCD screen, enable controller, and
1619	* turn on the backlight.
1620	*/
1621	if (old_state != C_ENABLE) {
1622	fbi->state = C_ENABLE;
1623	pxafb_enable_controller(fbi);
1624	__pxafb_lcd_power(fbi, on: 1);
1625	__pxafb_backlight_power(fbi, on: 1);
1626	}
1627	break;
1628	}
1629	mutex_unlock(lock: &fbi->ctrlr_lock);
1630	}
1631
1632	/*
1633	* Our LCD controller task (which is called when we blank or unblank)
1634	* via keventd.
1635	*/
1636	static void pxafb_task(struct work_struct *work)
1637	{
1638	struct pxafb_info *fbi =
1639	container_of(work, struct pxafb_info, task);
1640	u_int state = xchg(&fbi->task_state, -1);
1641
1642	set_ctrlr_state(fbi, state);
1643	}
1644
1645	#ifdef CONFIG_CPU_FREQ
1646	/*
1647	* CPU clock speed change handler. We need to adjust the LCD timing
1648	* parameters when the CPU clock is adjusted by the power management
1649	* subsystem.
1650	*
1651	* TODO: Determine why f->new != 10*get_lclk_frequency_10khz()
1652	*/
1653	static int
1654	pxafb_freq_transition(struct notifier_block *nb, unsigned long val, void *data)
1655	{
1656	struct pxafb_info *fbi = TO_INF(nb, freq_transition);
1657	/* TODO struct cpufreq_freqs *f = data; */
1658	u_int pcd;
1659
1660	switch (val) {
1661	case CPUFREQ_PRECHANGE:
1662	#ifdef CONFIG_FB_PXA_OVERLAY
1663	if (!(fbi->overlay[0].usage || fbi->overlay[1].usage))
1664	#endif
1665	set_ctrlr_state(fbi, C_DISABLE_CLKCHANGE);
1666	break;
1667
1668	case CPUFREQ_POSTCHANGE:
1669	pcd = get_pcd(fbi, pixclock: fbi->fb.var.pixclock);
1670	set_hsync_time(fbi, pcd);
1671	fbi->reg_lccr3 = (fbi->reg_lccr3 & ~0xff) |
1672	LCCR3_PixClkDiv(pcd);
1673	set_ctrlr_state(fbi, C_ENABLE_CLKCHANGE);
1674	break;
1675	}
1676	return 0;
1677	}
1678	#endif
1679
1680	#ifdef CONFIG_PM
1681	/*
1682	* Power management hooks. Note that we won't be called from IRQ context,
1683	* unlike the blank functions above, so we may sleep.
1684	*/
1685	static int pxafb_suspend(struct device *dev)
1686	{
1687	struct pxafb_info *fbi = dev_get_drvdata(dev);
1688
1689	set_ctrlr_state(fbi, C_DISABLE_PM);
1690	return 0;
1691	}
1692
1693	static int pxafb_resume(struct device *dev)
1694	{
1695	struct pxafb_info *fbi = dev_get_drvdata(dev);
1696
1697	set_ctrlr_state(fbi, C_ENABLE_PM);
1698	return 0;
1699	}
1700
1701	static const struct dev_pm_ops pxafb_pm_ops = {
1702	.suspend = pxafb_suspend,
1703	.resume = pxafb_resume,
1704	};
1705	#endif
1706
1707	static int pxafb_init_video_memory(struct pxafb_info *fbi)
1708	{
1709	int size = PAGE_ALIGN(fbi->video_mem_size);
1710
1711	fbi->video_mem = alloc_pages_exact(size, GFP_KERNEL | __GFP_ZERO);
1712	if (fbi->video_mem == NULL)
1713	return -ENOMEM;
1714
1715	fbi->video_mem_phys = virt_to_phys(address: fbi->video_mem);
1716	fbi->video_mem_size = size;
1717
1718	fbi->fb.fix.smem_start = fbi->video_mem_phys;
1719	fbi->fb.fix.smem_len = fbi->video_mem_size;
1720	fbi->fb.screen_base = fbi->video_mem;
1721
1722	return fbi->video_mem ? 0 : -ENOMEM;
1723	}
1724
1725	static void pxafb_decode_mach_info(struct pxafb_info *fbi,
1726	struct pxafb_mach_info *inf)
1727	{
1728	unsigned int lcd_conn = inf->lcd_conn;
1729	struct pxafb_mode_info *m;
1730	int i;
1731
1732	fbi->cmap_inverse = inf->cmap_inverse;
1733	fbi->cmap_static = inf->cmap_static;
1734	fbi->lccr4 = inf->lccr4;
1735
1736	switch (lcd_conn & LCD_TYPE_MASK) {
1737	case LCD_TYPE_MONO_STN:
1738	fbi->lccr0 = LCCR0_CMS;
1739	break;
1740	case LCD_TYPE_MONO_DSTN:
1741	fbi->lccr0 = LCCR0_CMS | LCCR0_SDS;
1742	break;
1743	case LCD_TYPE_COLOR_STN:
1744	fbi->lccr0 = 0;
1745	break;
1746	case LCD_TYPE_COLOR_DSTN:
1747	fbi->lccr0 = LCCR0_SDS;
1748	break;
1749	case LCD_TYPE_COLOR_TFT:
1750	fbi->lccr0 = LCCR0_PAS;
1751	break;
1752	case LCD_TYPE_SMART_PANEL:
1753	fbi->lccr0 = LCCR0_LCDT | LCCR0_PAS;
1754	break;
1755	default:
1756	/* fall back to backward compatibility way */
1757	fbi->lccr0 = inf->lccr0;
1758	fbi->lccr3 = inf->lccr3;
1759	goto decode_mode;
1760	}
1761
1762	if (lcd_conn == LCD_MONO_STN_8BPP)
1763	fbi->lccr0 |= LCCR0_DPD;
1764
1765	fbi->lccr0 |= (lcd_conn & LCD_ALTERNATE_MAPPING) ? LCCR0_LDDALT : 0;
1766
1767	fbi->lccr3 = LCCR3_Acb((inf->lcd_conn >> 10) & 0xff);
1768	fbi->lccr3 |= (lcd_conn & LCD_BIAS_ACTIVE_LOW) ? LCCR3_OEP : 0;
1769	fbi->lccr3 |= (lcd_conn & LCD_PCLK_EDGE_FALL) ? LCCR3_PCP : 0;
1770
1771	decode_mode:
1772	pxafb_setmode(var: &fbi->fb.var, mode: &inf->modes[0]);
1773
1774	/* decide video memory size as follows:
1775	* 1. default to mode of maximum resolution
1776	* 2. allow platform to override
1777	* 3. allow module parameter to override
1778	*/
1779	for (i = 0, m = &inf->modes[0]; i < inf->num_modes; i++, m++)
1780	fbi->video_mem_size = max_t(size_t, fbi->video_mem_size,
1781	m->xres * m->yres * m->bpp / 8);
1782
1783	if (inf->video_mem_size > fbi->video_mem_size)
1784	fbi->video_mem_size = inf->video_mem_size;
1785
1786	if (video_mem_size > fbi->video_mem_size)
1787	fbi->video_mem_size = video_mem_size;
1788	}
1789
1790	static struct pxafb_info *pxafb_init_fbinfo(struct device *dev,
1791	struct pxafb_mach_info *inf)
1792	{
1793	struct pxafb_info *fbi;
1794	void *addr;
1795
1796	/* Alloc the pxafb_info and pseudo_palette in one step */
1797	fbi = devm_kzalloc(dev, size: sizeof(struct pxafb_info) + sizeof(u32) * 16,
1798	GFP_KERNEL);
1799	if (!fbi)
1800	return ERR_PTR(error: -ENOMEM);
1801
1802	fbi->dev = dev;
1803	fbi->inf = inf;
1804
1805	fbi->clk = devm_clk_get(dev, NULL);
1806	if (IS_ERR(ptr: fbi->clk))
1807	return ERR_CAST(ptr: fbi->clk);
1808
1809	strcpy(p: fbi->fb.fix.id, PXA_NAME);
1810
1811	fbi->fb.fix.type = FB_TYPE_PACKED_PIXELS;
1812	fbi->fb.fix.type_aux = 0;
1813	fbi->fb.fix.xpanstep = 0;
1814	fbi->fb.fix.ypanstep = 1;
1815	fbi->fb.fix.ywrapstep = 0;
1816	fbi->fb.fix.accel = FB_ACCEL_NONE;
1817
1818	fbi->fb.var.nonstd = 0;
1819	fbi->fb.var.activate = FB_ACTIVATE_NOW;
1820	fbi->fb.var.height = -1;
1821	fbi->fb.var.width = -1;
1822	fbi->fb.var.accel_flags = FB_ACCELF_TEXT;
1823	fbi->fb.var.vmode = FB_VMODE_NONINTERLACED;
1824
1825	fbi->fb.fbops = &pxafb_ops;
1826	fbi->fb.node = -1;
1827
1828	addr = fbi;
1829	addr = addr + sizeof(struct pxafb_info);
1830	fbi->fb.pseudo_palette = addr;
1831
1832	fbi->state = C_STARTUP;
1833	fbi->task_state = (u_char)-1;
1834
1835	pxafb_decode_mach_info(fbi, inf);
1836
1837	#ifdef CONFIG_FB_PXA_OVERLAY
1838	/* place overlay(s) on top of base */
1839	if (pxafb_overlay_supported())
1840	fbi->lccr0 |= LCCR0_OUC;
1841	#endif
1842
1843	init_waitqueue_head(&fbi->ctrlr_wait);
1844	INIT_WORK(&fbi->task, pxafb_task);
1845	mutex_init(&fbi->ctrlr_lock);
1846	init_completion(x: &fbi->disable_done);
1847
1848	return fbi;
1849	}
1850
1851	#ifdef CONFIG_FB_PXA_PARAMETERS
1852	static int parse_opt_mode(struct device *dev, const char *this_opt,
1853	struct pxafb_mach_info *inf)
1854	{
1855	const char *name = this_opt+5;
1856	unsigned int namelen = strlen(name);
1857	int res_specified = 0, bpp_specified = 0;
1858	unsigned int xres = 0, yres = 0, bpp = 0;
1859	int yres_specified = 0;
1860	int i;
1861	for (i = namelen-1; i >= 0; i--) {
1862	switch (name[i]) {
1863	case '-':
1864	namelen = i;
1865	if (!bpp_specified && !yres_specified) {
1866	bpp = simple_strtoul(&name[i+1], NULL, 0);
1867	bpp_specified = 1;
1868	} else
1869	goto done;
1870	break;
1871	case 'x':
1872	if (!yres_specified) {
1873	yres = simple_strtoul(&name[i+1], NULL, 0);
1874	yres_specified = 1;
1875	} else
1876	goto done;
1877	break;
1878	case '0' ... '9':
1879	break;
1880	default:
1881	goto done;
1882	}
1883	}
1884	if (i < 0 && yres_specified) {
1885	xres = simple_strtoul(name, NULL, 0);
1886	res_specified = 1;
1887	}
1888	done:
1889	if (res_specified) {
1890	dev_info(dev, "overriding resolution: %dx%d\n", xres, yres);
1891	inf->modes[0].xres = xres; inf->modes[0].yres = yres;
1892	}
1893	if (bpp_specified)
1894	switch (bpp) {
1895	case 1:
1896	case 2:
1897	case 4:
1898	case 8:
1899	case 16:
1900	inf->modes[0].bpp = bpp;
1901	dev_info(dev, "overriding bit depth: %d\n", bpp);
1902	break;
1903	default:
1904	dev_err(dev, "Depth %d is not valid\n", bpp);
1905	return -EINVAL;
1906	}
1907	return 0;
1908	}
1909
1910	static int parse_opt(struct device *dev, char *this_opt,
1911	struct pxafb_mach_info *inf)
1912	{
1913	struct pxafb_mode_info *mode = &inf->modes[0];
1914	char s[64];
1915
1916	s[0] = '\0';
1917
1918	if (!strncmp(this_opt, "vmem:", 5)) {
1919	video_mem_size = memparse(this_opt + 5, NULL);
1920	} else if (!strncmp(this_opt, "mode:", 5)) {
1921	return parse_opt_mode(dev, this_opt, inf);
1922	} else if (!strncmp(this_opt, "pixclock:", 9)) {
1923	mode->pixclock = simple_strtoul(this_opt+9, NULL, 0);
1924	sprintf(s, "pixclock: %ld\n", mode->pixclock);
1925	} else if (!strncmp(this_opt, "left:", 5)) {
1926	mode->left_margin = simple_strtoul(this_opt+5, NULL, 0);
1927	sprintf(s, "left: %u\n", mode->left_margin);
1928	} else if (!strncmp(this_opt, "right:", 6)) {
1929	mode->right_margin = simple_strtoul(this_opt+6, NULL, 0);
1930	sprintf(s, "right: %u\n", mode->right_margin);
1931	} else if (!strncmp(this_opt, "upper:", 6)) {
1932	mode->upper_margin = simple_strtoul(this_opt+6, NULL, 0);
1933	sprintf(s, "upper: %u\n", mode->upper_margin);
1934	} else if (!strncmp(this_opt, "lower:", 6)) {
1935	mode->lower_margin = simple_strtoul(this_opt+6, NULL, 0);
1936	sprintf(s, "lower: %u\n", mode->lower_margin);
1937	} else if (!strncmp(this_opt, "hsynclen:", 9)) {
1938	mode->hsync_len = simple_strtoul(this_opt+9, NULL, 0);
1939	sprintf(s, "hsynclen: %u\n", mode->hsync_len);
1940	} else if (!strncmp(this_opt, "vsynclen:", 9)) {
1941	mode->vsync_len = simple_strtoul(this_opt+9, NULL, 0);
1942	sprintf(s, "vsynclen: %u\n", mode->vsync_len);
1943	} else if (!strncmp(this_opt, "hsync:", 6)) {
1944	if (simple_strtoul(this_opt+6, NULL, 0) == 0) {
1945	sprintf(s, "hsync: Active Low\n");
1946	mode->sync &= ~FB_SYNC_HOR_HIGH_ACT;
1947	} else {
1948	sprintf(s, "hsync: Active High\n");
1949	mode->sync |= FB_SYNC_HOR_HIGH_ACT;
1950	}
1951	} else if (!strncmp(this_opt, "vsync:", 6)) {
1952	if (simple_strtoul(this_opt+6, NULL, 0) == 0) {
1953	sprintf(s, "vsync: Active Low\n");
1954	mode->sync &= ~FB_SYNC_VERT_HIGH_ACT;
1955	} else {
1956	sprintf(s, "vsync: Active High\n");
1957	mode->sync |= FB_SYNC_VERT_HIGH_ACT;
1958	}
1959	} else if (!strncmp(this_opt, "dpc:", 4)) {
1960	if (simple_strtoul(this_opt+4, NULL, 0) == 0) {
1961	sprintf(s, "double pixel clock: false\n");
1962	inf->lccr3 &= ~LCCR3_DPC;
1963	} else {
1964	sprintf(s, "double pixel clock: true\n");
1965	inf->lccr3 |= LCCR3_DPC;
1966	}
1967	} else if (!strncmp(this_opt, "outputen:", 9)) {
1968	if (simple_strtoul(this_opt+9, NULL, 0) == 0) {
1969	sprintf(s, "output enable: active low\n");
1970	inf->lccr3 = (inf->lccr3 & ~LCCR3_OEP) | LCCR3_OutEnL;
1971	} else {
1972	sprintf(s, "output enable: active high\n");
1973	inf->lccr3 = (inf->lccr3 & ~LCCR3_OEP) | LCCR3_OutEnH;
1974	}
1975	} else if (!strncmp(this_opt, "pixclockpol:", 12)) {
1976	if (simple_strtoul(this_opt+12, NULL, 0) == 0) {
1977	sprintf(s, "pixel clock polarity: falling edge\n");
1978	inf->lccr3 = (inf->lccr3 & ~LCCR3_PCP) | LCCR3_PixFlEdg;
1979	} else {
1980	sprintf(s, "pixel clock polarity: rising edge\n");
1981	inf->lccr3 = (inf->lccr3 & ~LCCR3_PCP) | LCCR3_PixRsEdg;
1982	}
1983	} else if (!strncmp(this_opt, "color", 5)) {
1984	inf->lccr0 = (inf->lccr0 & ~LCCR0_CMS) | LCCR0_Color;
1985	} else if (!strncmp(this_opt, "mono", 4)) {
1986	inf->lccr0 = (inf->lccr0 & ~LCCR0_CMS) | LCCR0_Mono;
1987	} else if (!strncmp(this_opt, "active", 6)) {
1988	inf->lccr0 = (inf->lccr0 & ~LCCR0_PAS) | LCCR0_Act;
1989	} else if (!strncmp(this_opt, "passive", 7)) {
1990	inf->lccr0 = (inf->lccr0 & ~LCCR0_PAS) | LCCR0_Pas;
1991	} else if (!strncmp(this_opt, "single", 6)) {
1992	inf->lccr0 = (inf->lccr0 & ~LCCR0_SDS) | LCCR0_Sngl;
1993	} else if (!strncmp(this_opt, "dual", 4)) {
1994	inf->lccr0 = (inf->lccr0 & ~LCCR0_SDS) | LCCR0_Dual;
1995	} else if (!strncmp(this_opt, "4pix", 4)) {
1996	inf->lccr0 = (inf->lccr0 & ~LCCR0_DPD) | LCCR0_4PixMono;
1997	} else if (!strncmp(this_opt, "8pix", 4)) {
1998	inf->lccr0 = (inf->lccr0 & ~LCCR0_DPD) | LCCR0_8PixMono;
1999	} else {
2000	dev_err(dev, "unknown option: %s\n", this_opt);
2001	return -EINVAL;
2002	}
2003
2004	if (s[0] != '\0')
2005	dev_info(dev, "override %s", s);
2006
2007	return 0;
2008	}
2009
2010	static int pxafb_parse_options(struct device *dev, char *options,
2011	struct pxafb_mach_info *inf)
2012	{
2013	char *this_opt;
2014	int ret;
2015
2016	if (!options || !*options)
2017	return 0;
2018
2019	dev_dbg(dev, "options are \"%s\"\n", options ? options : "null");
2020
2021	/* could be made table driven or similar?... */
2022	while ((this_opt = strsep(&options, ",")) != NULL) {
2023	ret = parse_opt(dev, this_opt, inf);
2024	if (ret)
2025	return ret;
2026	}
2027	return 0;
2028	}
2029
2030	static char g_options[256] = "";
2031
2032	#ifndef MODULE
2033	static int __init pxafb_setup_options(void)
2034	{
2035	char *options = NULL;
2036
2037	if (fb_get_options("pxafb", &options))
2038	return -ENODEV;
2039
2040	if (options)
2041	strscpy(g_options, options, sizeof(g_options));
2042
2043	return 0;
2044	}
2045	#else
2046	#define pxafb_setup_options() (0)
2047
2048	module_param_string(options, g_options, sizeof(g_options), 0);
2049	MODULE_PARM_DESC(options, "LCD parameters (see Documentation/fb/pxafb.rst)");
2050	#endif
2051
2052	#else
2053	#define pxafb_parse_options(...) (0)
2054	#define pxafb_setup_options() (0)
2055	#endif
2056
2057	#ifdef DEBUG_VAR
2058	/* Check for various illegal bit-combinations. Currently only
2059	* a warning is given. */
2060	static void pxafb_check_options(struct device *dev, struct pxafb_mach_info *inf)
2061	{
2062	if (inf->lcd_conn)
2063	return;
2064
2065	if (inf->lccr0 & LCCR0_INVALID_CONFIG_MASK)
2066	dev_warn(dev, "machine LCCR0 setting contains "
2067	"illegal bits: %08x\n",
2068	inf->lccr0 & LCCR0_INVALID_CONFIG_MASK);
2069	if (inf->lccr3 & LCCR3_INVALID_CONFIG_MASK)
2070	dev_warn(dev, "machine LCCR3 setting contains "
2071	"illegal bits: %08x\n",
2072	inf->lccr3 & LCCR3_INVALID_CONFIG_MASK);
2073	if (inf->lccr0 & LCCR0_DPD &&
2074	((inf->lccr0 & LCCR0_PAS) != LCCR0_Pas ||
2075	(inf->lccr0 & LCCR0_SDS) != LCCR0_Sngl ||
2076	(inf->lccr0 & LCCR0_CMS) != LCCR0_Mono))
2077	dev_warn(dev, "Double Pixel Data (DPD) mode is "
2078	"only valid in passive mono"
2079	" single panel mode\n");
2080	if ((inf->lccr0 & LCCR0_PAS) == LCCR0_Act &&
2081	(inf->lccr0 & LCCR0_SDS) == LCCR0_Dual)
2082	dev_warn(dev, "Dual panel only valid in passive mode\n");
2083	if ((inf->lccr0 & LCCR0_PAS) == LCCR0_Pas &&
2084	(inf->modes->upper_margin || inf->modes->lower_margin))
2085	dev_warn(dev, "Upper and lower margins must be 0 in "
2086	"passive mode\n");
2087	}
2088	#else
2089	#define pxafb_check_options(...) do {} while (0)
2090	#endif
2091
2092	#if defined(CONFIG_OF)
2093	static const char * const lcd_types[] = {
2094	"unknown", "mono-stn", "mono-dstn", "color-stn", "color-dstn",
2095	"color-tft", "smart-panel", NULL
2096	};
2097
2098	static int of_get_pxafb_display(struct device *dev, struct device_node *disp,
2099	struct pxafb_mach_info *info, u32 bus_width)
2100	{
2101	struct display_timings *timings;
2102	struct videomode vm;
2103	int i, ret = -EINVAL;
2104	const char *s;
2105
2106	ret = of_property_read_string(np: disp, propname: "lcd-type", out_string: &s);
2107	if (ret)
2108	s = "color-tft";
2109
2110	i = match_string(array: lcd_types, n: -1, string: s);
2111	if (i < 0) {
2112	dev_err(dev, "lcd-type %s is unknown\n", s);
2113	return i;
2114	}
2115	info->lcd_conn |= LCD_CONN_TYPE(i);
2116	info->lcd_conn |= LCD_CONN_WIDTH(bus_width);
2117
2118	timings = of_get_display_timings(np: disp);
2119	if (!timings)
2120	return -EINVAL;
2121
2122	ret = -ENOMEM;
2123	info->modes = devm_kcalloc(dev, n: timings->num_timings,
2124	size: sizeof(info->modes[0]),
2125	GFP_KERNEL);
2126	if (!info->modes)
2127	goto out;
2128	info->num_modes = timings->num_timings;
2129
2130	for (i = 0; i < timings->num_timings; i++) {
2131	ret = videomode_from_timings(disp: timings, vm: &vm, index: i);
2132	if (ret) {
2133	dev_err(dev, "videomode_from_timings %d failed: %d\n",
2134	i, ret);
2135	goto out;
2136	}
2137	if (vm.flags & DISPLAY_FLAGS_PIXDATA_POSEDGE)
2138	info->lcd_conn |= LCD_PCLK_EDGE_RISE;
2139	if (vm.flags & DISPLAY_FLAGS_PIXDATA_NEGEDGE)
2140	info->lcd_conn |= LCD_PCLK_EDGE_FALL;
2141	if (vm.flags & DISPLAY_FLAGS_DE_HIGH)
2142	info->lcd_conn |= LCD_BIAS_ACTIVE_HIGH;
2143	if (vm.flags & DISPLAY_FLAGS_DE_LOW)
2144	info->lcd_conn |= LCD_BIAS_ACTIVE_LOW;
2145	if (vm.flags & DISPLAY_FLAGS_HSYNC_HIGH)
2146	info->modes[i].sync |= FB_SYNC_HOR_HIGH_ACT;
2147	if (vm.flags & DISPLAY_FLAGS_VSYNC_HIGH)
2148	info->modes[i].sync |= FB_SYNC_VERT_HIGH_ACT;
2149
2150	info->modes[i].pixclock = 1000000000UL / (vm.pixelclock / 1000);
2151	info->modes[i].xres = vm.hactive;
2152	info->modes[i].yres = vm.vactive;
2153	info->modes[i].hsync_len = vm.hsync_len;
2154	info->modes[i].left_margin = vm.hback_porch;
2155	info->modes[i].right_margin = vm.hfront_porch;
2156	info->modes[i].vsync_len = vm.vsync_len;
2157	info->modes[i].upper_margin = vm.vback_porch;
2158	info->modes[i].lower_margin = vm.vfront_porch;
2159	}
2160	ret = 0;
2161
2162	out:
2163	display_timings_release(disp: timings);
2164	return ret;
2165	}
2166
2167	static int of_get_pxafb_mode_info(struct device *dev,
2168	struct pxafb_mach_info *info)
2169	{
2170	struct device_node *display, *np;
2171	u32 bus_width;
2172	int ret, i;
2173
2174	np = of_graph_get_next_endpoint(parent: dev->of_node, NULL);
2175	if (!np) {
2176	dev_err(dev, "could not find endpoint\n");
2177	return -EINVAL;
2178	}
2179	ret = of_property_read_u32(np, propname: "bus-width", out_value: &bus_width);
2180	if (ret) {
2181	dev_err(dev, "no bus-width specified: %d\n", ret);
2182	of_node_put(node: np);
2183	return ret;
2184	}
2185
2186	display = of_graph_get_remote_port_parent(node: np);
2187	of_node_put(node: np);
2188	if (!display) {
2189	dev_err(dev, "no display defined\n");
2190	return -EINVAL;
2191	}
2192
2193	ret = of_get_pxafb_display(dev, disp: display, info, bus_width);
2194	of_node_put(node: display);
2195	if (ret)
2196	return ret;
2197
2198	for (i = 0; i < info->num_modes; i++)
2199	info->modes[i].bpp = bus_width;
2200
2201	return 0;
2202	}
2203
2204	static struct pxafb_mach_info *of_pxafb_of_mach_info(struct device *dev)
2205	{
2206	int ret;
2207	struct pxafb_mach_info *info;
2208
2209	if (!dev->of_node)
2210	return NULL;
2211	info = devm_kzalloc(dev, size: sizeof(*info), GFP_KERNEL);
2212	if (!info)
2213	return ERR_PTR(error: -ENOMEM);
2214	ret = of_get_pxafb_mode_info(dev, info);
2215	if (ret)
2216	return ERR_PTR(error: ret);
2217
2218	/*
2219	* On purpose, neither lccrX registers nor video memory size can be
2220	* specified through device-tree, they are considered more a debug hack
2221	* available through command line.
2222	*/
2223	return info;
2224	}
2225	#else
2226	static struct pxafb_mach_info *of_pxafb_of_mach_info(struct device *dev)
2227	{
2228	return NULL;
2229	}
2230	#endif
2231
2232	static int pxafb_probe(struct platform_device *dev)
2233	{
2234	struct pxafb_info *fbi;
2235	struct pxafb_mach_info *inf, *pdata;
2236	int i, irq, ret;
2237
2238	dev_dbg(&dev->dev, "pxafb_probe\n");
2239
2240	ret = -ENOMEM;
2241	pdata = dev_get_platdata(dev: &dev->dev);
2242	inf = devm_kmalloc(dev: &dev->dev, size: sizeof(*inf), GFP_KERNEL);
2243	if (!inf)
2244	goto failed;
2245
2246	if (pdata) {
2247	*inf = *pdata;
2248	inf->modes =
2249	devm_kmalloc_array(dev: &dev->dev, n: pdata->num_modes,
2250	size: sizeof(inf->modes[0]), GFP_KERNEL);
2251	if (!inf->modes)
2252	goto failed;
2253	for (i = 0; i < inf->num_modes; i++)
2254	inf->modes[i] = pdata->modes[i];
2255	} else {
2256	inf = of_pxafb_of_mach_info(dev: &dev->dev);
2257	}
2258
2259	if (IS_ERR_OR_NULL(ptr: inf))
2260	goto failed;
2261
2262	ret = pxafb_parse_options(&dev->dev, g_options, inf);
2263	if (ret < 0)
2264	goto failed;
2265
2266	pxafb_check_options(dev: &dev->dev, inf);
2267
2268	dev_dbg(&dev->dev, "got a %dx%dx%d LCD\n",
2269	inf->modes->xres,
2270	inf->modes->yres,
2271	inf->modes->bpp);
2272	if (inf->modes->xres == 0 ||
2273	inf->modes->yres == 0 ||
2274	inf->modes->bpp == 0) {
2275	dev_err(&dev->dev, "Invalid resolution or bit depth\n");
2276	ret = -EINVAL;
2277	goto failed;
2278	}
2279
2280	fbi = pxafb_init_fbinfo(dev: &dev->dev, inf);
2281	if (IS_ERR(ptr: fbi)) {
2282	dev_err(&dev->dev, "Failed to initialize framebuffer device\n");
2283	ret = PTR_ERR(ptr: fbi);
2284	goto failed;
2285	}
2286
2287	if (cpu_is_pxa3xx() && inf->acceleration_enabled)
2288	fbi->fb.fix.accel = FB_ACCEL_PXA3XX;
2289
2290	fbi->backlight_power = inf->pxafb_backlight_power;
2291	fbi->lcd_power = inf->pxafb_lcd_power;
2292
2293	fbi->lcd_supply = devm_regulator_get_optional(dev: &dev->dev, id: "lcd");
2294	if (IS_ERR(ptr: fbi->lcd_supply)) {
2295	if (PTR_ERR(ptr: fbi->lcd_supply) == -EPROBE_DEFER)
2296	return -EPROBE_DEFER;
2297
2298	fbi->lcd_supply = NULL;
2299	}
2300
2301	fbi->mmio_base = devm_platform_ioremap_resource(pdev: dev, index: 0);
2302	if (IS_ERR(ptr: fbi->mmio_base)) {
2303	dev_err(&dev->dev, "failed to get I/O memory\n");
2304	ret = PTR_ERR(ptr: fbi->mmio_base);
2305	goto failed;
2306	}
2307
2308	fbi->dma_buff_size = PAGE_ALIGN(sizeof(struct pxafb_dma_buff));
2309	fbi->dma_buff = dma_alloc_coherent(dev: fbi->dev, size: fbi->dma_buff_size,
2310	dma_handle: &fbi->dma_buff_phys, GFP_KERNEL);
2311	if (fbi->dma_buff == NULL) {
2312	dev_err(&dev->dev, "failed to allocate memory for DMA\n");
2313	ret = -ENOMEM;
2314	goto failed;
2315	}
2316
2317	ret = pxafb_init_video_memory(fbi);
2318	if (ret) {
2319	dev_err(&dev->dev, "Failed to allocate video RAM: %d\n", ret);
2320	ret = -ENOMEM;
2321	goto failed_free_dma;
2322	}
2323
2324	irq = platform_get_irq(dev, 0);
2325	if (irq < 0) {
2326	ret = -ENODEV;
2327	goto failed_free_mem;
2328	}
2329
2330	ret = devm_request_irq(dev: &dev->dev, irq, handler: pxafb_handle_irq, irqflags: 0, devname: "LCD", dev_id: fbi);
2331	if (ret) {
2332	dev_err(&dev->dev, "request_irq failed: %d\n", ret);
2333	ret = -EBUSY;
2334	goto failed_free_mem;
2335	}
2336
2337	ret = pxafb_smart_init(fbi);
2338	if (ret) {
2339	dev_err(&dev->dev, "failed to initialize smartpanel\n");
2340	goto failed_free_mem;
2341	}
2342
2343	/*
2344	* This makes sure that our colour bitfield
2345	* descriptors are correctly initialised.
2346	*/
2347	ret = pxafb_check_var(var: &fbi->fb.var, info: &fbi->fb);
2348	if (ret) {
2349	dev_err(&dev->dev, "failed to get suitable mode\n");
2350	goto failed_free_mem;
2351	}
2352
2353	ret = pxafb_set_par(info: &fbi->fb);
2354	if (ret) {
2355	dev_err(&dev->dev, "Failed to set parameters\n");
2356	goto failed_free_mem;
2357	}
2358
2359	platform_set_drvdata(pdev: dev, data: fbi);
2360
2361	ret = register_framebuffer(fb_info: &fbi->fb);
2362	if (ret < 0) {
2363	dev_err(&dev->dev,
2364	"Failed to register framebuffer device: %d\n", ret);
2365	goto failed_free_cmap;
2366	}
2367
2368	pxafb_overlay_init(fbi);
2369
2370	#ifdef CONFIG_CPU_FREQ
2371	fbi->freq_transition.notifier_call = pxafb_freq_transition;
2372	cpufreq_register_notifier(nb: &fbi->freq_transition,
2373	CPUFREQ_TRANSITION_NOTIFIER);
2374	#endif
2375
2376	/*
2377	* Ok, now enable the LCD controller
2378	*/
2379	set_ctrlr_state(fbi, C_ENABLE);
2380
2381	return 0;
2382
2383	failed_free_cmap:
2384	if (fbi->fb.cmap.len)
2385	fb_dealloc_cmap(cmap: &fbi->fb.cmap);
2386	failed_free_mem:
2387	free_pages_exact(virt: fbi->video_mem, size: fbi->video_mem_size);
2388	failed_free_dma:
2389	dma_free_coherent(dev: &dev->dev, size: fbi->dma_buff_size,
2390	cpu_addr: fbi->dma_buff, dma_handle: fbi->dma_buff_phys);
2391	failed:
2392	return ret;
2393	}
2394
2395	static void pxafb_remove(struct platform_device *dev)
2396	{
2397	struct pxafb_info *fbi = platform_get_drvdata(pdev: dev);
2398	struct fb_info *info;
2399
2400	if (!fbi)
2401	return;
2402
2403	info = &fbi->fb;
2404
2405	pxafb_overlay_exit(fbi);
2406	unregister_framebuffer(fb_info: info);
2407
2408	pxafb_disable_controller(fbi);
2409
2410	if (fbi->fb.cmap.len)
2411	fb_dealloc_cmap(cmap: &fbi->fb.cmap);
2412
2413	free_pages_exact(virt: fbi->video_mem, size: fbi->video_mem_size);
2414
2415	dma_free_coherent(dev: &dev->dev, size: fbi->dma_buff_size, cpu_addr: fbi->dma_buff,
2416	dma_handle: fbi->dma_buff_phys);
2417	}
2418
2419	static const struct of_device_id pxafb_of_dev_id[] = {
2420	{ .compatible = "marvell,pxa270-lcdc", },
2421	{ .compatible = "marvell,pxa300-lcdc", },
2422	{ .compatible = "marvell,pxa2xx-lcdc", },
2423	{ /* sentinel */ }
2424	};
2425	MODULE_DEVICE_TABLE(of, pxafb_of_dev_id);
2426
2427	static struct platform_driver pxafb_driver = {
2428	.probe = pxafb_probe,
2429	.remove_new = pxafb_remove,
2430	.driver = {
2431	.name = "pxa2xx-fb",
2432	.of_match_table = pxafb_of_dev_id,
2433	#ifdef CONFIG_PM
2434	.pm = &pxafb_pm_ops,
2435	#endif
2436	},
2437	};
2438
2439	static int __init pxafb_init(void)
2440	{
2441	if (pxafb_setup_options())
2442	return -EINVAL;
2443
2444	return platform_driver_register(&pxafb_driver);
2445	}
2446
2447	static void __exit pxafb_exit(void)
2448	{
2449	platform_driver_unregister(&pxafb_driver);
2450	}
2451
2452	module_init(pxafb_init);
2453	module_exit(pxafb_exit);
2454
2455	MODULE_DESCRIPTION("loadable framebuffer driver for PXA");
2456	MODULE_LICENSE("GPL");
2457