1 | /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ |
2 | /* |
3 | * Copyright (c) 2021 Dávid Virág |
4 | * |
5 | * Device Tree binding constants for Exynos7885 clock controller. |
6 | */ |
7 | |
8 | #ifndef _DT_BINDINGS_CLOCK_EXYNOS_7885_H |
9 | #define _DT_BINDINGS_CLOCK_EXYNOS_7885_H |
10 | |
11 | /* CMU_TOP */ |
12 | #define CLK_FOUT_SHARED0_PLL 1 |
13 | #define CLK_FOUT_SHARED1_PLL 2 |
14 | #define CLK_DOUT_SHARED0_DIV2 3 |
15 | #define CLK_DOUT_SHARED0_DIV3 4 |
16 | #define CLK_DOUT_SHARED0_DIV4 5 |
17 | #define CLK_DOUT_SHARED0_DIV5 6 |
18 | #define CLK_DOUT_SHARED1_DIV2 7 |
19 | #define CLK_DOUT_SHARED1_DIV3 8 |
20 | #define CLK_DOUT_SHARED1_DIV4 9 |
21 | #define CLK_MOUT_CORE_BUS 10 |
22 | #define CLK_MOUT_CORE_CCI 11 |
23 | #define CLK_MOUT_CORE_G3D 12 |
24 | #define CLK_DOUT_CORE_BUS 13 |
25 | #define CLK_DOUT_CORE_CCI 14 |
26 | #define CLK_DOUT_CORE_G3D 15 |
27 | #define CLK_GOUT_CORE_BUS 16 |
28 | #define CLK_GOUT_CORE_CCI 17 |
29 | #define CLK_GOUT_CORE_G3D 18 |
30 | #define CLK_MOUT_PERI_BUS 19 |
31 | #define CLK_MOUT_PERI_SPI0 20 |
32 | #define CLK_MOUT_PERI_SPI1 21 |
33 | #define CLK_MOUT_PERI_UART0 22 |
34 | #define CLK_MOUT_PERI_UART1 23 |
35 | #define CLK_MOUT_PERI_UART2 24 |
36 | #define CLK_MOUT_PERI_USI0 25 |
37 | #define CLK_MOUT_PERI_USI1 26 |
38 | #define CLK_MOUT_PERI_USI2 27 |
39 | #define CLK_DOUT_PERI_BUS 28 |
40 | #define CLK_DOUT_PERI_SPI0 29 |
41 | #define CLK_DOUT_PERI_SPI1 30 |
42 | #define CLK_DOUT_PERI_UART0 31 |
43 | #define CLK_DOUT_PERI_UART1 32 |
44 | #define CLK_DOUT_PERI_UART2 33 |
45 | #define CLK_DOUT_PERI_USI0 34 |
46 | #define CLK_DOUT_PERI_USI1 35 |
47 | #define CLK_DOUT_PERI_USI2 36 |
48 | #define CLK_GOUT_PERI_BUS 37 |
49 | #define CLK_GOUT_PERI_SPI0 38 |
50 | #define CLK_GOUT_PERI_SPI1 39 |
51 | #define CLK_GOUT_PERI_UART0 40 |
52 | #define CLK_GOUT_PERI_UART1 41 |
53 | #define CLK_GOUT_PERI_UART2 42 |
54 | #define CLK_GOUT_PERI_USI0 43 |
55 | #define CLK_GOUT_PERI_USI1 44 |
56 | #define CLK_GOUT_PERI_USI2 45 |
57 | #define CLK_MOUT_FSYS_BUS 46 |
58 | #define CLK_MOUT_FSYS_MMC_CARD 47 |
59 | #define CLK_MOUT_FSYS_MMC_EMBD 48 |
60 | #define CLK_MOUT_FSYS_MMC_SDIO 49 |
61 | #define CLK_MOUT_FSYS_USB30DRD 50 |
62 | #define CLK_DOUT_FSYS_BUS 51 |
63 | #define CLK_DOUT_FSYS_MMC_CARD 52 |
64 | #define CLK_DOUT_FSYS_MMC_EMBD 53 |
65 | #define CLK_DOUT_FSYS_MMC_SDIO 54 |
66 | #define CLK_DOUT_FSYS_USB30DRD 55 |
67 | #define CLK_GOUT_FSYS_BUS 56 |
68 | #define CLK_GOUT_FSYS_MMC_CARD 57 |
69 | #define CLK_GOUT_FSYS_MMC_EMBD 58 |
70 | #define CLK_GOUT_FSYS_MMC_SDIO 59 |
71 | #define CLK_GOUT_FSYS_USB30DRD 60 |
72 | |
73 | /* CMU_CORE */ |
74 | #define CLK_MOUT_CORE_BUS_USER 1 |
75 | #define CLK_MOUT_CORE_CCI_USER 2 |
76 | #define CLK_MOUT_CORE_G3D_USER 3 |
77 | #define CLK_MOUT_CORE_GIC 4 |
78 | #define CLK_DOUT_CORE_BUSP 5 |
79 | #define CLK_GOUT_CCI_ACLK 6 |
80 | #define CLK_GOUT_GIC400_CLK 7 |
81 | #define CLK_GOUT_TREX_D_CORE_ACLK 8 |
82 | #define CLK_GOUT_TREX_D_CORE_GCLK 9 |
83 | #define CLK_GOUT_TREX_D_CORE_PCLK 10 |
84 | #define CLK_GOUT_TREX_P_CORE_ACLK_P_CORE 11 |
85 | #define CLK_GOUT_TREX_P_CORE_CCLK_P_CORE 12 |
86 | #define CLK_GOUT_TREX_P_CORE_PCLK 13 |
87 | #define CLK_GOUT_TREX_P_CORE_PCLK_P_CORE 14 |
88 | |
89 | /* CMU_PERI */ |
90 | #define CLK_MOUT_PERI_BUS_USER 1 |
91 | #define CLK_MOUT_PERI_SPI0_USER 2 |
92 | #define CLK_MOUT_PERI_SPI1_USER 3 |
93 | #define CLK_MOUT_PERI_UART0_USER 4 |
94 | #define CLK_MOUT_PERI_UART1_USER 5 |
95 | #define CLK_MOUT_PERI_UART2_USER 6 |
96 | #define CLK_MOUT_PERI_USI0_USER 7 |
97 | #define CLK_MOUT_PERI_USI1_USER 8 |
98 | #define CLK_MOUT_PERI_USI2_USER 9 |
99 | #define CLK_GOUT_GPIO_TOP_PCLK 10 |
100 | #define CLK_GOUT_HSI2C0_PCLK 11 |
101 | #define CLK_GOUT_HSI2C1_PCLK 12 |
102 | #define CLK_GOUT_HSI2C2_PCLK 13 |
103 | #define CLK_GOUT_HSI2C3_PCLK 14 |
104 | #define CLK_GOUT_I2C0_PCLK 15 |
105 | #define CLK_GOUT_I2C1_PCLK 16 |
106 | #define CLK_GOUT_I2C2_PCLK 17 |
107 | #define CLK_GOUT_I2C3_PCLK 18 |
108 | #define CLK_GOUT_I2C4_PCLK 19 |
109 | #define CLK_GOUT_I2C5_PCLK 20 |
110 | #define CLK_GOUT_I2C6_PCLK 21 |
111 | #define CLK_GOUT_I2C7_PCLK 22 |
112 | #define CLK_GOUT_PWM_MOTOR_PCLK 23 |
113 | #define CLK_GOUT_SPI0_PCLK 24 |
114 | #define CLK_GOUT_SPI0_EXT_CLK 25 |
115 | #define CLK_GOUT_SPI1_PCLK 26 |
116 | #define CLK_GOUT_SPI1_EXT_CLK 27 |
117 | #define CLK_GOUT_UART0_EXT_UCLK 28 |
118 | #define CLK_GOUT_UART0_PCLK 29 |
119 | #define CLK_GOUT_UART1_EXT_UCLK 30 |
120 | #define CLK_GOUT_UART1_PCLK 31 |
121 | #define CLK_GOUT_UART2_EXT_UCLK 32 |
122 | #define CLK_GOUT_UART2_PCLK 33 |
123 | #define CLK_GOUT_USI0_PCLK 34 |
124 | #define CLK_GOUT_USI0_SCLK 35 |
125 | #define CLK_GOUT_USI1_PCLK 36 |
126 | #define CLK_GOUT_USI1_SCLK 37 |
127 | #define CLK_GOUT_USI2_PCLK 38 |
128 | #define CLK_GOUT_USI2_SCLK 39 |
129 | #define CLK_GOUT_MCT_PCLK 40 |
130 | #define CLK_GOUT_SYSREG_PERI_PCLK 41 |
131 | #define CLK_GOUT_WDT0_PCLK 42 |
132 | #define CLK_GOUT_WDT1_PCLK 43 |
133 | |
134 | /* CMU_FSYS */ |
135 | #define CLK_MOUT_FSYS_BUS_USER 1 |
136 | #define CLK_MOUT_FSYS_MMC_CARD_USER 2 |
137 | #define CLK_MOUT_FSYS_MMC_EMBD_USER 3 |
138 | #define CLK_MOUT_FSYS_MMC_SDIO_USER 4 |
139 | #define CLK_MOUT_FSYS_USB30DRD_USER 4 |
140 | #define CLK_GOUT_MMC_CARD_ACLK 5 |
141 | #define CLK_GOUT_MMC_CARD_SDCLKIN 6 |
142 | #define CLK_GOUT_MMC_EMBD_ACLK 7 |
143 | #define CLK_GOUT_MMC_EMBD_SDCLKIN 8 |
144 | #define CLK_GOUT_MMC_SDIO_ACLK 9 |
145 | #define CLK_GOUT_MMC_SDIO_SDCLKIN 10 |
146 | |
147 | #endif /* _DT_BINDINGS_CLOCK_EXYNOS_7885_H */ |
148 | |