1 | // SPDX-License-Identifier: GPL-2.0-only |
2 | /* |
3 | * Copyright (C) 2021 Dávid Virág <virag.david003@gmail.com> |
4 | * Author: Dávid Virág <virag.david003@gmail.com> |
5 | * |
6 | * Common Clock Framework support for Exynos7885 SoC. |
7 | */ |
8 | |
9 | #include <linux/clk.h> |
10 | #include <linux/clk-provider.h> |
11 | #include <linux/of.h> |
12 | #include <linux/platform_device.h> |
13 | |
14 | #include <dt-bindings/clock/exynos7885.h> |
15 | |
16 | #include "clk.h" |
17 | #include "clk-exynos-arm64.h" |
18 | |
19 | /* NOTE: Must be equal to the last clock ID increased by one */ |
20 | #define CLKS_NR_TOP (CLK_GOUT_FSYS_USB30DRD + 1) |
21 | #define CLKS_NR_CORE (CLK_GOUT_TREX_P_CORE_PCLK_P_CORE + 1) |
22 | #define CLKS_NR_PERI (CLK_GOUT_WDT1_PCLK + 1) |
23 | #define CLKS_NR_FSYS (CLK_GOUT_MMC_SDIO_SDCLKIN + 1) |
24 | |
25 | /* ---- CMU_TOP ------------------------------------------------------------- */ |
26 | |
27 | /* Register Offset definitions for CMU_TOP (0x12060000) */ |
28 | #define PLL_LOCKTIME_PLL_SHARED0 0x0000 |
29 | #define PLL_LOCKTIME_PLL_SHARED1 0x0004 |
30 | #define PLL_CON0_PLL_SHARED0 0x0100 |
31 | #define PLL_CON0_PLL_SHARED1 0x0120 |
32 | #define CLK_CON_MUX_MUX_CLKCMU_CORE_BUS 0x1014 |
33 | #define CLK_CON_MUX_MUX_CLKCMU_CORE_CCI 0x1018 |
34 | #define CLK_CON_MUX_MUX_CLKCMU_CORE_G3D 0x101c |
35 | #define CLK_CON_MUX_MUX_CLKCMU_FSYS_BUS 0x1028 |
36 | #define CLK_CON_MUX_MUX_CLKCMU_FSYS_MMC_CARD 0x102c |
37 | #define CLK_CON_MUX_MUX_CLKCMU_FSYS_MMC_EMBD 0x1030 |
38 | #define CLK_CON_MUX_MUX_CLKCMU_FSYS_MMC_SDIO 0x1034 |
39 | #define CLK_CON_MUX_MUX_CLKCMU_FSYS_USB30DRD 0x1038 |
40 | #define CLK_CON_MUX_MUX_CLKCMU_PERI_BUS 0x1058 |
41 | #define CLK_CON_MUX_MUX_CLKCMU_PERI_SPI0 0x105c |
42 | #define CLK_CON_MUX_MUX_CLKCMU_PERI_SPI1 0x1060 |
43 | #define CLK_CON_MUX_MUX_CLKCMU_PERI_UART0 0x1064 |
44 | #define CLK_CON_MUX_MUX_CLKCMU_PERI_UART1 0x1068 |
45 | #define CLK_CON_MUX_MUX_CLKCMU_PERI_UART2 0x106c |
46 | #define CLK_CON_MUX_MUX_CLKCMU_PERI_USI0 0x1070 |
47 | #define CLK_CON_MUX_MUX_CLKCMU_PERI_USI1 0x1074 |
48 | #define CLK_CON_MUX_MUX_CLKCMU_PERI_USI2 0x1078 |
49 | #define CLK_CON_DIV_CLKCMU_CORE_BUS 0x181c |
50 | #define CLK_CON_DIV_CLKCMU_CORE_CCI 0x1820 |
51 | #define CLK_CON_DIV_CLKCMU_CORE_G3D 0x1824 |
52 | #define CLK_CON_DIV_CLKCMU_FSYS_BUS 0x1844 |
53 | #define CLK_CON_DIV_CLKCMU_FSYS_MMC_CARD 0x1848 |
54 | #define CLK_CON_DIV_CLKCMU_FSYS_MMC_EMBD 0x184c |
55 | #define CLK_CON_DIV_CLKCMU_FSYS_MMC_SDIO 0x1850 |
56 | #define CLK_CON_DIV_CLKCMU_FSYS_USB30DRD 0x1854 |
57 | #define CLK_CON_DIV_CLKCMU_PERI_BUS 0x1874 |
58 | #define CLK_CON_DIV_CLKCMU_PERI_SPI0 0x1878 |
59 | #define CLK_CON_DIV_CLKCMU_PERI_SPI1 0x187c |
60 | #define CLK_CON_DIV_CLKCMU_PERI_UART0 0x1880 |
61 | #define CLK_CON_DIV_CLKCMU_PERI_UART1 0x1884 |
62 | #define CLK_CON_DIV_CLKCMU_PERI_UART2 0x1888 |
63 | #define CLK_CON_DIV_CLKCMU_PERI_USI0 0x188c |
64 | #define CLK_CON_DIV_CLKCMU_PERI_USI1 0x1890 |
65 | #define CLK_CON_DIV_CLKCMU_PERI_USI2 0x1894 |
66 | #define CLK_CON_DIV_PLL_SHARED0_DIV2 0x189c |
67 | #define CLK_CON_DIV_PLL_SHARED0_DIV3 0x18a0 |
68 | #define CLK_CON_DIV_PLL_SHARED0_DIV4 0x18a4 |
69 | #define CLK_CON_DIV_PLL_SHARED0_DIV5 0x18a8 |
70 | #define CLK_CON_DIV_PLL_SHARED1_DIV2 0x18ac |
71 | #define CLK_CON_DIV_PLL_SHARED1_DIV3 0x18b0 |
72 | #define CLK_CON_DIV_PLL_SHARED1_DIV4 0x18b4 |
73 | #define CLK_CON_GAT_GATE_CLKCMUC_PERI_UART1 0x2004 |
74 | #define CLK_CON_GAT_GATE_CLKCMU_CORE_BUS 0x201c |
75 | #define CLK_CON_GAT_GATE_CLKCMU_CORE_CCI 0x2020 |
76 | #define CLK_CON_GAT_GATE_CLKCMU_CORE_G3D 0x2024 |
77 | #define CLK_CON_GAT_GATE_CLKCMU_FSYS_BUS 0x2044 |
78 | #define CLK_CON_GAT_GATE_CLKCMU_FSYS_MMC_CARD 0x2048 |
79 | #define CLK_CON_GAT_GATE_CLKCMU_FSYS_MMC_EMBD 0x204c |
80 | #define CLK_CON_GAT_GATE_CLKCMU_FSYS_MMC_SDIO 0x2050 |
81 | #define CLK_CON_GAT_GATE_CLKCMU_FSYS_USB30DRD 0x2054 |
82 | #define CLK_CON_GAT_GATE_CLKCMU_PERI_BUS 0x207c |
83 | #define CLK_CON_GAT_GATE_CLKCMU_PERI_SPI0 0x2080 |
84 | #define CLK_CON_GAT_GATE_CLKCMU_PERI_SPI1 0x2084 |
85 | #define CLK_CON_GAT_GATE_CLKCMU_PERI_UART0 0x2088 |
86 | #define CLK_CON_GAT_GATE_CLKCMU_PERI_UART2 0x208c |
87 | #define CLK_CON_GAT_GATE_CLKCMU_PERI_USI0 0x2090 |
88 | #define CLK_CON_GAT_GATE_CLKCMU_PERI_USI1 0x2094 |
89 | #define CLK_CON_GAT_GATE_CLKCMU_PERI_USI2 0x2098 |
90 | |
91 | static const unsigned long top_clk_regs[] __initconst = { |
92 | PLL_LOCKTIME_PLL_SHARED0, |
93 | PLL_LOCKTIME_PLL_SHARED1, |
94 | PLL_CON0_PLL_SHARED0, |
95 | PLL_CON0_PLL_SHARED1, |
96 | CLK_CON_MUX_MUX_CLKCMU_CORE_BUS, |
97 | CLK_CON_MUX_MUX_CLKCMU_CORE_CCI, |
98 | CLK_CON_MUX_MUX_CLKCMU_CORE_G3D, |
99 | CLK_CON_MUX_MUX_CLKCMU_FSYS_BUS, |
100 | CLK_CON_MUX_MUX_CLKCMU_FSYS_MMC_CARD, |
101 | CLK_CON_MUX_MUX_CLKCMU_FSYS_MMC_EMBD, |
102 | CLK_CON_MUX_MUX_CLKCMU_FSYS_MMC_SDIO, |
103 | CLK_CON_MUX_MUX_CLKCMU_FSYS_USB30DRD, |
104 | CLK_CON_MUX_MUX_CLKCMU_PERI_BUS, |
105 | CLK_CON_MUX_MUX_CLKCMU_PERI_SPI0, |
106 | CLK_CON_MUX_MUX_CLKCMU_PERI_SPI1, |
107 | CLK_CON_MUX_MUX_CLKCMU_PERI_UART0, |
108 | CLK_CON_MUX_MUX_CLKCMU_PERI_UART1, |
109 | CLK_CON_MUX_MUX_CLKCMU_PERI_UART2, |
110 | CLK_CON_MUX_MUX_CLKCMU_PERI_USI0, |
111 | CLK_CON_MUX_MUX_CLKCMU_PERI_USI1, |
112 | CLK_CON_MUX_MUX_CLKCMU_PERI_USI2, |
113 | CLK_CON_DIV_CLKCMU_CORE_BUS, |
114 | CLK_CON_DIV_CLKCMU_CORE_CCI, |
115 | CLK_CON_DIV_CLKCMU_CORE_G3D, |
116 | CLK_CON_DIV_CLKCMU_FSYS_BUS, |
117 | CLK_CON_DIV_CLKCMU_FSYS_MMC_CARD, |
118 | CLK_CON_DIV_CLKCMU_FSYS_MMC_EMBD, |
119 | CLK_CON_DIV_CLKCMU_FSYS_MMC_SDIO, |
120 | CLK_CON_DIV_CLKCMU_FSYS_USB30DRD, |
121 | CLK_CON_DIV_CLKCMU_PERI_BUS, |
122 | CLK_CON_DIV_CLKCMU_PERI_SPI0, |
123 | CLK_CON_DIV_CLKCMU_PERI_SPI1, |
124 | CLK_CON_DIV_CLKCMU_PERI_UART0, |
125 | CLK_CON_DIV_CLKCMU_PERI_UART1, |
126 | CLK_CON_DIV_CLKCMU_PERI_UART2, |
127 | CLK_CON_DIV_CLKCMU_PERI_USI0, |
128 | CLK_CON_DIV_CLKCMU_PERI_USI1, |
129 | CLK_CON_DIV_CLKCMU_PERI_USI2, |
130 | CLK_CON_DIV_PLL_SHARED0_DIV2, |
131 | CLK_CON_DIV_PLL_SHARED0_DIV3, |
132 | CLK_CON_DIV_PLL_SHARED0_DIV4, |
133 | CLK_CON_DIV_PLL_SHARED0_DIV5, |
134 | CLK_CON_DIV_PLL_SHARED1_DIV2, |
135 | CLK_CON_DIV_PLL_SHARED1_DIV3, |
136 | CLK_CON_DIV_PLL_SHARED1_DIV4, |
137 | CLK_CON_GAT_GATE_CLKCMUC_PERI_UART1, |
138 | CLK_CON_GAT_GATE_CLKCMU_CORE_BUS, |
139 | CLK_CON_GAT_GATE_CLKCMU_CORE_CCI, |
140 | CLK_CON_GAT_GATE_CLKCMU_CORE_G3D, |
141 | CLK_CON_GAT_GATE_CLKCMU_FSYS_BUS, |
142 | CLK_CON_GAT_GATE_CLKCMU_FSYS_MMC_CARD, |
143 | CLK_CON_GAT_GATE_CLKCMU_FSYS_MMC_EMBD, |
144 | CLK_CON_GAT_GATE_CLKCMU_FSYS_MMC_SDIO, |
145 | CLK_CON_GAT_GATE_CLKCMU_FSYS_USB30DRD, |
146 | CLK_CON_GAT_GATE_CLKCMU_PERI_BUS, |
147 | CLK_CON_GAT_GATE_CLKCMU_PERI_SPI0, |
148 | CLK_CON_GAT_GATE_CLKCMU_PERI_SPI1, |
149 | CLK_CON_GAT_GATE_CLKCMU_PERI_UART0, |
150 | CLK_CON_GAT_GATE_CLKCMU_PERI_UART2, |
151 | CLK_CON_GAT_GATE_CLKCMU_PERI_USI0, |
152 | CLK_CON_GAT_GATE_CLKCMU_PERI_USI1, |
153 | CLK_CON_GAT_GATE_CLKCMU_PERI_USI2, |
154 | }; |
155 | |
156 | static const struct samsung_pll_clock top_pll_clks[] __initconst = { |
157 | PLL(pll_1417x, CLK_FOUT_SHARED0_PLL, "fout_shared0_pll" , "oscclk" , |
158 | PLL_LOCKTIME_PLL_SHARED0, PLL_CON0_PLL_SHARED0, |
159 | NULL), |
160 | PLL(pll_1417x, CLK_FOUT_SHARED1_PLL, "fout_shared1_pll" , "oscclk" , |
161 | PLL_LOCKTIME_PLL_SHARED1, PLL_CON0_PLL_SHARED1, |
162 | NULL), |
163 | }; |
164 | |
165 | /* List of parent clocks for Muxes in CMU_TOP: for CMU_CORE */ |
166 | PNAME(mout_core_bus_p) = { "dout_shared0_div2" , "dout_shared1_div2" , |
167 | "dout_shared0_div3" , "dout_shared0_div3" }; |
168 | PNAME(mout_core_cci_p) = { "dout_shared0_div2" , "dout_shared1_div2" , |
169 | "dout_shared0_div3" , "dout_shared0_div3" }; |
170 | PNAME(mout_core_g3d_p) = { "dout_shared0_div2" , "dout_shared1_div2" , |
171 | "dout_shared0_div3" , "dout_shared0_div3" }; |
172 | |
173 | /* List of parent clocks for Muxes in CMU_TOP: for CMU_PERI */ |
174 | PNAME(mout_peri_bus_p) = { "dout_shared0_div4" , "dout_shared1_div4" }; |
175 | PNAME(mout_peri_spi0_p) = { "oscclk" , "dout_shared0_div4" }; |
176 | PNAME(mout_peri_spi1_p) = { "oscclk" , "dout_shared0_div4" }; |
177 | PNAME(mout_peri_uart0_p) = { "oscclk" , "dout_shared0_div4" }; |
178 | PNAME(mout_peri_uart1_p) = { "oscclk" , "dout_shared0_div4" }; |
179 | PNAME(mout_peri_uart2_p) = { "oscclk" , "dout_shared0_div4" }; |
180 | PNAME(mout_peri_usi0_p) = { "oscclk" , "dout_shared0_div4" }; |
181 | PNAME(mout_peri_usi1_p) = { "oscclk" , "dout_shared0_div4" }; |
182 | PNAME(mout_peri_usi2_p) = { "oscclk" , "dout_shared0_div4" }; |
183 | |
184 | /* List of parent clocks for Muxes in CMU_TOP: for CMU_FSYS */ |
185 | PNAME(mout_fsys_bus_p) = { "dout_shared0_div2" , "dout_shared1_div2" }; |
186 | PNAME(mout_fsys_mmc_card_p) = { "dout_shared0_div2" , "dout_shared1_div2" }; |
187 | PNAME(mout_fsys_mmc_embd_p) = { "dout_shared0_div2" , "dout_shared1_div2" }; |
188 | PNAME(mout_fsys_mmc_sdio_p) = { "dout_shared0_div2" , "dout_shared1_div2" }; |
189 | PNAME(mout_fsys_usb30drd_p) = { "dout_shared0_div4" , "dout_shared1_div4" }; |
190 | |
191 | static const struct samsung_mux_clock top_mux_clks[] __initconst = { |
192 | /* CORE */ |
193 | MUX(CLK_MOUT_CORE_BUS, "mout_core_bus" , mout_core_bus_p, |
194 | CLK_CON_MUX_MUX_CLKCMU_CORE_BUS, 0, 2), |
195 | MUX(CLK_MOUT_CORE_CCI, "mout_core_cci" , mout_core_cci_p, |
196 | CLK_CON_MUX_MUX_CLKCMU_CORE_CCI, 0, 2), |
197 | MUX(CLK_MOUT_CORE_G3D, "mout_core_g3d" , mout_core_g3d_p, |
198 | CLK_CON_MUX_MUX_CLKCMU_CORE_G3D, 0, 2), |
199 | |
200 | /* PERI */ |
201 | MUX(CLK_MOUT_PERI_BUS, "mout_peri_bus" , mout_peri_bus_p, |
202 | CLK_CON_MUX_MUX_CLKCMU_PERI_BUS, 0, 1), |
203 | MUX(CLK_MOUT_PERI_SPI0, "mout_peri_spi0" , mout_peri_spi0_p, |
204 | CLK_CON_MUX_MUX_CLKCMU_PERI_SPI0, 0, 1), |
205 | MUX(CLK_MOUT_PERI_SPI1, "mout_peri_spi1" , mout_peri_spi1_p, |
206 | CLK_CON_MUX_MUX_CLKCMU_PERI_SPI1, 0, 1), |
207 | MUX(CLK_MOUT_PERI_UART0, "mout_peri_uart0" , mout_peri_uart0_p, |
208 | CLK_CON_MUX_MUX_CLKCMU_PERI_UART0, 0, 1), |
209 | MUX(CLK_MOUT_PERI_UART1, "mout_peri_uart1" , mout_peri_uart1_p, |
210 | CLK_CON_MUX_MUX_CLKCMU_PERI_UART1, 0, 1), |
211 | MUX(CLK_MOUT_PERI_UART2, "mout_peri_uart2" , mout_peri_uart2_p, |
212 | CLK_CON_MUX_MUX_CLKCMU_PERI_UART2, 0, 1), |
213 | MUX(CLK_MOUT_PERI_USI0, "mout_peri_usi0" , mout_peri_usi0_p, |
214 | CLK_CON_MUX_MUX_CLKCMU_PERI_USI0, 0, 1), |
215 | MUX(CLK_MOUT_PERI_USI1, "mout_peri_usi1" , mout_peri_usi1_p, |
216 | CLK_CON_MUX_MUX_CLKCMU_PERI_USI1, 0, 1), |
217 | MUX(CLK_MOUT_PERI_USI2, "mout_peri_usi2" , mout_peri_usi2_p, |
218 | CLK_CON_MUX_MUX_CLKCMU_PERI_USI2, 0, 1), |
219 | |
220 | /* FSYS */ |
221 | MUX(CLK_MOUT_FSYS_BUS, "mout_fsys_bus" , mout_fsys_bus_p, |
222 | CLK_CON_MUX_MUX_CLKCMU_FSYS_BUS, 0, 1), |
223 | MUX(CLK_MOUT_FSYS_MMC_CARD, "mout_fsys_mmc_card" , mout_fsys_mmc_card_p, |
224 | CLK_CON_MUX_MUX_CLKCMU_FSYS_MMC_CARD, 0, 1), |
225 | MUX(CLK_MOUT_FSYS_MMC_EMBD, "mout_fsys_mmc_embd" , mout_fsys_mmc_embd_p, |
226 | CLK_CON_MUX_MUX_CLKCMU_FSYS_MMC_EMBD, 0, 1), |
227 | MUX(CLK_MOUT_FSYS_MMC_SDIO, "mout_fsys_mmc_sdio" , mout_fsys_mmc_sdio_p, |
228 | CLK_CON_MUX_MUX_CLKCMU_FSYS_MMC_SDIO, 0, 1), |
229 | MUX(CLK_MOUT_FSYS_USB30DRD, "mout_fsys_usb30drd" , mout_fsys_usb30drd_p, |
230 | CLK_CON_MUX_MUX_CLKCMU_FSYS_USB30DRD, 0, 1), |
231 | }; |
232 | |
233 | static const struct samsung_div_clock top_div_clks[] __initconst = { |
234 | /* TOP */ |
235 | DIV(CLK_DOUT_SHARED0_DIV2, "dout_shared0_div2" , "fout_shared0_pll" , |
236 | CLK_CON_DIV_PLL_SHARED0_DIV2, 0, 1), |
237 | DIV(CLK_DOUT_SHARED0_DIV3, "dout_shared0_div3" , "fout_shared0_pll" , |
238 | CLK_CON_DIV_PLL_SHARED0_DIV3, 0, 2), |
239 | DIV(CLK_DOUT_SHARED0_DIV4, "dout_shared0_div4" , "dout_shared0_div2" , |
240 | CLK_CON_DIV_PLL_SHARED0_DIV4, 0, 1), |
241 | DIV(CLK_DOUT_SHARED0_DIV5, "dout_shared0_div5" , "fout_shared0_pll" , |
242 | CLK_CON_DIV_PLL_SHARED0_DIV5, 0, 3), |
243 | DIV(CLK_DOUT_SHARED1_DIV2, "dout_shared1_div2" , "fout_shared1_pll" , |
244 | CLK_CON_DIV_PLL_SHARED1_DIV2, 0, 1), |
245 | DIV(CLK_DOUT_SHARED1_DIV3, "dout_shared1_div3" , "fout_shared1_pll" , |
246 | CLK_CON_DIV_PLL_SHARED1_DIV3, 0, 2), |
247 | DIV(CLK_DOUT_SHARED1_DIV4, "dout_shared1_div4" , "dout_shared1_div2" , |
248 | CLK_CON_DIV_PLL_SHARED1_DIV4, 0, 1), |
249 | |
250 | /* CORE */ |
251 | DIV(CLK_DOUT_CORE_BUS, "dout_core_bus" , "gout_core_bus" , |
252 | CLK_CON_DIV_CLKCMU_CORE_BUS, 0, 3), |
253 | DIV(CLK_DOUT_CORE_CCI, "dout_core_cci" , "gout_core_cci" , |
254 | CLK_CON_DIV_CLKCMU_CORE_CCI, 0, 3), |
255 | DIV(CLK_DOUT_CORE_G3D, "dout_core_g3d" , "gout_core_g3d" , |
256 | CLK_CON_DIV_CLKCMU_CORE_G3D, 0, 3), |
257 | |
258 | /* PERI */ |
259 | DIV(CLK_DOUT_PERI_BUS, "dout_peri_bus" , "gout_peri_bus" , |
260 | CLK_CON_DIV_CLKCMU_PERI_BUS, 0, 4), |
261 | DIV(CLK_DOUT_PERI_SPI0, "dout_peri_spi0" , "gout_peri_spi0" , |
262 | CLK_CON_DIV_CLKCMU_PERI_SPI0, 0, 6), |
263 | DIV(CLK_DOUT_PERI_SPI1, "dout_peri_spi1" , "gout_peri_spi1" , |
264 | CLK_CON_DIV_CLKCMU_PERI_SPI1, 0, 6), |
265 | DIV(CLK_DOUT_PERI_UART0, "dout_peri_uart0" , "gout_peri_uart0" , |
266 | CLK_CON_DIV_CLKCMU_PERI_UART0, 0, 4), |
267 | DIV(CLK_DOUT_PERI_UART1, "dout_peri_uart1" , "gout_peri_uart1" , |
268 | CLK_CON_DIV_CLKCMU_PERI_UART1, 0, 4), |
269 | DIV(CLK_DOUT_PERI_UART2, "dout_peri_uart2" , "gout_peri_uart2" , |
270 | CLK_CON_DIV_CLKCMU_PERI_UART2, 0, 4), |
271 | DIV(CLK_DOUT_PERI_USI0, "dout_peri_usi0" , "gout_peri_usi0" , |
272 | CLK_CON_DIV_CLKCMU_PERI_USI0, 0, 4), |
273 | DIV(CLK_DOUT_PERI_USI1, "dout_peri_usi1" , "gout_peri_usi1" , |
274 | CLK_CON_DIV_CLKCMU_PERI_USI1, 0, 4), |
275 | DIV(CLK_DOUT_PERI_USI2, "dout_peri_usi2" , "gout_peri_usi2" , |
276 | CLK_CON_DIV_CLKCMU_PERI_USI2, 0, 4), |
277 | |
278 | /* FSYS */ |
279 | DIV(CLK_DOUT_FSYS_BUS, "dout_fsys_bus" , "gout_fsys_bus" , |
280 | CLK_CON_DIV_CLKCMU_FSYS_BUS, 0, 4), |
281 | DIV(CLK_DOUT_FSYS_MMC_CARD, "dout_fsys_mmc_card" , "gout_fsys_mmc_card" , |
282 | CLK_CON_DIV_CLKCMU_FSYS_MMC_CARD, 0, 9), |
283 | DIV(CLK_DOUT_FSYS_MMC_EMBD, "dout_fsys_mmc_embd" , "gout_fsys_mmc_embd" , |
284 | CLK_CON_DIV_CLKCMU_FSYS_MMC_EMBD, 0, 9), |
285 | DIV(CLK_DOUT_FSYS_MMC_SDIO, "dout_fsys_mmc_sdio" , "gout_fsys_mmc_sdio" , |
286 | CLK_CON_DIV_CLKCMU_FSYS_MMC_SDIO, 0, 9), |
287 | DIV(CLK_DOUT_FSYS_USB30DRD, "dout_fsys_usb30drd" , "gout_fsys_usb30drd" , |
288 | CLK_CON_DIV_CLKCMU_FSYS_USB30DRD, 0, 4), |
289 | }; |
290 | |
291 | static const struct samsung_gate_clock top_gate_clks[] __initconst = { |
292 | /* CORE */ |
293 | GATE(CLK_GOUT_CORE_BUS, "gout_core_bus" , "mout_core_bus" , |
294 | CLK_CON_GAT_GATE_CLKCMU_CORE_BUS, 21, 0, 0), |
295 | GATE(CLK_GOUT_CORE_CCI, "gout_core_cci" , "mout_core_cci" , |
296 | CLK_CON_GAT_GATE_CLKCMU_CORE_CCI, 21, 0, 0), |
297 | GATE(CLK_GOUT_CORE_G3D, "gout_core_g3d" , "mout_core_g3d" , |
298 | CLK_CON_GAT_GATE_CLKCMU_CORE_G3D, 21, 0, 0), |
299 | |
300 | /* PERI */ |
301 | GATE(CLK_GOUT_PERI_BUS, "gout_peri_bus" , "mout_peri_bus" , |
302 | CLK_CON_GAT_GATE_CLKCMU_PERI_BUS, 21, 0, 0), |
303 | GATE(CLK_GOUT_PERI_SPI0, "gout_peri_spi0" , "mout_peri_spi0" , |
304 | CLK_CON_GAT_GATE_CLKCMU_PERI_SPI0, 21, 0, 0), |
305 | GATE(CLK_GOUT_PERI_SPI1, "gout_peri_spi1" , "mout_peri_spi1" , |
306 | CLK_CON_GAT_GATE_CLKCMU_PERI_SPI1, 21, 0, 0), |
307 | GATE(CLK_GOUT_PERI_UART0, "gout_peri_uart0" , "mout_peri_uart0" , |
308 | CLK_CON_GAT_GATE_CLKCMU_PERI_UART0, 21, 0, 0), |
309 | GATE(CLK_GOUT_PERI_UART1, "gout_peri_uart1" , "mout_peri_uart1" , |
310 | CLK_CON_GAT_GATE_CLKCMUC_PERI_UART1, 21, 0, 0), |
311 | GATE(CLK_GOUT_PERI_UART2, "gout_peri_uart2" , "mout_peri_uart2" , |
312 | CLK_CON_GAT_GATE_CLKCMU_PERI_UART2, 21, 0, 0), |
313 | GATE(CLK_GOUT_PERI_USI0, "gout_peri_usi0" , "mout_peri_usi0" , |
314 | CLK_CON_GAT_GATE_CLKCMU_PERI_USI0, 21, 0, 0), |
315 | GATE(CLK_GOUT_PERI_USI1, "gout_peri_usi1" , "mout_peri_usi1" , |
316 | CLK_CON_GAT_GATE_CLKCMU_PERI_USI1, 21, 0, 0), |
317 | GATE(CLK_GOUT_PERI_USI2, "gout_peri_usi2" , "mout_peri_usi2" , |
318 | CLK_CON_GAT_GATE_CLKCMU_PERI_USI2, 21, 0, 0), |
319 | |
320 | /* FSYS */ |
321 | GATE(CLK_GOUT_FSYS_BUS, "gout_fsys_bus" , "mout_fsys_bus" , |
322 | CLK_CON_GAT_GATE_CLKCMU_FSYS_BUS, 21, 0, 0), |
323 | GATE(CLK_GOUT_FSYS_MMC_CARD, "gout_fsys_mmc_card" , "mout_fsys_mmc_card" , |
324 | CLK_CON_GAT_GATE_CLKCMU_FSYS_MMC_CARD, 21, 0, 0), |
325 | GATE(CLK_GOUT_FSYS_MMC_EMBD, "gout_fsys_mmc_embd" , "mout_fsys_mmc_embd" , |
326 | CLK_CON_GAT_GATE_CLKCMU_FSYS_MMC_EMBD, 21, 0, 0), |
327 | GATE(CLK_GOUT_FSYS_MMC_SDIO, "gout_fsys_mmc_sdio" , "mout_fsys_mmc_sdio" , |
328 | CLK_CON_GAT_GATE_CLKCMU_FSYS_MMC_SDIO, 21, 0, 0), |
329 | GATE(CLK_GOUT_FSYS_USB30DRD, "gout_fsys_usb30drd" , "mout_fsys_usb30drd" , |
330 | CLK_CON_GAT_GATE_CLKCMU_FSYS_USB30DRD, 21, 0, 0), |
331 | }; |
332 | |
333 | static const struct samsung_cmu_info top_cmu_info __initconst = { |
334 | .pll_clks = top_pll_clks, |
335 | .nr_pll_clks = ARRAY_SIZE(top_pll_clks), |
336 | .mux_clks = top_mux_clks, |
337 | .nr_mux_clks = ARRAY_SIZE(top_mux_clks), |
338 | .div_clks = top_div_clks, |
339 | .nr_div_clks = ARRAY_SIZE(top_div_clks), |
340 | .gate_clks = top_gate_clks, |
341 | .nr_gate_clks = ARRAY_SIZE(top_gate_clks), |
342 | .nr_clk_ids = CLKS_NR_TOP, |
343 | .clk_regs = top_clk_regs, |
344 | .nr_clk_regs = ARRAY_SIZE(top_clk_regs), |
345 | }; |
346 | |
347 | static void __init exynos7885_cmu_top_init(struct device_node *np) |
348 | { |
349 | exynos_arm64_register_cmu(NULL, np, cmu: &top_cmu_info); |
350 | } |
351 | |
352 | /* Register CMU_TOP early, as it's a dependency for other early domains */ |
353 | CLK_OF_DECLARE(exynos7885_cmu_top, "samsung,exynos7885-cmu-top" , |
354 | exynos7885_cmu_top_init); |
355 | |
356 | /* ---- CMU_PERI ------------------------------------------------------------ */ |
357 | |
358 | /* Register Offset definitions for CMU_PERI (0x10010000) */ |
359 | #define PLL_CON0_MUX_CLKCMU_PERI_BUS_USER 0x0100 |
360 | #define PLL_CON0_MUX_CLKCMU_PERI_SPI0_USER 0x0120 |
361 | #define PLL_CON0_MUX_CLKCMU_PERI_SPI1_USER 0x0140 |
362 | #define PLL_CON0_MUX_CLKCMU_PERI_UART0_USER 0x0160 |
363 | #define PLL_CON0_MUX_CLKCMU_PERI_UART1_USER 0x0180 |
364 | #define PLL_CON0_MUX_CLKCMU_PERI_UART2_USER 0x01a0 |
365 | #define PLL_CON0_MUX_CLKCMU_PERI_USI0_USER 0x01c0 |
366 | #define PLL_CON0_MUX_CLKCMU_PERI_USI1_USER 0x01e0 |
367 | #define PLL_CON0_MUX_CLKCMU_PERI_USI2_USER 0x0200 |
368 | #define CLK_CON_GAT_GOUT_PERI_GPIO_TOP_PCLK 0x2024 |
369 | #define CLK_CON_GAT_GOUT_PERI_HSI2C_0_PCLK 0x2028 |
370 | #define CLK_CON_GAT_GOUT_PERI_HSI2C_1_PCLK 0x202c |
371 | #define CLK_CON_GAT_GOUT_PERI_HSI2C_2_PCLK 0x2030 |
372 | #define CLK_CON_GAT_GOUT_PERI_HSI2C_3_PCLK 0x2034 |
373 | #define CLK_CON_GAT_GOUT_PERI_I2C_0_PCLK 0x2038 |
374 | #define CLK_CON_GAT_GOUT_PERI_I2C_1_PCLK 0x203c |
375 | #define CLK_CON_GAT_GOUT_PERI_I2C_2_PCLK 0x2040 |
376 | #define CLK_CON_GAT_GOUT_PERI_I2C_3_PCLK 0x2044 |
377 | #define CLK_CON_GAT_GOUT_PERI_I2C_4_PCLK 0x2048 |
378 | #define CLK_CON_GAT_GOUT_PERI_I2C_5_PCLK 0x204c |
379 | #define CLK_CON_GAT_GOUT_PERI_I2C_6_PCLK 0x2050 |
380 | #define CLK_CON_GAT_GOUT_PERI_I2C_7_PCLK 0x2054 |
381 | #define CLK_CON_GAT_GOUT_PERI_PWM_MOTOR_PCLK 0x2058 |
382 | #define CLK_CON_GAT_GOUT_PERI_SPI_0_PCLK 0x205c |
383 | #define CLK_CON_GAT_GOUT_PERI_SPI_0_EXT_CLK 0x2060 |
384 | #define CLK_CON_GAT_GOUT_PERI_SPI_1_PCLK 0x2064 |
385 | #define CLK_CON_GAT_GOUT_PERI_SPI_1_EXT_CLK 0x2068 |
386 | #define CLK_CON_GAT_GOUT_PERI_UART_0_EXT_UCLK 0x206c |
387 | #define CLK_CON_GAT_GOUT_PERI_UART_0_PCLK 0x2070 |
388 | #define CLK_CON_GAT_GOUT_PERI_UART_1_EXT_UCLK 0x2074 |
389 | #define CLK_CON_GAT_GOUT_PERI_UART_1_PCLK 0x2078 |
390 | #define CLK_CON_GAT_GOUT_PERI_UART_2_EXT_UCLK 0x207c |
391 | #define CLK_CON_GAT_GOUT_PERI_UART_2_PCLK 0x2080 |
392 | #define CLK_CON_GAT_GOUT_PERI_USI0_PCLK 0x2084 |
393 | #define CLK_CON_GAT_GOUT_PERI_USI0_SCLK 0x2088 |
394 | #define CLK_CON_GAT_GOUT_PERI_USI1_PCLK 0x208c |
395 | #define CLK_CON_GAT_GOUT_PERI_USI1_SCLK 0x2090 |
396 | #define CLK_CON_GAT_GOUT_PERI_USI2_PCLK 0x2094 |
397 | #define CLK_CON_GAT_GOUT_PERI_USI2_SCLK 0x2098 |
398 | #define CLK_CON_GAT_GOUT_PERI_MCT_PCLK 0x20a0 |
399 | #define CLK_CON_GAT_GOUT_PERI_SYSREG_PERI_PCLK 0x20b0 |
400 | #define CLK_CON_GAT_GOUT_PERI_WDT_CLUSTER0_PCLK 0x20b4 |
401 | #define CLK_CON_GAT_GOUT_PERI_WDT_CLUSTER1_PCLK 0x20b8 |
402 | |
403 | static const unsigned long peri_clk_regs[] __initconst = { |
404 | PLL_CON0_MUX_CLKCMU_PERI_BUS_USER, |
405 | PLL_CON0_MUX_CLKCMU_PERI_SPI0_USER, |
406 | PLL_CON0_MUX_CLKCMU_PERI_SPI1_USER, |
407 | PLL_CON0_MUX_CLKCMU_PERI_UART0_USER, |
408 | PLL_CON0_MUX_CLKCMU_PERI_UART1_USER, |
409 | PLL_CON0_MUX_CLKCMU_PERI_UART2_USER, |
410 | PLL_CON0_MUX_CLKCMU_PERI_USI0_USER, |
411 | PLL_CON0_MUX_CLKCMU_PERI_USI1_USER, |
412 | PLL_CON0_MUX_CLKCMU_PERI_USI2_USER, |
413 | CLK_CON_GAT_GOUT_PERI_GPIO_TOP_PCLK, |
414 | CLK_CON_GAT_GOUT_PERI_HSI2C_0_PCLK, |
415 | CLK_CON_GAT_GOUT_PERI_HSI2C_1_PCLK, |
416 | CLK_CON_GAT_GOUT_PERI_HSI2C_2_PCLK, |
417 | CLK_CON_GAT_GOUT_PERI_HSI2C_3_PCLK, |
418 | CLK_CON_GAT_GOUT_PERI_I2C_0_PCLK, |
419 | CLK_CON_GAT_GOUT_PERI_I2C_1_PCLK, |
420 | CLK_CON_GAT_GOUT_PERI_I2C_2_PCLK, |
421 | CLK_CON_GAT_GOUT_PERI_I2C_3_PCLK, |
422 | CLK_CON_GAT_GOUT_PERI_I2C_4_PCLK, |
423 | CLK_CON_GAT_GOUT_PERI_I2C_5_PCLK, |
424 | CLK_CON_GAT_GOUT_PERI_I2C_6_PCLK, |
425 | CLK_CON_GAT_GOUT_PERI_I2C_7_PCLK, |
426 | CLK_CON_GAT_GOUT_PERI_PWM_MOTOR_PCLK, |
427 | CLK_CON_GAT_GOUT_PERI_SPI_0_PCLK, |
428 | CLK_CON_GAT_GOUT_PERI_SPI_0_EXT_CLK, |
429 | CLK_CON_GAT_GOUT_PERI_SPI_1_PCLK, |
430 | CLK_CON_GAT_GOUT_PERI_SPI_1_EXT_CLK, |
431 | CLK_CON_GAT_GOUT_PERI_UART_0_EXT_UCLK, |
432 | CLK_CON_GAT_GOUT_PERI_UART_0_PCLK, |
433 | CLK_CON_GAT_GOUT_PERI_UART_1_EXT_UCLK, |
434 | CLK_CON_GAT_GOUT_PERI_UART_1_PCLK, |
435 | CLK_CON_GAT_GOUT_PERI_UART_2_EXT_UCLK, |
436 | CLK_CON_GAT_GOUT_PERI_UART_2_PCLK, |
437 | CLK_CON_GAT_GOUT_PERI_USI0_PCLK, |
438 | CLK_CON_GAT_GOUT_PERI_USI0_SCLK, |
439 | CLK_CON_GAT_GOUT_PERI_USI1_PCLK, |
440 | CLK_CON_GAT_GOUT_PERI_USI1_SCLK, |
441 | CLK_CON_GAT_GOUT_PERI_USI2_PCLK, |
442 | CLK_CON_GAT_GOUT_PERI_USI2_SCLK, |
443 | CLK_CON_GAT_GOUT_PERI_MCT_PCLK, |
444 | CLK_CON_GAT_GOUT_PERI_SYSREG_PERI_PCLK, |
445 | CLK_CON_GAT_GOUT_PERI_WDT_CLUSTER0_PCLK, |
446 | CLK_CON_GAT_GOUT_PERI_WDT_CLUSTER1_PCLK, |
447 | }; |
448 | |
449 | /* List of parent clocks for Muxes in CMU_PERI */ |
450 | PNAME(mout_peri_bus_user_p) = { "oscclk" , "dout_peri_bus" }; |
451 | PNAME(mout_peri_spi0_user_p) = { "oscclk" , "dout_peri_spi0" }; |
452 | PNAME(mout_peri_spi1_user_p) = { "oscclk" , "dout_peri_spi1" }; |
453 | PNAME(mout_peri_uart0_user_p) = { "oscclk" , "dout_peri_uart0" }; |
454 | PNAME(mout_peri_uart1_user_p) = { "oscclk" , "dout_peri_uart1" }; |
455 | PNAME(mout_peri_uart2_user_p) = { "oscclk" , "dout_peri_uart2" }; |
456 | PNAME(mout_peri_usi0_user_p) = { "oscclk" , "dout_peri_usi0" }; |
457 | PNAME(mout_peri_usi1_user_p) = { "oscclk" , "dout_peri_usi1" }; |
458 | PNAME(mout_peri_usi2_user_p) = { "oscclk" , "dout_peri_usi2" }; |
459 | |
460 | static const struct samsung_mux_clock peri_mux_clks[] __initconst = { |
461 | MUX(CLK_MOUT_PERI_BUS_USER, "mout_peri_bus_user" , mout_peri_bus_user_p, |
462 | PLL_CON0_MUX_CLKCMU_PERI_BUS_USER, 4, 1), |
463 | MUX(CLK_MOUT_PERI_SPI0_USER, "mout_peri_spi0_user" , mout_peri_spi0_user_p, |
464 | PLL_CON0_MUX_CLKCMU_PERI_SPI0_USER, 4, 1), |
465 | MUX(CLK_MOUT_PERI_SPI1_USER, "mout_peri_spi1_user" , mout_peri_spi1_user_p, |
466 | PLL_CON0_MUX_CLKCMU_PERI_SPI1_USER, 4, 1), |
467 | MUX(CLK_MOUT_PERI_UART0_USER, "mout_peri_uart0_user" , |
468 | mout_peri_uart0_user_p, PLL_CON0_MUX_CLKCMU_PERI_UART0_USER, 4, 1), |
469 | MUX(CLK_MOUT_PERI_UART1_USER, "mout_peri_uart1_user" , |
470 | mout_peri_uart1_user_p, PLL_CON0_MUX_CLKCMU_PERI_UART1_USER, 4, 1), |
471 | MUX(CLK_MOUT_PERI_UART2_USER, "mout_peri_uart2_user" , |
472 | mout_peri_uart2_user_p, PLL_CON0_MUX_CLKCMU_PERI_UART2_USER, 4, 1), |
473 | MUX(CLK_MOUT_PERI_USI0_USER, "mout_peri_usi0_user" , |
474 | mout_peri_usi0_user_p, PLL_CON0_MUX_CLKCMU_PERI_USI0_USER, 4, 1), |
475 | MUX(CLK_MOUT_PERI_USI1_USER, "mout_peri_usi1_user" , |
476 | mout_peri_usi1_user_p, PLL_CON0_MUX_CLKCMU_PERI_USI1_USER, 4, 1), |
477 | MUX(CLK_MOUT_PERI_USI2_USER, "mout_peri_usi2_user" , |
478 | mout_peri_usi2_user_p, PLL_CON0_MUX_CLKCMU_PERI_USI2_USER, 4, 1), |
479 | }; |
480 | |
481 | static const struct samsung_gate_clock peri_gate_clks[] __initconst = { |
482 | /* TODO: Should be enabled in GPIO driver (or made CLK_IS_CRITICAL) */ |
483 | GATE(CLK_GOUT_GPIO_TOP_PCLK, "gout_gpio_top_pclk" , |
484 | "mout_peri_bus_user" , |
485 | CLK_CON_GAT_GOUT_PERI_GPIO_TOP_PCLK, 21, CLK_IGNORE_UNUSED, 0), |
486 | GATE(CLK_GOUT_HSI2C0_PCLK, "gout_hsi2c0_pclk" , "mout_peri_bus_user" , |
487 | CLK_CON_GAT_GOUT_PERI_HSI2C_0_PCLK, 21, 0, 0), |
488 | GATE(CLK_GOUT_HSI2C1_PCLK, "gout_hsi2c1_pclk" , "mout_peri_bus_user" , |
489 | CLK_CON_GAT_GOUT_PERI_HSI2C_1_PCLK, 21, 0, 0), |
490 | GATE(CLK_GOUT_HSI2C2_PCLK, "gout_hsi2c2_pclk" , "mout_peri_bus_user" , |
491 | CLK_CON_GAT_GOUT_PERI_HSI2C_2_PCLK, 21, 0, 0), |
492 | GATE(CLK_GOUT_HSI2C3_PCLK, "gout_hsi2c3_pclk" , "mout_peri_bus_user" , |
493 | CLK_CON_GAT_GOUT_PERI_HSI2C_3_PCLK, 21, 0, 0), |
494 | GATE(CLK_GOUT_I2C0_PCLK, "gout_i2c0_pclk" , "mout_peri_bus_user" , |
495 | CLK_CON_GAT_GOUT_PERI_I2C_0_PCLK, 21, 0, 0), |
496 | GATE(CLK_GOUT_I2C1_PCLK, "gout_i2c1_pclk" , "mout_peri_bus_user" , |
497 | CLK_CON_GAT_GOUT_PERI_I2C_1_PCLK, 21, 0, 0), |
498 | GATE(CLK_GOUT_I2C2_PCLK, "gout_i2c2_pclk" , "mout_peri_bus_user" , |
499 | CLK_CON_GAT_GOUT_PERI_I2C_2_PCLK, 21, 0, 0), |
500 | GATE(CLK_GOUT_I2C3_PCLK, "gout_i2c3_pclk" , "mout_peri_bus_user" , |
501 | CLK_CON_GAT_GOUT_PERI_I2C_3_PCLK, 21, 0, 0), |
502 | GATE(CLK_GOUT_I2C4_PCLK, "gout_i2c4_pclk" , "mout_peri_bus_user" , |
503 | CLK_CON_GAT_GOUT_PERI_I2C_4_PCLK, 21, 0, 0), |
504 | GATE(CLK_GOUT_I2C5_PCLK, "gout_i2c5_pclk" , "mout_peri_bus_user" , |
505 | CLK_CON_GAT_GOUT_PERI_I2C_5_PCLK, 21, 0, 0), |
506 | GATE(CLK_GOUT_I2C6_PCLK, "gout_i2c6_pclk" , "mout_peri_bus_user" , |
507 | CLK_CON_GAT_GOUT_PERI_I2C_6_PCLK, 21, 0, 0), |
508 | GATE(CLK_GOUT_I2C7_PCLK, "gout_i2c7_pclk" , "mout_peri_bus_user" , |
509 | CLK_CON_GAT_GOUT_PERI_I2C_7_PCLK, 21, 0, 0), |
510 | GATE(CLK_GOUT_PWM_MOTOR_PCLK, "gout_pwm_motor_pclk" , |
511 | "mout_peri_bus_user" , |
512 | CLK_CON_GAT_GOUT_PERI_PWM_MOTOR_PCLK, 21, 0, 0), |
513 | GATE(CLK_GOUT_SPI0_PCLK, "gout_spi0_pclk" , "mout_peri_bus_user" , |
514 | CLK_CON_GAT_GOUT_PERI_SPI_0_PCLK, 21, 0, 0), |
515 | GATE(CLK_GOUT_SPI0_EXT_CLK, "gout_spi0_ipclk" , "mout_peri_spi0_user" , |
516 | CLK_CON_GAT_GOUT_PERI_SPI_0_EXT_CLK, 21, 0, 0), |
517 | GATE(CLK_GOUT_SPI1_PCLK, "gout_spi1_pclk" , "mout_peri_bus_user" , |
518 | CLK_CON_GAT_GOUT_PERI_SPI_1_PCLK, 21, 0, 0), |
519 | GATE(CLK_GOUT_SPI1_EXT_CLK, "gout_spi1_ipclk" , "mout_peri_spi1_user" , |
520 | CLK_CON_GAT_GOUT_PERI_SPI_1_EXT_CLK, 21, 0, 0), |
521 | GATE(CLK_GOUT_UART0_EXT_UCLK, "gout_uart0_ext_uclk" , "mout_peri_uart0_user" , |
522 | CLK_CON_GAT_GOUT_PERI_UART_0_EXT_UCLK, 21, 0, 0), |
523 | GATE(CLK_GOUT_UART0_PCLK, "gout_uart0_pclk" , "mout_peri_bus_user" , |
524 | CLK_CON_GAT_GOUT_PERI_UART_0_PCLK, 21, 0, 0), |
525 | GATE(CLK_GOUT_UART1_EXT_UCLK, "gout_uart1_ext_uclk" , "mout_peri_uart1_user" , |
526 | CLK_CON_GAT_GOUT_PERI_UART_1_EXT_UCLK, 21, 0, 0), |
527 | GATE(CLK_GOUT_UART1_PCLK, "gout_uart1_pclk" , "mout_peri_bus_user" , |
528 | CLK_CON_GAT_GOUT_PERI_UART_1_PCLK, 21, 0, 0), |
529 | GATE(CLK_GOUT_UART2_EXT_UCLK, "gout_uart2_ext_uclk" , "mout_peri_uart2_user" , |
530 | CLK_CON_GAT_GOUT_PERI_UART_2_EXT_UCLK, 21, 0, 0), |
531 | GATE(CLK_GOUT_UART2_PCLK, "gout_uart2_pclk" , "mout_peri_bus_user" , |
532 | CLK_CON_GAT_GOUT_PERI_UART_2_PCLK, 21, 0, 0), |
533 | GATE(CLK_GOUT_USI0_PCLK, "gout_usi0_pclk" , "mout_peri_bus_user" , |
534 | CLK_CON_GAT_GOUT_PERI_USI0_PCLK, 21, 0, 0), |
535 | GATE(CLK_GOUT_USI0_SCLK, "gout_usi0_sclk" , "mout_peri_usi0_user" , |
536 | CLK_CON_GAT_GOUT_PERI_USI0_SCLK, 21, 0, 0), |
537 | GATE(CLK_GOUT_USI1_PCLK, "gout_usi1_pclk" , "mout_peri_bus_user" , |
538 | CLK_CON_GAT_GOUT_PERI_USI1_PCLK, 21, 0, 0), |
539 | GATE(CLK_GOUT_USI1_SCLK, "gout_usi1_sclk" , "mout_peri_usi1_user" , |
540 | CLK_CON_GAT_GOUT_PERI_USI1_SCLK, 21, 0, 0), |
541 | GATE(CLK_GOUT_USI2_PCLK, "gout_usi2_pclk" , "mout_peri_bus_user" , |
542 | CLK_CON_GAT_GOUT_PERI_USI2_PCLK, 21, 0, 0), |
543 | GATE(CLK_GOUT_USI2_SCLK, "gout_usi2_sclk" , "mout_peri_usi2_user" , |
544 | CLK_CON_GAT_GOUT_PERI_USI2_SCLK, 21, 0, 0), |
545 | GATE(CLK_GOUT_MCT_PCLK, "gout_mct_pclk" , "mout_peri_bus_user" , |
546 | CLK_CON_GAT_GOUT_PERI_MCT_PCLK, 21, 0, 0), |
547 | GATE(CLK_GOUT_SYSREG_PERI_PCLK, "gout_sysreg_peri_pclk" , |
548 | "mout_peri_bus_user" , |
549 | CLK_CON_GAT_GOUT_PERI_SYSREG_PERI_PCLK, 21, 0, 0), |
550 | GATE(CLK_GOUT_WDT0_PCLK, "gout_wdt0_pclk" , "mout_peri_bus_user" , |
551 | CLK_CON_GAT_GOUT_PERI_WDT_CLUSTER0_PCLK, 21, 0, 0), |
552 | GATE(CLK_GOUT_WDT1_PCLK, "gout_wdt1_pclk" , "mout_peri_bus_user" , |
553 | CLK_CON_GAT_GOUT_PERI_WDT_CLUSTER1_PCLK, 21, 0, 0), |
554 | }; |
555 | |
556 | static const struct samsung_cmu_info peri_cmu_info __initconst = { |
557 | .mux_clks = peri_mux_clks, |
558 | .nr_mux_clks = ARRAY_SIZE(peri_mux_clks), |
559 | .gate_clks = peri_gate_clks, |
560 | .nr_gate_clks = ARRAY_SIZE(peri_gate_clks), |
561 | .nr_clk_ids = CLKS_NR_PERI, |
562 | .clk_regs = peri_clk_regs, |
563 | .nr_clk_regs = ARRAY_SIZE(peri_clk_regs), |
564 | .clk_name = "dout_peri_bus" , |
565 | }; |
566 | |
567 | static void __init exynos7885_cmu_peri_init(struct device_node *np) |
568 | { |
569 | exynos_arm64_register_cmu(NULL, np, cmu: &peri_cmu_info); |
570 | } |
571 | |
572 | /* Register CMU_PERI early, as it's needed for MCT timer */ |
573 | CLK_OF_DECLARE(exynos7885_cmu_peri, "samsung,exynos7885-cmu-peri" , |
574 | exynos7885_cmu_peri_init); |
575 | |
576 | /* ---- CMU_CORE ------------------------------------------------------------ */ |
577 | |
578 | /* Register Offset definitions for CMU_CORE (0x12000000) */ |
579 | #define PLL_CON0_MUX_CLKCMU_CORE_BUS_USER 0x0100 |
580 | #define PLL_CON0_MUX_CLKCMU_CORE_CCI_USER 0x0120 |
581 | #define PLL_CON0_MUX_CLKCMU_CORE_G3D_USER 0x0140 |
582 | #define CLK_CON_MUX_MUX_CLK_CORE_GIC 0x1000 |
583 | #define CLK_CON_DIV_DIV_CLK_CORE_BUSP 0x1800 |
584 | #define CLK_CON_GAT_GOUT_CORE_CCI_550_ACLK 0x2054 |
585 | #define CLK_CON_GAT_GOUT_CORE_GIC400_CLK 0x2058 |
586 | #define CLK_CON_GAT_GOUT_CORE_TREX_D_CORE_ACLK 0x215c |
587 | #define CLK_CON_GAT_GOUT_CORE_TREX_D_CORE_GCLK 0x2160 |
588 | #define CLK_CON_GAT_GOUT_CORE_TREX_D_CORE_PCLK 0x2164 |
589 | #define CLK_CON_GAT_GOUT_CORE_TREX_P_CORE_ACLK_P_CORE 0x2168 |
590 | #define CLK_CON_GAT_GOUT_CORE_TREX_P_CORE_CCLK_P_CORE 0x216c |
591 | #define CLK_CON_GAT_GOUT_CORE_TREX_P_CORE_PCLK 0x2170 |
592 | #define CLK_CON_GAT_GOUT_CORE_TREX_P_CORE_PCLK_P_CORE 0x2174 |
593 | |
594 | static const unsigned long core_clk_regs[] __initconst = { |
595 | PLL_CON0_MUX_CLKCMU_CORE_BUS_USER, |
596 | PLL_CON0_MUX_CLKCMU_CORE_CCI_USER, |
597 | PLL_CON0_MUX_CLKCMU_CORE_G3D_USER, |
598 | CLK_CON_MUX_MUX_CLK_CORE_GIC, |
599 | CLK_CON_DIV_DIV_CLK_CORE_BUSP, |
600 | CLK_CON_GAT_GOUT_CORE_CCI_550_ACLK, |
601 | CLK_CON_GAT_GOUT_CORE_GIC400_CLK, |
602 | CLK_CON_GAT_GOUT_CORE_TREX_D_CORE_ACLK, |
603 | CLK_CON_GAT_GOUT_CORE_TREX_D_CORE_GCLK, |
604 | CLK_CON_GAT_GOUT_CORE_TREX_D_CORE_PCLK, |
605 | CLK_CON_GAT_GOUT_CORE_TREX_P_CORE_ACLK_P_CORE, |
606 | CLK_CON_GAT_GOUT_CORE_TREX_P_CORE_CCLK_P_CORE, |
607 | CLK_CON_GAT_GOUT_CORE_TREX_P_CORE_PCLK, |
608 | CLK_CON_GAT_GOUT_CORE_TREX_P_CORE_PCLK_P_CORE, |
609 | }; |
610 | |
611 | /* List of parent clocks for Muxes in CMU_CORE */ |
612 | PNAME(mout_core_bus_user_p) = { "oscclk" , "dout_core_bus" }; |
613 | PNAME(mout_core_cci_user_p) = { "oscclk" , "dout_core_cci" }; |
614 | PNAME(mout_core_g3d_user_p) = { "oscclk" , "dout_core_g3d" }; |
615 | PNAME(mout_core_gic_p) = { "dout_core_busp" , "oscclk" }; |
616 | |
617 | static const struct samsung_mux_clock core_mux_clks[] __initconst = { |
618 | MUX(CLK_MOUT_CORE_BUS_USER, "mout_core_bus_user" , mout_core_bus_user_p, |
619 | PLL_CON0_MUX_CLKCMU_CORE_BUS_USER, 4, 1), |
620 | MUX(CLK_MOUT_CORE_CCI_USER, "mout_core_cci_user" , mout_core_cci_user_p, |
621 | PLL_CON0_MUX_CLKCMU_CORE_CCI_USER, 4, 1), |
622 | MUX(CLK_MOUT_CORE_G3D_USER, "mout_core_g3d_user" , mout_core_g3d_user_p, |
623 | PLL_CON0_MUX_CLKCMU_CORE_G3D_USER, 4, 1), |
624 | MUX(CLK_MOUT_CORE_GIC, "mout_core_gic" , mout_core_gic_p, |
625 | CLK_CON_MUX_MUX_CLK_CORE_GIC, 0, 1), |
626 | }; |
627 | |
628 | static const struct samsung_div_clock core_div_clks[] __initconst = { |
629 | DIV(CLK_DOUT_CORE_BUSP, "dout_core_busp" , "mout_core_bus_user" , |
630 | CLK_CON_DIV_DIV_CLK_CORE_BUSP, 0, 2), |
631 | }; |
632 | |
633 | static const struct samsung_gate_clock core_gate_clks[] __initconst = { |
634 | /* CCI (interconnect) clock must be always running */ |
635 | GATE(CLK_GOUT_CCI_ACLK, "gout_cci_aclk" , "mout_core_cci_user" , |
636 | CLK_CON_GAT_GOUT_CORE_CCI_550_ACLK, 21, CLK_IS_CRITICAL, 0), |
637 | /* GIC (interrupt controller) clock must be always running */ |
638 | GATE(CLK_GOUT_GIC400_CLK, "gout_gic400_clk" , "mout_core_gic" , |
639 | CLK_CON_GAT_GOUT_CORE_GIC400_CLK, 21, CLK_IS_CRITICAL, 0), |
640 | /* |
641 | * TREX D and P Core (seems to be related to "bus traffic shaper") |
642 | * clocks must always be running |
643 | */ |
644 | GATE(CLK_GOUT_TREX_D_CORE_ACLK, "gout_trex_d_core_aclk" , "mout_core_bus_user" , |
645 | CLK_CON_GAT_GOUT_CORE_TREX_D_CORE_ACLK, 21, CLK_IS_CRITICAL, 0), |
646 | GATE(CLK_GOUT_TREX_D_CORE_GCLK, "gout_trex_d_core_gclk" , "mout_core_g3d_user" , |
647 | CLK_CON_GAT_GOUT_CORE_TREX_D_CORE_GCLK, 21, CLK_IS_CRITICAL, 0), |
648 | GATE(CLK_GOUT_TREX_D_CORE_PCLK, "gout_trex_d_core_pclk" , "dout_core_busp" , |
649 | CLK_CON_GAT_GOUT_CORE_TREX_D_CORE_PCLK, 21, CLK_IS_CRITICAL, 0), |
650 | GATE(CLK_GOUT_TREX_P_CORE_ACLK_P_CORE, "gout_trex_p_core_aclk_p_core" , |
651 | "mout_core_bus_user" , CLK_CON_GAT_GOUT_CORE_TREX_P_CORE_ACLK_P_CORE, 21, |
652 | CLK_IS_CRITICAL, 0), |
653 | GATE(CLK_GOUT_TREX_P_CORE_CCLK_P_CORE, "gout_trex_p_core_cclk_p_core" , |
654 | "mout_core_cci_user" , CLK_CON_GAT_GOUT_CORE_TREX_P_CORE_CCLK_P_CORE, 21, |
655 | CLK_IS_CRITICAL, 0), |
656 | GATE(CLK_GOUT_TREX_P_CORE_PCLK, "gout_trex_p_core_pclk" , "dout_core_busp" , |
657 | CLK_CON_GAT_GOUT_CORE_TREX_P_CORE_PCLK, 21, CLK_IS_CRITICAL, 0), |
658 | GATE(CLK_GOUT_TREX_P_CORE_PCLK_P_CORE, "gout_trex_p_core_pclk_p_core" , |
659 | "dout_core_busp" , CLK_CON_GAT_GOUT_CORE_TREX_P_CORE_PCLK_P_CORE, 21, |
660 | CLK_IS_CRITICAL, 0), |
661 | }; |
662 | |
663 | static const struct samsung_cmu_info core_cmu_info __initconst = { |
664 | .mux_clks = core_mux_clks, |
665 | .nr_mux_clks = ARRAY_SIZE(core_mux_clks), |
666 | .div_clks = core_div_clks, |
667 | .nr_div_clks = ARRAY_SIZE(core_div_clks), |
668 | .gate_clks = core_gate_clks, |
669 | .nr_gate_clks = ARRAY_SIZE(core_gate_clks), |
670 | .nr_clk_ids = CLKS_NR_CORE, |
671 | .clk_regs = core_clk_regs, |
672 | .nr_clk_regs = ARRAY_SIZE(core_clk_regs), |
673 | .clk_name = "dout_core_bus" , |
674 | }; |
675 | |
676 | /* ---- CMU_FSYS ------------------------------------------------------------ */ |
677 | |
678 | /* Register Offset definitions for CMU_FSYS (0x13400000) */ |
679 | #define PLL_CON0_MUX_CLKCMU_FSYS_BUS_USER 0x0100 |
680 | #define PLL_CON0_MUX_CLKCMU_FSYS_MMC_CARD_USER 0x0120 |
681 | #define PLL_CON0_MUX_CLKCMU_FSYS_MMC_EMBD_USER 0x0140 |
682 | #define PLL_CON0_MUX_CLKCMU_FSYS_MMC_SDIO_USER 0x0160 |
683 | #define PLL_CON0_MUX_CLKCMU_FSYS_USB30DRD_USER 0x0180 |
684 | #define CLK_CON_GAT_GOUT_FSYS_MMC_CARD_I_ACLK 0x2030 |
685 | #define CLK_CON_GAT_GOUT_FSYS_MMC_CARD_SDCLKIN 0x2034 |
686 | #define CLK_CON_GAT_GOUT_FSYS_MMC_EMBD_I_ACLK 0x2038 |
687 | #define CLK_CON_GAT_GOUT_FSYS_MMC_EMBD_SDCLKIN 0x203c |
688 | #define CLK_CON_GAT_GOUT_FSYS_MMC_SDIO_I_ACLK 0x2040 |
689 | #define CLK_CON_GAT_GOUT_FSYS_MMC_SDIO_SDCLKIN 0x2044 |
690 | |
691 | static const unsigned long fsys_clk_regs[] __initconst = { |
692 | PLL_CON0_MUX_CLKCMU_FSYS_BUS_USER, |
693 | PLL_CON0_MUX_CLKCMU_FSYS_MMC_CARD_USER, |
694 | PLL_CON0_MUX_CLKCMU_FSYS_MMC_EMBD_USER, |
695 | PLL_CON0_MUX_CLKCMU_FSYS_MMC_SDIO_USER, |
696 | PLL_CON0_MUX_CLKCMU_FSYS_USB30DRD_USER, |
697 | CLK_CON_GAT_GOUT_FSYS_MMC_CARD_I_ACLK, |
698 | CLK_CON_GAT_GOUT_FSYS_MMC_CARD_SDCLKIN, |
699 | CLK_CON_GAT_GOUT_FSYS_MMC_EMBD_I_ACLK, |
700 | CLK_CON_GAT_GOUT_FSYS_MMC_EMBD_SDCLKIN, |
701 | CLK_CON_GAT_GOUT_FSYS_MMC_SDIO_I_ACLK, |
702 | CLK_CON_GAT_GOUT_FSYS_MMC_SDIO_SDCLKIN, |
703 | }; |
704 | |
705 | /* List of parent clocks for Muxes in CMU_FSYS */ |
706 | PNAME(mout_fsys_bus_user_p) = { "oscclk" , "dout_fsys_bus" }; |
707 | PNAME(mout_fsys_mmc_card_user_p) = { "oscclk" , "dout_fsys_mmc_card" }; |
708 | PNAME(mout_fsys_mmc_embd_user_p) = { "oscclk" , "dout_fsys_mmc_embd" }; |
709 | PNAME(mout_fsys_mmc_sdio_user_p) = { "oscclk" , "dout_fsys_mmc_sdio" }; |
710 | PNAME(mout_fsys_usb30drd_user_p) = { "oscclk" , "dout_fsys_usb30drd" }; |
711 | |
712 | static const struct samsung_mux_clock fsys_mux_clks[] __initconst = { |
713 | MUX(CLK_MOUT_FSYS_BUS_USER, "mout_fsys_bus_user" , mout_fsys_bus_user_p, |
714 | PLL_CON0_MUX_CLKCMU_FSYS_BUS_USER, 4, 1), |
715 | MUX_F(CLK_MOUT_FSYS_MMC_CARD_USER, "mout_fsys_mmc_card_user" , |
716 | mout_fsys_mmc_card_user_p, PLL_CON0_MUX_CLKCMU_FSYS_MMC_CARD_USER, |
717 | 4, 1, CLK_SET_RATE_PARENT, 0), |
718 | MUX_F(CLK_MOUT_FSYS_MMC_EMBD_USER, "mout_fsys_mmc_embd_user" , |
719 | mout_fsys_mmc_embd_user_p, PLL_CON0_MUX_CLKCMU_FSYS_MMC_EMBD_USER, |
720 | 4, 1, CLK_SET_RATE_PARENT, 0), |
721 | MUX_F(CLK_MOUT_FSYS_MMC_SDIO_USER, "mout_fsys_mmc_sdio_user" , |
722 | mout_fsys_mmc_sdio_user_p, PLL_CON0_MUX_CLKCMU_FSYS_MMC_SDIO_USER, |
723 | 4, 1, CLK_SET_RATE_PARENT, 0), |
724 | MUX_F(CLK_MOUT_FSYS_USB30DRD_USER, "mout_fsys_usb30drd_user" , |
725 | mout_fsys_usb30drd_user_p, PLL_CON0_MUX_CLKCMU_FSYS_USB30DRD_USER, |
726 | 4, 1, CLK_SET_RATE_PARENT, 0), |
727 | }; |
728 | |
729 | static const struct samsung_gate_clock fsys_gate_clks[] __initconst = { |
730 | GATE(CLK_GOUT_MMC_CARD_ACLK, "gout_mmc_card_aclk" , "mout_fsys_bus_user" , |
731 | CLK_CON_GAT_GOUT_FSYS_MMC_CARD_I_ACLK, 21, 0, 0), |
732 | GATE(CLK_GOUT_MMC_CARD_SDCLKIN, "gout_mmc_card_sdclkin" , |
733 | "mout_fsys_mmc_card_user" , CLK_CON_GAT_GOUT_FSYS_MMC_CARD_SDCLKIN, |
734 | 21, CLK_SET_RATE_PARENT, 0), |
735 | GATE(CLK_GOUT_MMC_EMBD_ACLK, "gout_mmc_embd_aclk" , "mout_fsys_bus_user" , |
736 | CLK_CON_GAT_GOUT_FSYS_MMC_EMBD_I_ACLK, 21, 0, 0), |
737 | GATE(CLK_GOUT_MMC_EMBD_SDCLKIN, "gout_mmc_embd_sdclkin" , |
738 | "mout_fsys_mmc_embd_user" , CLK_CON_GAT_GOUT_FSYS_MMC_EMBD_SDCLKIN, |
739 | 21, CLK_SET_RATE_PARENT, 0), |
740 | GATE(CLK_GOUT_MMC_SDIO_ACLK, "gout_mmc_sdio_aclk" , "mout_fsys_bus_user" , |
741 | CLK_CON_GAT_GOUT_FSYS_MMC_SDIO_I_ACLK, 21, 0, 0), |
742 | GATE(CLK_GOUT_MMC_SDIO_SDCLKIN, "gout_mmc_sdio_sdclkin" , |
743 | "mout_fsys_mmc_sdio_user" , CLK_CON_GAT_GOUT_FSYS_MMC_SDIO_SDCLKIN, |
744 | 21, CLK_SET_RATE_PARENT, 0), |
745 | }; |
746 | |
747 | static const struct samsung_cmu_info fsys_cmu_info __initconst = { |
748 | .mux_clks = fsys_mux_clks, |
749 | .nr_mux_clks = ARRAY_SIZE(fsys_mux_clks), |
750 | .gate_clks = fsys_gate_clks, |
751 | .nr_gate_clks = ARRAY_SIZE(fsys_gate_clks), |
752 | .nr_clk_ids = CLKS_NR_FSYS, |
753 | .clk_regs = fsys_clk_regs, |
754 | .nr_clk_regs = ARRAY_SIZE(fsys_clk_regs), |
755 | .clk_name = "dout_fsys_bus" , |
756 | }; |
757 | |
758 | /* ---- platform_driver ----------------------------------------------------- */ |
759 | |
760 | static int __init exynos7885_cmu_probe(struct platform_device *pdev) |
761 | { |
762 | const struct samsung_cmu_info *info; |
763 | struct device *dev = &pdev->dev; |
764 | |
765 | info = of_device_get_match_data(dev); |
766 | exynos_arm64_register_cmu(dev, np: dev->of_node, cmu: info); |
767 | |
768 | return 0; |
769 | } |
770 | |
771 | static const struct of_device_id exynos7885_cmu_of_match[] = { |
772 | { |
773 | .compatible = "samsung,exynos7885-cmu-core" , |
774 | .data = &core_cmu_info, |
775 | }, { |
776 | .compatible = "samsung,exynos7885-cmu-fsys" , |
777 | .data = &fsys_cmu_info, |
778 | }, { |
779 | }, |
780 | }; |
781 | |
782 | static struct platform_driver exynos7885_cmu_driver __refdata = { |
783 | .driver = { |
784 | .name = "exynos7885-cmu" , |
785 | .of_match_table = exynos7885_cmu_of_match, |
786 | .suppress_bind_attrs = true, |
787 | }, |
788 | .probe = exynos7885_cmu_probe, |
789 | }; |
790 | |
791 | static int __init exynos7885_cmu_init(void) |
792 | { |
793 | return platform_driver_register(&exynos7885_cmu_driver); |
794 | } |
795 | core_initcall(exynos7885_cmu_init); |
796 | |