| 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
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| 2 | /* |
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| 3 | * Copyright 2014 Freescale Semiconductor, Inc. |
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| 4 | */ |
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| 5 | |
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| 6 | #ifndef __DT_BINDINGS_CLOCK_IMX6QDL_H |
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| 7 | #define __DT_BINDINGS_CLOCK_IMX6QDL_H |
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| 8 | |
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| 9 | #define IMX6QDL_CLK_DUMMY 0 |
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| 10 | #define IMX6QDL_CLK_CKIL 1 |
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| 11 | #define IMX6QDL_CLK_CKIH 2 |
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| 12 | #define IMX6QDL_CLK_OSC 3 |
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| 13 | #define IMX6QDL_CLK_PLL2_PFD0_352M 4 |
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| 14 | #define IMX6QDL_CLK_PLL2_PFD1_594M 5 |
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| 15 | #define IMX6QDL_CLK_PLL2_PFD2_396M 6 |
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| 16 | #define IMX6QDL_CLK_PLL3_PFD0_720M 7 |
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| 17 | #define IMX6QDL_CLK_PLL3_PFD1_540M 8 |
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| 18 | #define IMX6QDL_CLK_PLL3_PFD2_508M 9 |
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| 19 | #define IMX6QDL_CLK_PLL3_PFD3_454M 10 |
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| 20 | #define IMX6QDL_CLK_PLL2_198M 11 |
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| 21 | #define IMX6QDL_CLK_PLL3_120M 12 |
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| 22 | #define IMX6QDL_CLK_PLL3_80M 13 |
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| 23 | #define IMX6QDL_CLK_PLL3_60M 14 |
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| 24 | #define IMX6QDL_CLK_TWD 15 |
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| 25 | #define IMX6QDL_CLK_STEP 16 |
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| 26 | #define IMX6QDL_CLK_PLL1_SW 17 |
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| 27 | #define IMX6QDL_CLK_PERIPH_PRE 18 |
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| 28 | #define IMX6QDL_CLK_PERIPH2_PRE 19 |
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| 29 | #define IMX6QDL_CLK_PERIPH_CLK2_SEL 20 |
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| 30 | #define IMX6QDL_CLK_PERIPH2_CLK2_SEL 21 |
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| 31 | #define IMX6QDL_CLK_AXI_SEL 22 |
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| 32 | #define IMX6QDL_CLK_ESAI_SEL 23 |
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| 33 | #define IMX6QDL_CLK_ASRC_SEL 24 |
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| 34 | #define IMX6QDL_CLK_SPDIF_SEL 25 |
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| 35 | #define IMX6QDL_CLK_GPU2D_AXI 26 |
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| 36 | #define IMX6QDL_CLK_GPU3D_AXI 27 |
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| 37 | #define IMX6QDL_CLK_GPU2D_CORE_SEL 28 |
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| 38 | #define IMX6QDL_CLK_GPU3D_CORE_SEL 29 |
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| 39 | #define IMX6QDL_CLK_GPU3D_SHADER_SEL 30 |
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| 40 | #define IMX6QDL_CLK_IPU1_SEL 31 |
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| 41 | #define IMX6QDL_CLK_IPU2_SEL 32 |
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| 42 | #define IMX6QDL_CLK_LDB_DI0_SEL 33 |
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| 43 | #define IMX6QDL_CLK_LDB_DI1_SEL 34 |
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| 44 | #define IMX6QDL_CLK_IPU1_DI0_PRE_SEL 35 |
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| 45 | #define IMX6QDL_CLK_IPU1_DI1_PRE_SEL 36 |
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| 46 | #define IMX6QDL_CLK_IPU2_DI0_PRE_SEL 37 |
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| 47 | #define IMX6QDL_CLK_IPU2_DI1_PRE_SEL 38 |
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| 48 | #define IMX6QDL_CLK_IPU1_DI0_SEL 39 |
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| 49 | #define IMX6QDL_CLK_IPU1_DI1_SEL 40 |
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| 50 | #define IMX6QDL_CLK_IPU2_DI0_SEL 41 |
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| 51 | #define IMX6QDL_CLK_IPU2_DI1_SEL 42 |
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| 52 | #define IMX6QDL_CLK_HSI_TX_SEL 43 |
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| 53 | #define IMX6QDL_CLK_PCIE_AXI_SEL 44 |
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| 54 | #define IMX6QDL_CLK_SSI1_SEL 45 |
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| 55 | #define IMX6QDL_CLK_SSI2_SEL 46 |
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| 56 | #define IMX6QDL_CLK_SSI3_SEL 47 |
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| 57 | #define IMX6QDL_CLK_USDHC1_SEL 48 |
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| 58 | #define IMX6QDL_CLK_USDHC2_SEL 49 |
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| 59 | #define IMX6QDL_CLK_USDHC3_SEL 50 |
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| 60 | #define IMX6QDL_CLK_USDHC4_SEL 51 |
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| 61 | #define IMX6QDL_CLK_ENFC_SEL 52 |
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| 62 | #define IMX6QDL_CLK_EIM_SEL 53 |
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| 63 | #define IMX6QDL_CLK_EIM_SLOW_SEL 54 |
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| 64 | #define IMX6QDL_CLK_VDO_AXI_SEL 55 |
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| 65 | #define IMX6QDL_CLK_VPU_AXI_SEL 56 |
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| 66 | #define IMX6QDL_CLK_CKO1_SEL 57 |
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| 67 | #define IMX6QDL_CLK_PERIPH 58 |
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| 68 | #define IMX6QDL_CLK_PERIPH2 59 |
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| 69 | #define IMX6QDL_CLK_PERIPH_CLK2 60 |
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| 70 | #define IMX6QDL_CLK_PERIPH2_CLK2 61 |
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| 71 | #define IMX6QDL_CLK_IPG 62 |
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| 72 | #define IMX6QDL_CLK_IPG_PER 63 |
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| 73 | #define IMX6QDL_CLK_ESAI_PRED 64 |
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| 74 | #define IMX6QDL_CLK_ESAI_PODF 65 |
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| 75 | #define IMX6QDL_CLK_ASRC_PRED 66 |
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| 76 | #define IMX6QDL_CLK_ASRC_PODF 67 |
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| 77 | #define IMX6QDL_CLK_SPDIF_PRED 68 |
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| 78 | #define IMX6QDL_CLK_SPDIF_PODF 69 |
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| 79 | #define IMX6QDL_CLK_CAN_ROOT 70 |
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| 80 | #define IMX6QDL_CLK_ECSPI_ROOT 71 |
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| 81 | #define IMX6QDL_CLK_GPU2D_CORE_PODF 72 |
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| 82 | #define IMX6QDL_CLK_GPU3D_CORE_PODF 73 |
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| 83 | #define IMX6QDL_CLK_GPU3D_SHADER 74 |
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| 84 | #define IMX6QDL_CLK_IPU1_PODF 75 |
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| 85 | #define IMX6QDL_CLK_IPU2_PODF 76 |
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| 86 | #define IMX6QDL_CLK_LDB_DI0_PODF 77 |
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| 87 | #define IMX6QDL_CLK_LDB_DI1_PODF 78 |
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| 88 | #define IMX6QDL_CLK_IPU1_DI0_PRE 79 |
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| 89 | #define IMX6QDL_CLK_IPU1_DI1_PRE 80 |
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| 90 | #define IMX6QDL_CLK_IPU2_DI0_PRE 81 |
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| 91 | #define IMX6QDL_CLK_IPU2_DI1_PRE 82 |
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| 92 | #define IMX6QDL_CLK_HSI_TX_PODF 83 |
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| 93 | #define IMX6QDL_CLK_SSI1_PRED 84 |
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| 94 | #define IMX6QDL_CLK_SSI1_PODF 85 |
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| 95 | #define IMX6QDL_CLK_SSI2_PRED 86 |
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| 96 | #define IMX6QDL_CLK_SSI2_PODF 87 |
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| 97 | #define IMX6QDL_CLK_SSI3_PRED 88 |
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| 98 | #define IMX6QDL_CLK_SSI3_PODF 89 |
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| 99 | #define IMX6QDL_CLK_UART_SERIAL_PODF 90 |
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| 100 | #define IMX6QDL_CLK_USDHC1_PODF 91 |
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| 101 | #define IMX6QDL_CLK_USDHC2_PODF 92 |
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| 102 | #define IMX6QDL_CLK_USDHC3_PODF 93 |
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| 103 | #define IMX6QDL_CLK_USDHC4_PODF 94 |
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| 104 | #define IMX6QDL_CLK_ENFC_PRED 95 |
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| 105 | #define IMX6QDL_CLK_ENFC_PODF 96 |
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| 106 | #define IMX6QDL_CLK_EIM_PODF 97 |
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| 107 | #define IMX6QDL_CLK_EIM_SLOW_PODF 98 |
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| 108 | #define IMX6QDL_CLK_VPU_AXI_PODF 99 |
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| 109 | #define IMX6QDL_CLK_CKO1_PODF 100 |
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| 110 | #define IMX6QDL_CLK_AXI 101 |
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| 111 | #define IMX6QDL_CLK_MMDC_CH0_AXI_PODF 102 |
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| 112 | #define IMX6QDL_CLK_MMDC_CH1_AXI_PODF 103 |
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| 113 | #define IMX6QDL_CLK_ARM 104 |
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| 114 | #define IMX6QDL_CLK_AHB 105 |
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| 115 | #define IMX6QDL_CLK_APBH_DMA 106 |
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| 116 | #define IMX6QDL_CLK_ASRC 107 |
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| 117 | #define IMX6QDL_CLK_CAN1_IPG 108 |
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| 118 | #define IMX6QDL_CLK_CAN1_SERIAL 109 |
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| 119 | #define IMX6QDL_CLK_CAN2_IPG 110 |
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| 120 | #define IMX6QDL_CLK_CAN2_SERIAL 111 |
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| 121 | #define IMX6QDL_CLK_ECSPI1 112 |
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| 122 | #define IMX6QDL_CLK_ECSPI2 113 |
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| 123 | #define IMX6QDL_CLK_ECSPI3 114 |
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| 124 | #define IMX6QDL_CLK_ECSPI4 115 |
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| 125 | #define IMX6Q_CLK_ECSPI5 116 |
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| 126 | #define IMX6DL_CLK_I2C4 116 |
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| 127 | #define IMX6QDL_CLK_ENET 117 |
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| 128 | #define IMX6QDL_CLK_ESAI_EXTAL 118 |
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| 129 | #define IMX6QDL_CLK_GPT_IPG 119 |
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| 130 | #define IMX6QDL_CLK_GPT_IPG_PER 120 |
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| 131 | #define IMX6QDL_CLK_GPU2D_CORE 121 |
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| 132 | #define IMX6QDL_CLK_GPU3D_CORE 122 |
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| 133 | #define IMX6QDL_CLK_HDMI_IAHB 123 |
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| 134 | #define IMX6QDL_CLK_HDMI_ISFR 124 |
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| 135 | #define IMX6QDL_CLK_I2C1 125 |
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| 136 | #define IMX6QDL_CLK_I2C2 126 |
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| 137 | #define IMX6QDL_CLK_I2C3 127 |
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| 138 | #define IMX6QDL_CLK_IIM 128 |
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| 139 | #define IMX6QDL_CLK_ENFC 129 |
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| 140 | #define IMX6QDL_CLK_IPU1 130 |
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| 141 | #define IMX6QDL_CLK_IPU1_DI0 131 |
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| 142 | #define IMX6QDL_CLK_IPU1_DI1 132 |
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| 143 | #define IMX6QDL_CLK_IPU2 133 |
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| 144 | #define IMX6QDL_CLK_IPU2_DI0 134 |
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| 145 | #define IMX6QDL_CLK_LDB_DI0 135 |
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| 146 | #define IMX6QDL_CLK_LDB_DI1 136 |
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| 147 | #define IMX6QDL_CLK_IPU2_DI1 137 |
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| 148 | #define IMX6QDL_CLK_HSI_TX 138 |
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| 149 | #define IMX6QDL_CLK_MLB 139 |
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| 150 | #define IMX6QDL_CLK_MMDC_CH0_AXI 140 |
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| 151 | #define IMX6QDL_CLK_MMDC_CH1_AXI 141 |
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| 152 | #define IMX6QDL_CLK_OCRAM 142 |
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| 153 | #define IMX6QDL_CLK_OPENVG_AXI 143 |
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| 154 | #define IMX6QDL_CLK_PCIE_AXI 144 |
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| 155 | #define IMX6QDL_CLK_PWM1 145 |
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| 156 | #define IMX6QDL_CLK_PWM2 146 |
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| 157 | #define IMX6QDL_CLK_PWM3 147 |
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| 158 | #define IMX6QDL_CLK_PWM4 148 |
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| 159 | #define IMX6QDL_CLK_PER1_BCH 149 |
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| 160 | #define IMX6QDL_CLK_GPMI_BCH_APB 150 |
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| 161 | #define IMX6QDL_CLK_GPMI_BCH 151 |
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| 162 | #define IMX6QDL_CLK_GPMI_IO 152 |
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| 163 | #define IMX6QDL_CLK_GPMI_APB 153 |
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| 164 | #define IMX6QDL_CLK_SATA 154 |
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| 165 | #define IMX6QDL_CLK_SDMA 155 |
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| 166 | #define IMX6QDL_CLK_SPBA 156 |
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| 167 | #define IMX6QDL_CLK_SSI1 157 |
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| 168 | #define IMX6QDL_CLK_SSI2 158 |
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| 169 | #define IMX6QDL_CLK_SSI3 159 |
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| 170 | #define IMX6QDL_CLK_UART_IPG 160 |
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| 171 | #define IMX6QDL_CLK_UART_SERIAL 161 |
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| 172 | #define IMX6QDL_CLK_USBOH3 162 |
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| 173 | #define IMX6QDL_CLK_USDHC1 163 |
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| 174 | #define IMX6QDL_CLK_USDHC2 164 |
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| 175 | #define IMX6QDL_CLK_USDHC3 165 |
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| 176 | #define IMX6QDL_CLK_USDHC4 166 |
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| 177 | #define IMX6QDL_CLK_VDO_AXI 167 |
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| 178 | #define IMX6QDL_CLK_VPU_AXI 168 |
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| 179 | #define IMX6QDL_CLK_CKO1 169 |
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| 180 | #define IMX6QDL_CLK_PLL1_SYS 170 |
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| 181 | #define IMX6QDL_CLK_PLL2_BUS 171 |
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| 182 | #define IMX6QDL_CLK_PLL3_USB_OTG 172 |
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| 183 | #define IMX6QDL_CLK_PLL4_AUDIO 173 |
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| 184 | #define IMX6QDL_CLK_PLL5_VIDEO 174 |
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| 185 | #define IMX6QDL_CLK_PLL8_MLB 175 |
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| 186 | #define IMX6QDL_CLK_PLL7_USB_HOST 176 |
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| 187 | #define IMX6QDL_CLK_PLL6_ENET 177 |
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| 188 | #define IMX6QDL_CLK_SSI1_IPG 178 |
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| 189 | #define IMX6QDL_CLK_SSI2_IPG 179 |
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| 190 | #define IMX6QDL_CLK_SSI3_IPG 180 |
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| 191 | #define IMX6QDL_CLK_ROM 181 |
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| 192 | #define IMX6QDL_CLK_USBPHY1 182 |
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| 193 | #define IMX6QDL_CLK_USBPHY2 183 |
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| 194 | #define IMX6QDL_CLK_LDB_DI0_DIV_3_5 184 |
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| 195 | #define IMX6QDL_CLK_LDB_DI1_DIV_3_5 185 |
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| 196 | #define IMX6QDL_CLK_SATA_REF 186 |
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| 197 | #define IMX6QDL_CLK_SATA_REF_100M 187 |
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| 198 | #define IMX6QDL_CLK_PCIE_REF 188 |
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| 199 | #define IMX6QDL_CLK_PCIE_REF_125M 189 |
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| 200 | #define IMX6QDL_CLK_ENET_REF 190 |
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| 201 | #define IMX6QDL_CLK_USBPHY1_GATE 191 |
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| 202 | #define IMX6QDL_CLK_USBPHY2_GATE 192 |
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| 203 | #define IMX6QDL_CLK_PLL4_POST_DIV 193 |
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| 204 | #define IMX6QDL_CLK_PLL5_POST_DIV 194 |
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| 205 | #define IMX6QDL_CLK_PLL5_VIDEO_DIV 195 |
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| 206 | #define IMX6QDL_CLK_EIM_SLOW 196 |
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| 207 | #define IMX6QDL_CLK_SPDIF 197 |
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| 208 | #define IMX6QDL_CLK_CKO2_SEL 198 |
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| 209 | #define IMX6QDL_CLK_CKO2_PODF 199 |
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| 210 | #define IMX6QDL_CLK_CKO2 200 |
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| 211 | #define IMX6QDL_CLK_CKO 201 |
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| 212 | #define IMX6QDL_CLK_VDOA 202 |
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| 213 | #define IMX6QDL_CLK_PLL4_AUDIO_DIV 203 |
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| 214 | #define IMX6QDL_CLK_LVDS1_SEL 204 |
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| 215 | #define IMX6QDL_CLK_LVDS2_SEL 205 |
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| 216 | #define IMX6QDL_CLK_LVDS1_GATE 206 |
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| 217 | #define IMX6QDL_CLK_LVDS2_GATE 207 |
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| 218 | #define IMX6QDL_CLK_ESAI_IPG 208 |
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| 219 | #define IMX6QDL_CLK_ESAI_MEM 209 |
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| 220 | #define IMX6QDL_CLK_ASRC_IPG 210 |
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| 221 | #define IMX6QDL_CLK_ASRC_MEM 211 |
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| 222 | #define IMX6QDL_CLK_LVDS1_IN 212 |
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| 223 | #define IMX6QDL_CLK_LVDS2_IN 213 |
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| 224 | #define IMX6QDL_CLK_ANACLK1 214 |
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| 225 | #define IMX6QDL_CLK_ANACLK2 215 |
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| 226 | #define IMX6QDL_PLL1_BYPASS_SRC 216 |
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| 227 | #define IMX6QDL_PLL2_BYPASS_SRC 217 |
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| 228 | #define IMX6QDL_PLL3_BYPASS_SRC 218 |
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| 229 | #define IMX6QDL_PLL4_BYPASS_SRC 219 |
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| 230 | #define IMX6QDL_PLL5_BYPASS_SRC 220 |
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| 231 | #define IMX6QDL_PLL6_BYPASS_SRC 221 |
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| 232 | #define IMX6QDL_PLL7_BYPASS_SRC 222 |
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| 233 | #define IMX6QDL_CLK_PLL1 223 |
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| 234 | #define IMX6QDL_CLK_PLL2 224 |
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| 235 | #define IMX6QDL_CLK_PLL3 225 |
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| 236 | #define IMX6QDL_CLK_PLL4 226 |
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| 237 | #define IMX6QDL_CLK_PLL5 227 |
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| 238 | #define IMX6QDL_CLK_PLL6 228 |
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| 239 | #define IMX6QDL_CLK_PLL7 229 |
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| 240 | #define IMX6QDL_PLL1_BYPASS 230 |
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| 241 | #define IMX6QDL_PLL2_BYPASS 231 |
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| 242 | #define IMX6QDL_PLL3_BYPASS 232 |
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| 243 | #define IMX6QDL_PLL4_BYPASS 233 |
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| 244 | #define IMX6QDL_PLL5_BYPASS 234 |
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| 245 | #define IMX6QDL_PLL6_BYPASS 235 |
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| 246 | #define IMX6QDL_PLL7_BYPASS 236 |
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| 247 | #define IMX6QDL_CLK_GPT_3M 237 |
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| 248 | #define IMX6QDL_CLK_VIDEO_27M 238 |
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| 249 | #define IMX6QDL_CLK_MIPI_CORE_CFG 239 |
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| 250 | #define IMX6QDL_CLK_MIPI_IPG 240 |
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| 251 | #define IMX6QDL_CLK_CAAM_MEM 241 |
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| 252 | #define IMX6QDL_CLK_CAAM_ACLK 242 |
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| 253 | #define IMX6QDL_CLK_CAAM_IPG 243 |
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| 254 | #define IMX6QDL_CLK_SPDIF_GCLK 244 |
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| 255 | #define IMX6QDL_CLK_UART_SEL 245 |
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| 256 | #define IMX6QDL_CLK_IPG_PER_SEL 246 |
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| 257 | #define IMX6QDL_CLK_ECSPI_SEL 247 |
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| 258 | #define IMX6QDL_CLK_CAN_SEL 248 |
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| 259 | #define IMX6QDL_CLK_MMDC_CH1_AXI_CG 249 |
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| 260 | #define IMX6QDL_CLK_PRE0 250 |
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| 261 | #define IMX6QDL_CLK_PRE1 251 |
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| 262 | #define IMX6QDL_CLK_PRE2 252 |
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| 263 | #define IMX6QDL_CLK_PRE3 253 |
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| 264 | #define IMX6QDL_CLK_PRG0_AXI 254 |
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| 265 | #define IMX6QDL_CLK_PRG1_AXI 255 |
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| 266 | #define IMX6QDL_CLK_PRG0_APB 256 |
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| 267 | #define IMX6QDL_CLK_PRG1_APB 257 |
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| 268 | #define IMX6QDL_CLK_PRE_AXI 258 |
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| 269 | #define IMX6QDL_CLK_MLB_SEL 259 |
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| 270 | #define IMX6QDL_CLK_MLB_PODF 260 |
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| 271 | #define IMX6QDL_CLK_EPIT1 261 |
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| 272 | #define IMX6QDL_CLK_EPIT2 262 |
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| 273 | #define IMX6QDL_CLK_MMDC_P0_IPG 263 |
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| 274 | #define IMX6QDL_CLK_DCIC1 264 |
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| 275 | #define IMX6QDL_CLK_DCIC2 265 |
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| 276 | #define IMX6QDL_CLK_ENET_REF_SEL 266 |
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| 277 | #define IMX6QDL_CLK_ENET_REF_PAD 267 |
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| 278 | #define IMX6QDL_CLK_END 268 |
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| 279 | |
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| 280 | #endif /* __DT_BINDINGS_CLOCK_IMX6QDL_H */ |
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| 281 | |
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