1/* SPDX-License-Identifier: GPL-2.0-only */
2/*
3 * Copyright (c) 2013, The Linux Foundation. All rights reserved.
4 */
5
6#ifndef _DT_BINDINGS_CLK_MSM_GCC_8660_H
7#define _DT_BINDINGS_CLK_MSM_GCC_8660_H
8
9#define AFAB_CLK_SRC 0
10#define AFAB_CORE_CLK 1
11#define SCSS_A_CLK 2
12#define SCSS_H_CLK 3
13#define SCSS_XO_SRC_CLK 4
14#define AFAB_EBI1_CH0_A_CLK 5
15#define AFAB_EBI1_CH1_A_CLK 6
16#define AFAB_AXI_S0_FCLK 7
17#define AFAB_AXI_S1_FCLK 8
18#define AFAB_AXI_S2_FCLK 9
19#define AFAB_AXI_S3_FCLK 10
20#define AFAB_AXI_S4_FCLK 11
21#define SFAB_CORE_CLK 12
22#define SFAB_AXI_S0_FCLK 13
23#define SFAB_AXI_S1_FCLK 14
24#define SFAB_AXI_S2_FCLK 15
25#define SFAB_AXI_S3_FCLK 16
26#define SFAB_AXI_S4_FCLK 17
27#define SFAB_AHB_S0_FCLK 18
28#define SFAB_AHB_S1_FCLK 19
29#define SFAB_AHB_S2_FCLK 20
30#define SFAB_AHB_S3_FCLK 21
31#define SFAB_AHB_S4_FCLK 22
32#define SFAB_AHB_S5_FCLK 23
33#define SFAB_AHB_S6_FCLK 24
34#define SFAB_ADM0_M0_A_CLK 25
35#define SFAB_ADM0_M1_A_CLK 26
36#define SFAB_ADM0_M2_A_CLK 27
37#define ADM0_CLK 28
38#define ADM0_PBUS_CLK 29
39#define SFAB_ADM1_M0_A_CLK 30
40#define SFAB_ADM1_M1_A_CLK 31
41#define SFAB_ADM1_M2_A_CLK 32
42#define MMFAB_ADM1_M3_A_CLK 33
43#define ADM1_CLK 34
44#define ADM1_PBUS_CLK 35
45#define IMEM0_A_CLK 36
46#define MAHB0_CLK 37
47#define SFAB_LPASS_Q6_A_CLK 38
48#define SFAB_AFAB_M_A_CLK 39
49#define AFAB_SFAB_M0_A_CLK 40
50#define AFAB_SFAB_M1_A_CLK 41
51#define DFAB_CLK_SRC 42
52#define DFAB_CLK 43
53#define DFAB_CORE_CLK 44
54#define SFAB_DFAB_M_A_CLK 45
55#define DFAB_SFAB_M_A_CLK 46
56#define DFAB_SWAY0_H_CLK 47
57#define DFAB_SWAY1_H_CLK 48
58#define DFAB_ARB0_H_CLK 49
59#define DFAB_ARB1_H_CLK 50
60#define PPSS_H_CLK 51
61#define PPSS_PROC_CLK 52
62#define PPSS_TIMER0_CLK 53
63#define PPSS_TIMER1_CLK 54
64#define PMEM_A_CLK 55
65#define DMA_BAM_H_CLK 56
66#define SIC_H_CLK 57
67#define SPS_TIC_H_CLK 58
68#define SLIMBUS_H_CLK 59
69#define SLIMBUS_XO_SRC_CLK 60
70#define CFPB_2X_CLK_SRC 61
71#define CFPB_CLK 62
72#define CFPB0_H_CLK 63
73#define CFPB1_H_CLK 64
74#define CFPB2_H_CLK 65
75#define EBI2_2X_CLK 66
76#define EBI2_CLK 67
77#define SFAB_CFPB_M_H_CLK 68
78#define CFPB_MASTER_H_CLK 69
79#define SFAB_CFPB_S_HCLK 70
80#define CFPB_SPLITTER_H_CLK 71
81#define TSIF_H_CLK 72
82#define TSIF_INACTIVITY_TIMERS_CLK 73
83#define TSIF_REF_SRC 74
84#define TSIF_REF_CLK 75
85#define CE1_H_CLK 76
86#define CE2_H_CLK 77
87#define SFPB_H_CLK_SRC 78
88#define SFPB_H_CLK 79
89#define SFAB_SFPB_M_H_CLK 80
90#define SFAB_SFPB_S_H_CLK 81
91#define RPM_PROC_CLK 82
92#define RPM_BUS_H_CLK 83
93#define RPM_SLEEP_CLK 84
94#define RPM_TIMER_CLK 85
95#define MODEM_AHB1_H_CLK 86
96#define MODEM_AHB2_H_CLK 87
97#define RPM_MSG_RAM_H_CLK 88
98#define SC_H_CLK 89
99#define SC_A_CLK 90
100#define PMIC_ARB0_H_CLK 91
101#define PMIC_ARB1_H_CLK 92
102#define PMIC_SSBI2_SRC 93
103#define PMIC_SSBI2_CLK 94
104#define SDC1_H_CLK 95
105#define SDC2_H_CLK 96
106#define SDC3_H_CLK 97
107#define SDC4_H_CLK 98
108#define SDC5_H_CLK 99
109#define SDC1_SRC 100
110#define SDC2_SRC 101
111#define SDC3_SRC 102
112#define SDC4_SRC 103
113#define SDC5_SRC 104
114#define SDC1_CLK 105
115#define SDC2_CLK 106
116#define SDC3_CLK 107
117#define SDC4_CLK 108
118#define SDC5_CLK 109
119#define USB_HS1_H_CLK 110
120#define USB_HS1_XCVR_SRC 111
121#define USB_HS1_XCVR_CLK 112
122#define USB_HS2_H_CLK 113
123#define USB_HS2_XCVR_SRC 114
124#define USB_HS2_XCVR_CLK 115
125#define USB_FS1_H_CLK 116
126#define USB_FS1_XCVR_FS_SRC 117
127#define USB_FS1_XCVR_FS_CLK 118
128#define USB_FS1_SYSTEM_CLK 119
129#define USB_FS2_H_CLK 120
130#define USB_FS2_XCVR_FS_SRC 121
131#define USB_FS2_XCVR_FS_CLK 122
132#define USB_FS2_SYSTEM_CLK 123
133#define GSBI_COMMON_SIM_SRC 124
134#define GSBI1_H_CLK 125
135#define GSBI2_H_CLK 126
136#define GSBI3_H_CLK 127
137#define GSBI4_H_CLK 128
138#define GSBI5_H_CLK 129
139#define GSBI6_H_CLK 130
140#define GSBI7_H_CLK 131
141#define GSBI8_H_CLK 132
142#define GSBI9_H_CLK 133
143#define GSBI10_H_CLK 134
144#define GSBI11_H_CLK 135
145#define GSBI12_H_CLK 136
146#define GSBI1_UART_SRC 137
147#define GSBI1_UART_CLK 138
148#define GSBI2_UART_SRC 139
149#define GSBI2_UART_CLK 140
150#define GSBI3_UART_SRC 141
151#define GSBI3_UART_CLK 142
152#define GSBI4_UART_SRC 143
153#define GSBI4_UART_CLK 144
154#define GSBI5_UART_SRC 145
155#define GSBI5_UART_CLK 146
156#define GSBI6_UART_SRC 147
157#define GSBI6_UART_CLK 148
158#define GSBI7_UART_SRC 149
159#define GSBI7_UART_CLK 150
160#define GSBI8_UART_SRC 151
161#define GSBI8_UART_CLK 152
162#define GSBI9_UART_SRC 153
163#define GSBI9_UART_CLK 154
164#define GSBI10_UART_SRC 155
165#define GSBI10_UART_CLK 156
166#define GSBI11_UART_SRC 157
167#define GSBI11_UART_CLK 158
168#define GSBI12_UART_SRC 159
169#define GSBI12_UART_CLK 160
170#define GSBI1_QUP_SRC 161
171#define GSBI1_QUP_CLK 162
172#define GSBI2_QUP_SRC 163
173#define GSBI2_QUP_CLK 164
174#define GSBI3_QUP_SRC 165
175#define GSBI3_QUP_CLK 166
176#define GSBI4_QUP_SRC 167
177#define GSBI4_QUP_CLK 168
178#define GSBI5_QUP_SRC 169
179#define GSBI5_QUP_CLK 170
180#define GSBI6_QUP_SRC 171
181#define GSBI6_QUP_CLK 172
182#define GSBI7_QUP_SRC 173
183#define GSBI7_QUP_CLK 174
184#define GSBI8_QUP_SRC 175
185#define GSBI8_QUP_CLK 176
186#define GSBI9_QUP_SRC 177
187#define GSBI9_QUP_CLK 178
188#define GSBI10_QUP_SRC 179
189#define GSBI10_QUP_CLK 180
190#define GSBI11_QUP_SRC 181
191#define GSBI11_QUP_CLK 182
192#define GSBI12_QUP_SRC 183
193#define GSBI12_QUP_CLK 184
194#define GSBI1_SIM_CLK 185
195#define GSBI2_SIM_CLK 186
196#define GSBI3_SIM_CLK 187
197#define GSBI4_SIM_CLK 188
198#define GSBI5_SIM_CLK 189
199#define GSBI6_SIM_CLK 190
200#define GSBI7_SIM_CLK 191
201#define GSBI8_SIM_CLK 192
202#define GSBI9_SIM_CLK 193
203#define GSBI10_SIM_CLK 194
204#define GSBI11_SIM_CLK 195
205#define GSBI12_SIM_CLK 196
206#define SPDM_CFG_H_CLK 197
207#define SPDM_MSTR_H_CLK 198
208#define SPDM_FF_CLK_SRC 199
209#define SPDM_FF_CLK 200
210#define SEC_CTRL_CLK 201
211#define SEC_CTRL_ACC_CLK_SRC 202
212#define SEC_CTRL_ACC_CLK 203
213#define TLMM_H_CLK 204
214#define TLMM_CLK 205
215#define MARM_CLK_SRC 206
216#define MARM_CLK 207
217#define MAHB1_SRC 208
218#define MAHB1_CLK 209
219#define SFAB_MSS_S_H_CLK 210
220#define MAHB2_SRC 211
221#define MAHB2_CLK 212
222#define MSS_MODEM_CLK_SRC 213
223#define MSS_MODEM_CXO_CLK 214
224#define MSS_SLP_CLK 215
225#define MSS_SYS_REF_CLK 216
226#define TSSC_CLK_SRC 217
227#define TSSC_CLK 218
228#define PDM_SRC 219
229#define PDM_CLK 220
230#define GP0_SRC 221
231#define GP0_CLK 222
232#define GP1_SRC 223
233#define GP1_CLK 224
234#define GP2_SRC 225
235#define GP2_CLK 226
236#define PMEM_CLK 227
237#define MPM_CLK 228
238#define EBI1_ASFAB_SRC 229
239#define EBI1_CLK_SRC 230
240#define EBI1_CH0_CLK 231
241#define EBI1_CH1_CLK 232
242#define SFAB_SMPSS_S_H_CLK 233
243#define PRNG_SRC 234
244#define PRNG_CLK 235
245#define PXO_SRC 236
246#define LPASS_CXO_CLK 237
247#define LPASS_PXO_CLK 238
248#define SPDM_CY_PORT0_CLK 239
249#define SPDM_CY_PORT1_CLK 240
250#define SPDM_CY_PORT2_CLK 241
251#define SPDM_CY_PORT3_CLK 242
252#define SPDM_CY_PORT4_CLK 243
253#define SPDM_CY_PORT5_CLK 244
254#define SPDM_CY_PORT6_CLK 245
255#define SPDM_CY_PORT7_CLK 246
256#define PLL0 247
257#define PLL0_VOTE 248
258#define PLL5 249
259#define PLL6 250
260#define PLL6_VOTE 251
261#define PLL8 252
262#define PLL8_VOTE 253
263#define PLL9 254
264#define PLL10 255
265#define PLL11 256
266#define PLL12 257
267
268#endif
269

source code of linux/include/dt-bindings/clock/qcom,gcc-msm8660.h