1/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */
2/*
3 * Copyright (c) 2022 MediaTek Inc.
4 * Author: Sam Shih <sam.shih@mediatek.com>
5 */
6
7#ifndef _DT_BINDINGS_RESET_CONTROLLER_MT7986
8#define _DT_BINDINGS_RESET_CONTROLLER_MT7986
9
10/* INFRACFG resets */
11#define MT7986_INFRACFG_PEXTP_MAC_SW_RST 6
12#define MT7986_INFRACFG_SSUSB_SW_RST 7
13#define MT7986_INFRACFG_EIP97_SW_RST 8
14#define MT7986_INFRACFG_AUDIO_SW_RST 13
15#define MT7986_INFRACFG_CQ_DMA_SW_RST 14
16
17#define MT7986_INFRACFG_TRNG_SW_RST 17
18#define MT7986_INFRACFG_AP_DMA_SW_RST 32
19#define MT7986_INFRACFG_I2C_SW_RST 33
20#define MT7986_INFRACFG_NFI_SW_RST 34
21#define MT7986_INFRACFG_SPI0_SW_RST 35
22#define MT7986_INFRACFG_SPI1_SW_RST 36
23#define MT7986_INFRACFG_UART0_SW_RST 37
24#define MT7986_INFRACFG_UART1_SW_RST 38
25#define MT7986_INFRACFG_UART2_SW_RST 39
26#define MT7986_INFRACFG_AUXADC_SW_RST 43
27
28#define MT7986_INFRACFG_APXGPT_SW_RST 66
29#define MT7986_INFRACFG_PWM_SW_RST 68
30
31#define MT7986_INFRACFG_SW_RST_NUM 69
32
33/* TOPRGU resets */
34#define MT7986_TOPRGU_APMIXEDSYS_SW_RST 0
35#define MT7986_TOPRGU_SGMII0_SW_RST 1
36#define MT7986_TOPRGU_SGMII1_SW_RST 2
37#define MT7986_TOPRGU_INFRA_SW_RST 3
38#define MT7986_TOPRGU_U2PHY_SW_RST 5
39#define MT7986_TOPRGU_PCIE_SW_RST 6
40#define MT7986_TOPRGU_SSUSB_SW_RST 7
41#define MT7986_TOPRGU_ETHDMA_SW_RST 20
42#define MT7986_TOPRGU_CONSYS_SW_RST 23
43
44#define MT7986_TOPRGU_SW_RST_NUM 24
45
46/* ETHSYS Subsystem resets */
47#define MT7986_ETHSYS_FE_SW_RST 6
48#define MT7986_ETHSYS_PMTR_SW_RST 8
49#define MT7986_ETHSYS_GMAC_SW_RST 23
50#define MT7986_ETHSYS_PPE0_SW_RST 30
51#define MT7986_ETHSYS_PPE1_SW_RST 31
52
53#define MT7986_ETHSYS_SW_RST_NUM 32
54
55#endif /* _DT_BINDINGS_RESET_CONTROLLER_MT7986 */
56

source code of linux/include/dt-bindings/reset/mt7986-resets.h