1/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
2/*
3 * Copyright (c) 2023, The Linux Foundation. All rights reserved.
4 */
5
6#ifndef _DT_BINDINGS_RESET_IPQ_GCC_5018_H
7#define _DT_BINDINGS_RESET_IPQ_GCC_5018_H
8
9#define GCC_APC0_VOLTAGE_DROOP_DETECTOR_BCR 0
10#define GCC_BLSP1_BCR 1
11#define GCC_BLSP1_QUP1_BCR 2
12#define GCC_BLSP1_QUP2_BCR 3
13#define GCC_BLSP1_QUP3_BCR 4
14#define GCC_BLSP1_UART1_BCR 5
15#define GCC_BLSP1_UART2_BCR 6
16#define GCC_BOOT_ROM_BCR 7
17#define GCC_BTSS_BCR 8
18#define GCC_CMN_BLK_BCR 9
19#define GCC_CMN_LDO_BCR 10
20#define GCC_CE_BCR 11
21#define GCC_CRYPTO_BCR 12
22#define GCC_DCC_BCR 13
23#define GCC_DCD_BCR 14
24#define GCC_DDRSS_BCR 15
25#define GCC_EDPD_BCR 16
26#define GCC_GEPHY_BCR 17
27#define GCC_GEPHY_MDC_SW_ARES 18
28#define GCC_GEPHY_DSP_HW_ARES 19
29#define GCC_GEPHY_RX_ARES 20
30#define GCC_GEPHY_TX_ARES 21
31#define GCC_GMAC0_BCR 22
32#define GCC_GMAC0_CFG_ARES 23
33#define GCC_GMAC0_SYS_ARES 24
34#define GCC_GMAC1_BCR 25
35#define GCC_GMAC1_CFG_ARES 26
36#define GCC_GMAC1_SYS_ARES 27
37#define GCC_IMEM_BCR 28
38#define GCC_LPASS_BCR 29
39#define GCC_MDIO0_BCR 30
40#define GCC_MDIO1_BCR 31
41#define GCC_MPM_BCR 32
42#define GCC_PCIE0_BCR 33
43#define GCC_PCIE0_LINK_DOWN_BCR 34
44#define GCC_PCIE0_PHY_BCR 35
45#define GCC_PCIE0PHY_PHY_BCR 36
46#define GCC_PCIE0_PIPE_ARES 37
47#define GCC_PCIE0_SLEEP_ARES 38
48#define GCC_PCIE0_CORE_STICKY_ARES 39
49#define GCC_PCIE0_AXI_MASTER_ARES 40
50#define GCC_PCIE0_AXI_SLAVE_ARES 41
51#define GCC_PCIE0_AHB_ARES 42
52#define GCC_PCIE0_AXI_MASTER_STICKY_ARES 43
53#define GCC_PCIE0_AXI_SLAVE_STICKY_ARES 44
54#define GCC_PCIE1_BCR 45
55#define GCC_PCIE1_LINK_DOWN_BCR 46
56#define GCC_PCIE1_PHY_BCR 47
57#define GCC_PCIE1PHY_PHY_BCR 48
58#define GCC_PCIE1_PIPE_ARES 49
59#define GCC_PCIE1_SLEEP_ARES 50
60#define GCC_PCIE1_CORE_STICKY_ARES 51
61#define GCC_PCIE1_AXI_MASTER_ARES 52
62#define GCC_PCIE1_AXI_SLAVE_ARES 53
63#define GCC_PCIE1_AHB_ARES 54
64#define GCC_PCIE1_AXI_MASTER_STICKY_ARES 55
65#define GCC_PCIE1_AXI_SLAVE_STICKY_ARES 56
66#define GCC_PCNOC_BCR 57
67#define GCC_PCNOC_BUS_TIMEOUT0_BCR 58
68#define GCC_PCNOC_BUS_TIMEOUT1_BCR 59
69#define GCC_PCNOC_BUS_TIMEOUT2_BCR 60
70#define GCC_PCNOC_BUS_TIMEOUT3_BCR 61
71#define GCC_PCNOC_BUS_TIMEOUT4_BCR 62
72#define GCC_PCNOC_BUS_TIMEOUT5_BCR 63
73#define GCC_PCNOC_BUS_TIMEOUT6_BCR 64
74#define GCC_PCNOC_BUS_TIMEOUT7_BCR 65
75#define GCC_PCNOC_BUS_TIMEOUT8_BCR 66
76#define GCC_PCNOC_BUS_TIMEOUT9_BCR 67
77#define GCC_PCNOC_BUS_TIMEOUT10_BCR 68
78#define GCC_PCNOC_BUS_TIMEOUT11_BCR 69
79#define GCC_PRNG_BCR 70
80#define GCC_Q6SS_DBG_ARES 71
81#define GCC_Q6_AHB_S_ARES 72
82#define GCC_Q6_AHB_ARES 73
83#define GCC_Q6_AXIM2_ARES 74
84#define GCC_Q6_AXIM_ARES 75
85#define GCC_Q6_AXIS_ARES 76
86#define GCC_QDSS_BCR 77
87#define GCC_QPIC_BCR 78
88#define GCC_QUSB2_0_PHY_BCR 79
89#define GCC_SDCC1_BCR 80
90#define GCC_SEC_CTRL_BCR 81
91#define GCC_SPDM_BCR 82
92#define GCC_SYSTEM_NOC_BCR 83
93#define GCC_TCSR_BCR 84
94#define GCC_TLMM_BCR 85
95#define GCC_UBI0_AXI_ARES 86
96#define GCC_UBI0_AHB_ARES 87
97#define GCC_UBI0_NC_AXI_ARES 88
98#define GCC_UBI0_DBG_ARES 89
99#define GCC_UBI0_UTCM_ARES 90
100#define GCC_UBI0_CORE_ARES 91
101#define GCC_UBI32_BCR 92
102#define GCC_UNIPHY_BCR 93
103#define GCC_UNIPHY_AHB_ARES 94
104#define GCC_UNIPHY_SYS_ARES 95
105#define GCC_UNIPHY_RX_ARES 96
106#define GCC_UNIPHY_TX_ARES 97
107#define GCC_USB0_BCR 98
108#define GCC_USB0_PHY_BCR 99
109#define GCC_WCSS_BCR 100
110#define GCC_WCSS_DBG_ARES 101
111#define GCC_WCSS_ECAHB_ARES 102
112#define GCC_WCSS_ACMT_ARES 103
113#define GCC_WCSS_DBG_BDG_ARES 104
114#define GCC_WCSS_AHB_S_ARES 105
115#define GCC_WCSS_AXI_M_ARES 106
116#define GCC_WCSS_AXI_S_ARES 107
117#define GCC_WCSS_Q6_BCR 108
118#define GCC_WCSSAON_RESET 109
119#define GCC_UNIPHY_SOFT_RESET 110
120#define GCC_GEPHY_MISC_ARES 111
121
122#endif
123

source code of linux/include/dt-bindings/reset/qcom,gcc-ipq5018.h