1	// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2	/*
3	* Copyright (c) 2023, The Linux Foundation. All rights reserved.
4	*/
5	#include <linux/clk-provider.h>
6	#include <linux/mod_devicetable.h>
7	#include <linux/module.h>
8	#include <linux/platform_device.h>
9	#include <linux/regmap.h>
10
11	#include <dt-bindings/clock/qcom,gcc-ipq5018.h>
12	#include <dt-bindings/reset/qcom,gcc-ipq5018.h>
13
14	#include "clk-alpha-pll.h"
15	#include "clk-branch.h"
16	#include "clk-rcg.h"
17	#include "clk-regmap.h"
18	#include "clk-regmap-divider.h"
19	#include "clk-regmap-mux.h"
20	#include "clk-regmap-phy-mux.h"
21	#include "reset.h"
22
23	/* Need to match the order of clocks in DT binding */
24	enum {
25	DT_XO,
26	DT_SLEEP_CLK,
27	DT_PCIE20_PHY0_PIPE_CLK,
28	DT_PCIE20_PHY1_PIPE_CLK,
29	DT_USB3_PHY0_CC_PIPE_CLK,
30	DT_GEPHY_RX_CLK,
31	DT_GEPHY_TX_CLK,
32	DT_UNIPHY_RX_CLK,
33	DT_UNIPHY_TX_CLK,
34	};
35
36	enum {
37	P_XO,
38	P_CORE_PI_SLEEP_CLK,
39	P_PCIE20_PHY0_PIPE,
40	P_PCIE20_PHY1_PIPE,
41	P_USB3PHY_0_PIPE,
42	P_GEPHY_RX,
43	P_GEPHY_TX,
44	P_UNIPHY_RX,
45	P_UNIPHY_TX,
46	P_GPLL0,
47	P_GPLL0_DIV2,
48	P_GPLL2,
49	P_GPLL4,
50	P_UBI32_PLL,
51	};
52
53	static const struct clk_parent_data gcc_xo_data[] = {
54	{ .index = DT_XO },
55	};
56
57	static const struct clk_parent_data gcc_sleep_clk_data[] = {
58	{ .index = DT_SLEEP_CLK },
59	};
60
61	static struct clk_alpha_pll gpll0_main = {
62	.offset = 0x21000,
63	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
64	.clkr = {
65	.enable_reg = 0x0b000,
66	.enable_mask = BIT(0),
67	.hw.init = &(struct clk_init_data) {
68	.name = "gpll0_main",
69	.parent_data = gcc_xo_data,
70	.num_parents = ARRAY_SIZE(gcc_xo_data),
71	.ops = &clk_alpha_pll_stromer_ops,
72	},
73	},
74	};
75
76	static struct clk_alpha_pll gpll2_main = {
77	.offset = 0x4a000,
78	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
79	.clkr = {
80	.enable_reg = 0x0b000,
81	.enable_mask = BIT(2),
82	.hw.init = &(struct clk_init_data) {
83	.name = "gpll2_main",
84	.parent_data = gcc_xo_data,
85	.num_parents = ARRAY_SIZE(gcc_xo_data),
86	.ops = &clk_alpha_pll_stromer_ops,
87	},
88	},
89	};
90
91	static struct clk_alpha_pll gpll4_main = {
92	.offset = 0x24000,
93	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
94	.clkr = {
95	.enable_reg = 0x0b000,
96	.enable_mask = BIT(5),
97	.hw.init = &(struct clk_init_data) {
98	.name = "gpll4_main",
99	.parent_data = gcc_xo_data,
100	.num_parents = ARRAY_SIZE(gcc_xo_data),
101	.ops = &clk_alpha_pll_stromer_ops,
102	},
103	},
104	};
105
106	static struct clk_alpha_pll ubi32_pll_main = {
107	.offset = 0x25000,
108	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
109	.clkr = {
110	.enable_reg = 0x0b000,
111	.enable_mask = BIT(6),
112	.hw.init = &(struct clk_init_data) {
113	.name = "ubi32_pll_main",
114	.parent_data = gcc_xo_data,
115	.num_parents = ARRAY_SIZE(gcc_xo_data),
116	.ops = &clk_alpha_pll_stromer_ops,
117	},
118	},
119	};
120
121	static struct clk_alpha_pll_postdiv gpll0 = {
122	.offset = 0x21000,
123	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
124	.width = 4,
125	.clkr.hw.init = &(struct clk_init_data) {
126	.name = "gpll0",
127	.parent_hws = (const struct clk_hw *[]) {
128	&gpll0_main.clkr.hw,
129	},
130	.num_parents = 1,
131	.ops = &clk_alpha_pll_postdiv_ro_ops,
132	},
133	};
134
135	static struct clk_alpha_pll_postdiv gpll2 = {
136	.offset = 0x4a000,
137	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
138	.width = 4,
139	.clkr.hw.init = &(struct clk_init_data) {
140	.name = "gpll2",
141	.parent_hws = (const struct clk_hw *[]) {
142	&gpll2_main.clkr.hw,
143	},
144	.num_parents = 1,
145	.ops = &clk_alpha_pll_postdiv_ro_ops,
146	},
147	};
148
149	static struct clk_alpha_pll_postdiv gpll4 = {
150	.offset = 0x24000,
151	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
152	.width = 4,
153	.clkr.hw.init = &(struct clk_init_data) {
154	.name = "gpll4",
155	.parent_hws = (const struct clk_hw *[]) {
156	&gpll4_main.clkr.hw,
157	},
158	.num_parents = 1,
159	.ops = &clk_alpha_pll_postdiv_ro_ops,
160	},
161	};
162
163	static struct clk_alpha_pll_postdiv ubi32_pll = {
164	.offset = 0x25000,
165	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
166	.width = 4,
167	.clkr.hw.init = &(struct clk_init_data) {
168	.name = "ubi32_pll",
169	.parent_hws = (const struct clk_hw *[]) {
170	&ubi32_pll_main.clkr.hw,
171	},
172	.num_parents = 1,
173	.ops = &clk_alpha_pll_postdiv_ro_ops,
174	.flags = CLK_SET_RATE_PARENT,
175	},
176	};
177
178	static struct clk_fixed_factor gpll0_out_main_div2 = {
179	.mult = 1,
180	.div = 2,
181	.hw.init = &(struct clk_init_data) {
182	.name = "gpll0_out_main_div2",
183	.parent_hws = (const struct clk_hw *[]) {
184	&gpll0_main.clkr.hw,
185	},
186	.num_parents = 1,
187	.ops = &clk_fixed_factor_ops,
188	.flags = CLK_SET_RATE_PARENT,
189	},
190	};
191
192	static const struct clk_parent_data gcc_xo_gpll0_gpll0_out_main_div2[] = {
193	{ .index = DT_XO },
194	{ .hw = &gpll0.clkr.hw },
195	{ .hw = &gpll0_out_main_div2.hw },
196	};
197
198	static const struct parent_map gcc_xo_gpll0_gpll0_out_main_div2_map[] = {
199	{ P_XO, 0 },
200	{ P_GPLL0, 1 },
201	{ P_GPLL0_DIV2, 4 },
202	};
203
204	static const struct clk_parent_data gcc_xo_gpll0[] = {
205	{ .index = DT_XO },
206	{ .hw = &gpll0.clkr.hw },
207	};
208
209	static const struct parent_map gcc_xo_gpll0_map[] = {
210	{ P_XO, 0 },
211	{ P_GPLL0, 1 },
212	};
213
214	static const struct clk_parent_data gcc_xo_gpll0_out_main_div2_gpll0[] = {
215	{ .index = DT_XO },
216	{ .hw = &gpll0_out_main_div2.hw },
217	{ .hw = &gpll0.clkr.hw },
218	};
219
220	static const struct parent_map gcc_xo_gpll0_out_main_div2_gpll0_map[] = {
221	{ P_XO, 0 },
222	{ P_GPLL0_DIV2, 2 },
223	{ P_GPLL0, 1 },
224	};
225
226	static const struct clk_parent_data gcc_xo_ubi32_gpll0[] = {
227	{ .index = DT_XO },
228	{ .hw = &ubi32_pll.clkr.hw },
229	{ .hw = &gpll0.clkr.hw },
230	};
231
232	static const struct parent_map gcc_xo_ubi32_gpll0_map[] = {
233	{ P_XO, 0 },
234	{ P_UBI32_PLL, 1 },
235	{ P_GPLL0, 2 },
236	};
237
238	static const struct clk_parent_data gcc_xo_gpll0_gpll2[] = {
239	{ .index = DT_XO },
240	{ .hw = &gpll0.clkr.hw },
241	{ .hw = &gpll2.clkr.hw },
242	};
243
244	static const struct parent_map gcc_xo_gpll0_gpll2_map[] = {
245	{ P_XO, 0 },
246	{ P_GPLL0, 1 },
247	{ P_GPLL2, 2 },
248	};
249
250	static const struct clk_parent_data gcc_xo_gpll0_gpll2_gpll4[] = {
251	{ .index = DT_XO },
252	{ .hw = &gpll0.clkr.hw },
253	{ .hw = &gpll2.clkr.hw },
254	{ .hw = &gpll4.clkr.hw },
255	};
256
257	static const struct parent_map gcc_xo_gpll0_gpll2_gpll4_map[] = {
258	{ P_XO, 0 },
259	{ P_GPLL0, 1 },
260	{ P_GPLL2, 2 },
261	{ P_GPLL4, 3 },
262	};
263
264	static const struct clk_parent_data gcc_xo_gpll0_gpll4[] = {
265	{ .index = DT_XO },
266	{ .hw = &gpll0.clkr.hw },
267	{ .hw = &gpll4.clkr.hw },
268	};
269
270	static const struct parent_map gcc_xo_gpll0_gpll4_map[] = {
271	{ P_XO, 0 },
272	{ P_GPLL0, 1 },
273	{ P_GPLL4, 2 },
274	};
275
276	static const struct clk_parent_data gcc_xo_gpll0_core_pi_sleep_clk[] = {
277	{ .index = DT_XO },
278	{ .hw = &gpll0.clkr.hw },
279	{ .index = DT_SLEEP_CLK },
280	};
281
282	static const struct parent_map gcc_xo_gpll0_core_pi_sleep_clk_map[] = {
283	{ P_XO, 0 },
284	{ P_GPLL0, 2 },
285	{ P_CORE_PI_SLEEP_CLK, 6 },
286	};
287
288	static const struct clk_parent_data gcc_xo_gpll0_gpll0_out_main_div2_sleep_clk[] = {
289	{ .index = DT_XO },
290	{ .hw = &gpll0.clkr.hw },
291	{ .hw = &gpll0_out_main_div2.hw },
292	{ .index = DT_SLEEP_CLK },
293	};
294
295	static const struct parent_map gcc_xo_gpll0_gpll0_out_main_div2_sleep_clk_map[] = {
296	{ P_XO, 0 },
297	{ P_GPLL0, 1 },
298	{ P_GPLL0_DIV2, 4 },
299	{ P_CORE_PI_SLEEP_CLK, 6 },
300	};
301
302	static const struct clk_parent_data gcc_xo_gpll0_gpll2_gpll0_out_main_div2[] = {
303	{ .index = DT_XO },
304	{ .hw = &gpll0.clkr.hw },
305	{ .hw = &gpll2.clkr.hw },
306	{ .hw = &gpll0_out_main_div2.hw },
307	};
308
309	static const struct parent_map gcc_xo_gpll0_gpll2_gpll0_out_main_div2_map[] = {
310	{ P_XO, 0 },
311	{ P_GPLL0, 1 },
312	{ P_GPLL2, 2 },
313	{ P_GPLL0_DIV2, 4 },
314	};
315
316	static const struct clk_parent_data gcc_xo_gpll4_gpll0_gpll0_out_main_div2[] = {
317	{ .index = DT_XO },
318	{ .hw = &gpll4.clkr.hw },
319	{ .hw = &gpll0.clkr.hw },
320	{ .hw = &gpll0_out_main_div2.hw },
321	};
322
323	static const struct parent_map gcc_xo_gpll4_gpll0_gpll0_out_main_div2_map1[] = {
324	{ P_XO, 0 },
325	{ P_GPLL4, 1 },
326	{ P_GPLL0, 2 },
327	{ P_GPLL0_DIV2, 4 },
328	};
329
330	static const struct parent_map gcc_xo_gpll4_gpll0_gpll0_out_main_div2_map2[] = {
331	{ P_XO, 0 },
332	{ P_GPLL4, 1 },
333	{ P_GPLL0, 3 },
334	{ P_GPLL0_DIV2, 4 },
335	};
336
337	static const struct clk_parent_data gcc_xo_gephy_gcc_rx_gephy_gcc_tx_ubi32_pll_gpll0[] = {
338	{ .index = DT_XO },
339	{ .index = DT_GEPHY_RX_CLK },
340	{ .index = DT_GEPHY_TX_CLK },
341	{ .hw = &ubi32_pll.clkr.hw },
342	{ .hw = &gpll0.clkr.hw },
343	};
344
345	static const struct parent_map gcc_xo_gephy_gcc_rx_gephy_gcc_tx_ubi32_pll_gpll0_map[] = {
346	{ P_XO, 0 },
347	{ P_GEPHY_RX, 1 },
348	{ P_GEPHY_TX, 2 },
349	{ P_UBI32_PLL, 3 },
350	{ P_GPLL0, 4 },
351	};
352
353	static const struct clk_parent_data gcc_xo_gephy_gcc_tx_gephy_gcc_rx_ubi32_pll_gpll0[] = {
354	{ .index = DT_XO },
355	{ .index = DT_GEPHY_TX_CLK },
356	{ .index = DT_GEPHY_RX_CLK },
357	{ .hw = &ubi32_pll.clkr.hw },
358	{ .hw = &gpll0.clkr.hw },
359	};
360
361	static const struct parent_map gcc_xo_gephy_gcc_tx_gephy_gcc_rx_ubi32_pll_gpll0_map[] = {
362	{ P_XO, 0 },
363	{ P_GEPHY_TX, 1 },
364	{ P_GEPHY_RX, 2 },
365	{ P_UBI32_PLL, 3 },
366	{ P_GPLL0, 4 },
367	};
368
369	static const struct clk_parent_data gcc_xo_uniphy_gcc_rx_uniphy_gcc_tx_ubi32_pll_gpll0[] = {
370	{ .index = DT_XO },
371	{ .index = DT_UNIPHY_RX_CLK },
372	{ .index = DT_UNIPHY_TX_CLK },
373	{ .hw = &ubi32_pll.clkr.hw },
374	{ .hw = &gpll0.clkr.hw },
375	};
376
377	static const struct parent_map gcc_xo_uniphy_gcc_rx_uniphy_gcc_tx_ubi32_pll_gpll0_map[] = {
378	{ P_XO, 0 },
379	{ P_UNIPHY_RX, 1 },
380	{ P_UNIPHY_TX, 2 },
381	{ P_UBI32_PLL, 3 },
382	{ P_GPLL0, 4 },
383	};
384
385	static const struct clk_parent_data gcc_xo_uniphy_gcc_tx_uniphy_gcc_rx_ubi32_pll_gpll0[] = {
386	{ .index = DT_XO },
387	{ .index = DT_UNIPHY_TX_CLK },
388	{ .index = DT_UNIPHY_RX_CLK },
389	{ .hw = &ubi32_pll.clkr.hw },
390	{ .hw = &gpll0.clkr.hw },
391	};
392
393	static const struct parent_map gcc_xo_uniphy_gcc_tx_uniphy_gcc_rx_ubi32_pll_gpll0_map[] = {
394	{ P_XO, 0 },
395	{ P_UNIPHY_TX, 1 },
396	{ P_UNIPHY_RX, 2 },
397	{ P_UBI32_PLL, 3 },
398	{ P_GPLL0, 4 },
399	};
400
401	static const struct clk_parent_data gcc_pcie20_phy0_pipe_clk_xo[] = {
402	{ .index = DT_PCIE20_PHY0_PIPE_CLK },
403	{ .index = DT_XO },
404	};
405
406	static const struct parent_map gcc_pcie20_phy0_pipe_clk_xo_map[] = {
407	{ P_PCIE20_PHY0_PIPE, 0 },
408	{ P_XO, 2 },
409	};
410
411	static const struct clk_parent_data gcc_pcie20_phy1_pipe_clk_xo[] = {
412	{ .index = DT_PCIE20_PHY1_PIPE_CLK },
413	{ .index = DT_XO },
414	};
415
416	static const struct parent_map gcc_pcie20_phy1_pipe_clk_xo_map[] = {
417	{ P_PCIE20_PHY1_PIPE, 0 },
418	{ P_XO, 2 },
419	};
420
421	static const struct clk_parent_data gcc_usb3phy_0_cc_pipe_clk_xo[] = {
422	{ .index = DT_USB3_PHY0_CC_PIPE_CLK },
423	{ .index = DT_XO },
424	};
425
426	static const struct parent_map gcc_usb3phy_0_cc_pipe_clk_xo_map[] = {
427	{ P_USB3PHY_0_PIPE, 0 },
428	{ P_XO, 2 },
429	};
430
431	static const struct freq_tbl ftbl_adss_pwm_clk_src[] = {
432	F(24000000, P_XO, 1, 0, 0),
433	F(100000000, P_GPLL0, 8, 0, 0),
434	{ }
435	};
436
437	static struct clk_rcg2 adss_pwm_clk_src = {
438	.cmd_rcgr = 0x1f008,
439	.freq_tbl = ftbl_adss_pwm_clk_src,
440	.hid_width = 5,
441	.parent_map = gcc_xo_gpll0_map,
442	.clkr.hw.init = &(struct clk_init_data) {
443	.name = "adss_pwm_clk_src",
444	.parent_data = gcc_xo_gpll0,
445	.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
446	.ops = &clk_rcg2_ops,
447	},
448	};
449
450	static const struct freq_tbl ftbl_blsp1_qup_i2c_apps_clk_src[] = {
451	F(50000000, P_GPLL0, 16, 0, 0),
452	{ }
453	};
454
455	static struct clk_rcg2 blsp1_qup1_i2c_apps_clk_src = {
456	.cmd_rcgr = 0x0200c,
457	.freq_tbl = ftbl_blsp1_qup_i2c_apps_clk_src,
458	.hid_width = 5,
459	.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
460	.clkr.hw.init = &(struct clk_init_data) {
461	.name = "blsp1_qup1_i2c_apps_clk_src",
462	.parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
463	.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
464	.ops = &clk_rcg2_ops,
465	},
466	};
467
468	static struct clk_rcg2 blsp1_qup2_i2c_apps_clk_src = {
469	.cmd_rcgr = 0x03000,
470	.freq_tbl = ftbl_blsp1_qup_i2c_apps_clk_src,
471	.hid_width = 5,
472	.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
473	.clkr.hw.init = &(struct clk_init_data) {
474	.name = "blsp1_qup2_i2c_apps_clk_src",
475	.parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
476	.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
477	.ops = &clk_rcg2_ops,
478	},
479	};
480
481	static struct clk_rcg2 blsp1_qup3_i2c_apps_clk_src = {
482	.cmd_rcgr = 0x04000,
483	.freq_tbl = ftbl_blsp1_qup_i2c_apps_clk_src,
484	.hid_width = 5,
485	.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
486	.clkr.hw.init = &(struct clk_init_data) {
487	.name = "blsp1_qup3_i2c_apps_clk_src",
488	.parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
489	.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
490	.ops = &clk_rcg2_ops,
491	},
492	};
493
494	static const struct freq_tbl ftbl_blsp1_qup_spi_apps_clk_src[] = {
495	F(960000, P_XO, 10, 2, 5),
496	F(4800000, P_XO, 5, 0, 0),
497	F(9600000, P_XO, 2, 4, 5),
498	F(16000000, P_GPLL0, 10, 1, 5),
499	F(24000000, P_XO, 1, 0, 0),
500	F(50000000, P_GPLL0, 16, 0, 0),
501	{ }
502	};
503
504	static struct clk_rcg2 blsp1_qup1_spi_apps_clk_src = {
505	.cmd_rcgr = 0x02024,
506	.freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src,
507	.mnd_width = 8,
508	.hid_width = 5,
509	.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
510	.clkr.hw.init = &(struct clk_init_data) {
511	.name = "blsp1_qup1_spi_apps_clk_src",
512	.parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
513	.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
514	.ops = &clk_rcg2_ops,
515	},
516	};
517
518	static struct clk_rcg2 blsp1_qup2_spi_apps_clk_src = {
519	.cmd_rcgr = 0x03014,
520	.freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src,
521	.mnd_width = 8,
522	.hid_width = 5,
523	.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
524	.clkr.hw.init = &(struct clk_init_data) {
525	.name = "blsp1_qup2_spi_apps_clk_src",
526	.parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
527	.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
528	.ops = &clk_rcg2_ops,
529	},
530	};
531
532	static struct clk_rcg2 blsp1_qup3_spi_apps_clk_src = {
533	.cmd_rcgr = 0x04014,
534	.freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src,
535	.mnd_width = 8,
536	.hid_width = 5,
537	.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
538	.clkr.hw.init = &(struct clk_init_data) {
539	.name = "blsp1_qup3_spi_apps_clk_src",
540	.parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
541	.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
542	.ops = &clk_rcg2_ops,
543	},
544	};
545
546	static const struct freq_tbl ftbl_blsp1_uart_apps_clk_src[] = {
547	F(3686400, P_GPLL0_DIV2, 1, 144, 15625),
548	F(7372800, P_GPLL0_DIV2, 1, 288, 15625),
549	F(14745600, P_GPLL0_DIV2, 1, 576, 15625),
550	F(24000000, P_XO, 1, 0, 0),
551	F(25000000, P_GPLL0, 16, 1, 2),
552	F(40000000, P_GPLL0, 1, 1, 20),
553	F(46400000, P_GPLL0, 1, 29, 500),
554	F(48000000, P_GPLL0, 1, 3, 50),
555	F(51200000, P_GPLL0, 1, 8, 125),
556	F(56000000, P_GPLL0, 1, 7, 100),
557	F(58982400, P_GPLL0, 1, 1152, 15625),
558	F(60000000, P_GPLL0, 1, 3, 40),
559	F(64000000, P_GPLL0, 10, 4, 5),
560	{ }
561	};
562
563	static struct clk_rcg2 blsp1_uart1_apps_clk_src = {
564	.cmd_rcgr = 0x02044,
565	.freq_tbl = ftbl_blsp1_uart_apps_clk_src,
566	.mnd_width = 16,
567	.hid_width = 5,
568	.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
569	.clkr.hw.init = &(struct clk_init_data) {
570	.name = "blsp1_uart1_apps_clk_src",
571	.parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
572	.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
573	.ops = &clk_rcg2_ops,
574	},
575	};
576
577	static struct clk_rcg2 blsp1_uart2_apps_clk_src = {
578	.cmd_rcgr = 0x03034,
579	.freq_tbl = ftbl_blsp1_uart_apps_clk_src,
580	.mnd_width = 16,
581	.hid_width = 5,
582	.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
583	.clkr.hw.init = &(struct clk_init_data) {
584	.name = "blsp1_uart2_apps_clk_src",
585	.parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
586	.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
587	.ops = &clk_rcg2_ops,
588	},
589	};
590
591	static const struct freq_tbl ftbl_crypto_clk_src[] = {
592	F(160000000, P_GPLL0, 5, 0, 0),
593	{ }
594	};
595
596	static struct clk_rcg2 crypto_clk_src = {
597	.cmd_rcgr = 0x16004,
598	.freq_tbl = ftbl_crypto_clk_src,
599	.hid_width = 5,
600	.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
601	.clkr.hw.init = &(struct clk_init_data) {
602	.name = "crypto_clk_src",
603	.parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
604	.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
605	.ops = &clk_rcg2_ops,
606	},
607	};
608
609	static const struct freq_tbl ftbl_gmac0_tx_clk_src[] = {
610	F(2500000, P_GEPHY_TX, 5, 0, 0),
611	F(24000000, P_XO, 1, 0, 0),
612	F(25000000, P_GEPHY_TX, 5, 0, 0),
613	F(125000000, P_GEPHY_TX, 1, 0, 0),
614	{ }
615	};
616
617	static struct clk_rcg2 gmac0_rx_clk_src = {
618	.cmd_rcgr = 0x68020,
619	.parent_map = gcc_xo_gephy_gcc_rx_gephy_gcc_tx_ubi32_pll_gpll0_map,
620	.hid_width = 5,
621	.freq_tbl = ftbl_gmac0_tx_clk_src,
622	.clkr.hw.init = &(struct clk_init_data) {
623	.name = "gmac0_rx_clk_src",
624	.parent_data = gcc_xo_gephy_gcc_rx_gephy_gcc_tx_ubi32_pll_gpll0,
625	.num_parents = ARRAY_SIZE(gcc_xo_gephy_gcc_rx_gephy_gcc_tx_ubi32_pll_gpll0),
626	.ops = &clk_rcg2_ops,
627	},
628	};
629
630	static struct clk_regmap_div gmac0_rx_div_clk_src = {
631	.reg = 0x68420,
632	.shift = 0,
633	.width = 4,
634	.clkr = {
635	.hw.init = &(struct clk_init_data) {
636	.name = "gmac0_rx_div_clk_src",
637	.parent_hws = (const struct clk_hw *[]) {
638	&gmac0_rx_clk_src.clkr.hw,
639	},
640	.num_parents = 1,
641	.ops = &clk_regmap_div_ops,
642	.flags = CLK_SET_RATE_PARENT,
643	},
644	},
645	};
646
647	static struct clk_rcg2 gmac0_tx_clk_src = {
648	.cmd_rcgr = 0x68028,
649	.parent_map = gcc_xo_gephy_gcc_tx_gephy_gcc_rx_ubi32_pll_gpll0_map,
650	.hid_width = 5,
651	.freq_tbl = ftbl_gmac0_tx_clk_src,
652	.clkr.hw.init = &(struct clk_init_data) {
653	.name = "gmac0_tx_clk_src",
654	.parent_data = gcc_xo_gephy_gcc_tx_gephy_gcc_rx_ubi32_pll_gpll0,
655	.num_parents = ARRAY_SIZE(gcc_xo_gephy_gcc_tx_gephy_gcc_rx_ubi32_pll_gpll0),
656	.ops = &clk_rcg2_ops,
657	},
658	};
659
660	static struct clk_regmap_div gmac0_tx_div_clk_src = {
661	.reg = 0x68424,
662	.shift = 0,
663	.width = 4,
664	.clkr = {
665	.hw.init = &(struct clk_init_data) {
666	.name = "gmac0_tx_div_clk_src",
667	.parent_hws = (const struct clk_hw *[]) {
668	&gmac0_tx_clk_src.clkr.hw,
669	},
670	.num_parents = 1,
671	.ops = &clk_regmap_div_ops,
672	.flags = CLK_SET_RATE_PARENT,
673	},
674	},
675	};
676
677	static const struct freq_tbl ftbl_gmac1_rx_clk_src[] = {
678	F(2500000, P_UNIPHY_RX, 12.5, 0, 0),
679	F(24000000, P_XO, 1, 0, 0),
680	F(25000000, P_UNIPHY_RX, 2.5, 0, 0),
681	F(125000000, P_UNIPHY_RX, 2.5, 0, 0),
682	F(125000000, P_UNIPHY_RX, 1, 0, 0),
683	F(312500000, P_UNIPHY_RX, 1, 0, 0),
684	{ }
685	};
686
687	static struct clk_rcg2 gmac1_rx_clk_src = {
688	.cmd_rcgr = 0x68030,
689	.parent_map = gcc_xo_uniphy_gcc_rx_uniphy_gcc_tx_ubi32_pll_gpll0_map,
690	.hid_width = 5,
691	.freq_tbl = ftbl_gmac1_rx_clk_src,
692	.clkr.hw.init = &(struct clk_init_data) {
693	.name = "gmac1_rx_clk_src",
694	.parent_data = gcc_xo_uniphy_gcc_rx_uniphy_gcc_tx_ubi32_pll_gpll0,
695	.num_parents = ARRAY_SIZE(gcc_xo_uniphy_gcc_rx_uniphy_gcc_tx_ubi32_pll_gpll0),
696	.ops = &clk_rcg2_ops,
697	},
698	};
699
700	static struct clk_regmap_div gmac1_rx_div_clk_src = {
701	.reg = 0x68430,
702	.shift = 0,
703	.width = 4,
704	.clkr = {
705	.hw.init = &(struct clk_init_data) {
706	.name = "gmac1_rx_div_clk_src",
707	.parent_hws = (const struct clk_hw *[]) {
708	&gmac1_rx_clk_src.clkr.hw,
709	},
710	.num_parents = 1,
711	.ops = &clk_regmap_div_ops,
712	.flags = CLK_SET_RATE_PARENT,
713	},
714	},
715	};
716
717	static const struct freq_tbl ftbl_gmac1_tx_clk_src[] = {
718	F(2500000, P_UNIPHY_TX, 12.5, 0, 0),
719	F(24000000, P_XO, 1, 0, 0),
720	F(25000000, P_UNIPHY_TX, 2.5, 0, 0),
721	F(125000000, P_UNIPHY_TX, 2.5, 0, 0),
722	F(125000000, P_UNIPHY_TX, 1, 0, 0),
723	F(312500000, P_UNIPHY_TX, 1, 0, 0),
724	{ }
725	};
726
727	static struct clk_rcg2 gmac1_tx_clk_src = {
728	.cmd_rcgr = 0x68038,
729	.parent_map = gcc_xo_uniphy_gcc_tx_uniphy_gcc_rx_ubi32_pll_gpll0_map,
730	.hid_width = 5,
731	.freq_tbl = ftbl_gmac1_tx_clk_src,
732	.clkr.hw.init = &(struct clk_init_data) {
733	.name = "gmac1_tx_clk_src",
734	.parent_data = gcc_xo_uniphy_gcc_tx_uniphy_gcc_rx_ubi32_pll_gpll0,
735	.num_parents = ARRAY_SIZE(gcc_xo_uniphy_gcc_tx_uniphy_gcc_rx_ubi32_pll_gpll0),
736	.ops = &clk_rcg2_ops,
737	},
738	};
739
740	static struct clk_regmap_div gmac1_tx_div_clk_src = {
741	.reg = 0x68434,
742	.shift = 0,
743	.width = 4,
744	.clkr = {
745	.hw.init = &(struct clk_init_data) {
746	.name = "gmac1_tx_div_clk_src",
747	.parent_hws = (const struct clk_hw *[]) {
748	&gmac1_tx_clk_src.clkr.hw,
749	},
750	.num_parents = 1,
751	.ops = &clk_regmap_div_ops,
752	.flags = CLK_SET_RATE_PARENT,
753	},
754	},
755	};
756
757	static const struct freq_tbl ftbl_gmac_clk_src[] = {
758	F(240000000, P_GPLL4, 5, 0, 0),
759	{ }
760	};
761
762	static struct clk_rcg2 gmac_clk_src = {
763	.cmd_rcgr = 0x68080,
764	.parent_map = gcc_xo_gpll0_gpll4_map,
765	.hid_width = 5,
766	.freq_tbl = ftbl_gmac_clk_src,
767	.clkr.hw.init = &(struct clk_init_data) {
768	.name = "gmac_clk_src",
769	.parent_data = gcc_xo_gpll0_gpll4,
770	.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll4),
771	.ops = &clk_rcg2_ops,
772	},
773	};
774
775	static const struct freq_tbl ftbl_gp_clk_src[] = {
776	F(200000000, P_GPLL0, 4, 0, 0),
777	{ }
778	};
779
780	static struct clk_rcg2 gp1_clk_src = {
781	.cmd_rcgr = 0x08004,
782	.freq_tbl = ftbl_gp_clk_src,
783	.mnd_width = 8,
784	.hid_width = 5,
785	.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_sleep_clk_map,
786	.clkr.hw.init = &(struct clk_init_data) {
787	.name = "gp1_clk_src",
788	.parent_data = gcc_xo_gpll0_gpll0_out_main_div2_sleep_clk,
789	.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2_sleep_clk),
790	.ops = &clk_rcg2_ops,
791	},
792	};
793
794	static struct clk_rcg2 gp2_clk_src = {
795	.cmd_rcgr = 0x09004,
796	.freq_tbl = ftbl_gp_clk_src,
797	.mnd_width = 8,
798	.hid_width = 5,
799	.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_sleep_clk_map,
800	.clkr.hw.init = &(struct clk_init_data) {
801	.name = "gp2_clk_src",
802	.parent_data = gcc_xo_gpll0_gpll0_out_main_div2_sleep_clk,
803	.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2_sleep_clk),
804	.ops = &clk_rcg2_ops,
805	},
806	};
807
808	static struct clk_rcg2 gp3_clk_src = {
809	.cmd_rcgr = 0x0a004,
810	.freq_tbl = ftbl_gp_clk_src,
811	.mnd_width = 8,
812	.hid_width = 5,
813	.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_sleep_clk_map,
814	.clkr.hw.init = &(struct clk_init_data) {
815	.name = "gp3_clk_src",
816	.parent_data = gcc_xo_gpll0_gpll0_out_main_div2_sleep_clk,
817	.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2_sleep_clk),
818	.ops = &clk_rcg2_ops,
819	},
820	};
821
822	static const struct freq_tbl ftbl_lpass_axim_clk_src[] = {
823	F(133333334, P_GPLL0, 6, 0, 0),
824	{ }
825	};
826
827	static struct clk_rcg2 lpass_axim_clk_src = {
828	.cmd_rcgr = 0x2e028,
829	.freq_tbl = ftbl_lpass_axim_clk_src,
830	.hid_width = 5,
831	.parent_map = gcc_xo_gpll0_map,
832	.clkr.hw.init = &(struct clk_init_data) {
833	.name = "lpass_axim_clk_src",
834	.parent_data = gcc_xo_gpll0,
835	.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
836	.ops = &clk_rcg2_ops,
837	},
838	};
839
840	static const struct freq_tbl ftbl_lpass_sway_clk_src[] = {
841	F(66666667, P_GPLL0, 12, 0, 0),
842	{ }
843	};
844
845	static struct clk_rcg2 lpass_sway_clk_src = {
846	.cmd_rcgr = 0x2e040,
847	.freq_tbl = ftbl_lpass_sway_clk_src,
848	.hid_width = 5,
849	.parent_map = gcc_xo_gpll0_map,
850	.clkr.hw.init = &(struct clk_init_data) {
851	.name = "lpass_sway_clk_src",
852	.parent_data = gcc_xo_gpll0,
853	.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
854	.ops = &clk_rcg2_ops,
855	},
856	};
857
858	static const struct freq_tbl ftbl_pcie0_aux_clk_src[] = {
859	F(2000000, P_XO, 12, 0, 0),
860	{ }
861	};
862
863	static struct clk_rcg2 pcie0_aux_clk_src = {
864	.cmd_rcgr = 0x75020,
865	.freq_tbl = ftbl_pcie0_aux_clk_src,
866	.mnd_width = 16,
867	.hid_width = 5,
868	.parent_map = gcc_xo_gpll0_core_pi_sleep_clk_map,
869	.clkr.hw.init = &(struct clk_init_data) {
870	.name = "pcie0_aux_clk_src",
871	.parent_data = gcc_xo_gpll0_core_pi_sleep_clk,
872	.num_parents = ARRAY_SIZE(gcc_xo_gpll0_core_pi_sleep_clk),
873	.ops = &clk_rcg2_ops,
874	},
875	};
876
877	static const struct freq_tbl ftbl_pcie0_axi_clk_src[] = {
878	F(240000000, P_GPLL4, 5, 0, 0),
879	{ }
880	};
881
882	static struct clk_rcg2 pcie0_axi_clk_src = {
883	.cmd_rcgr = 0x75050,
884	.freq_tbl = ftbl_pcie0_axi_clk_src,
885	.hid_width = 5,
886	.parent_map = gcc_xo_gpll0_gpll4_map,
887	.clkr.hw.init = &(struct clk_init_data) {
888	.name = "pcie0_axi_clk_src",
889	.parent_data = gcc_xo_gpll0_gpll4,
890	.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll4),
891	.ops = &clk_rcg2_ops,
892	},
893	};
894
895	static struct clk_rcg2 pcie1_aux_clk_src = {
896	.cmd_rcgr = 0x76020,
897	.freq_tbl = ftbl_pcie0_aux_clk_src,
898	.mnd_width = 16,
899	.hid_width = 5,
900	.parent_map = gcc_xo_gpll0_core_pi_sleep_clk_map,
901	.clkr.hw.init = &(struct clk_init_data) {
902	.name = "pcie1_aux_clk_src",
903	.parent_data = gcc_xo_gpll0_core_pi_sleep_clk,
904	.num_parents = ARRAY_SIZE(gcc_xo_gpll0_core_pi_sleep_clk),
905	.ops = &clk_rcg2_ops,
906	},
907	};
908
909	static struct clk_rcg2 pcie1_axi_clk_src = {
910	.cmd_rcgr = 0x76050,
911	.freq_tbl = ftbl_gp_clk_src,
912	.hid_width = 5,
913	.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
914	.clkr.hw.init = &(struct clk_init_data) {
915	.name = "pcie1_axi_clk_src",
916	.parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
917	.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
918	.ops = &clk_rcg2_ops,
919	},
920	};
921
922	static struct clk_regmap_mux pcie0_pipe_clk_src = {
923	.reg = 0x7501c,
924	.shift = 8,
925	.width = 2,
926	.parent_map = gcc_pcie20_phy0_pipe_clk_xo_map,
927	.clkr = {
928	.hw.init = &(struct clk_init_data) {
929	.name = "pcie0_pipe_clk_src",
930	.parent_data = gcc_pcie20_phy0_pipe_clk_xo,
931	.num_parents = ARRAY_SIZE(gcc_pcie20_phy0_pipe_clk_xo),
932	.ops = &clk_regmap_mux_closest_ops,
933	.flags = CLK_SET_RATE_PARENT,
934	},
935	},
936	};
937
938	static struct clk_regmap_mux pcie1_pipe_clk_src = {
939	.reg = 0x7601c,
940	.shift = 8,
941	.width = 2,
942	.parent_map = gcc_pcie20_phy1_pipe_clk_xo_map, .clkr = {
943	.hw.init = &(struct clk_init_data) {
944	.name = "pcie1_pipe_clk_src",
945	.parent_data = gcc_pcie20_phy1_pipe_clk_xo,
946	.num_parents = ARRAY_SIZE(gcc_pcie20_phy1_pipe_clk_xo),
947	.ops = &clk_regmap_mux_closest_ops,
948	.flags = CLK_SET_RATE_PARENT,
949	},
950	},
951	};
952
953	static const struct freq_tbl ftbl_pcnoc_bfdcd_clk_src[] = {
954	F(100000000, P_GPLL0, 8, 0, 0),
955	{ }
956	};
957
958	static struct clk_rcg2 pcnoc_bfdcd_clk_src = {
959	.cmd_rcgr = 0x27000,
960	.freq_tbl = ftbl_pcnoc_bfdcd_clk_src,
961	.hid_width = 5,
962	.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
963	.clkr.hw.init = &(struct clk_init_data) {
964	.name = "pcnoc_bfdcd_clk_src",
965	.parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
966	.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
967	.ops = &clk_rcg2_ops,
968	},
969	};
970
971	static struct clk_fixed_factor pcnoc_clk_src = {
972	.mult = 1,
973	.div = 1,
974	.hw.init = &(struct clk_init_data) {
975	.name = "pcnoc_clk_src",
976	.parent_hws = (const struct clk_hw *[]) {
977	&pcnoc_bfdcd_clk_src.clkr.hw,
978	},
979	.num_parents = 1,
980	.ops = &clk_fixed_factor_ops,
981	.flags = CLK_SET_RATE_PARENT,
982	},
983	};
984
985	static const struct freq_tbl ftbl_qdss_at_clk_src[] = {
986	F(240000000, P_GPLL4, 5, 0, 0),
987	{ }
988	};
989
990	static struct clk_rcg2 qdss_at_clk_src = {
991	.cmd_rcgr = 0x2900c,
992	.freq_tbl = ftbl_qdss_at_clk_src,
993	.hid_width = 5,
994	.parent_map = gcc_xo_gpll4_gpll0_gpll0_out_main_div2_map1,
995	.clkr.hw.init = &(struct clk_init_data) {
996	.name = "qdss_at_clk_src",
997	.parent_data = gcc_xo_gpll4_gpll0_gpll0_out_main_div2,
998	.num_parents = ARRAY_SIZE(gcc_xo_gpll4_gpll0_gpll0_out_main_div2),
999	.ops = &clk_rcg2_ops,
1000	},
1001	};
1002
1003	static const struct freq_tbl ftbl_qdss_stm_clk_src[] = {
1004	F(200000000, P_GPLL0, 4, 0, 0),
1005	{ }
1006	};
1007
1008	static struct clk_rcg2 qdss_stm_clk_src = {
1009	.cmd_rcgr = 0x2902c,
1010	.freq_tbl = ftbl_qdss_stm_clk_src,
1011	.hid_width = 5,
1012	.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
1013	.clkr.hw.init = &(struct clk_init_data) {
1014	.name = "qdss_stm_clk_src",
1015	.parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
1016	.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
1017	.ops = &clk_rcg2_ops,
1018	},
1019	};
1020
1021	static const struct freq_tbl ftbl_qdss_traceclkin_clk_src[] = {
1022	F(266666667, P_GPLL0, 3, 0, 0),
1023	{ }
1024	};
1025
1026	static struct clk_rcg2 qdss_traceclkin_clk_src = {
1027	.cmd_rcgr = 0x29048,
1028	.freq_tbl = ftbl_qdss_traceclkin_clk_src,
1029	.hid_width = 5,
1030	.parent_map = gcc_xo_gpll4_gpll0_gpll0_out_main_div2_map1,
1031	.clkr.hw.init = &(struct clk_init_data) {
1032	.name = "qdss_traceclkin_clk_src",
1033	.parent_data = gcc_xo_gpll4_gpll0_gpll0_out_main_div2,
1034	.num_parents = ARRAY_SIZE(gcc_xo_gpll4_gpll0_gpll0_out_main_div2),
1035	.ops = &clk_rcg2_ops,
1036	},
1037	};
1038
1039	static const struct freq_tbl ftbl_qdss_tsctr_clk_src[] = {
1040	F(600000000, P_GPLL4, 2, 0, 0),
1041	{ }
1042	};
1043
1044	static struct clk_rcg2 qdss_tsctr_clk_src = {
1045	.cmd_rcgr = 0x29064,
1046	.freq_tbl = ftbl_qdss_tsctr_clk_src,
1047	.hid_width = 5,
1048	.parent_map = gcc_xo_gpll4_gpll0_gpll0_out_main_div2_map1,
1049	.clkr.hw.init = &(struct clk_init_data) {
1050	.name = "qdss_tsctr_clk_src",
1051	.parent_data = gcc_xo_gpll4_gpll0_gpll0_out_main_div2,
1052	.num_parents = ARRAY_SIZE(gcc_xo_gpll4_gpll0_gpll0_out_main_div2),
1053	.ops = &clk_rcg2_ops,
1054	},
1055	};
1056
1057	static struct clk_fixed_factor qdss_tsctr_div2_clk_src = {
1058	.mult = 1,
1059	.div = 2,
1060	.hw.init = &(struct clk_init_data) {
1061	.name = "qdss_tsctr_div2_clk_src",
1062	.parent_hws = (const struct clk_hw *[]) {
1063	&qdss_tsctr_clk_src.clkr.hw,
1064	},
1065	.num_parents = 1,
1066	.flags = CLK_SET_RATE_PARENT,
1067	.ops = &clk_fixed_factor_ops,
1068	},
1069	};
1070
1071	static struct clk_fixed_factor qdss_dap_sync_clk_src = {
1072	.mult = 1,
1073	.div = 4,
1074	.hw.init = &(struct clk_init_data) {
1075	.name = "qdss_dap_sync_clk_src",
1076	.parent_hws = (const struct clk_hw *[]) {
1077	&qdss_tsctr_clk_src.clkr.hw,
1078	},
1079	.num_parents = 1,
1080	.ops = &clk_fixed_factor_ops,
1081	},
1082	};
1083
1084	static struct clk_fixed_factor eud_at_clk_src = {
1085	.mult = 1,
1086	.div = 6,
1087	.hw.init = &(struct clk_init_data) {
1088	.name = "eud_at_clk_src",
1089	.parent_hws = (const struct clk_hw *[]) {
1090	&qdss_at_clk_src.clkr.hw,
1091	},
1092	.num_parents = 1,
1093	.ops = &clk_fixed_factor_ops,
1094	.flags = CLK_SET_RATE_PARENT,
1095	},
1096	};
1097
1098	static const struct freq_tbl ftbl_qpic_io_macro_clk_src[] = {
1099	F(24000000, P_XO, 1, 0, 0),
1100	F(100000000, P_GPLL0, 8, 0, 0),
1101	F(200000000, P_GPLL0, 4, 0, 0),
1102	F(320000000, P_GPLL0, 2.5, 0, 0),
1103	{ }
1104	};
1105
1106	static struct clk_rcg2 qpic_io_macro_clk_src = {
1107	.cmd_rcgr = 0x57010,
1108	.freq_tbl = ftbl_qpic_io_macro_clk_src,
1109	.hid_width = 5,
1110	.parent_map = gcc_xo_gpll0_gpll2_map,
1111	.clkr.hw.init = &(struct clk_init_data) {
1112	.name = "qpic_io_macro_clk_src",
1113	.parent_data = gcc_xo_gpll0_gpll2,
1114	.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll2),
1115	.ops = &clk_rcg2_ops,
1116	},
1117	};
1118
1119	static const struct freq_tbl ftbl_sdcc1_apps_clk_src[] = {
1120	F(143713, P_XO, 1, 1, 167),
1121	F(400000, P_XO, 1, 1, 60),
1122	F(24000000, P_XO, 1, 0, 0),
1123	F(48000000, P_GPLL2, 12, 1, 2),
1124	F(96000000, P_GPLL2, 12, 0, 0),
1125	F(177777778, P_GPLL0, 1, 2, 9),
1126	F(192000000, P_GPLL2, 6, 0, 0),
1127	F(200000000, P_GPLL0, 4, 0, 0),
1128	{ }
1129	};
1130
1131	static struct clk_rcg2 sdcc1_apps_clk_src = {
1132	.cmd_rcgr = 0x42004,
1133	.freq_tbl = ftbl_sdcc1_apps_clk_src,
1134	.mnd_width = 8,
1135	.hid_width = 5,
1136	.parent_map = gcc_xo_gpll0_gpll2_gpll0_out_main_div2_map,
1137	.clkr.hw.init = &(struct clk_init_data) {
1138	.name = "sdcc1_apps_clk_src",
1139	.parent_data = gcc_xo_gpll0_gpll2_gpll0_out_main_div2,
1140	.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll2_gpll0_out_main_div2),
1141	.ops = &clk_rcg2_floor_ops,
1142	},
1143	};
1144
1145	static const struct freq_tbl ftbl_system_noc_bfdcd_clk_src[] = {
1146	F(266666667, P_GPLL0, 3, 0, 0),
1147	{ }
1148	};
1149
1150	static struct clk_rcg2 system_noc_bfdcd_clk_src = {
1151	.cmd_rcgr = 0x26004,
1152	.freq_tbl = ftbl_system_noc_bfdcd_clk_src,
1153	.hid_width = 5,
1154	.parent_map = gcc_xo_gpll0_gpll2_gpll0_out_main_div2_map,
1155	.clkr.hw.init = &(struct clk_init_data) {
1156	.name = "system_noc_bfdcd_clk_src",
1157	.parent_data = gcc_xo_gpll0_gpll2_gpll0_out_main_div2,
1158	.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll2_gpll0_out_main_div2),
1159	.ops = &clk_rcg2_ops,
1160	},
1161	};
1162
1163	static struct clk_fixed_factor system_noc_clk_src = {
1164	.mult = 1,
1165	.div = 1,
1166	.hw.init = &(struct clk_init_data) {
1167	.name = "system_noc_clk_src",
1168	.parent_hws = (const struct clk_hw *[]) {
1169	&system_noc_bfdcd_clk_src.clkr.hw,
1170	},
1171	.num_parents = 1,
1172	.ops = &clk_fixed_factor_ops,
1173	.flags = CLK_SET_RATE_PARENT,
1174	},
1175	};
1176
1177	static const struct freq_tbl ftbl_apss_axi_clk_src[] = {
1178	F(400000000, P_GPLL0, 2, 0, 0),
1179	{ }
1180	};
1181
1182	static struct clk_rcg2 ubi0_axi_clk_src = {
1183	.cmd_rcgr = 0x68088,
1184	.freq_tbl = ftbl_apss_axi_clk_src,
1185	.hid_width = 5,
1186	.parent_map = gcc_xo_gpll0_gpll2_map,
1187	.clkr.hw.init = &(struct clk_init_data) {
1188	.name = "ubi0_axi_clk_src",
1189	.parent_data = gcc_xo_gpll0_gpll2,
1190	.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll2),
1191	.ops = &clk_rcg2_ops,
1192	.flags = CLK_SET_RATE_PARENT,
1193	},
1194	};
1195
1196	static const struct freq_tbl ftbl_ubi0_core_clk_src[] = {
1197	F(850000000, P_UBI32_PLL, 1, 0, 0),
1198	F(1000000000, P_UBI32_PLL, 1, 0, 0),
1199	{ }
1200	};
1201
1202	static struct clk_rcg2 ubi0_core_clk_src = {
1203	.cmd_rcgr = 0x68100,
1204	.freq_tbl = ftbl_ubi0_core_clk_src,
1205	.hid_width = 5,
1206	.parent_map = gcc_xo_ubi32_gpll0_map,
1207	.clkr.hw.init = &(struct clk_init_data) {
1208	.name = "ubi0_core_clk_src",
1209	.parent_data = gcc_xo_ubi32_gpll0,
1210	.num_parents = ARRAY_SIZE(gcc_xo_ubi32_gpll0),
1211	.ops = &clk_rcg2_ops,
1212	.flags = CLK_SET_RATE_PARENT,
1213	},
1214	};
1215
1216	static struct clk_rcg2 usb0_aux_clk_src = {
1217	.cmd_rcgr = 0x3e05c,
1218	.freq_tbl = ftbl_pcie0_aux_clk_src,
1219	.mnd_width = 16,
1220	.hid_width = 5,
1221	.parent_map = gcc_xo_gpll0_core_pi_sleep_clk_map,
1222	.clkr.hw.init = &(struct clk_init_data) {
1223	.name = "usb0_aux_clk_src",
1224	.parent_data = gcc_xo_gpll0_core_pi_sleep_clk,
1225	.num_parents = ARRAY_SIZE(gcc_xo_gpll0_core_pi_sleep_clk),
1226	.ops = &clk_rcg2_ops,
1227	},
1228	};
1229
1230	static const struct freq_tbl ftbl_usb0_lfps_clk_src[] = {
1231	F(25000000, P_GPLL0, 16, 1, 2),
1232	{ }
1233	};
1234
1235	static struct clk_rcg2 usb0_lfps_clk_src = {
1236	.cmd_rcgr = 0x3e090,
1237	.freq_tbl = ftbl_usb0_lfps_clk_src,
1238	.mnd_width = 8,
1239	.hid_width = 5,
1240	.parent_map = gcc_xo_gpll0_map,
1241	.clkr.hw.init = &(struct clk_init_data) {
1242	.name = "usb0_lfps_clk_src",
1243	.parent_data = gcc_xo_gpll0,
1244	.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
1245	.ops = &clk_rcg2_ops,
1246	},
1247	};
1248
1249	static struct clk_rcg2 usb0_master_clk_src = {
1250	.cmd_rcgr = 0x3e00c,
1251	.freq_tbl = ftbl_gp_clk_src,
1252	.mnd_width = 8,
1253	.hid_width = 5,
1254	.parent_map = gcc_xo_gpll0_out_main_div2_gpll0_map,
1255	.clkr.hw.init = &(struct clk_init_data) {
1256	.name = "usb0_master_clk_src",
1257	.parent_data = gcc_xo_gpll0_out_main_div2_gpll0,
1258	.num_parents = ARRAY_SIZE(gcc_xo_gpll0_out_main_div2_gpll0),
1259	.ops = &clk_rcg2_ops,
1260	},
1261	};
1262
1263	static const struct freq_tbl ftbl_usb0_mock_utmi_clk_src[] = {
1264	F(60000000, P_GPLL4, 10, 1, 2),
1265	{ }
1266	};
1267
1268	static struct clk_rcg2 usb0_mock_utmi_clk_src = {
1269	.cmd_rcgr = 0x3e020,
1270	.freq_tbl = ftbl_usb0_mock_utmi_clk_src,
1271	.mnd_width = 8,
1272	.hid_width = 5,
1273	.parent_map = gcc_xo_gpll4_gpll0_gpll0_out_main_div2_map2,
1274	.clkr.hw.init = &(struct clk_init_data) {
1275	.name = "usb0_mock_utmi_clk_src",
1276	.parent_data = gcc_xo_gpll4_gpll0_gpll0_out_main_div2,
1277	.num_parents = ARRAY_SIZE(gcc_xo_gpll4_gpll0_gpll0_out_main_div2),
1278	.ops = &clk_rcg2_ops,
1279	},
1280	};
1281
1282	static struct clk_regmap_mux usb0_pipe_clk_src = {
1283	.reg = 0x3e048,
1284	.shift = 8,
1285	.width = 2,
1286	.parent_map = gcc_usb3phy_0_cc_pipe_clk_xo_map,
1287	.clkr = {
1288	.hw.init = &(struct clk_init_data) {
1289	.name = "usb0_pipe_clk_src",
1290	.parent_data = gcc_usb3phy_0_cc_pipe_clk_xo,
1291	.num_parents = ARRAY_SIZE(gcc_usb3phy_0_cc_pipe_clk_xo),
1292	.ops = &clk_regmap_mux_closest_ops,
1293	.flags = CLK_SET_RATE_PARENT,
1294	},
1295	},
1296	};
1297
1298	static const struct freq_tbl ftbl_q6_axi_clk_src[] = {
1299	F(400000000, P_GPLL0, 2, 0, 0),
1300	{ }
1301	};
1302
1303	static struct clk_rcg2 q6_axi_clk_src = {
1304	.cmd_rcgr = 0x59120,
1305	.freq_tbl = ftbl_q6_axi_clk_src,
1306	.hid_width = 5,
1307	.parent_map = gcc_xo_gpll0_gpll2_gpll4_map,
1308	.clkr.hw.init = &(struct clk_init_data) {
1309	.name = "q6_axi_clk_src",
1310	.parent_data = gcc_xo_gpll0_gpll2_gpll4,
1311	.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll2_gpll4),
1312	.ops = &clk_rcg2_ops,
1313	},
1314	};
1315
1316	static const struct freq_tbl ftbl_wcss_ahb_clk_src[] = {
1317	F(133333333, P_GPLL0, 6, 0, 0),
1318	{ }
1319	};
1320
1321	static struct clk_rcg2 wcss_ahb_clk_src = {
1322	.cmd_rcgr = 0x59020,
1323	.freq_tbl = ftbl_wcss_ahb_clk_src,
1324	.hid_width = 5,
1325	.parent_map = gcc_xo_gpll0_map,
1326	.clkr.hw.init = &(struct clk_init_data) {
1327	.name = "wcss_ahb_clk_src",
1328	.parent_data = gcc_xo_gpll0,
1329	.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
1330	.ops = &clk_rcg2_ops,
1331	},
1332	};
1333
1334	static struct clk_branch gcc_sleep_clk_src = {
1335	.halt_reg = 0x30000,
1336	.clkr = {
1337	.enable_reg = 0x30000,
1338	.enable_mask = BIT(1),
1339	.hw.init = &(struct clk_init_data) {
1340	.name = "gcc_sleep_clk_src",
1341	.parent_data = gcc_sleep_clk_data,
1342	.num_parents = ARRAY_SIZE(gcc_sleep_clk_data),
1343	.ops = &clk_branch2_ops,
1344	},
1345	},
1346	};
1347
1348	static struct clk_branch gcc_xo_clk_src = {
1349	.halt_reg = 0x30018,
1350	.clkr = {
1351	.enable_reg = 0x30018,
1352	.enable_mask = BIT(1),
1353	.hw.init = &(struct clk_init_data) {
1354	.name = "gcc_xo_clk_src",
1355	.parent_data = gcc_xo_data,
1356	.num_parents = ARRAY_SIZE(gcc_xo_data),
1357	.flags = CLK_SET_RATE_PARENT,
1358	.ops = &clk_branch2_ops,
1359	},
1360	},
1361	};
1362
1363	static struct clk_branch gcc_xo_clk = {
1364	.halt_reg = 0x30030,
1365	.clkr = {
1366	.enable_reg = 0x30030,
1367	.enable_mask = BIT(0),
1368	.hw.init = &(struct clk_init_data) {
1369	.name = "gcc_xo_clk",
1370	.parent_hws = (const struct clk_hw *[]) {
1371	&gcc_xo_clk_src.clkr.hw,
1372	},
1373	.num_parents = 1,
1374	.flags = CLK_SET_RATE_PARENT,
1375	.ops = &clk_branch2_ops,
1376	},
1377	},
1378	};
1379
1380	static struct clk_branch gcc_adss_pwm_clk = {
1381	.halt_reg = 0x1f020,
1382	.clkr = {
1383	.enable_reg = 0x1f020,
1384	.enable_mask = BIT(0),
1385	.hw.init = &(struct clk_init_data) {
1386	.name = "gcc_adss_pwm_clk",
1387	.parent_hws = (const struct clk_hw *[]) {
1388	&adss_pwm_clk_src.clkr.hw,
1389	},
1390	.num_parents = 1,
1391	.flags = CLK_SET_RATE_PARENT,
1392	.ops = &clk_branch2_ops,
1393	},
1394	},
1395	};
1396
1397	static struct clk_branch gcc_blsp1_ahb_clk = {
1398	.halt_reg = 0x01008,
1399	.halt_check = BRANCH_HALT_VOTED,
1400	.clkr = {
1401	.enable_reg = 0x0b004,
1402	.enable_mask = BIT(10),
1403	.hw.init = &(struct clk_init_data) {
1404	.name = "gcc_blsp1_ahb_clk",
1405	.parent_hws = (const struct clk_hw *[]) {
1406	&pcnoc_clk_src.hw,
1407	},
1408	.num_parents = 1,
1409	.flags = CLK_SET_RATE_PARENT,
1410	.ops = &clk_branch2_ops,
1411	},
1412	},
1413	};
1414
1415	static struct clk_branch gcc_blsp1_qup1_i2c_apps_clk = {
1416	.halt_reg = 0x02008,
1417	.clkr = {
1418	.enable_reg = 0x02008,
1419	.enable_mask = BIT(0),
1420	.hw.init = &(struct clk_init_data) {
1421	.name = "gcc_blsp1_qup1_i2c_apps_clk",
1422	.parent_hws = (const struct clk_hw *[]) {
1423	&blsp1_qup1_i2c_apps_clk_src.clkr.hw,
1424	},
1425	.num_parents = 1,
1426	.flags = CLK_SET_RATE_PARENT,
1427	.ops = &clk_branch2_ops,
1428	},
1429	},
1430	};
1431
1432	static struct clk_branch gcc_blsp1_qup1_spi_apps_clk = {
1433	.halt_reg = 0x02004,
1434	.clkr = {
1435	.enable_reg = 0x02004,
1436	.enable_mask = BIT(0),
1437	.hw.init = &(struct clk_init_data) {
1438	.name = "gcc_blsp1_qup1_spi_apps_clk",
1439	.parent_hws = (const struct clk_hw *[]) {
1440	&blsp1_qup1_spi_apps_clk_src.clkr.hw,
1441	},
1442	.num_parents = 1,
1443	.flags = CLK_SET_RATE_PARENT,
1444	.ops = &clk_branch2_ops,
1445	},
1446	},
1447	};
1448
1449	static struct clk_branch gcc_blsp1_qup2_i2c_apps_clk = {
1450	.halt_reg = 0x03010,
1451	.clkr = {
1452	.enable_reg = 0x03010,
1453	.enable_mask = BIT(0),
1454	.hw.init = &(struct clk_init_data) {
1455	.name = "gcc_blsp1_qup2_i2c_apps_clk",
1456	.parent_hws = (const struct clk_hw *[]) {
1457	&blsp1_qup2_i2c_apps_clk_src.clkr.hw,
1458	},
1459	.num_parents = 1,
1460	.flags = CLK_SET_RATE_PARENT,
1461	.ops = &clk_branch2_ops,
1462	},
1463	},
1464	};
1465
1466	static struct clk_branch gcc_blsp1_qup2_spi_apps_clk = {
1467	.halt_reg = 0x0300c,
1468	.clkr = {
1469	.enable_reg = 0x0300c,
1470	.enable_mask = BIT(0),
1471	.hw.init = &(struct clk_init_data) {
1472	.name = "gcc_blsp1_qup2_spi_apps_clk",
1473	.parent_hws = (const struct clk_hw *[]) {
1474	&blsp1_qup2_spi_apps_clk_src.clkr.hw,
1475	},
1476	.num_parents = 1,
1477	.flags = CLK_SET_RATE_PARENT,
1478	.ops = &clk_branch2_ops,
1479	},
1480	},
1481	};
1482
1483	static struct clk_branch gcc_blsp1_qup3_i2c_apps_clk = {
1484	.halt_reg = 0x04010,
1485	.clkr = {
1486	.enable_reg = 0x04010,
1487	.enable_mask = BIT(0),
1488	.hw.init = &(struct clk_init_data) {
1489	.name = "gcc_blsp1_qup3_i2c_apps_clk",
1490	.parent_hws = (const struct clk_hw *[]) {
1491	&blsp1_qup3_i2c_apps_clk_src.clkr.hw,
1492	},
1493	.num_parents = 1,
1494	.flags = CLK_SET_RATE_PARENT,
1495	.ops = &clk_branch2_ops,
1496	},
1497	},
1498	};
1499
1500	static struct clk_branch gcc_blsp1_qup3_spi_apps_clk = {
1501	.halt_reg = 0x0400c,
1502	.clkr = {
1503	.enable_reg = 0x0400c,
1504	.enable_mask = BIT(0),
1505	.hw.init = &(struct clk_init_data) {
1506	.name = "gcc_blsp1_qup3_spi_apps_clk",
1507	.parent_hws = (const struct clk_hw *[]) {
1508	&blsp1_qup3_spi_apps_clk_src.clkr.hw,
1509	},
1510	.num_parents = 1,
1511	.flags = CLK_SET_RATE_PARENT,
1512	.ops = &clk_branch2_ops,
1513	},
1514	},
1515	};
1516
1517	static struct clk_branch gcc_blsp1_uart1_apps_clk = {
1518	.halt_reg = 0x0203c,
1519	.clkr = {
1520	.enable_reg = 0x0203c,
1521	.enable_mask = BIT(0),
1522	.hw.init = &(struct clk_init_data) {
1523	.name = "gcc_blsp1_uart1_apps_clk",
1524	.parent_hws = (const struct clk_hw *[]) {
1525	&blsp1_uart1_apps_clk_src.clkr.hw,
1526	},
1527	.num_parents = 1,
1528	.flags = CLK_SET_RATE_PARENT,
1529	.ops = &clk_branch2_ops,
1530	},
1531	},
1532	};
1533
1534	static struct clk_branch gcc_blsp1_uart2_apps_clk = {
1535	.halt_reg = 0x0302c,
1536	.clkr = {
1537	.enable_reg = 0x0302c,
1538	.enable_mask = BIT(0),
1539	.hw.init = &(struct clk_init_data) {
1540	.name = "gcc_blsp1_uart2_apps_clk",
1541	.parent_hws = (const struct clk_hw *[]) {
1542	&blsp1_uart2_apps_clk_src.clkr.hw,
1543	},
1544	.num_parents = 1,
1545	.flags = CLK_SET_RATE_PARENT,
1546	.ops = &clk_branch2_ops,
1547	},
1548	},
1549	};
1550
1551	static struct clk_branch gcc_btss_lpo_clk = {
1552	.halt_reg = 0x1c004,
1553	.clkr = {
1554	.enable_reg = 0x1c004,
1555	.enable_mask = BIT(0),
1556	.hw.init = &(struct clk_init_data) {
1557	.name = "gcc_btss_lpo_clk",
1558	.ops = &clk_branch2_ops,
1559	},
1560	},
1561	};
1562
1563	static struct clk_branch gcc_cmn_blk_ahb_clk = {
1564	.halt_reg = 0x56308,
1565	.clkr = {
1566	.enable_reg = 0x56308,
1567	.enable_mask = BIT(0),
1568	.hw.init = &(struct clk_init_data) {
1569	.name = "gcc_cmn_blk_ahb_clk",
1570	.parent_hws = (const struct clk_hw *[]) {
1571	&pcnoc_clk_src.hw,
1572	},
1573	.num_parents = 1,
1574	.flags = CLK_SET_RATE_PARENT,
1575	.ops = &clk_branch2_ops,
1576	},
1577	},
1578	};
1579
1580	static struct clk_branch gcc_cmn_blk_sys_clk = {
1581	.halt_reg = 0x5630c,
1582	.clkr = {
1583	.enable_reg = 0x5630c,
1584	.enable_mask = BIT(0),
1585	.hw.init = &(struct clk_init_data) {
1586	.name = "gcc_cmn_blk_sys_clk",
1587	.parent_hws = (const struct clk_hw *[]) {
1588	&gcc_xo_clk_src.clkr.hw,
1589	},
1590	.num_parents = 1,
1591	.flags = CLK_SET_RATE_PARENT,
1592	.ops = &clk_branch2_ops,
1593	},
1594	},
1595	};
1596
1597	static struct clk_branch gcc_crypto_ahb_clk = {
1598	.halt_reg = 0x16024,
1599	.halt_check = BRANCH_HALT_VOTED,
1600	.clkr = {
1601	.enable_reg = 0x0b004,
1602	.enable_mask = BIT(0),
1603	.hw.init = &(struct clk_init_data) {
1604	.name = "gcc_crypto_ahb_clk",
1605	.parent_hws = (const struct clk_hw *[]) {
1606	&pcnoc_clk_src.hw,
1607	},
1608	.num_parents = 1,
1609	.flags = CLK_SET_RATE_PARENT,
1610	.ops = &clk_branch2_ops,
1611	},
1612	},
1613	};
1614
1615	static struct clk_branch gcc_crypto_axi_clk = {
1616	.halt_reg = 0x16020,
1617	.halt_check = BRANCH_HALT_VOTED,
1618	.clkr = {
1619	.enable_reg = 0x0b004,
1620	.enable_mask = BIT(1),
1621	.hw.init = &(struct clk_init_data) {
1622	.name = "gcc_crypto_axi_clk",
1623	.parent_hws = (const struct clk_hw *[]) {
1624	&pcnoc_clk_src.hw,
1625	},
1626	.num_parents = 1,
1627	.flags = CLK_SET_RATE_PARENT,
1628	.ops = &clk_branch2_ops,
1629	},
1630	},
1631	};
1632
1633	static struct clk_branch gcc_crypto_clk = {
1634	.halt_reg = 0x1601c,
1635	.halt_check = BRANCH_HALT_VOTED,
1636	.clkr = {
1637	.enable_reg = 0x0b004,
1638	.enable_mask = BIT(2),
1639	.hw.init = &(struct clk_init_data) {
1640	.name = "gcc_crypto_clk",
1641	.parent_hws = (const struct clk_hw *[]) {
1642	&crypto_clk_src.clkr.hw,
1643	},
1644	.num_parents = 1,
1645	.flags = CLK_SET_RATE_PARENT,
1646	.ops = &clk_branch2_ops,
1647	},
1648	},
1649	};
1650
1651	static struct clk_branch gcc_dcc_clk = {
1652	.halt_reg = 0x77004,
1653	.clkr = {
1654	.enable_reg = 0x77004,
1655	.enable_mask = BIT(0),
1656	.hw.init = &(struct clk_init_data) {
1657	.name = "gcc_dcc_clk",
1658	.parent_hws = (const struct clk_hw *[]) {
1659	&pcnoc_clk_src.hw,
1660	},
1661	.num_parents = 1,
1662	.flags = CLK_SET_RATE_PARENT,
1663	.ops = &clk_branch2_ops,
1664	},
1665	},
1666	};
1667
1668	static struct clk_branch gcc_gephy_rx_clk = {
1669	.halt_reg = 0x56010,
1670	.halt_check = BRANCH_HALT_DELAY,
1671	.clkr = {
1672	.enable_reg = 0x56010,
1673	.enable_mask = BIT(0),
1674	.hw.init = &(struct clk_init_data) {
1675	.name = "gcc_gephy_rx_clk",
1676	.parent_hws = (const struct clk_hw *[]) {
1677	&gmac0_rx_div_clk_src.clkr.hw,
1678	},
1679	.num_parents = 1,
1680	.ops = &clk_branch2_ops,
1681	.flags = CLK_SET_RATE_PARENT,
1682	},
1683	},
1684	};
1685
1686	static struct clk_branch gcc_gephy_tx_clk = {
1687	.halt_reg = 0x56014,
1688	.halt_check = BRANCH_HALT_DELAY,
1689	.clkr = {
1690	.enable_reg = 0x56014,
1691	.enable_mask = BIT(0),
1692	.hw.init = &(struct clk_init_data) {
1693	.name = "gcc_gephy_tx_clk",
1694	.parent_hws = (const struct clk_hw *[]) {
1695	&gmac0_tx_div_clk_src.clkr.hw,
1696	},
1697	.num_parents = 1,
1698	.ops = &clk_branch2_ops,
1699	.flags = CLK_SET_RATE_PARENT,
1700	},
1701	},
1702	};
1703
1704	static struct clk_branch gcc_gmac0_cfg_clk = {
1705	.halt_reg = 0x68304,
1706	.clkr = {
1707	.enable_reg = 0x68304,
1708	.enable_mask = BIT(0),
1709	.hw.init = &(struct clk_init_data) {
1710	.name = "gcc_gmac0_cfg_clk",
1711	.parent_hws = (const struct clk_hw *[]) {
1712	&gmac_clk_src.clkr.hw,
1713	},
1714	.num_parents = 1,
1715	.flags = CLK_SET_RATE_PARENT,
1716	.ops = &clk_branch2_ops,
1717	},
1718	},
1719	};
1720
1721	static struct clk_branch gcc_gmac0_ptp_clk = {
1722	.halt_reg = 0x68300,
1723	.clkr = {
1724	.enable_reg = 0x68300,
1725	.enable_mask = BIT(0),
1726	.hw.init = &(struct clk_init_data) {
1727	.name = "gcc_gmac0_ptp_clk",
1728	.parent_hws = (const struct clk_hw *[]) {
1729	&gmac_clk_src.clkr.hw,
1730	},
1731	.num_parents = 1,
1732	.flags = CLK_SET_RATE_PARENT,
1733	.ops = &clk_branch2_ops,
1734	},
1735	},
1736	};
1737
1738	static struct clk_branch gcc_gmac0_rx_clk = {
1739	.halt_reg = 0x68240,
1740	.clkr = {
1741	.enable_reg = 0x68240,
1742	.enable_mask = BIT(0),
1743	.hw.init = &(struct clk_init_data) {
1744	.name = "gcc_gmac0_rx_clk",
1745	.parent_hws = (const struct clk_hw *[]) {
1746	&gmac0_rx_div_clk_src.clkr.hw,
1747	},
1748	.num_parents = 1,
1749	.ops = &clk_branch2_ops,
1750	.flags = CLK_SET_RATE_PARENT,
1751	},
1752	},
1753	};
1754
1755	static struct clk_branch gcc_gmac0_sys_clk = {
1756	.halt_reg = 0x68190,
1757	.halt_check = BRANCH_HALT_DELAY,
1758	.halt_bit = 31,
1759	.clkr = {
1760	.enable_reg = 0x68190,
1761	.enable_mask = BIT(0),
1762	.hw.init = &(struct clk_init_data) {
1763	.name = "gcc_gmac0_sys_clk",
1764	.parent_hws = (const struct clk_hw *[]) {
1765	&gmac_clk_src.clkr.hw,
1766	},
1767	.num_parents = 1,
1768	.flags = CLK_SET_RATE_PARENT,
1769	.ops = &clk_branch2_ops,
1770	},
1771	},
1772	};
1773
1774	static struct clk_branch gcc_gmac0_tx_clk = {
1775	.halt_reg = 0x68244,
1776	.clkr = {
1777	.enable_reg = 0x68244,
1778	.enable_mask = BIT(0),
1779	.hw.init = &(struct clk_init_data) {
1780	.name = "gcc_gmac0_tx_clk",
1781	.parent_hws = (const struct clk_hw *[]) {
1782	&gmac0_tx_div_clk_src.clkr.hw,
1783	},
1784	.num_parents = 1,
1785	.ops = &clk_branch2_ops,
1786	.flags = CLK_SET_RATE_PARENT,
1787	},
1788	},
1789	};
1790
1791	static struct clk_branch gcc_gmac1_cfg_clk = {
1792	.halt_reg = 0x68324,
1793	.clkr = {
1794	.enable_reg = 0x68324,
1795	.enable_mask = BIT(0),
1796	.hw.init = &(struct clk_init_data) {
1797	.name = "gcc_gmac1_cfg_clk",
1798	.parent_hws = (const struct clk_hw *[]) {
1799	&gmac_clk_src.clkr.hw,
1800	},
1801	.num_parents = 1,
1802	.flags = CLK_SET_RATE_PARENT,
1803	.ops = &clk_branch2_ops,
1804	},
1805	},
1806	};
1807
1808	static struct clk_branch gcc_gmac1_ptp_clk = {
1809	.halt_reg = 0x68320,
1810	.clkr = {
1811	.enable_reg = 0x68320,
1812	.enable_mask = BIT(0),
1813	.hw.init = &(struct clk_init_data) {
1814	.name = "gcc_gmac1_ptp_clk",
1815	.parent_hws = (const struct clk_hw *[]) {
1816	&gmac_clk_src.clkr.hw,
1817	},
1818	.num_parents = 1,
1819	.flags = CLK_SET_RATE_PARENT,
1820	.ops = &clk_branch2_ops,
1821	},
1822	},
1823	};
1824
1825	static struct clk_branch gcc_gmac1_rx_clk = {
1826	.halt_reg = 0x68248,
1827	.clkr = {
1828	.enable_reg = 0x68248,
1829	.enable_mask = BIT(0),
1830	.hw.init = &(struct clk_init_data) {
1831	.name = "gcc_gmac1_rx_clk",
1832	.parent_hws = (const struct clk_hw *[]) {
1833	&gmac1_rx_div_clk_src.clkr.hw,
1834	},
1835	.num_parents = 1,
1836	.ops = &clk_branch2_ops,
1837	.flags = CLK_SET_RATE_PARENT,
1838	},
1839	},
1840	};
1841
1842	static struct clk_branch gcc_gmac1_sys_clk = {
1843	.halt_reg = 0x68310,
1844	.clkr = {
1845	.enable_reg = 0x68310,
1846	.enable_mask = BIT(0),
1847	.hw.init = &(struct clk_init_data) {
1848	.name = "gcc_gmac1_sys_clk",
1849	.parent_hws = (const struct clk_hw *[]) {
1850	&gmac_clk_src.clkr.hw,
1851	},
1852	.num_parents = 1,
1853	.flags = CLK_SET_RATE_PARENT,
1854	.ops = &clk_branch2_ops,
1855	},
1856	},
1857	};
1858
1859	static struct clk_branch gcc_gmac1_tx_clk = {
1860	.halt_reg = 0x6824c,
1861	.clkr = {
1862	.enable_reg = 0x6824c,
1863	.enable_mask = BIT(0),
1864	.hw.init = &(struct clk_init_data) {
1865	.name = "gcc_gmac1_tx_clk",
1866	.parent_hws = (const struct clk_hw *[]) {
1867	&gmac1_tx_div_clk_src.clkr.hw,
1868	},
1869	.num_parents = 1,
1870	.ops = &clk_branch2_ops,
1871	.flags = CLK_SET_RATE_PARENT,
1872	},
1873	},
1874	};
1875
1876	static struct clk_branch gcc_gp1_clk = {
1877	.halt_reg = 0x08000,
1878	.clkr = {
1879	.enable_reg = 0x08000,
1880	.enable_mask = BIT(0),
1881	.hw.init = &(struct clk_init_data) {
1882	.name = "gcc_gp1_clk",
1883	.parent_hws = (const struct clk_hw *[]) {
1884	&gp1_clk_src.clkr.hw,
1885	},
1886	.num_parents = 1,
1887	.flags = CLK_SET_RATE_PARENT,
1888	.ops = &clk_branch2_ops,
1889	},
1890	},
1891	};
1892
1893	static struct clk_branch gcc_gp2_clk = {
1894	.halt_reg = 0x09000,
1895	.clkr = {
1896	.enable_reg = 0x09000,
1897	.enable_mask = BIT(0),
1898	.hw.init = &(struct clk_init_data) {
1899	.name = "gcc_gp2_clk",
1900	.parent_hws = (const struct clk_hw *[]) {
1901	&gp2_clk_src.clkr.hw,
1902	},
1903	.num_parents = 1,
1904	.flags = CLK_SET_RATE_PARENT,
1905	.ops = &clk_branch2_ops,
1906	},
1907	},
1908	};
1909
1910	static struct clk_branch gcc_gp3_clk = {
1911	.halt_reg = 0x0a000,
1912	.clkr = {
1913	.enable_reg = 0x0a000,
1914	.enable_mask = BIT(0),
1915	.hw.init = &(struct clk_init_data) {
1916	.name = "gcc_gp3_clk",
1917	.parent_hws = (const struct clk_hw *[]) {
1918	&gp3_clk_src.clkr.hw,
1919	},
1920	.num_parents = 1,
1921	.flags = CLK_SET_RATE_PARENT,
1922	.ops = &clk_branch2_ops,
1923	},
1924	},
1925	};
1926
1927	static struct clk_branch gcc_lpass_core_axim_clk = {
1928	.halt_reg = 0x2e048,
1929	.halt_check = BRANCH_VOTED,
1930	.clkr = {
1931	.enable_reg = 0x2e048,
1932	.enable_mask = BIT(0),
1933	.hw.init = &(struct clk_init_data) {
1934	.name = "gcc_lpass_core_axim_clk",
1935	.parent_hws = (const struct clk_hw *[]) {
1936	&lpass_axim_clk_src.clkr.hw,
1937	},
1938	.num_parents = 1,
1939	.flags = CLK_SET_RATE_PARENT,
1940	.ops = &clk_branch2_ops,
1941	},
1942	},
1943	};
1944
1945	static struct clk_branch gcc_lpass_sway_clk = {
1946	.halt_reg = 0x2e04c,
1947	.clkr = {
1948	.enable_reg = 0x2e04c,
1949	.enable_mask = BIT(0),
1950	.hw.init = &(struct clk_init_data) {
1951	.name = "gcc_lpass_sway_clk",
1952	.parent_hws = (const struct clk_hw *[]) {
1953	&lpass_sway_clk_src.clkr.hw,
1954	},
1955	.num_parents = 1,
1956	.flags = CLK_SET_RATE_PARENT,
1957	.ops = &clk_branch2_ops,
1958	},
1959	},
1960	};
1961
1962	static struct clk_branch gcc_mdio0_ahb_clk = {
1963	.halt_reg = 0x58004,
1964	.clkr = {
1965	.enable_reg = 0x58004,
1966	.enable_mask = BIT(0),
1967	.hw.init = &(struct clk_init_data) {
1968	.name = "gcc_mdioi0_ahb_clk",
1969	.parent_hws = (const struct clk_hw *[]) {
1970	&pcnoc_clk_src.hw,
1971	},
1972	.num_parents = 1,
1973	.flags = CLK_SET_RATE_PARENT,
1974	.ops = &clk_branch2_ops,
1975	},
1976	},
1977	};
1978
1979	static struct clk_branch gcc_mdio1_ahb_clk = {
1980	.halt_reg = 0x58014,
1981	.clkr = {
1982	.enable_reg = 0x58014,
1983	.enable_mask = BIT(0),
1984	.hw.init = &(struct clk_init_data) {
1985	.name = "gcc_mdio1_ahb_clk",
1986	.parent_hws = (const struct clk_hw *[]) {
1987	&pcnoc_clk_src.hw,
1988	},
1989	.num_parents = 1,
1990	.flags = CLK_SET_RATE_PARENT,
1991	.ops = &clk_branch2_ops,
1992	},
1993	},
1994	};
1995
1996	static struct clk_branch gcc_pcie0_ahb_clk = {
1997	.halt_reg = 0x75010,
1998	.clkr = {
1999	.enable_reg = 0x75010,
2000	.enable_mask = BIT(0),
2001	.hw.init = &(struct clk_init_data) {
2002	.name = "gcc_pcie0_ahb_clk",
2003	.parent_hws = (const struct clk_hw *[]) {
2004	&pcnoc_clk_src.hw,
2005	},
2006	.num_parents = 1,
2007	.flags = CLK_SET_RATE_PARENT,
2008	.ops = &clk_branch2_ops,
2009	},
2010	},
2011	};
2012
2013	static struct clk_branch gcc_pcie0_aux_clk = {
2014	.halt_reg = 0x75014,
2015	.clkr = {
2016	.enable_reg = 0x75014,
2017	.enable_mask = BIT(0),
2018	.hw.init = &(struct clk_init_data) {
2019	.name = "gcc_pcie0_aux_clk",
2020	.parent_hws = (const struct clk_hw *[]) {
2021	&pcie0_aux_clk_src.clkr.hw,
2022	},
2023	.num_parents = 1,
2024	.flags = CLK_SET_RATE_PARENT,
2025	.ops = &clk_branch2_ops,
2026	},
2027	},
2028	};
2029
2030	static struct clk_branch gcc_pcie0_axi_m_clk = {
2031	.halt_reg = 0x75008,
2032	.clkr = {
2033	.enable_reg = 0x75008,
2034	.enable_mask = BIT(0),
2035	.hw.init = &(struct clk_init_data) {
2036	.name = "gcc_pcie0_axi_m_clk",
2037	.parent_hws = (const struct clk_hw *[]) {
2038	&pcie0_axi_clk_src.clkr.hw,
2039	},
2040	.num_parents = 1,
2041	.flags = CLK_SET_RATE_PARENT,
2042	.ops = &clk_branch2_ops,
2043	},
2044	},
2045	};
2046
2047	static struct clk_branch gcc_pcie0_axi_s_bridge_clk = {
2048	.halt_reg = 0x75048,
2049	.clkr = {
2050	.enable_reg = 0x75048,
2051	.enable_mask = BIT(0),
2052	.hw.init = &(struct clk_init_data) {
2053	.name = "gcc_pcie0_axi_s_bridge_clk",
2054	.parent_hws = (const struct clk_hw *[]) {
2055	&pcie0_axi_clk_src.clkr.hw,
2056	},
2057	.num_parents = 1,
2058	.flags = CLK_SET_RATE_PARENT,
2059	.ops = &clk_branch2_ops,
2060	},
2061	},
2062	};
2063
2064	static struct clk_branch gcc_pcie0_axi_s_clk = {
2065	.halt_reg = 0x7500c,
2066	.clkr = {
2067	.enable_reg = 0x7500c,
2068	.enable_mask = BIT(0),
2069	.hw.init = &(struct clk_init_data) {
2070	.name = "gcc_pcie0_axi_s_clk",
2071	.parent_hws = (const struct clk_hw *[]) {
2072	&pcie0_axi_clk_src.clkr.hw,
2073	},
2074	.num_parents = 1,
2075	.flags = CLK_SET_RATE_PARENT,
2076	.ops = &clk_branch2_ops,
2077	},
2078	},
2079	};
2080
2081	static struct clk_branch gcc_pcie0_pipe_clk = {
2082	.halt_reg = 0x75018,
2083	.halt_check = BRANCH_HALT_DELAY,
2084	.halt_bit = 31,
2085	.clkr = {
2086	.enable_reg = 0x75018,
2087	.enable_mask = BIT(0),
2088	.hw.init = &(struct clk_init_data) {
2089	.name = "gcc_pcie0_pipe_clk",
2090	.parent_hws = (const struct clk_hw *[]) {
2091	&pcie0_pipe_clk_src.clkr.hw,
2092	},
2093	.num_parents = 1,
2094	.flags = CLK_SET_RATE_PARENT,
2095	.ops = &clk_branch2_ops,
2096	},
2097	},
2098	};
2099
2100	static struct clk_branch gcc_pcie1_ahb_clk = {
2101	.halt_reg = 0x76010,
2102	.clkr = {
2103	.enable_reg = 0x76010,
2104	.enable_mask = BIT(0),
2105	.hw.init = &(struct clk_init_data) {
2106	.name = "gcc_pcie1_ahb_clk",
2107	.parent_hws = (const struct clk_hw *[]) {
2108	&pcnoc_clk_src.hw,
2109	},
2110	.num_parents = 1,
2111	.flags = CLK_SET_RATE_PARENT,
2112	.ops = &clk_branch2_ops,
2113	},
2114	},
2115	};
2116
2117	static struct clk_branch gcc_pcie1_aux_clk = {
2118	.halt_reg = 0x76014,
2119	.clkr = {
2120	.enable_reg = 0x76014,
2121	.enable_mask = BIT(0),
2122	.hw.init = &(struct clk_init_data) {
2123	.name = "gcc_pcie1_aux_clk",
2124	.parent_hws = (const struct clk_hw *[]) {
2125	&pcie1_aux_clk_src.clkr.hw,
2126	},
2127	.num_parents = 1,
2128	.flags = CLK_SET_RATE_PARENT,
2129	.ops = &clk_branch2_ops,
2130	},
2131	},
2132	};
2133
2134	static struct clk_branch gcc_pcie1_axi_m_clk = {
2135	.halt_reg = 0x76008,
2136	.clkr = {
2137	.enable_reg = 0x76008,
2138	.enable_mask = BIT(0),
2139	.hw.init = &(struct clk_init_data) {
2140	.name = "gcc_pcie1_axi_m_clk",
2141	.parent_hws = (const struct clk_hw *[]) {
2142	&pcie1_axi_clk_src.clkr.hw,
2143	},
2144	.num_parents = 1,
2145	.flags = CLK_SET_RATE_PARENT,
2146	.ops = &clk_branch2_ops,
2147	},
2148	},
2149	};
2150
2151	static struct clk_branch gcc_pcie1_axi_s_bridge_clk = {
2152	.halt_reg = 0x76048,
2153	.clkr = {
2154	.enable_reg = 0x76048,
2155	.enable_mask = BIT(0),
2156	.hw.init = &(struct clk_init_data) {
2157	.name = "gcc_pcie1_axi_s_bridge_clk",
2158	.parent_hws = (const struct clk_hw *[]) {
2159	&pcie1_axi_clk_src.clkr.hw,
2160	},
2161	.num_parents = 1,
2162	.flags = CLK_SET_RATE_PARENT,
2163	.ops = &clk_branch2_ops,
2164	},
2165	},
2166	};
2167
2168	static struct clk_branch gcc_pcie1_axi_s_clk = {
2169	.halt_reg = 0x7600c,
2170	.clkr = {
2171	.enable_reg = 0x7600c,
2172	.enable_mask = BIT(0),
2173	.hw.init = &(struct clk_init_data) {
2174	.name = "gcc_pcie1_axi_s_clk",
2175	.parent_hws = (const struct clk_hw *[]) {
2176	&pcie1_axi_clk_src.clkr.hw,
2177	},
2178	.num_parents = 1,
2179	.flags = CLK_SET_RATE_PARENT,
2180	.ops = &clk_branch2_ops,
2181	},
2182	},
2183	};
2184
2185	static struct clk_branch gcc_pcie1_pipe_clk = {
2186	.halt_reg = 0x76018,
2187	.halt_check = BRANCH_HALT_DELAY,
2188	.halt_bit = 31,
2189	.clkr = {
2190	.enable_reg = 0x76018,
2191	.enable_mask = BIT(0),
2192	.hw.init = &(struct clk_init_data) {
2193	.name = "gcc_pcie1_pipe_clk",
2194	.parent_hws = (const struct clk_hw *[]) {
2195	&pcie1_pipe_clk_src.clkr.hw,
2196	},
2197	.num_parents = 1,
2198	.flags = CLK_SET_RATE_PARENT,
2199	.ops = &clk_branch2_ops,
2200	},
2201	},
2202	};
2203
2204	static struct clk_branch gcc_prng_ahb_clk = {
2205	.halt_reg = 0x13004,
2206	.halt_check = BRANCH_HALT_VOTED,
2207	.clkr = {
2208	.enable_reg = 0x0b004,
2209	.enable_mask = BIT(8),
2210	.hw.init = &(struct clk_init_data) {
2211	.name = "gcc_prng_ahb_clk",
2212	.parent_hws = (const struct clk_hw *[]) {
2213	&pcnoc_clk_src.hw,
2214	},
2215	.num_parents = 1,
2216	.flags = CLK_SET_RATE_PARENT,
2217	.ops = &clk_branch2_ops,
2218	},
2219	},
2220	};
2221
2222	static struct clk_branch gcc_q6_ahb_clk = {
2223	.halt_reg = 0x59138,
2224	.clkr = {
2225	.enable_reg = 0x59138,
2226	.enable_mask = BIT(0),
2227	.hw.init = &(struct clk_init_data) {
2228	.name = "gcc_q6_ahb_clk",
2229	.parent_hws = (const struct clk_hw *[]) {
2230	&wcss_ahb_clk_src.clkr.hw,
2231	},
2232	.num_parents = 1,
2233	.flags = CLK_SET_RATE_PARENT,
2234	.ops = &clk_branch2_ops,
2235	},
2236	},
2237	};
2238
2239	static struct clk_branch gcc_q6_ahb_s_clk = {
2240	.halt_reg = 0x5914c,
2241	.clkr = {
2242	.enable_reg = 0x5914c,
2243	.enable_mask = BIT(0),
2244	.hw.init = &(struct clk_init_data) {
2245	.name = "gcc_q6_ahb_s_clk",
2246	.parent_hws = (const struct clk_hw *[]) {
2247	&wcss_ahb_clk_src.clkr.hw,
2248	},
2249	.num_parents = 1,
2250	.flags = CLK_SET_RATE_PARENT,
2251	.ops = &clk_branch2_ops,
2252	},
2253	},
2254	};
2255
2256	static struct clk_branch gcc_q6_axim_clk = {
2257	.halt_reg = 0x5913c,
2258	.clkr = {
2259	.enable_reg = 0x5913c,
2260	.enable_mask = BIT(0),
2261	.hw.init = &(struct clk_init_data) {
2262	.name = "gcc_q6_axim_clk",
2263	.parent_hws = (const struct clk_hw *[]) {
2264	&q6_axi_clk_src.clkr.hw,
2265	},
2266	.num_parents = 1,
2267	.flags = CLK_SET_RATE_PARENT,
2268	.ops = &clk_branch2_ops,
2269	},
2270	},
2271	};
2272
2273	static struct clk_branch gcc_q6_axim2_clk = {
2274	.halt_reg = 0x59150,
2275	.clkr = {
2276	.enable_reg = 0x59150,
2277	.enable_mask = BIT(0),
2278	.hw.init = &(struct clk_init_data) {
2279	.name = "gcc_q6_axim2_clk",
2280	.parent_hws = (const struct clk_hw *[]) {
2281	&q6_axi_clk_src.clkr.hw,
2282	},
2283	.num_parents = 1,
2284	.flags = CLK_SET_RATE_PARENT,
2285	.ops = &clk_branch2_ops,
2286	},
2287	},
2288	};
2289
2290	static struct clk_branch gcc_q6_axis_clk = {
2291	.halt_reg = 0x59154,
2292	.clkr = {
2293	.enable_reg = 0x59154,
2294	.enable_mask = BIT(0),
2295	.hw.init = &(struct clk_init_data) {
2296	.name = "gcc_q6_axis_clk",
2297	.parent_hws = (const struct clk_hw *[]) {
2298	&system_noc_clk_src.hw,
2299	},
2300	.num_parents = 1,
2301	.flags = CLK_SET_RATE_PARENT,
2302	.ops = &clk_branch2_ops,
2303	},
2304	},
2305	};
2306
2307	static struct clk_branch gcc_q6_tsctr_1to2_clk = {
2308	.halt_reg = 0x59148,
2309	.clkr = {
2310	.enable_reg = 0x59148,
2311	.enable_mask = BIT(0),
2312	.hw.init = &(struct clk_init_data) {
2313	.name = "gcc_q6_tsctr_1to2_clk",
2314	.parent_hws = (const struct clk_hw *[]) {
2315	&qdss_tsctr_div2_clk_src.hw,
2316	},
2317	.num_parents = 1,
2318	.flags = CLK_SET_RATE_PARENT,
2319	.ops = &clk_branch2_ops,
2320	},
2321	},
2322	};
2323
2324	static struct clk_branch gcc_q6ss_atbm_clk = {
2325	.halt_reg = 0x59144,
2326	.clkr = {
2327	.enable_reg = 0x59144,
2328	.enable_mask = BIT(0),
2329	.hw.init = &(struct clk_init_data) {
2330	.name = "gcc_q6ss_atbm_clk",
2331	.parent_hws = (const struct clk_hw *[]) {
2332	&qdss_at_clk_src.clkr.hw,
2333	},
2334	.num_parents = 1,
2335	.flags = CLK_SET_RATE_PARENT,
2336	.ops = &clk_branch2_ops,
2337	},
2338	},
2339	};
2340
2341	static struct clk_branch gcc_q6ss_pclkdbg_clk = {
2342	.halt_reg = 0x59140,
2343	.clkr = {
2344	.enable_reg = 0x59140,
2345	.enable_mask = BIT(0),
2346	.hw.init = &(struct clk_init_data) {
2347	.name = "gcc_q6ss_pclkdbg_clk",
2348	.parent_hws = (const struct clk_hw *[]) {
2349	&qdss_dap_sync_clk_src.hw,
2350	},
2351	.num_parents = 1,
2352	.flags = CLK_SET_RATE_PARENT,
2353	.ops = &clk_branch2_ops,
2354	},
2355	},
2356	};
2357
2358	static struct clk_branch gcc_q6ss_trig_clk = {
2359	.halt_reg = 0x59128,
2360	.clkr = {
2361	.enable_reg = 0x59128,
2362	.enable_mask = BIT(0),
2363	.hw.init = &(struct clk_init_data) {
2364	.name = "gcc_q6ss_trig_clk",
2365	.parent_hws = (const struct clk_hw *[]) {
2366	&qdss_dap_sync_clk_src.hw,
2367	},
2368	.num_parents = 1,
2369	.flags = CLK_SET_RATE_PARENT,
2370	.ops = &clk_branch2_ops,
2371	},
2372	},
2373	};
2374
2375	static struct clk_branch gcc_qdss_at_clk = {
2376	.halt_reg = 0x29024,
2377	.clkr = {
2378	.enable_reg = 0x29024,
2379	.enable_mask = BIT(0),
2380	.hw.init = &(struct clk_init_data) {
2381	.name = "gcc_qdss_at_clk",
2382	.parent_hws = (const struct clk_hw *[]) {
2383	&qdss_at_clk_src.clkr.hw,
2384	},
2385	.num_parents = 1,
2386	.flags = CLK_SET_RATE_PARENT,
2387	.ops = &clk_branch2_ops,
2388	},
2389	},
2390	};
2391
2392	static struct clk_branch gcc_qdss_dap_clk = {
2393	.halt_reg = 0x29084,
2394	.clkr = {
2395	.enable_reg = 0x29084,
2396	.enable_mask = BIT(0),
2397	.hw.init = &(struct clk_init_data) {
2398	.name = "gcc_qdss_dap_clk",
2399	.parent_hws = (const struct clk_hw *[]) {
2400	&qdss_tsctr_clk_src.clkr.hw,
2401	},
2402	.num_parents = 1,
2403	.flags = CLK_SET_RATE_PARENT,
2404	.ops = &clk_branch2_ops,
2405	},
2406	},
2407	};
2408
2409	static struct clk_branch gcc_qdss_cfg_ahb_clk = {
2410	.halt_reg = 0x29008,
2411	.clkr = {
2412	.enable_reg = 0x29008,
2413	.enable_mask = BIT(0),
2414	.hw.init = &(struct clk_init_data) {
2415	.name = "gcc_qdss_cfg_ahb_clk",
2416	.parent_hws = (const struct clk_hw *[]) {
2417	&pcnoc_clk_src.hw,
2418	},
2419	.num_parents = 1,
2420	.flags = CLK_SET_RATE_PARENT,
2421	.ops = &clk_branch2_ops,
2422	},
2423	},
2424	};
2425
2426	static struct clk_branch gcc_qdss_dap_ahb_clk = {
2427	.halt_reg = 0x29004,
2428	.clkr = {
2429	.enable_reg = 0x29004,
2430	.enable_mask = BIT(0),
2431	.hw.init = &(struct clk_init_data) {
2432	.name = "gcc_qdss_dap_ahb_clk",
2433	.parent_hws = (const struct clk_hw *[]) {
2434	&pcnoc_clk_src.hw,
2435	},
2436	.num_parents = 1,
2437	.flags = CLK_SET_RATE_PARENT,
2438	.ops = &clk_branch2_ops,
2439	},
2440	},
2441	};
2442
2443	static struct clk_branch gcc_qdss_etr_usb_clk = {
2444	.halt_reg = 0x29028,
2445	.clkr = {
2446	.enable_reg = 0x29028,
2447	.enable_mask = BIT(0),
2448	.hw.init = &(struct clk_init_data) {
2449	.name = "gcc_qdss_etr_usb_clk",
2450	.parent_hws = (const struct clk_hw *[]) {
2451	&system_noc_clk_src.hw,
2452	},
2453	.num_parents = 1,
2454	.flags = CLK_SET_RATE_PARENT,
2455	.ops = &clk_branch2_ops,
2456	},
2457	},
2458	};
2459
2460	static struct clk_branch gcc_qdss_eud_at_clk = {
2461	.halt_reg = 0x29020,
2462	.clkr = {
2463	.enable_reg = 0x29020,
2464	.enable_mask = BIT(0),
2465	.hw.init = &(struct clk_init_data) {
2466	.name = "gcc_qdss_eud_at_clk",
2467	.parent_hws = (const struct clk_hw *[]) {
2468	&eud_at_clk_src.hw,
2469	},
2470	.num_parents = 1,
2471	.flags = CLK_SET_RATE_PARENT,
2472	.ops = &clk_branch2_ops,
2473	},
2474	},
2475	};
2476
2477	static struct clk_branch gcc_qdss_stm_clk = {
2478	.halt_reg = 0x29044,
2479	.clkr = {
2480	.enable_reg = 0x29044,
2481	.enable_mask = BIT(0),
2482	.hw.init = &(struct clk_init_data) {
2483	.name = "gcc_qdss_stm_clk",
2484	.parent_hws = (const struct clk_hw *[]) {
2485	&qdss_stm_clk_src.clkr.hw,
2486	},
2487	.num_parents = 1,
2488	.flags = CLK_SET_RATE_PARENT,
2489	.ops = &clk_branch2_ops,
2490	},
2491	},
2492	};
2493
2494	static struct clk_branch gcc_qdss_traceclkin_clk = {
2495	.halt_reg = 0x29060,
2496	.clkr = {
2497	.enable_reg = 0x29060,
2498	.enable_mask = BIT(0),
2499	.hw.init = &(struct clk_init_data) {
2500	.name = "gcc_qdss_traceclkin_clk",
2501	.parent_hws = (const struct clk_hw *[]) {
2502	&qdss_traceclkin_clk_src.clkr.hw,
2503	},
2504	.num_parents = 1,
2505	.flags = CLK_SET_RATE_PARENT,
2506	.ops = &clk_branch2_ops,
2507	},
2508	},
2509	};
2510
2511	static struct clk_branch gcc_qdss_tsctr_div8_clk = {
2512	.halt_reg = 0x2908c,
2513	.clkr = {
2514	.enable_reg = 0x2908c,
2515	.enable_mask = BIT(0),
2516	.hw.init = &(struct clk_init_data) {
2517	.name = "gcc_qdss_tsctr_div8_clk",
2518	.parent_hws = (const struct clk_hw *[]) {
2519	&qdss_tsctr_clk_src.clkr.hw,
2520	},
2521	.num_parents = 1,
2522	.flags = CLK_SET_RATE_PARENT,
2523	.ops = &clk_branch2_ops,
2524	},
2525	},
2526	};
2527
2528	static struct clk_branch gcc_qpic_ahb_clk = {
2529	.halt_reg = 0x57024,
2530	.clkr = {
2531	.enable_reg = 0x57024,
2532	.enable_mask = BIT(0),
2533	.hw.init = &(struct clk_init_data) {
2534	.name = "gcc_qpic_ahb_clk",
2535	.parent_hws = (const struct clk_hw *[]) {
2536	&pcnoc_clk_src.hw,
2537	},
2538	.num_parents = 1,
2539	.flags = CLK_SET_RATE_PARENT,
2540	.ops = &clk_branch2_ops,
2541	},
2542	},
2543	};
2544
2545	static struct clk_branch gcc_qpic_clk = {
2546	.halt_reg = 0x57020,
2547	.clkr = {
2548	.enable_reg = 0x57020,
2549	.enable_mask = BIT(0),
2550	.hw.init = &(struct clk_init_data) {
2551	.name = "gcc_qpic_clk",
2552	.parent_hws = (const struct clk_hw *[]) {
2553	&pcnoc_clk_src.hw,
2554	},
2555	.num_parents = 1,
2556	.flags = CLK_SET_RATE_PARENT,
2557	.ops = &clk_branch2_ops,
2558	},
2559	},
2560	};
2561
2562	static struct clk_branch gcc_qpic_io_macro_clk = {
2563	.halt_reg = 0x5701c,
2564	.clkr = {
2565	.enable_reg = 0x5701c,
2566	.enable_mask = BIT(0),
2567	.hw.init = &(struct clk_init_data) {
2568	.name = "gcc_qpic_io_macro_clk",
2569	.parent_hws = (const struct clk_hw *[]) {
2570	&qpic_io_macro_clk_src.clkr.hw,
2571	},
2572	.num_parents = 1,
2573	.flags = CLK_SET_RATE_PARENT,
2574	.ops = &clk_branch2_ops,
2575	},
2576	},
2577	};
2578
2579	static struct clk_branch gcc_sdcc1_ahb_clk = {
2580	.halt_reg = 0x4201c,
2581	.clkr = {
2582	.enable_reg = 0x4201c,
2583	.enable_mask = BIT(0),
2584	.hw.init = &(struct clk_init_data) {
2585	.name = "gcc_sdcc1_ahb_clk",
2586	.parent_hws = (const struct clk_hw *[]) {
2587	&pcnoc_clk_src.hw,
2588	},
2589	.num_parents = 1,
2590	.flags = CLK_SET_RATE_PARENT,
2591	.ops = &clk_branch2_ops,
2592	},
2593	},
2594	};
2595
2596	static struct clk_branch gcc_sdcc1_apps_clk = {
2597	.halt_reg = 0x42018,
2598	.clkr = {
2599	.enable_reg = 0x42018,
2600	.enable_mask = BIT(0),
2601	.hw.init = &(struct clk_init_data) {
2602	.name = "gcc_sdcc1_apps_clk",
2603	.parent_hws = (const struct clk_hw *[]) {
2604	&sdcc1_apps_clk_src.clkr.hw,
2605	},
2606	.num_parents = 1,
2607	.flags = CLK_SET_RATE_PARENT,
2608	.ops = &clk_branch2_ops,
2609	},
2610	},
2611	};
2612
2613	static struct clk_branch gcc_snoc_gmac0_ahb_clk = {
2614	.halt_reg = 0x260a0,
2615	.clkr = {
2616	.enable_reg = 0x260a0,
2617	.enable_mask = BIT(0),
2618	.hw.init = &(struct clk_init_data) {
2619	.name = "gcc_snoc_gmac0_ahb_clk",
2620	.parent_hws = (const struct clk_hw *[]) {
2621	&gmac_clk_src.clkr.hw,
2622	},
2623	.num_parents = 1,
2624	.flags = CLK_SET_RATE_PARENT,
2625	.ops = &clk_branch2_ops,
2626	},
2627	},
2628	};
2629
2630	static struct clk_branch gcc_snoc_gmac0_axi_clk = {
2631	.halt_reg = 0x26084,
2632	.clkr = {
2633	.enable_reg = 0x26084,
2634	.enable_mask = BIT(0),
2635	.hw.init = &(struct clk_init_data) {
2636	.name = "gcc_snoc_gmac0_axi_clk",
2637	.parent_hws = (const struct clk_hw *[]) {
2638	&gmac_clk_src.clkr.hw,
2639	},
2640	.num_parents = 1,
2641	.flags = CLK_SET_RATE_PARENT,
2642	.ops = &clk_branch2_ops,
2643	},
2644	},
2645	};
2646
2647	static struct clk_branch gcc_snoc_gmac1_ahb_clk = {
2648	.halt_reg = 0x260a4,
2649	.clkr = {
2650	.enable_reg = 0x260a4,
2651	.enable_mask = BIT(0),
2652	.hw.init = &(struct clk_init_data) {
2653	.name = "gcc_snoc_gmac1_ahb_clk",
2654	.parent_hws = (const struct clk_hw *[]) {
2655	&gmac_clk_src.clkr.hw,
2656	},
2657	.num_parents = 1,
2658	.flags = CLK_SET_RATE_PARENT,
2659	.ops = &clk_branch2_ops,
2660	},
2661	},
2662	};
2663
2664	static struct clk_branch gcc_snoc_gmac1_axi_clk = {
2665	.halt_reg = 0x26088,
2666	.clkr = {
2667	.enable_reg = 0x26088,
2668	.enable_mask = BIT(0),
2669	.hw.init = &(struct clk_init_data) {
2670	.name = "gcc_snoc_gmac1_axi_clk",
2671	.parent_hws = (const struct clk_hw *[]) {
2672	&gmac_clk_src.clkr.hw,
2673	},
2674	.num_parents = 1,
2675	.flags = CLK_SET_RATE_PARENT,
2676	.ops = &clk_branch2_ops,
2677	},
2678	},
2679	};
2680
2681	static struct clk_branch gcc_snoc_lpass_axim_clk = {
2682	.halt_reg = 0x26074,
2683	.clkr = {
2684	.enable_reg = 0x26074,
2685	.enable_mask = BIT(0),
2686	.hw.init = &(struct clk_init_data) {
2687	.name = "gcc_snoc_lpass_axim_clk",
2688	.parent_hws = (const struct clk_hw *[]) {
2689	&lpass_axim_clk_src.clkr.hw,
2690	},
2691	.num_parents = 1,
2692	.flags = CLK_SET_RATE_PARENT,
2693	.ops = &clk_branch2_ops,
2694	},
2695	},
2696	};
2697
2698	static struct clk_branch gcc_snoc_lpass_sway_clk = {
2699	.halt_reg = 0x26078,
2700	.clkr = {
2701	.enable_reg = 0x26078,
2702	.enable_mask = BIT(0),
2703	.hw.init = &(struct clk_init_data) {
2704	.name = "gcc_snoc_lpass_sway_clk",
2705	.parent_hws = (const struct clk_hw *[]) {
2706	&lpass_sway_clk_src.clkr.hw,
2707	},
2708	.num_parents = 1,
2709	.flags = CLK_SET_RATE_PARENT,
2710	.ops = &clk_branch2_ops,
2711	},
2712	},
2713	};
2714
2715	static struct clk_branch gcc_snoc_ubi0_axi_clk = {
2716	.halt_reg = 0x26094,
2717	.clkr = {
2718	.enable_reg = 0x26094,
2719	.enable_mask = BIT(0),
2720	.hw.init = &(struct clk_init_data) {
2721	.name = "gcc_snoc_ubi0_axi_clk",
2722	.parent_hws = (const struct clk_hw *[]) {
2723	&ubi0_axi_clk_src.clkr.hw,
2724	},
2725	.num_parents = 1,
2726	.flags = CLK_SET_RATE_PARENT,
2727	.ops = &clk_branch2_ops,
2728	},
2729	},
2730	};
2731
2732	static struct clk_branch gcc_sys_noc_pcie0_axi_clk = {
2733	.halt_reg = 0x26048,
2734	.clkr = {
2735	.enable_reg = 0x26048,
2736	.enable_mask = BIT(0),
2737	.hw.init = &(struct clk_init_data) {
2738	.name = "gcc_sys_noc_pcie0_axi_clk",
2739	.parent_hws = (const struct clk_hw *[]) {
2740	&pcie0_axi_clk_src.clkr.hw,
2741	},
2742	.num_parents = 1,
2743	.flags = CLK_SET_RATE_PARENT,
2744	.ops = &clk_branch2_ops,
2745	},
2746	},
2747	};
2748
2749	static struct clk_branch gcc_sys_noc_pcie1_axi_clk = {
2750	.halt_reg = 0x2604c,
2751	.clkr = {
2752	.enable_reg = 0x2604c,
2753	.enable_mask = BIT(0),
2754	.hw.init = &(struct clk_init_data) {
2755	.name = "gcc_sys_noc_pcie1_axi_clk",
2756	.parent_hws = (const struct clk_hw *[]) {
2757	&pcie1_axi_clk_src.clkr.hw,
2758	},
2759	.num_parents = 1,
2760	.flags = CLK_SET_RATE_PARENT,
2761	.ops = &clk_branch2_ops,
2762	},
2763	},
2764	};
2765
2766	static struct clk_branch gcc_sys_noc_qdss_stm_axi_clk = {
2767	.halt_reg = 0x26024,
2768	.clkr = {
2769	.enable_reg = 0x26024,
2770	.enable_mask = BIT(0),
2771	.hw.init = &(struct clk_init_data) {
2772	.name = "gcc_sys_noc_qdss_stm_axi_clk",
2773	.parent_hws = (const struct clk_hw *[]) {
2774	&qdss_stm_clk_src.clkr.hw,
2775	},
2776	.num_parents = 1,
2777	.flags = CLK_SET_RATE_PARENT,
2778	.ops = &clk_branch2_ops,
2779	},
2780	},
2781	};
2782
2783	static struct clk_branch gcc_sys_noc_usb0_axi_clk = {
2784	.halt_reg = 0x26040,
2785	.clkr = {
2786	.enable_reg = 0x26040,
2787	.enable_mask = BIT(0),
2788	.hw.init = &(struct clk_init_data) {
2789	.name = "gcc_sys_noc_usb0_axi_clk",
2790	.parent_hws = (const struct clk_hw *[]) {
2791	&usb0_master_clk_src.clkr.hw,
2792	},
2793	.num_parents = 1,
2794	.flags = CLK_SET_RATE_PARENT,
2795	.ops = &clk_branch2_ops,
2796	},
2797	},
2798	};
2799
2800	static struct clk_branch gcc_sys_noc_wcss_ahb_clk = {
2801	.halt_reg = 0x26034,
2802	.clkr = {
2803	.enable_reg = 0x26034,
2804	.enable_mask = BIT(0),
2805	.hw.init = &(struct clk_init_data) {
2806	.name = "gcc_sys_noc_wcss_ahb_clk",
2807	.parent_hws = (const struct clk_hw *[]) {
2808	&wcss_ahb_clk_src.clkr.hw,
2809	},
2810	.num_parents = 1,
2811	.flags = CLK_SET_RATE_PARENT,
2812	.ops = &clk_branch2_ops,
2813	},
2814	},
2815	};
2816
2817	static struct clk_branch gcc_ubi0_axi_clk = {
2818	.halt_reg = 0x68200,
2819	.halt_check = BRANCH_HALT_DELAY,
2820	.clkr = {
2821	.enable_reg = 0x68200,
2822	.enable_mask = BIT(0),
2823	.hw.init = &(struct clk_init_data) {
2824	.name = "gcc_ubi0_axi_clk",
2825	.parent_hws = (const struct clk_hw *[]) {
2826	&ubi0_axi_clk_src.clkr.hw,
2827	},
2828	.num_parents = 1,
2829	.flags = CLK_SET_RATE_PARENT,
2830	.ops = &clk_branch2_ops,
2831	},
2832	},
2833	};
2834
2835	static struct clk_branch gcc_ubi0_cfg_clk = {
2836	.halt_reg = 0x68160,
2837	.halt_check = BRANCH_HALT_DELAY,
2838	.clkr = {
2839	.enable_reg = 0x68160,
2840	.enable_mask = BIT(0),
2841	.hw.init = &(struct clk_init_data) {
2842	.name = "gcc_ubi0_cfg_clk",
2843	.parent_hws = (const struct clk_hw *[]) {
2844	&pcnoc_clk_src.hw,
2845	},
2846	.num_parents = 1,
2847	.flags = CLK_SET_RATE_PARENT,
2848	.ops = &clk_branch2_ops,
2849	},
2850	},
2851	};
2852
2853	static struct clk_branch gcc_ubi0_dbg_clk = {
2854	.halt_reg = 0x68214,
2855	.halt_check = BRANCH_HALT_DELAY,
2856	.clkr = {
2857	.enable_reg = 0x68214,
2858	.enable_mask = BIT(0),
2859	.hw.init = &(struct clk_init_data) {
2860	.name = "gcc_ubi0_dbg_clk",
2861	.parent_hws = (const struct clk_hw *[]) {
2862	&qdss_tsctr_clk_src.clkr.hw,
2863	},
2864	.num_parents = 1,
2865	.flags = CLK_SET_RATE_PARENT,
2866	.ops = &clk_branch2_ops,
2867	},
2868	},
2869	};
2870
2871	static struct clk_branch gcc_ubi0_core_clk = {
2872	.halt_reg = 0x68210,
2873	.halt_check = BRANCH_HALT_DELAY,
2874	.clkr = {
2875	.enable_reg = 0x68210,
2876	.enable_mask = BIT(0),
2877	.hw.init = &(struct clk_init_data) {
2878	.name = "gcc_ubi0_core_clk",
2879	.parent_hws = (const struct clk_hw *[]) {
2880	&ubi0_core_clk_src.clkr.hw,
2881	},
2882	.num_parents = 1,
2883	.flags = CLK_SET_RATE_PARENT,
2884	.ops = &clk_branch2_ops,
2885	},
2886	},
2887	};
2888
2889	static struct clk_branch gcc_ubi0_nc_axi_clk = {
2890	.halt_reg = 0x68204,
2891	.halt_check = BRANCH_HALT_DELAY,
2892	.clkr = {
2893	.enable_reg = 0x68204,
2894	.enable_mask = BIT(0),
2895	.hw.init = &(struct clk_init_data) {
2896	.name = "gcc_ubi0_nc_axi_clk",
2897	.parent_hws = (const struct clk_hw *[]) {
2898	&system_noc_clk_src.hw,
2899	},
2900	.num_parents = 1,
2901	.flags = CLK_SET_RATE_PARENT,
2902	.ops = &clk_branch2_ops,
2903	},
2904	},
2905	};
2906
2907	static struct clk_branch gcc_ubi0_utcm_clk = {
2908	.halt_reg = 0x68208,
2909	.halt_check = BRANCH_HALT_DELAY,
2910	.clkr = {
2911	.enable_reg = 0x68208,
2912	.enable_mask = BIT(0),
2913	.hw.init = &(struct clk_init_data) {
2914	.name = "gcc_ubi0_utcm_clk",
2915	.parent_hws = (const struct clk_hw *[]) {
2916	&system_noc_clk_src.hw,
2917	},
2918	.num_parents = 1,
2919	.flags = CLK_SET_RATE_PARENT,
2920	.ops = &clk_branch2_ops,
2921	},
2922	},
2923	};
2924
2925	static struct clk_branch gcc_uniphy_ahb_clk = {
2926	.halt_reg = 0x56108,
2927	.clkr = {
2928	.enable_reg = 0x56108,
2929	.enable_mask = BIT(0),
2930	.hw.init = &(struct clk_init_data) {
2931	.name = "gcc_uniphy_ahb_clk",
2932	.parent_hws = (const struct clk_hw *[]) {
2933	&pcnoc_clk_src.hw,
2934	},
2935	.num_parents = 1,
2936	.flags = CLK_SET_RATE_PARENT,
2937	.ops = &clk_branch2_ops,
2938	},
2939	},
2940	};
2941
2942	static struct clk_branch gcc_uniphy_rx_clk = {
2943	.halt_reg = 0x56110,
2944	.clkr = {
2945	.enable_reg = 0x56110,
2946	.enable_mask = BIT(0),
2947	.hw.init = &(struct clk_init_data) {
2948	.name = "gcc_uniphy_rx_clk",
2949	.parent_hws = (const struct clk_hw *[]) {
2950	&gmac1_rx_div_clk_src.clkr.hw,
2951	},
2952	.num_parents = 1,
2953	.ops = &clk_branch2_ops,
2954	.flags = CLK_SET_RATE_PARENT,
2955	},
2956	},
2957	};
2958
2959	static struct clk_branch gcc_uniphy_tx_clk = {
2960	.halt_reg = 0x56114,
2961	.clkr = {
2962	.enable_reg = 0x56114,
2963	.enable_mask = BIT(0),
2964	.hw.init = &(struct clk_init_data) {
2965	.name = "gcc_uniphy_tx_clk",
2966	.parent_hws = (const struct clk_hw *[]) {
2967	&gmac1_tx_div_clk_src.clkr.hw,
2968	},
2969	.num_parents = 1,
2970	.ops = &clk_branch2_ops,
2971	.flags = CLK_SET_RATE_PARENT,
2972	},
2973	},
2974	};
2975
2976	static struct clk_branch gcc_uniphy_sys_clk = {
2977	.halt_reg = 0x5610c,
2978	.clkr = {
2979	.enable_reg = 0x5610c,
2980	.enable_mask = BIT(0),
2981	.hw.init = &(struct clk_init_data) {
2982	.name = "gcc_uniphy_sys_clk",
2983	.parent_hws = (const struct clk_hw *[]) {
2984	&gcc_xo_clk_src.clkr.hw,
2985	},
2986	.num_parents = 1,
2987	.flags = CLK_SET_RATE_PARENT,
2988	.ops = &clk_branch2_ops,
2989	},
2990	},
2991	};
2992
2993	static struct clk_branch gcc_usb0_aux_clk = {
2994	.halt_reg = 0x3e044,
2995	.clkr = {
2996	.enable_reg = 0x3e044,
2997	.enable_mask = BIT(0),
2998	.hw.init = &(struct clk_init_data) {
2999	.name = "gcc_usb0_aux_clk",
3000	.parent_hws = (const struct clk_hw *[]) {
3001	&usb0_aux_clk_src.clkr.hw,
3002	},
3003	.num_parents = 1,
3004	.flags = CLK_SET_RATE_PARENT,
3005	.ops = &clk_branch2_ops,
3006	},
3007	},
3008	};
3009
3010	static struct clk_branch gcc_usb0_eud_at_clk = {
3011	.halt_reg = 0x3e04c,
3012	.halt_check = BRANCH_HALT_VOTED,
3013	.clkr = {
3014	.enable_reg = 0x3e04c,
3015	.enable_mask = BIT(0),
3016	.hw.init = &(struct clk_init_data) {
3017	.name = "gcc_usb0_eud_at_clk",
3018	.parent_hws = (const struct clk_hw *[]) {
3019	&eud_at_clk_src.hw,
3020	},
3021	.num_parents = 1,
3022	.flags = CLK_SET_RATE_PARENT,
3023	.ops = &clk_branch2_ops,
3024	},
3025	},
3026	};
3027
3028	static struct clk_branch gcc_usb0_lfps_clk = {
3029	.halt_reg = 0x3e050,
3030	.clkr = {
3031	.enable_reg = 0x3e050,
3032	.enable_mask = BIT(0),
3033	.hw.init = &(struct clk_init_data) {
3034	.name = "gcc_usb0_lfps_clk",
3035	.parent_hws = (const struct clk_hw *[]) {
3036	&usb0_lfps_clk_src.clkr.hw,
3037	},
3038	.num_parents = 1,
3039	.flags = CLK_SET_RATE_PARENT,
3040	.ops = &clk_branch2_ops,
3041	},
3042	},
3043	};
3044
3045	static struct clk_branch gcc_usb0_master_clk = {
3046	.halt_reg = 0x3e000,
3047	.clkr = {
3048	.enable_reg = 0x3e000,
3049	.enable_mask = BIT(0),
3050	.hw.init = &(struct clk_init_data) {
3051	.name = "gcc_usb0_master_clk",
3052	.parent_hws = (const struct clk_hw *[]) {
3053	&usb0_master_clk_src.clkr.hw,
3054	},
3055	.num_parents = 1,
3056	.flags = CLK_SET_RATE_PARENT,
3057	.ops = &clk_branch2_ops,
3058	},
3059	},
3060	};
3061
3062	static struct clk_branch gcc_usb0_mock_utmi_clk = {
3063	.halt_reg = 0x3e008,
3064	.clkr = {
3065	.enable_reg = 0x3e008,
3066	.enable_mask = BIT(0),
3067	.hw.init = &(struct clk_init_data) {
3068	.name = "gcc_usb0_mock_utmi_clk",
3069	.parent_hws = (const struct clk_hw *[]) {
3070	&usb0_mock_utmi_clk_src.clkr.hw,
3071	},
3072	.num_parents = 1,
3073	.flags = CLK_SET_RATE_PARENT,
3074	.ops = &clk_branch2_ops,
3075	},
3076	},
3077	};
3078
3079	static struct clk_branch gcc_usb0_phy_cfg_ahb_clk = {
3080	.halt_reg = 0x3e080,
3081	.clkr = {
3082	.enable_reg = 0x3e080,
3083	.enable_mask = BIT(0),
3084	.hw.init = &(struct clk_init_data) {
3085	.name = "gcc_usb0_phy_cfg_ahb_clk",
3086	.parent_hws = (const struct clk_hw *[]) {
3087	&pcnoc_clk_src.hw,
3088	},
3089	.num_parents = 1,
3090	.flags = CLK_SET_RATE_PARENT,
3091	.ops = &clk_branch2_ops,
3092	},
3093	},
3094	};
3095
3096	static struct clk_branch gcc_usb0_sleep_clk = {
3097	.halt_reg = 0x3e004,
3098	.clkr = {
3099	.enable_reg = 0x3e004,
3100	.enable_mask = BIT(0),
3101	.hw.init = &(struct clk_init_data) {
3102	.name = "gcc_usb0_sleep_clk",
3103	.parent_hws = (const struct clk_hw *[]) {
3104	&gcc_sleep_clk_src.clkr.hw,
3105	},
3106	.num_parents = 1,
3107	.flags = CLK_SET_RATE_PARENT,
3108	.ops = &clk_branch2_ops,
3109	},
3110	},
3111	};
3112
3113	static struct clk_branch gcc_usb0_pipe_clk = {
3114	.halt_reg = 0x3e040,
3115	.halt_check = BRANCH_HALT_DELAY,
3116	.clkr = {
3117	.enable_reg = 0x3e040,
3118	.enable_mask = BIT(0),
3119	.hw.init = &(struct clk_init_data) {
3120	.name = "gcc_usb0_pipe_clk",
3121	.parent_hws = (const struct clk_hw *[]) {
3122	&usb0_pipe_clk_src.clkr.hw,
3123	},
3124	.num_parents = 1,
3125	.flags = CLK_SET_RATE_PARENT,
3126	.ops = &clk_branch2_ops,
3127	},
3128	},
3129	};
3130
3131	static struct clk_branch gcc_wcss_acmt_clk = {
3132	.halt_reg = 0x59064,
3133	.clkr = {
3134	.enable_reg = 0x59064,
3135	.enable_mask = BIT(0),
3136	.hw.init = &(struct clk_init_data) {
3137	.name = "gcc_wcss_acmt_clk",
3138	.parent_hws = (const struct clk_hw *[]) {
3139	&wcss_ahb_clk_src.clkr.hw,
3140	},
3141	.num_parents = 1,
3142	.flags = CLK_SET_RATE_PARENT,
3143	.ops = &clk_branch2_ops,
3144	},
3145	},
3146	};
3147
3148	static struct clk_branch gcc_wcss_ahb_s_clk = {
3149	.halt_reg = 0x59034,
3150	.clkr = {
3151	.enable_reg = 0x59034,
3152	.enable_mask = BIT(0),
3153	.hw.init = &(struct clk_init_data) {
3154	.name = "gcc_wcss_ahb_s_clk",
3155	.parent_hws = (const struct clk_hw *[]) {
3156	&wcss_ahb_clk_src.clkr.hw,
3157	},
3158	.num_parents = 1,
3159	.flags = CLK_SET_RATE_PARENT,
3160	.ops = &clk_branch2_ops,
3161	},
3162	},
3163	};
3164
3165	static struct clk_branch gcc_wcss_axi_m_clk = {
3166	.halt_reg = 0x5903c,
3167	.clkr = {
3168	.enable_reg = 0x5903c,
3169	.enable_mask = BIT(0),
3170	.hw.init = &(struct clk_init_data) {
3171	.name = "gcc_wcss_axi_m_clk",
3172	.parent_hws = (const struct clk_hw *[]) {
3173	&system_noc_clk_src.hw,
3174	},
3175	.num_parents = 1,
3176	.flags = CLK_SET_RATE_PARENT,
3177	.ops = &clk_branch2_ops,
3178	},
3179	},
3180	};
3181
3182	static struct clk_branch gcc_wcss_axi_s_clk = {
3183	.halt_reg = 0x59068,
3184	.clkr = {
3185	.enable_reg = 0x59068,
3186	.enable_mask = BIT(0),
3187	.hw.init = &(struct clk_init_data) {
3188	.name = "gcc_wi_s_clk",
3189	.parent_hws = (const struct clk_hw *[]) {
3190	&system_noc_clk_src.hw,
3191	},
3192	.num_parents = 1,
3193	.flags = CLK_SET_RATE_PARENT,
3194	.ops = &clk_branch2_ops,
3195	},
3196	},
3197	};
3198
3199	static struct clk_branch gcc_wcss_dbg_ifc_apb_bdg_clk = {
3200	.halt_reg = 0x59050,
3201	.clkr = {
3202	.enable_reg = 0x59050,
3203	.enable_mask = BIT(0),
3204	.hw.init = &(struct clk_init_data) {
3205	.name = "gcc_wcss_dbg_ifc_apb_bdg_clk",
3206	.parent_hws = (const struct clk_hw *[]) {
3207	&qdss_dap_sync_clk_src.hw,
3208	},
3209	.num_parents = 1,
3210	.flags = CLK_SET_RATE_PARENT,
3211	.ops = &clk_branch2_ops,
3212	},
3213	},
3214	};
3215
3216	static struct clk_branch gcc_wcss_dbg_ifc_apb_clk = {
3217	.halt_reg = 0x59040,
3218	.clkr = {
3219	.enable_reg = 0x59040,
3220	.enable_mask = BIT(0),
3221	.hw.init = &(struct clk_init_data) {
3222	.name = "gcc_wcss_dbg_ifc_apb_clk",
3223	.parent_hws = (const struct clk_hw *[]) {
3224	&qdss_dap_sync_clk_src.hw,
3225	},
3226	.num_parents = 1,
3227	.flags = CLK_SET_RATE_PARENT,
3228	.ops = &clk_branch2_ops,
3229	},
3230	},
3231	};
3232
3233	static struct clk_branch gcc_wcss_dbg_ifc_atb_bdg_clk = {
3234	.halt_reg = 0x59054,
3235	.clkr = {
3236	.enable_reg = 0x59054,
3237	.enable_mask = BIT(0),
3238	.hw.init = &(struct clk_init_data) {
3239	.name = "gcc_wcss_dbg_ifc_atb_bdg_clk",
3240	.parent_hws = (const struct clk_hw *[]) {
3241	&qdss_at_clk_src.clkr.hw,
3242	},
3243	.num_parents = 1,
3244	.flags = CLK_SET_RATE_PARENT,
3245	.ops = &clk_branch2_ops,
3246	},
3247	},
3248	};
3249
3250	static struct clk_branch gcc_wcss_dbg_ifc_atb_clk = {
3251	.halt_reg = 0x59044,
3252	.clkr = {
3253	.enable_reg = 0x59044,
3254	.enable_mask = BIT(0),
3255	.hw.init = &(struct clk_init_data) {
3256	.name = "gcc_wcss_dbg_ifc_atb_clk",
3257	.parent_hws = (const struct clk_hw *[]) {
3258	&qdss_at_clk_src.clkr.hw,
3259	},
3260	.num_parents = 1,
3261	.flags = CLK_SET_RATE_PARENT,
3262	.ops = &clk_branch2_ops,
3263	},
3264	},
3265	};
3266
3267	static struct clk_branch gcc_wcss_dbg_ifc_dapbus_bdg_clk = {
3268	.halt_reg = 0x59060,
3269	.clkr = {
3270	.enable_reg = 0x59060,
3271	.enable_mask = BIT(0),
3272	.hw.init = &(struct clk_init_data) {
3273	.name = "gcc_wcss_dbg_ifc_dapbus_bdg_clk",
3274	.parent_hws = (const struct clk_hw *[]) {
3275	&qdss_dap_sync_clk_src.hw,
3276	},
3277	.num_parents = 1,
3278	.flags = CLK_SET_RATE_PARENT,
3279	.ops = &clk_branch2_ops,
3280	},
3281	},
3282	};
3283
3284	static struct clk_branch gcc_wcss_dbg_ifc_dapbus_clk = {
3285	.halt_reg = 0x5905c,
3286	.clkr = {
3287	.enable_reg = 0x5905c,
3288	.enable_mask = BIT(0),
3289	.hw.init = &(struct clk_init_data) {
3290	.name = "gcc_wcss_dbg_ifc_dapbus_clk",
3291	.parent_hws = (const struct clk_hw *[]) {
3292	&qdss_dap_sync_clk_src.hw,
3293	},
3294	.num_parents = 1,
3295	.flags = CLK_SET_RATE_PARENT,
3296	.ops = &clk_branch2_ops,
3297	},
3298	},
3299	};
3300
3301	static struct clk_branch gcc_wcss_dbg_ifc_nts_bdg_clk = {
3302	.halt_reg = 0x59058,
3303	.clkr = {
3304	.enable_reg = 0x59058,
3305	.enable_mask = BIT(0),
3306	.hw.init = &(struct clk_init_data) {
3307	.name = "gcc_wcss_dbg_ifc_nts_bdg_clk",
3308	.parent_hws = (const struct clk_hw *[]) {
3309	&qdss_tsctr_div2_clk_src.hw,
3310	},
3311	.num_parents = 1,
3312	.flags = CLK_SET_RATE_PARENT,
3313	.ops = &clk_branch2_ops,
3314	},
3315	},
3316	};
3317
3318	static struct clk_branch gcc_wcss_dbg_ifc_nts_clk = {
3319	.halt_reg = 0x59048,
3320	.clkr = {
3321	.enable_reg = 0x59048,
3322	.enable_mask = BIT(0),
3323	.hw.init = &(struct clk_init_data) {
3324	.name = "gcc_wcss_dbg_ifc_nts_clk",
3325	.parent_hws = (const struct clk_hw *[]) {
3326	&qdss_tsctr_div2_clk_src.hw,
3327	},
3328	.num_parents = 1,
3329	.flags = CLK_SET_RATE_PARENT,
3330	.ops = &clk_branch2_ops,
3331	},
3332	},
3333	};
3334
3335	static struct clk_branch gcc_wcss_ecahb_clk = {
3336	.halt_reg = 0x59038,
3337	.clkr = {
3338	.enable_reg = 0x59038,
3339	.enable_mask = BIT(0),
3340	.hw.init = &(struct clk_init_data) {
3341	.name = "gcc_wcss_ecahb_clk",
3342	.parent_hws = (const struct clk_hw *[]) {
3343	&wcss_ahb_clk_src.clkr.hw,
3344	},
3345	.num_parents = 1,
3346	.flags = CLK_SET_RATE_PARENT,
3347	.ops = &clk_branch2_ops,
3348	},
3349	},
3350	};
3351
3352	static struct clk_hw *gcc_ipq5018_hws[] = {
3353	&gpll0_out_main_div2.hw,
3354	&pcnoc_clk_src.hw,
3355	&system_noc_clk_src.hw,
3356	&qdss_dap_sync_clk_src.hw,
3357	&qdss_tsctr_div2_clk_src.hw,
3358	&eud_at_clk_src.hw,
3359	};
3360
3361	static const struct alpha_pll_config ubi32_pll_config = {
3362	.l = 0x29,
3363	.alpha = 0xaaaaaaaa,
3364	.alpha_hi = 0xaa,
3365	.config_ctl_val = 0x4001075b,
3366	.main_output_mask = BIT(0),
3367	.aux_output_mask = BIT(1),
3368	.alpha_en_mask = BIT(24),
3369	.vco_val = 0x1,
3370	.vco_mask = GENMASK(21, 20),
3371	.test_ctl_val = 0x0,
3372	.test_ctl_hi_val = 0x0,
3373	};
3374
3375	static struct clk_regmap *gcc_ipq5018_clks[] = {
3376	[GPLL0_MAIN] = &gpll0_main.clkr,
3377	[GPLL0] = &gpll0.clkr,
3378	[GPLL2_MAIN] = &gpll2_main.clkr,
3379	[GPLL2] = &gpll2.clkr,
3380	[GPLL4_MAIN] = &gpll4_main.clkr,
3381	[GPLL4] = &gpll4.clkr,
3382	[UBI32_PLL_MAIN] = &ubi32_pll_main.clkr,
3383	[UBI32_PLL] = &ubi32_pll.clkr,
3384	[ADSS_PWM_CLK_SRC] = &adss_pwm_clk_src.clkr,
3385	[BLSP1_QUP1_I2C_APPS_CLK_SRC] = &blsp1_qup1_i2c_apps_clk_src.clkr,
3386	[BLSP1_QUP1_SPI_APPS_CLK_SRC] = &blsp1_qup1_spi_apps_clk_src.clkr,
3387	[BLSP1_QUP2_I2C_APPS_CLK_SRC] = &blsp1_qup2_i2c_apps_clk_src.clkr,
3388	[BLSP1_QUP2_SPI_APPS_CLK_SRC] = &blsp1_qup2_spi_apps_clk_src.clkr,
3389	[BLSP1_QUP3_I2C_APPS_CLK_SRC] = &blsp1_qup3_i2c_apps_clk_src.clkr,
3390	[BLSP1_QUP3_SPI_APPS_CLK_SRC] = &blsp1_qup3_spi_apps_clk_src.clkr,
3391	[BLSP1_UART1_APPS_CLK_SRC] = &blsp1_uart1_apps_clk_src.clkr,
3392	[BLSP1_UART2_APPS_CLK_SRC] = &blsp1_uart2_apps_clk_src.clkr,
3393	[CRYPTO_CLK_SRC] = &crypto_clk_src.clkr,
3394	[GCC_ADSS_PWM_CLK] = &gcc_adss_pwm_clk.clkr,
3395	[GCC_BLSP1_AHB_CLK] = &gcc_blsp1_ahb_clk.clkr,
3396	[GCC_BLSP1_QUP1_I2C_APPS_CLK] = &gcc_blsp1_qup1_i2c_apps_clk.clkr,
3397	[GCC_BLSP1_QUP1_SPI_APPS_CLK] = &gcc_blsp1_qup1_spi_apps_clk.clkr,
3398	[GCC_BLSP1_QUP2_I2C_APPS_CLK] = &gcc_blsp1_qup2_i2c_apps_clk.clkr,
3399	[GCC_BLSP1_QUP2_SPI_APPS_CLK] = &gcc_blsp1_qup2_spi_apps_clk.clkr,
3400	[GCC_BLSP1_QUP3_I2C_APPS_CLK] = &gcc_blsp1_qup3_i2c_apps_clk.clkr,
3401	[GCC_BLSP1_QUP3_SPI_APPS_CLK] = &gcc_blsp1_qup3_spi_apps_clk.clkr,
3402	[GCC_BLSP1_UART1_APPS_CLK] = &gcc_blsp1_uart1_apps_clk.clkr,
3403	[GCC_BLSP1_UART2_APPS_CLK] = &gcc_blsp1_uart2_apps_clk.clkr,
3404	[GCC_BTSS_LPO_CLK] = &gcc_btss_lpo_clk.clkr,
3405	[GCC_CMN_BLK_AHB_CLK] = &gcc_cmn_blk_ahb_clk.clkr,
3406	[GCC_CMN_BLK_SYS_CLK] = &gcc_cmn_blk_sys_clk.clkr,
3407	[GCC_CRYPTO_AHB_CLK] = &gcc_crypto_ahb_clk.clkr,
3408	[GCC_CRYPTO_AXI_CLK] = &gcc_crypto_axi_clk.clkr,
3409	[GCC_CRYPTO_CLK] = &gcc_crypto_clk.clkr,
3410	[GCC_DCC_CLK] = &gcc_dcc_clk.clkr,
3411	[GCC_GEPHY_RX_CLK] = &gcc_gephy_rx_clk.clkr,
3412	[GCC_GEPHY_TX_CLK] = &gcc_gephy_tx_clk.clkr,
3413	[GCC_GMAC0_CFG_CLK] = &gcc_gmac0_cfg_clk.clkr,
3414	[GCC_GMAC0_PTP_CLK] = &gcc_gmac0_ptp_clk.clkr,
3415	[GCC_GMAC0_RX_CLK] = &gcc_gmac0_rx_clk.clkr,
3416	[GCC_GMAC0_SYS_CLK] = &gcc_gmac0_sys_clk.clkr,
3417	[GCC_GMAC0_TX_CLK] = &gcc_gmac0_tx_clk.clkr,
3418	[GCC_GMAC1_CFG_CLK] = &gcc_gmac1_cfg_clk.clkr,
3419	[GCC_GMAC1_PTP_CLK] = &gcc_gmac1_ptp_clk.clkr,
3420	[GCC_GMAC1_RX_CLK] = &gcc_gmac1_rx_clk.clkr,
3421	[GCC_GMAC1_SYS_CLK] = &gcc_gmac1_sys_clk.clkr,
3422	[GCC_GMAC1_TX_CLK] = &gcc_gmac1_tx_clk.clkr,
3423	[GCC_GP1_CLK] = &gcc_gp1_clk.clkr,
3424	[GCC_GP2_CLK] = &gcc_gp2_clk.clkr,
3425	[GCC_GP3_CLK] = &gcc_gp3_clk.clkr,
3426	[GCC_LPASS_CORE_AXIM_CLK] = &gcc_lpass_core_axim_clk.clkr,
3427	[GCC_LPASS_SWAY_CLK] = &gcc_lpass_sway_clk.clkr,
3428	[GCC_MDIO0_AHB_CLK] = &gcc_mdio0_ahb_clk.clkr,
3429	[GCC_MDIO1_AHB_CLK] = &gcc_mdio1_ahb_clk.clkr,
3430	[GCC_PCIE0_AHB_CLK] = &gcc_pcie0_ahb_clk.clkr,
3431	[GCC_PCIE0_AUX_CLK] = &gcc_pcie0_aux_clk.clkr,
3432	[GCC_PCIE0_AXI_M_CLK] = &gcc_pcie0_axi_m_clk.clkr,
3433	[GCC_PCIE0_AXI_S_BRIDGE_CLK] = &gcc_pcie0_axi_s_bridge_clk.clkr,
3434	[GCC_PCIE0_AXI_S_CLK] = &gcc_pcie0_axi_s_clk.clkr,
3435	[GCC_PCIE1_AHB_CLK] = &gcc_pcie1_ahb_clk.clkr,
3436	[GCC_PCIE1_AUX_CLK] = &gcc_pcie1_aux_clk.clkr,
3437	[GCC_PCIE1_AXI_M_CLK] = &gcc_pcie1_axi_m_clk.clkr,
3438	[GCC_PCIE1_AXI_S_BRIDGE_CLK] = &gcc_pcie1_axi_s_bridge_clk.clkr,
3439	[GCC_PCIE1_AXI_S_CLK] = &gcc_pcie1_axi_s_clk.clkr,
3440	[GCC_PRNG_AHB_CLK] = &gcc_prng_ahb_clk.clkr,
3441	[GCC_Q6_AXIM_CLK] = &gcc_q6_axim_clk.clkr,
3442	[GCC_Q6_AXIM2_CLK] = &gcc_q6_axim2_clk.clkr,
3443	[GCC_Q6_AXIS_CLK] = &gcc_q6_axis_clk.clkr,
3444	[GCC_Q6_AHB_CLK] = &gcc_q6_ahb_clk.clkr,
3445	[GCC_Q6_AHB_S_CLK] = &gcc_q6_ahb_s_clk.clkr,
3446	[GCC_Q6_TSCTR_1TO2_CLK] = &gcc_q6_tsctr_1to2_clk.clkr,
3447	[GCC_Q6SS_ATBM_CLK] = &gcc_q6ss_atbm_clk.clkr,
3448	[GCC_Q6SS_PCLKDBG_CLK] = &gcc_q6ss_pclkdbg_clk.clkr,
3449	[GCC_Q6SS_TRIG_CLK] = &gcc_q6ss_trig_clk.clkr,
3450	[GCC_QDSS_AT_CLK] = &gcc_qdss_at_clk.clkr,
3451	[GCC_QDSS_CFG_AHB_CLK] = &gcc_qdss_cfg_ahb_clk.clkr,
3452	[GCC_QDSS_DAP_AHB_CLK] = &gcc_qdss_dap_ahb_clk.clkr,
3453	[GCC_QDSS_DAP_CLK] = &gcc_qdss_dap_clk.clkr,
3454	[GCC_QDSS_ETR_USB_CLK] = &gcc_qdss_etr_usb_clk.clkr,
3455	[GCC_QDSS_EUD_AT_CLK] = &gcc_qdss_eud_at_clk.clkr,
3456	[GCC_QDSS_STM_CLK] = &gcc_qdss_stm_clk.clkr,
3457	[GCC_QDSS_TRACECLKIN_CLK] = &gcc_qdss_traceclkin_clk.clkr,
3458	[GCC_QDSS_TSCTR_DIV8_CLK] = &gcc_qdss_tsctr_div8_clk.clkr,
3459	[GCC_QPIC_AHB_CLK] = &gcc_qpic_ahb_clk.clkr,
3460	[GCC_QPIC_CLK] = &gcc_qpic_clk.clkr,
3461	[GCC_QPIC_IO_MACRO_CLK] = &gcc_qpic_io_macro_clk.clkr,
3462	[GCC_SDCC1_AHB_CLK] = &gcc_sdcc1_ahb_clk.clkr,
3463	[GCC_SDCC1_APPS_CLK] = &gcc_sdcc1_apps_clk.clkr,
3464	[GCC_SLEEP_CLK_SRC] = &gcc_sleep_clk_src.clkr,
3465	[GCC_SNOC_GMAC0_AHB_CLK] = &gcc_snoc_gmac0_ahb_clk.clkr,
3466	[GCC_SNOC_GMAC0_AXI_CLK] = &gcc_snoc_gmac0_axi_clk.clkr,
3467	[GCC_SNOC_GMAC1_AHB_CLK] = &gcc_snoc_gmac1_ahb_clk.clkr,
3468	[GCC_SNOC_GMAC1_AXI_CLK] = &gcc_snoc_gmac1_axi_clk.clkr,
3469	[GCC_SNOC_LPASS_AXIM_CLK] = &gcc_snoc_lpass_axim_clk.clkr,
3470	[GCC_SNOC_LPASS_SWAY_CLK] = &gcc_snoc_lpass_sway_clk.clkr,
3471	[GCC_SNOC_UBI0_AXI_CLK] = &gcc_snoc_ubi0_axi_clk.clkr,
3472	[GCC_SYS_NOC_PCIE0_AXI_CLK] = &gcc_sys_noc_pcie0_axi_clk.clkr,
3473	[GCC_SYS_NOC_PCIE1_AXI_CLK] = &gcc_sys_noc_pcie1_axi_clk.clkr,
3474	[GCC_SYS_NOC_QDSS_STM_AXI_CLK] = &gcc_sys_noc_qdss_stm_axi_clk.clkr,
3475	[GCC_SYS_NOC_USB0_AXI_CLK] = &gcc_sys_noc_usb0_axi_clk.clkr,
3476	[GCC_SYS_NOC_WCSS_AHB_CLK] = &gcc_sys_noc_wcss_ahb_clk.clkr,
3477	[GCC_UBI0_AXI_CLK] = &gcc_ubi0_axi_clk.clkr,
3478	[GCC_UBI0_CFG_CLK] = &gcc_ubi0_cfg_clk.clkr,
3479	[GCC_UBI0_CORE_CLK] = &gcc_ubi0_core_clk.clkr,
3480	[GCC_UBI0_DBG_CLK] = &gcc_ubi0_dbg_clk.clkr,
3481	[GCC_UBI0_NC_AXI_CLK] = &gcc_ubi0_nc_axi_clk.clkr,
3482	[GCC_UBI0_UTCM_CLK] = &gcc_ubi0_utcm_clk.clkr,
3483	[GCC_UNIPHY_AHB_CLK] = &gcc_uniphy_ahb_clk.clkr,
3484	[GCC_UNIPHY_RX_CLK] = &gcc_uniphy_rx_clk.clkr,
3485	[GCC_UNIPHY_SYS_CLK] = &gcc_uniphy_sys_clk.clkr,
3486	[GCC_UNIPHY_TX_CLK] = &gcc_uniphy_tx_clk.clkr,
3487	[GCC_USB0_AUX_CLK] = &gcc_usb0_aux_clk.clkr,
3488	[GCC_USB0_EUD_AT_CLK] = &gcc_usb0_eud_at_clk.clkr,
3489	[GCC_USB0_LFPS_CLK] = &gcc_usb0_lfps_clk.clkr,
3490	[GCC_USB0_MASTER_CLK] = &gcc_usb0_master_clk.clkr,
3491	[GCC_USB0_MOCK_UTMI_CLK] = &gcc_usb0_mock_utmi_clk.clkr,
3492	[GCC_USB0_PHY_CFG_AHB_CLK] = &gcc_usb0_phy_cfg_ahb_clk.clkr,
3493	[GCC_USB0_SLEEP_CLK] = &gcc_usb0_sleep_clk.clkr,
3494	[GCC_WCSS_ACMT_CLK] = &gcc_wcss_acmt_clk.clkr,
3495	[GCC_WCSS_AHB_S_CLK] = &gcc_wcss_ahb_s_clk.clkr,
3496	[GCC_WCSS_AXI_M_CLK] = &gcc_wcss_axi_m_clk.clkr,
3497	[GCC_WCSS_AXI_S_CLK] = &gcc_wcss_axi_s_clk.clkr,
3498	[GCC_WCSS_DBG_IFC_APB_BDG_CLK] = &gcc_wcss_dbg_ifc_apb_bdg_clk.clkr,
3499	[GCC_WCSS_DBG_IFC_APB_CLK] = &gcc_wcss_dbg_ifc_apb_clk.clkr,
3500	[GCC_WCSS_DBG_IFC_ATB_BDG_CLK] = &gcc_wcss_dbg_ifc_atb_bdg_clk.clkr,
3501	[GCC_WCSS_DBG_IFC_ATB_CLK] = &gcc_wcss_dbg_ifc_atb_clk.clkr,
3502	[GCC_WCSS_DBG_IFC_DAPBUS_BDG_CLK] = &gcc_wcss_dbg_ifc_dapbus_bdg_clk.clkr,
3503	[GCC_WCSS_DBG_IFC_DAPBUS_CLK] = &gcc_wcss_dbg_ifc_dapbus_clk.clkr,
3504	[GCC_WCSS_DBG_IFC_NTS_BDG_CLK] = &gcc_wcss_dbg_ifc_nts_bdg_clk.clkr,
3505	[GCC_WCSS_DBG_IFC_NTS_CLK] = &gcc_wcss_dbg_ifc_nts_clk.clkr,
3506	[GCC_WCSS_ECAHB_CLK] = &gcc_wcss_ecahb_clk.clkr,
3507	[GCC_XO_CLK] = &gcc_xo_clk.clkr,
3508	[GCC_XO_CLK_SRC] = &gcc_xo_clk_src.clkr,
3509	[GMAC0_RX_CLK_SRC] = &gmac0_rx_clk_src.clkr,
3510	[GMAC0_RX_DIV_CLK_SRC] = &gmac0_rx_div_clk_src.clkr,
3511	[GMAC0_TX_CLK_SRC] = &gmac0_tx_clk_src.clkr,
3512	[GMAC0_TX_DIV_CLK_SRC] = &gmac0_tx_div_clk_src.clkr,
3513	[GMAC1_RX_CLK_SRC] = &gmac1_rx_clk_src.clkr,
3514	[GMAC1_RX_DIV_CLK_SRC] = &gmac1_rx_div_clk_src.clkr,
3515	[GMAC1_TX_CLK_SRC] = &gmac1_tx_clk_src.clkr,
3516	[GMAC1_TX_DIV_CLK_SRC] = &gmac1_tx_div_clk_src.clkr,
3517	[GMAC_CLK_SRC] = &gmac_clk_src.clkr,
3518	[GP1_CLK_SRC] = &gp1_clk_src.clkr,
3519	[GP2_CLK_SRC] = &gp2_clk_src.clkr,
3520	[GP3_CLK_SRC] = &gp3_clk_src.clkr,
3521	[LPASS_AXIM_CLK_SRC] = &lpass_axim_clk_src.clkr,
3522	[LPASS_SWAY_CLK_SRC] = &lpass_sway_clk_src.clkr,
3523	[PCIE0_AUX_CLK_SRC] = &pcie0_aux_clk_src.clkr,
3524	[PCIE0_AXI_CLK_SRC] = &pcie0_axi_clk_src.clkr,
3525	[PCIE1_AUX_CLK_SRC] = &pcie1_aux_clk_src.clkr,
3526	[PCIE1_AXI_CLK_SRC] = &pcie1_axi_clk_src.clkr,
3527	[PCNOC_BFDCD_CLK_SRC] = &pcnoc_bfdcd_clk_src.clkr,
3528	[Q6_AXI_CLK_SRC] = &q6_axi_clk_src.clkr,
3529	[QDSS_AT_CLK_SRC] = &qdss_at_clk_src.clkr,
3530	[QDSS_STM_CLK_SRC] = &qdss_stm_clk_src.clkr,
3531	[QDSS_TSCTR_CLK_SRC] = &qdss_tsctr_clk_src.clkr,
3532	[QDSS_TRACECLKIN_CLK_SRC] = &qdss_traceclkin_clk_src.clkr,
3533	[QPIC_IO_MACRO_CLK_SRC] = &qpic_io_macro_clk_src.clkr,
3534	[SDCC1_APPS_CLK_SRC] = &sdcc1_apps_clk_src.clkr,
3535	[SYSTEM_NOC_BFDCD_CLK_SRC] = &system_noc_bfdcd_clk_src.clkr,
3536	[UBI0_AXI_CLK_SRC] = &ubi0_axi_clk_src.clkr,
3537	[UBI0_CORE_CLK_SRC] = &ubi0_core_clk_src.clkr,
3538	[USB0_AUX_CLK_SRC] = &usb0_aux_clk_src.clkr,
3539	[USB0_LFPS_CLK_SRC] = &usb0_lfps_clk_src.clkr,
3540	[USB0_MASTER_CLK_SRC] = &usb0_master_clk_src.clkr,
3541	[USB0_MOCK_UTMI_CLK_SRC] = &usb0_mock_utmi_clk_src.clkr,
3542	[WCSS_AHB_CLK_SRC] = &wcss_ahb_clk_src.clkr,
3543	[PCIE0_PIPE_CLK_SRC] = &pcie0_pipe_clk_src.clkr,
3544	[PCIE1_PIPE_CLK_SRC] = &pcie1_pipe_clk_src.clkr,
3545	[GCC_PCIE0_PIPE_CLK] = &gcc_pcie0_pipe_clk.clkr,
3546	[GCC_PCIE1_PIPE_CLK] = &gcc_pcie1_pipe_clk.clkr,
3547	[USB0_PIPE_CLK_SRC] = &usb0_pipe_clk_src.clkr,
3548	[GCC_USB0_PIPE_CLK] = &gcc_usb0_pipe_clk.clkr,
3549	};
3550
3551	static const struct qcom_reset_map gcc_ipq5018_resets[] = {
3552	[GCC_APC0_VOLTAGE_DROOP_DETECTOR_BCR] = { 0x78000, 0 },
3553	[GCC_BLSP1_BCR] = { 0x01000, 0 },
3554	[GCC_BLSP1_QUP1_BCR] = { 0x02000, 0 },
3555	[GCC_BLSP1_QUP2_BCR] = { 0x03008, 0 },
3556	[GCC_BLSP1_QUP3_BCR] = { 0x04008, 0 },
3557	[GCC_BLSP1_UART1_BCR] = { 0x02038, 0 },
3558	[GCC_BLSP1_UART2_BCR] = { 0x03028, 0 },
3559	[GCC_BOOT_ROM_BCR] = { 0x13008, 0 },
3560	[GCC_BTSS_BCR] = { 0x1c000, 0 },
3561	[GCC_CMN_BLK_BCR] = { 0x56300, 0 },
3562	[GCC_CMN_LDO_BCR] = { 0x33000, 0 },
3563	[GCC_CE_BCR] = { 0x33014, 0 },
3564	[GCC_CRYPTO_BCR] = { 0x16000, 0 },
3565	[GCC_DCC_BCR] = { 0x77000, 0 },
3566	[GCC_DCD_BCR] = { 0x2a000, 0 },
3567	[GCC_DDRSS_BCR] = { 0x1e000, 0 },
3568	[GCC_EDPD_BCR] = { 0x3a000, 0 },
3569	[GCC_GEPHY_BCR] = { 0x56000, 0 },
3570	[GCC_GEPHY_MDC_SW_ARES] = { 0x56004, 0 },
3571	[GCC_GEPHY_DSP_HW_ARES] = { 0x56004, 1 },
3572	[GCC_GEPHY_RX_ARES] = { 0x56004, 2 },
3573	[GCC_GEPHY_TX_ARES] = { 0x56004, 3 },
3574	[GCC_GMAC0_BCR] = { 0x19000, 0 },
3575	[GCC_GMAC0_CFG_ARES] = { 0x68428, 0 },
3576	[GCC_GMAC0_SYS_ARES] = { 0x68428, 1 },
3577	[GCC_GMAC1_BCR] = { 0x19100, 0 },
3578	[GCC_GMAC1_CFG_ARES] = { 0x68438, 0 },
3579	[GCC_GMAC1_SYS_ARES] = { 0x68438, 1 },
3580	[GCC_IMEM_BCR] = { 0x0e000, 0 },
3581	[GCC_LPASS_BCR] = { 0x2e000, 0 },
3582	[GCC_MDIO0_BCR] = { 0x58000, 0 },
3583	[GCC_MDIO1_BCR] = { 0x58010, 0 },
3584	[GCC_MPM_BCR] = { 0x2c000, 0 },
3585	[GCC_PCIE0_BCR] = { 0x75004, 0 },
3586	[GCC_PCIE0_LINK_DOWN_BCR] = { 0x750a8, 0 },
3587	[GCC_PCIE0_PHY_BCR] = { 0x75038, 0 },
3588	[GCC_PCIE0PHY_PHY_BCR] = { 0x7503c, 0 },
3589	[GCC_PCIE0_PIPE_ARES] = { 0x75040, 0 },
3590	[GCC_PCIE0_SLEEP_ARES] = { 0x75040, 1 },
3591	[GCC_PCIE0_CORE_STICKY_ARES] = { 0x75040, 2 },
3592	[GCC_PCIE0_AXI_MASTER_ARES] = { 0x75040, 3 },
3593	[GCC_PCIE0_AXI_SLAVE_ARES] = { 0x75040, 4 },
3594	[GCC_PCIE0_AHB_ARES] = { 0x75040, 5 },
3595	[GCC_PCIE0_AXI_MASTER_STICKY_ARES] = { 0x75040, 6 },
3596	[GCC_PCIE0_AXI_SLAVE_STICKY_ARES] = { 0x75040, 7 },
3597	[GCC_PCIE1_BCR] = { 0x76004, 0 },
3598	[GCC_PCIE1_LINK_DOWN_BCR] = { 0x76044, 0 },
3599	[GCC_PCIE1_PHY_BCR] = { 0x76038, 0 },
3600	[GCC_PCIE1PHY_PHY_BCR] = { 0x7603c, 0 },
3601	[GCC_PCIE1_PIPE_ARES] = { 0x76040, 0 },
3602	[GCC_PCIE1_SLEEP_ARES] = { 0x76040, 1 },
3603	[GCC_PCIE1_CORE_STICKY_ARES] = { 0x76040, 2 },
3604	[GCC_PCIE1_AXI_MASTER_ARES] = { 0x76040, 3 },
3605	[GCC_PCIE1_AXI_SLAVE_ARES] = { 0x76040, 4 },
3606	[GCC_PCIE1_AHB_ARES] = { 0x76040, 5 },
3607	[GCC_PCIE1_AXI_MASTER_STICKY_ARES] = { 0x76040, 6 },
3608	[GCC_PCIE1_AXI_SLAVE_STICKY_ARES] = { 0x76040, 7 },
3609	[GCC_PCNOC_BCR] = { 0x27018, 0 },
3610	[GCC_PCNOC_BUS_TIMEOUT0_BCR] = { 0x48000, 0 },
3611	[GCC_PCNOC_BUS_TIMEOUT1_BCR] = { 0x48008, 0 },
3612	[GCC_PCNOC_BUS_TIMEOUT2_BCR] = { 0x48010, 0 },
3613	[GCC_PCNOC_BUS_TIMEOUT3_BCR] = { 0x48018, 0 },
3614	[GCC_PCNOC_BUS_TIMEOUT4_BCR] = { 0x48020, 0 },
3615	[GCC_PCNOC_BUS_TIMEOUT5_BCR] = { 0x48028, 0 },
3616	[GCC_PCNOC_BUS_TIMEOUT6_BCR] = { 0x48030, 0 },
3617	[GCC_PCNOC_BUS_TIMEOUT7_BCR] = { 0x48038, 0 },
3618	[GCC_PCNOC_BUS_TIMEOUT8_BCR] = { 0x48040, 0 },
3619	[GCC_PCNOC_BUS_TIMEOUT9_BCR] = { 0x48048, 0 },
3620	[GCC_PCNOC_BUS_TIMEOUT10_BCR] = { 0x48050, 0 },
3621	[GCC_PCNOC_BUS_TIMEOUT11_BCR] = { 0x48058, 0 },
3622	[GCC_PRNG_BCR] = { 0x13000, 0 },
3623	[GCC_Q6SS_DBG_ARES] = { 0x59110, 0 },
3624	[GCC_Q6_AHB_S_ARES] = { 0x59110, 1 },
3625	[GCC_Q6_AHB_ARES] = { 0x59110, 2 },
3626	[GCC_Q6_AXIM2_ARES] = { 0x59110, 3 },
3627	[GCC_Q6_AXIM_ARES] = { 0x59110, 4 },
3628	[GCC_Q6_AXIS_ARES] = { 0x59158, 0 },
3629	[GCC_QDSS_BCR] = { 0x29000, 0 },
3630	[GCC_QPIC_BCR] = { 0x57018, 0 },
3631	[GCC_QUSB2_0_PHY_BCR] = { 0x41030, 0 },
3632	[GCC_SDCC1_BCR] = { 0x42000, 0 },
3633	[GCC_SEC_CTRL_BCR] = { 0x1a000, 0 },
3634	[GCC_SPDM_BCR] = { 0x2f000, 0 },
3635	[GCC_SYSTEM_NOC_BCR] = { 0x26000, 0 },
3636	[GCC_TCSR_BCR] = { 0x28000, 0 },
3637	[GCC_TLMM_BCR] = { 0x34000, 0 },
3638	[GCC_UBI0_AXI_ARES] = { 0x68010, 0 },
3639	[GCC_UBI0_AHB_ARES] = { 0x68010, 1 },
3640	[GCC_UBI0_NC_AXI_ARES] = { 0x68010, 2 },
3641	[GCC_UBI0_DBG_ARES] = { 0x68010, 3 },
3642	[GCC_UBI0_UTCM_ARES] = { 0x68010, 6 },
3643	[GCC_UBI0_CORE_ARES] = { 0x68010, 7 },
3644	[GCC_UBI32_BCR] = { 0x19064, 0 },
3645	[GCC_UNIPHY_BCR] = { 0x56100, 0 },
3646	[GCC_UNIPHY_AHB_ARES] = { 0x56104, 0 },
3647	[GCC_UNIPHY_SYS_ARES] = { 0x56104, 1 },
3648	[GCC_UNIPHY_RX_ARES] = { 0x56104, 4 },
3649	[GCC_UNIPHY_TX_ARES] = { 0x56104, 5 },
3650	[GCC_UNIPHY_SOFT_RESET] = {0x56104, 0 },
3651	[GCC_USB0_BCR] = { 0x3e070, 0 },
3652	[GCC_USB0_PHY_BCR] = { 0x3e034, 0 },
3653	[GCC_WCSS_BCR] = { 0x18000, 0 },
3654	[GCC_WCSS_DBG_ARES] = { 0x59008, 0 },
3655	[GCC_WCSS_ECAHB_ARES] = { 0x59008, 1 },
3656	[GCC_WCSS_ACMT_ARES] = { 0x59008, 2 },
3657	[GCC_WCSS_DBG_BDG_ARES] = { 0x59008, 3 },
3658	[GCC_WCSS_AHB_S_ARES] = { 0x59008, 4 },
3659	[GCC_WCSS_AXI_M_ARES] = { 0x59008, 5 },
3660	[GCC_WCSS_AXI_S_ARES] = { 0x59008, 6 },
3661	[GCC_WCSS_Q6_BCR] = { 0x18004, 0 },
3662	[GCC_WCSSAON_RESET] = { 0x59010, 0},
3663	[GCC_GEPHY_MISC_ARES] = { 0x56004, 0 },
3664	};
3665
3666	static const struct of_device_id gcc_ipq5018_match_table[] = {
3667	{ .compatible = "qcom,gcc-ipq5018" },
3668	{ }
3669	};
3670	MODULE_DEVICE_TABLE(of, gcc_ipq5018_match_table);
3671
3672	static const struct regmap_config gcc_ipq5018_regmap_config = {
3673	.reg_bits = 32,
3674	.reg_stride = 4,
3675	.val_bits = 32,
3676	.max_register = 0x7fffc,
3677	.fast_io = true,
3678	};
3679
3680	static const struct qcom_cc_desc gcc_ipq5018_desc = {
3681	.config = &gcc_ipq5018_regmap_config,
3682	.clks = gcc_ipq5018_clks,
3683	.num_clks = ARRAY_SIZE(gcc_ipq5018_clks),
3684	.resets = gcc_ipq5018_resets,
3685	.num_resets = ARRAY_SIZE(gcc_ipq5018_resets),
3686	.clk_hws = gcc_ipq5018_hws,
3687	.num_clk_hws = ARRAY_SIZE(gcc_ipq5018_hws),
3688	};
3689
3690	static int gcc_ipq5018_probe(struct platform_device *pdev)
3691	{
3692	struct regmap *regmap;
3693	struct qcom_cc_desc ipq5018_desc = gcc_ipq5018_desc;
3694
3695	regmap = qcom_cc_map(pdev, desc: &ipq5018_desc);
3696	if (IS_ERR(ptr: regmap))
3697	return PTR_ERR(ptr: regmap);
3698
3699	clk_alpha_pll_configure(pll: &ubi32_pll_main, regmap, config: &ubi32_pll_config);
3700
3701	return qcom_cc_really_probe(pdev, desc: &ipq5018_desc, regmap);
3702	}
3703
3704	static struct platform_driver gcc_ipq5018_driver = {
3705	.probe = gcc_ipq5018_probe,
3706	.driver = {
3707	.name = "qcom,gcc-ipq5018",
3708	.of_match_table = gcc_ipq5018_match_table,
3709	},
3710	};
3711
3712	static int __init gcc_ipq5018_init(void)
3713	{
3714	return platform_driver_register(&gcc_ipq5018_driver);
3715	}
3716	core_initcall(gcc_ipq5018_init);
3717
3718	static void __exit gcc_ipq5018_exit(void)
3719	{
3720	platform_driver_unregister(&gcc_ipq5018_driver);
3721	}
3722	module_exit(gcc_ipq5018_exit);
3723
3724	MODULE_DESCRIPTION("Qualcomm Technologies, Inc. GCC IPQ5018 Driver");
3725	MODULE_LICENSE("GPL");
3726