1 | /* SPDX-License-Identifier: GPL-2.0-or-later */ |
2 | /* |
3 | * include/linux/amba/pl022.h |
4 | * |
5 | * Copyright (C) 2008-2009 ST-Ericsson AB |
6 | * Copyright (C) 2006 STMicroelectronics Pvt. Ltd. |
7 | * |
8 | * Author: Linus Walleij <linus.walleij@stericsson.com> |
9 | * |
10 | * Initial version inspired by: |
11 | * linux-2.6.17-rc3-mm1/drivers/spi/pxa2xx_spi.c |
12 | * Initial adoption to PL022 by: |
13 | * Sachin Verma <sachin.verma@st.com> |
14 | */ |
15 | |
16 | #ifndef _SSP_PL022_H |
17 | #define _SSP_PL022_H |
18 | |
19 | #include <linux/dmaengine.h> |
20 | #include <linux/types.h> |
21 | |
22 | /** |
23 | * whether SSP is in loopback mode or not |
24 | */ |
25 | enum ssp_loopback { |
26 | LOOPBACK_DISABLED, |
27 | LOOPBACK_ENABLED |
28 | }; |
29 | |
30 | /** |
31 | * enum ssp_interface - interfaces allowed for this SSP Controller |
32 | * @SSP_INTERFACE_MOTOROLA_SPI: Motorola Interface |
33 | * @SSP_INTERFACE_TI_SYNC_SERIAL: Texas Instrument Synchronous Serial |
34 | * interface |
35 | * @SSP_INTERFACE_NATIONAL_MICROWIRE: National Semiconductor Microwire |
36 | * interface |
37 | * @SSP_INTERFACE_UNIDIRECTIONAL: Unidirectional interface (STn8810 |
38 | * &STn8815 only) |
39 | */ |
40 | enum ssp_interface { |
41 | SSP_INTERFACE_MOTOROLA_SPI, |
42 | SSP_INTERFACE_TI_SYNC_SERIAL, |
43 | SSP_INTERFACE_NATIONAL_MICROWIRE, |
44 | SSP_INTERFACE_UNIDIRECTIONAL |
45 | }; |
46 | |
47 | /** |
48 | * enum ssp_hierarchy - whether SSP is configured as Master or Slave |
49 | */ |
50 | enum ssp_hierarchy { |
51 | SSP_MASTER, |
52 | SSP_SLAVE |
53 | }; |
54 | |
55 | /** |
56 | * enum ssp_clock_params - clock parameters, to set SSP clock at a |
57 | * desired freq |
58 | */ |
59 | struct ssp_clock_params { |
60 | u8 cpsdvsr; /* value from 2 to 254 (even only!) */ |
61 | u8 scr; /* value from 0 to 255 */ |
62 | }; |
63 | |
64 | /** |
65 | * enum ssp_rx_endian - endianess of Rx FIFO Data |
66 | * this feature is only available in ST versionf of PL022 |
67 | */ |
68 | enum ssp_rx_endian { |
69 | SSP_RX_MSB, |
70 | SSP_RX_LSB |
71 | }; |
72 | |
73 | /** |
74 | * enum ssp_tx_endian - endianess of Tx FIFO Data |
75 | */ |
76 | enum ssp_tx_endian { |
77 | SSP_TX_MSB, |
78 | SSP_TX_LSB |
79 | }; |
80 | |
81 | /** |
82 | * enum ssp_data_size - number of bits in one data element |
83 | */ |
84 | enum ssp_data_size { |
85 | SSP_DATA_BITS_4 = 0x03, SSP_DATA_BITS_5, SSP_DATA_BITS_6, |
86 | SSP_DATA_BITS_7, SSP_DATA_BITS_8, SSP_DATA_BITS_9, |
87 | SSP_DATA_BITS_10, SSP_DATA_BITS_11, SSP_DATA_BITS_12, |
88 | SSP_DATA_BITS_13, SSP_DATA_BITS_14, SSP_DATA_BITS_15, |
89 | SSP_DATA_BITS_16, SSP_DATA_BITS_17, SSP_DATA_BITS_18, |
90 | SSP_DATA_BITS_19, SSP_DATA_BITS_20, SSP_DATA_BITS_21, |
91 | SSP_DATA_BITS_22, SSP_DATA_BITS_23, SSP_DATA_BITS_24, |
92 | SSP_DATA_BITS_25, SSP_DATA_BITS_26, SSP_DATA_BITS_27, |
93 | SSP_DATA_BITS_28, SSP_DATA_BITS_29, SSP_DATA_BITS_30, |
94 | SSP_DATA_BITS_31, SSP_DATA_BITS_32 |
95 | }; |
96 | |
97 | /** |
98 | * enum ssp_mode - SSP mode of operation (Communication modes) |
99 | */ |
100 | enum ssp_mode { |
101 | INTERRUPT_TRANSFER, |
102 | POLLING_TRANSFER, |
103 | DMA_TRANSFER |
104 | }; |
105 | |
106 | /** |
107 | * enum ssp_rx_level_trig - receive FIFO watermark level which triggers |
108 | * IT: Interrupt fires when _N_ or more elements in RX FIFO. |
109 | */ |
110 | enum ssp_rx_level_trig { |
111 | SSP_RX_1_OR_MORE_ELEM, |
112 | SSP_RX_4_OR_MORE_ELEM, |
113 | SSP_RX_8_OR_MORE_ELEM, |
114 | SSP_RX_16_OR_MORE_ELEM, |
115 | SSP_RX_32_OR_MORE_ELEM |
116 | }; |
117 | |
118 | /** |
119 | * Transmit FIFO watermark level which triggers (IT Interrupt fires |
120 | * when _N_ or more empty locations in TX FIFO) |
121 | */ |
122 | enum ssp_tx_level_trig { |
123 | SSP_TX_1_OR_MORE_EMPTY_LOC, |
124 | SSP_TX_4_OR_MORE_EMPTY_LOC, |
125 | SSP_TX_8_OR_MORE_EMPTY_LOC, |
126 | SSP_TX_16_OR_MORE_EMPTY_LOC, |
127 | SSP_TX_32_OR_MORE_EMPTY_LOC |
128 | }; |
129 | |
130 | /** |
131 | * enum SPI Clock Phase - clock phase (Motorola SPI interface only) |
132 | * @SSP_CLK_FIRST_EDGE: Receive data on first edge transition (actual direction depends on polarity) |
133 | * @SSP_CLK_SECOND_EDGE: Receive data on second edge transition (actual direction depends on polarity) |
134 | */ |
135 | enum ssp_spi_clk_phase { |
136 | SSP_CLK_FIRST_EDGE, |
137 | SSP_CLK_SECOND_EDGE |
138 | }; |
139 | |
140 | /** |
141 | * enum SPI Clock Polarity - clock polarity (Motorola SPI interface only) |
142 | * @SSP_CLK_POL_IDLE_LOW: Low inactive level |
143 | * @SSP_CLK_POL_IDLE_HIGH: High inactive level |
144 | */ |
145 | enum ssp_spi_clk_pol { |
146 | SSP_CLK_POL_IDLE_LOW, |
147 | SSP_CLK_POL_IDLE_HIGH |
148 | }; |
149 | |
150 | /** |
151 | * Microwire Conrol Lengths Command size in microwire format |
152 | */ |
153 | enum ssp_microwire_ctrl_len { |
154 | SSP_BITS_4 = 0x03, SSP_BITS_5, SSP_BITS_6, |
155 | SSP_BITS_7, SSP_BITS_8, SSP_BITS_9, |
156 | SSP_BITS_10, SSP_BITS_11, SSP_BITS_12, |
157 | SSP_BITS_13, SSP_BITS_14, SSP_BITS_15, |
158 | SSP_BITS_16, SSP_BITS_17, SSP_BITS_18, |
159 | SSP_BITS_19, SSP_BITS_20, SSP_BITS_21, |
160 | SSP_BITS_22, SSP_BITS_23, SSP_BITS_24, |
161 | SSP_BITS_25, SSP_BITS_26, SSP_BITS_27, |
162 | SSP_BITS_28, SSP_BITS_29, SSP_BITS_30, |
163 | SSP_BITS_31, SSP_BITS_32 |
164 | }; |
165 | |
166 | /** |
167 | * enum Microwire Wait State |
168 | * @SSP_MWIRE_WAIT_ZERO: No wait state inserted after last command bit |
169 | * @SSP_MWIRE_WAIT_ONE: One wait state inserted after last command bit |
170 | */ |
171 | enum ssp_microwire_wait_state { |
172 | SSP_MWIRE_WAIT_ZERO, |
173 | SSP_MWIRE_WAIT_ONE |
174 | }; |
175 | |
176 | /** |
177 | * enum ssp_duplex - whether Full/Half Duplex on microwire, only |
178 | * available in the ST Micro variant. |
179 | * @SSP_MICROWIRE_CHANNEL_FULL_DUPLEX: SSPTXD becomes bi-directional, |
180 | * SSPRXD not used |
181 | * @SSP_MICROWIRE_CHANNEL_HALF_DUPLEX: SSPTXD is an output, SSPRXD is |
182 | * an input. |
183 | */ |
184 | enum ssp_duplex { |
185 | SSP_MICROWIRE_CHANNEL_FULL_DUPLEX, |
186 | SSP_MICROWIRE_CHANNEL_HALF_DUPLEX |
187 | }; |
188 | |
189 | /** |
190 | * enum ssp_clkdelay - an optional clock delay on the feedback clock |
191 | * only available in the ST Micro PL023 variant. |
192 | * @SSP_FEEDBACK_CLK_DELAY_NONE: no delay, the data coming in from the |
193 | * slave is sampled directly |
194 | * @SSP_FEEDBACK_CLK_DELAY_1T: the incoming slave data is sampled with |
195 | * a delay of T-dt |
196 | * @SSP_FEEDBACK_CLK_DELAY_2T: dito with a delay if 2T-dt |
197 | * @SSP_FEEDBACK_CLK_DELAY_3T: dito with a delay if 3T-dt |
198 | * @SSP_FEEDBACK_CLK_DELAY_4T: dito with a delay if 4T-dt |
199 | * @SSP_FEEDBACK_CLK_DELAY_5T: dito with a delay if 5T-dt |
200 | * @SSP_FEEDBACK_CLK_DELAY_6T: dito with a delay if 6T-dt |
201 | * @SSP_FEEDBACK_CLK_DELAY_7T: dito with a delay if 7T-dt |
202 | */ |
203 | enum ssp_clkdelay { |
204 | SSP_FEEDBACK_CLK_DELAY_NONE, |
205 | SSP_FEEDBACK_CLK_DELAY_1T, |
206 | SSP_FEEDBACK_CLK_DELAY_2T, |
207 | SSP_FEEDBACK_CLK_DELAY_3T, |
208 | SSP_FEEDBACK_CLK_DELAY_4T, |
209 | SSP_FEEDBACK_CLK_DELAY_5T, |
210 | SSP_FEEDBACK_CLK_DELAY_6T, |
211 | SSP_FEEDBACK_CLK_DELAY_7T |
212 | }; |
213 | |
214 | /** |
215 | * CHIP select/deselect commands |
216 | */ |
217 | enum ssp_chip_select { |
218 | SSP_CHIP_SELECT, |
219 | SSP_CHIP_DESELECT |
220 | }; |
221 | |
222 | |
223 | struct dma_chan; |
224 | /** |
225 | * struct pl022_ssp_master - device.platform_data for SPI controller devices. |
226 | * @bus_id: identifier for this bus |
227 | * @enable_dma: if true enables DMA driven transfers. |
228 | * @dma_filter: callback filter for dma_request_channel. |
229 | * @dma_rx_param: parameter to locate an RX DMA channel. |
230 | * @dma_tx_param: parameter to locate a TX DMA channel. |
231 | * @autosuspend_delay: delay in ms following transfer completion before the |
232 | * runtime power management system suspends the device. A setting of 0 |
233 | * indicates no delay and the device will be suspended immediately. |
234 | * @rt: indicates the controller should run the message pump with realtime |
235 | * priority to minimise the transfer latency on the bus. |
236 | */ |
237 | struct pl022_ssp_controller { |
238 | u16 bus_id; |
239 | u8 enable_dma:1; |
240 | dma_filter_fn dma_filter; |
241 | void *dma_rx_param; |
242 | void *dma_tx_param; |
243 | int autosuspend_delay; |
244 | bool rt; |
245 | }; |
246 | |
247 | /** |
248 | * struct ssp_config_chip - spi_board_info.controller_data for SPI |
249 | * slave devices, copied to spi_device.controller_data. |
250 | * |
251 | * @iface: Interface type(Motorola, TI, Microwire, Universal) |
252 | * @hierarchy: sets whether interface is master or slave |
253 | * @slave_tx_disable: SSPTXD is disconnected (in slave mode only) |
254 | * @clk_freq: Tune freq parameters of SSP(when in master mode) |
255 | * @com_mode: communication mode: polling, Interrupt or DMA |
256 | * @rx_lev_trig: Rx FIFO watermark level (for IT & DMA mode) |
257 | * @tx_lev_trig: Tx FIFO watermark level (for IT & DMA mode) |
258 | * @ctrl_len: Microwire interface: Control length |
259 | * @wait_state: Microwire interface: Wait state |
260 | * @duplex: Microwire interface: Full/Half duplex |
261 | * @clkdelay: on the PL023 variant, the delay in feeback clock cycles |
262 | * before sampling the incoming line |
263 | */ |
264 | struct pl022_config_chip { |
265 | enum ssp_interface iface; |
266 | enum ssp_hierarchy hierarchy; |
267 | bool slave_tx_disable; |
268 | struct ssp_clock_params clk_freq; |
269 | enum ssp_mode com_mode; |
270 | enum ssp_rx_level_trig rx_lev_trig; |
271 | enum ssp_tx_level_trig tx_lev_trig; |
272 | enum ssp_microwire_ctrl_len ctrl_len; |
273 | enum ssp_microwire_wait_state wait_state; |
274 | enum ssp_duplex duplex; |
275 | enum ssp_clkdelay clkdelay; |
276 | }; |
277 | |
278 | #endif /* _SSP_PL022_H */ |
279 | |