| 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
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| 2 | /* |
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| 3 | * Copyright (C) 2016-17 Synopsys, Inc. (www.synopsys.com) |
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| 4 | */ |
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| 5 | |
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| 6 | #ifndef __SOC_ARC_TIMERS_H |
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| 7 | #define __SOC_ARC_TIMERS_H |
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| 8 | |
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| 9 | #include <soc/arc/aux.h> |
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| 10 | |
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| 11 | /* Timer related Aux registers */ |
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| 12 | #define ARC_REG_TIMER0_LIMIT 0x23 /* timer 0 limit */ |
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| 13 | #define ARC_REG_TIMER0_CTRL 0x22 /* timer 0 control */ |
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| 14 | #define ARC_REG_TIMER0_CNT 0x21 /* timer 0 count */ |
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| 15 | #define ARC_REG_TIMER1_LIMIT 0x102 /* timer 1 limit */ |
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| 16 | #define ARC_REG_TIMER1_CTRL 0x101 /* timer 1 control */ |
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| 17 | #define ARC_REG_TIMER1_CNT 0x100 /* timer 1 count */ |
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| 18 | |
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| 19 | /* CTRL reg bits */ |
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| 20 | #define ARC_TIMER_CTRL_IE (1 << 0) /* Interrupt when Count reaches limit */ |
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| 21 | #define ARC_TIMER_CTRL_NH (1 << 1) /* Count only when CPU NOT halted */ |
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| 22 | |
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| 23 | #define ARC_TIMERN_MAX 0xFFFFFFFF |
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| 24 | |
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| 25 | #define ARC_REG_TIMERS_BCR 0x75 |
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| 26 | |
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| 27 | struct bcr_timer { |
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| 28 | #ifdef CONFIG_CPU_BIG_ENDIAN |
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| 29 | unsigned int pad2:15, rtsc:1, pad1:5, rtc:1, t1:1, t0:1, ver:8; |
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| 30 | #else |
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| 31 | unsigned int ver:8, t0:1, t1:1, rtc:1, pad1:5, rtsc:1, pad2:15; |
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| 32 | #endif |
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| 33 | }; |
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| 34 | |
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| 35 | #endif |
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| 36 | |
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