1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
2 | /* |
3 | * Copyright (C) 2008, Creative Technology Ltd. All Rights Reserved. |
4 | */ |
5 | |
6 | #ifndef CT20K1REG_H |
7 | #define CT20K1REG_H |
8 | |
9 | /* 20k1 registers */ |
10 | #define DSPXRAM_START 0x000000 |
11 | #define DSPXRAM_END 0x013FFC |
12 | #define DSPAXRAM_START 0x020000 |
13 | #define DSPAXRAM_END 0x023FFC |
14 | #define DSPYRAM_START 0x040000 |
15 | #define DSPYRAM_END 0x04FFFC |
16 | #define DSPAYRAM_START 0x020000 |
17 | #define DSPAYRAM_END 0x063FFC |
18 | #define DSPMICRO_START 0x080000 |
19 | #define DSPMICRO_END 0x0B3FFC |
20 | #define DSP0IO_START 0x100000 |
21 | #define DSP0IO_END 0x101FFC |
22 | #define AUDIORINGIPDSP0_START 0x100000 |
23 | #define AUDIORINGIPDSP0_END 0x1003FC |
24 | #define AUDIORINGOPDSP0_START 0x100400 |
25 | #define AUDIORINGOPDSP0_END 0x1007FC |
26 | #define AUDPARARINGIODSP0_START 0x100800 |
27 | #define AUDPARARINGIODSP0_END 0x100BFC |
28 | #define DSP0LOCALHWREG_START 0x100C00 |
29 | #define DSP0LOCALHWREG_END 0x100C3C |
30 | #define DSP0XYRAMAGINDEX_START 0x100C40 |
31 | #define DSP0XYRAMAGINDEX_END 0x100C5C |
32 | #define DSP0XYRAMAGMDFR_START 0x100C60 |
33 | #define DSP0XYRAMAGMDFR_END 0x100C7C |
34 | #define DSP0INTCONTLVEC_START 0x100C80 |
35 | #define DSP0INTCONTLVEC_END 0x100CD8 |
36 | #define INTCONTLGLOBALREG_START 0x100D1C |
37 | #define INTCONTLGLOBALREG_END 0x100D3C |
38 | #define HOSTINTFPORTADDRCONTDSP0 0x100D40 |
39 | #define HOSTINTFPORTDATADSP0 0x100D44 |
40 | #define TIME0PERENBDSP0 0x100D60 |
41 | #define TIME0COUNTERDSP0 0x100D64 |
42 | #define TIME1PERENBDSP0 0x100D68 |
43 | #define TIME1COUNTERDSP0 0x100D6C |
44 | #define TIME2PERENBDSP0 0x100D70 |
45 | #define TIME2COUNTERDSP0 0x100D74 |
46 | #define TIME3PERENBDSP0 0x100D78 |
47 | #define TIME3COUNTERDSP0 0x100D7C |
48 | #define XRAMINDOPERREFNOUP_STARTDSP0 0x100D80 |
49 | #define XRAMINDOPERREFNOUP_ENDDSP0 0x100D9C |
50 | #define XRAMINDOPERREFUP_STARTDSP0 0x100DA0 |
51 | #define XRAMINDOPERREFUP_ENDDSP0 0x100DBC |
52 | #define YRAMINDOPERREFNOUP_STARTDSP0 0x100DC0 |
53 | #define YRAMINDOPERREFNOUP_ENDDSP0 0x100DDC |
54 | #define YRAMINDOPERREFUP_STARTDSP0 0x100DE0 |
55 | #define YRAMINDOPERREFUP_ENDDSP0 0x100DFC |
56 | #define DSP0CONDCODE 0x100E00 |
57 | #define DSP0STACKFLAG 0x100E04 |
58 | #define DSP0PROGCOUNTSTACKPTREG 0x100E08 |
59 | #define DSP0PROGCOUNTSTACKDATAREG 0x100E0C |
60 | #define DSP0CURLOOPADDRREG 0x100E10 |
61 | #define DSP0CURLOOPCOUNT 0x100E14 |
62 | #define DSP0TOPLOOPCOUNTSTACK 0x100E18 |
63 | #define DSP0TOPLOOPADDRSTACK 0x100E1C |
64 | #define DSP0LOOPSTACKPTR 0x100E20 |
65 | #define DSP0STASSTACKDATAREG 0x100E24 |
66 | #define DSP0STASSTACKPTR 0x100E28 |
67 | #define DSP0PROGCOUNT 0x100E2C |
68 | #define GLOBDSPDEBGREG 0x100E30 |
69 | #define GLOBDSPBREPTRREG 0x100E30 |
70 | #define DSP0XYRAMBASE_START 0x100EA0 |
71 | #define DSP0XYRAMBASE_END 0x100EBC |
72 | #define DSP0XYRAMLENG_START 0x100EC0 |
73 | #define DSP0XYRAMLENG_END 0x100EDC |
74 | #define SEMAPHOREREGDSP0 0x100EE0 |
75 | #define DSP0INTCONTMASKREG 0x100EE4 |
76 | #define DSP0INTCONTPENDREG 0x100EE8 |
77 | #define DSP0INTCONTSERVINT 0x100EEC |
78 | #define DSPINTCONTEXTINTMODREG 0x100EEC |
79 | #define GPIODSP0 0x100EFC |
80 | #define DMADSPBASEADDRREG_STARTDSP0 0x100F00 |
81 | #define DMADSPBASEADDRREG_ENDDSP0 0x100F1C |
82 | #define DMAHOSTBASEADDRREG_STARTDSP0 0x100F20 |
83 | #define DMAHOSTBASEADDRREG_ENDDSP0 0x100F3C |
84 | #define DMADSPCURADDRREG_STARTDSP0 0x100F40 |
85 | #define DMADSPCURADDRREG_ENDDSP0 0x100F5C |
86 | #define DMAHOSTCURADDRREG_STARTDSP0 0x100F60 |
87 | #define DMAHOSTCURADDRREG_ENDDSP0 0x100F7C |
88 | #define DMATANXCOUNTREG_STARTDSP0 0x100F80 |
89 | #define DMATANXCOUNTREG_ENDDSP0 0x100F9C |
90 | #define DMATIMEBUGREG_STARTDSP0 0x100FA0 |
91 | #define DMATIMEBUGREG_ENDDSP0 0x100FAC |
92 | #define DMACNTLMODFREG_STARTDSP0 0x100FA0 |
93 | #define DMACNTLMODFREG_ENDDSP0 0x100FAC |
94 | |
95 | #define DMAGLOBSTATSREGDSP0 0x100FEC |
96 | #define DSP0XGPRAM_START 0x101000 |
97 | #define DSP0XGPRAM_END 0x1017FC |
98 | #define DSP0YGPRAM_START 0x101800 |
99 | #define DSP0YGPRAM_END 0x101FFC |
100 | |
101 | |
102 | |
103 | |
104 | #define AUDIORINGIPDSP1_START 0x102000 |
105 | #define AUDIORINGIPDSP1_END 0x1023FC |
106 | #define AUDIORINGOPDSP1_START 0x102400 |
107 | #define AUDIORINGOPDSP1_END 0x1027FC |
108 | #define AUDPARARINGIODSP1_START 0x102800 |
109 | #define AUDPARARINGIODSP1_END 0x102BFC |
110 | #define DSP1LOCALHWREG_START 0x102C00 |
111 | #define DSP1LOCALHWREG_END 0x102C3C |
112 | #define DSP1XYRAMAGINDEX_START 0x102C40 |
113 | #define DSP1XYRAMAGINDEX_END 0x102C5C |
114 | #define DSP1XYRAMAGMDFR_START 0x102C60 |
115 | #define DSP1XYRAMAGMDFR_END 0x102C7C |
116 | #define DSP1INTCONTLVEC_START 0x102C80 |
117 | #define DSP1INTCONTLVEC_END 0x102CD8 |
118 | #define HOSTINTFPORTADDRCONTDSP1 0x102D40 |
119 | #define HOSTINTFPORTDATADSP1 0x102D44 |
120 | #define TIME0PERENBDSP1 0x102D60 |
121 | #define TIME0COUNTERDSP1 0x102D64 |
122 | #define TIME1PERENBDSP1 0x102D68 |
123 | #define TIME1COUNTERDSP1 0x102D6C |
124 | #define TIME2PERENBDSP1 0x102D70 |
125 | #define TIME2COUNTERDSP1 0x102D74 |
126 | #define TIME3PERENBDSP1 0x102D78 |
127 | #define TIME3COUNTERDSP1 0x102D7C |
128 | #define XRAMINDOPERREFNOUP_STARTDSP1 0x102D80 |
129 | #define XRAMINDOPERREFNOUP_ENDDSP1 0x102D9C |
130 | #define XRAMINDOPERREFUP_STARTDSP1 0x102DA0 |
131 | #define XRAMINDOPERREFUP_ENDDSP1 0x102DBC |
132 | #define YRAMINDOPERREFNOUP_STARTDSP1 0x102DC0 |
133 | #define YRAMINDOPERREFNOUP_ENDDSP1 0x102DDC |
134 | #define YRAMINDOPERREFUP_STARTDSP1 0x102DE0 |
135 | #define YRAMINDOPERREFUP_ENDDSP1 0x102DFC |
136 | |
137 | #define DSP1CONDCODE 0x102E00 |
138 | #define DSP1STACKFLAG 0x102E04 |
139 | #define DSP1PROGCOUNTSTACKPTREG 0x102E08 |
140 | #define DSP1PROGCOUNTSTACKDATAREG 0x102E0C |
141 | #define DSP1CURLOOPADDRREG 0x102E10 |
142 | #define DSP1CURLOOPCOUNT 0x102E14 |
143 | #define DSP1TOPLOOPCOUNTSTACK 0x102E18 |
144 | #define DSP1TOPLOOPADDRSTACK 0x102E1C |
145 | #define DSP1LOOPSTACKPTR 0x102E20 |
146 | #define DSP1STASSTACKDATAREG 0x102E24 |
147 | #define DSP1STASSTACKPTR 0x102E28 |
148 | #define DSP1PROGCOUNT 0x102E2C |
149 | #define DSP1XYRAMBASE_START 0x102EA0 |
150 | #define DSP1XYRAMBASE_END 0x102EBC |
151 | #define DSP1XYRAMLENG_START 0x102EC0 |
152 | #define DSP1XYRAMLENG_END 0x102EDC |
153 | #define SEMAPHOREREGDSP1 0x102EE0 |
154 | #define DSP1INTCONTMASKREG 0x102EE4 |
155 | #define DSP1INTCONTPENDREG 0x102EE8 |
156 | #define DSP1INTCONTSERVINT 0x102EEC |
157 | #define GPIODSP1 0x102EFC |
158 | #define DMADSPBASEADDRREG_STARTDSP1 0x102F00 |
159 | #define DMADSPBASEADDRREG_ENDDSP1 0x102F1C |
160 | #define DMAHOSTBASEADDRREG_STARTDSP1 0x102F20 |
161 | #define DMAHOSTBASEADDRREG_ENDDSP1 0x102F3C |
162 | #define DMADSPCURADDRREG_STARTDSP1 0x102F40 |
163 | #define DMADSPCURADDRREG_ENDDSP1 0x102F5C |
164 | #define DMAHOSTCURADDRREG_STARTDSP1 0x102F60 |
165 | #define DMAHOSTCURADDRREG_ENDDSP1 0x102F7C |
166 | #define DMATANXCOUNTREG_STARTDSP1 0x102F80 |
167 | #define DMATANXCOUNTREG_ENDDSP1 0x102F9C |
168 | #define DMATIMEBUGREG_STARTDSP1 0x102FA0 |
169 | #define DMATIMEBUGREG_ENDDSP1 0x102FAC |
170 | #define DMACNTLMODFREG_STARTDSP1 0x102FA0 |
171 | #define DMACNTLMODFREG_ENDDSP1 0x102FAC |
172 | |
173 | #define DMAGLOBSTATSREGDSP1 0x102FEC |
174 | #define DSP1XGPRAM_START 0x103000 |
175 | #define DSP1XGPRAM_END 0x1033FC |
176 | #define DSP1YGPRAM_START 0x103400 |
177 | #define DSP1YGPRAM_END 0x1037FC |
178 | |
179 | |
180 | |
181 | #define AUDIORINGIPDSP2_START 0x104000 |
182 | #define AUDIORINGIPDSP2_END 0x1043FC |
183 | #define AUDIORINGOPDSP2_START 0x104400 |
184 | #define AUDIORINGOPDSP2_END 0x1047FC |
185 | #define AUDPARARINGIODSP2_START 0x104800 |
186 | #define AUDPARARINGIODSP2_END 0x104BFC |
187 | #define DSP2LOCALHWREG_START 0x104C00 |
188 | #define DSP2LOCALHWREG_END 0x104C3C |
189 | #define DSP2XYRAMAGINDEX_START 0x104C40 |
190 | #define DSP2XYRAMAGINDEX_END 0x104C5C |
191 | #define DSP2XYRAMAGMDFR_START 0x104C60 |
192 | #define DSP2XYRAMAGMDFR_END 0x104C7C |
193 | #define DSP2INTCONTLVEC_START 0x104C80 |
194 | #define DSP2INTCONTLVEC_END 0x104CD8 |
195 | #define HOSTINTFPORTADDRCONTDSP2 0x104D40 |
196 | #define HOSTINTFPORTDATADSP2 0x104D44 |
197 | #define TIME0PERENBDSP2 0x104D60 |
198 | #define TIME0COUNTERDSP2 0x104D64 |
199 | #define TIME1PERENBDSP2 0x104D68 |
200 | #define TIME1COUNTERDSP2 0x104D6C |
201 | #define TIME2PERENBDSP2 0x104D70 |
202 | #define TIME2COUNTERDSP2 0x104D74 |
203 | #define TIME3PERENBDSP2 0x104D78 |
204 | #define TIME3COUNTERDSP2 0x104D7C |
205 | #define XRAMINDOPERREFNOUP_STARTDSP2 0x104D80 |
206 | #define XRAMINDOPERREFNOUP_ENDDSP2 0x104D9C |
207 | #define XRAMINDOPERREFUP_STARTDSP2 0x104DA0 |
208 | #define XRAMINDOPERREFUP_ENDDSP2 0x104DBC |
209 | #define YRAMINDOPERREFNOUP_STARTDSP2 0x104DC0 |
210 | #define YRAMINDOPERREFNOUP_ENDDSP2 0x104DDC |
211 | #define YRAMINDOPERREFUP_STARTDSP2 0x104DE0 |
212 | #define YRAMINDOPERREFUP_ENDDSP2 0x104DFC |
213 | #define DSP2CONDCODE 0x104E00 |
214 | #define DSP2STACKFLAG 0x104E04 |
215 | #define DSP2PROGCOUNTSTACKPTREG 0x104E08 |
216 | #define DSP2PROGCOUNTSTACKDATAREG 0x104E0C |
217 | #define DSP2CURLOOPADDRREG 0x104E10 |
218 | #define DSP2CURLOOPCOUNT 0x104E14 |
219 | #define DSP2TOPLOOPCOUNTSTACK 0x104E18 |
220 | #define DSP2TOPLOOPADDRSTACK 0x104E1C |
221 | #define DSP2LOOPSTACKPTR 0x104E20 |
222 | #define DSP2STASSTACKDATAREG 0x104E24 |
223 | #define DSP2STASSTACKPTR 0x104E28 |
224 | #define DSP2PROGCOUNT 0x104E2C |
225 | #define DSP2XYRAMBASE_START 0x104EA0 |
226 | #define DSP2XYRAMBASE_END 0x104EBC |
227 | #define DSP2XYRAMLENG_START 0x104EC0 |
228 | #define DSP2XYRAMLENG_END 0x104EDC |
229 | #define SEMAPHOREREGDSP2 0x104EE0 |
230 | #define DSP2INTCONTMASKREG 0x104EE4 |
231 | #define DSP2INTCONTPENDREG 0x104EE8 |
232 | #define DSP2INTCONTSERVINT 0x104EEC |
233 | #define GPIODSP2 0x104EFC |
234 | #define DMADSPBASEADDRREG_STARTDSP2 0x104F00 |
235 | #define DMADSPBASEADDRREG_ENDDSP2 0x104F1C |
236 | #define DMAHOSTBASEADDRREG_STARTDSP2 0x104F20 |
237 | #define DMAHOSTBASEADDRREG_ENDDSP2 0x104F3C |
238 | #define DMADSPCURADDRREG_STARTDSP2 0x104F40 |
239 | #define DMADSPCURADDRREG_ENDDSP2 0x104F5C |
240 | #define DMAHOSTCURADDRREG_STARTDSP2 0x104F60 |
241 | #define DMAHOSTCURADDRREG_ENDDSP2 0x104F7C |
242 | #define DMATANXCOUNTREG_STARTDSP2 0x104F80 |
243 | #define DMATANXCOUNTREG_ENDDSP2 0x104F9C |
244 | #define DMATIMEBUGREG_STARTDSP2 0x104FA0 |
245 | #define DMATIMEBUGREG_ENDDSP2 0x104FAC |
246 | #define DMACNTLMODFREG_STARTDSP2 0x104FA0 |
247 | #define DMACNTLMODFREG_ENDDSP2 0x104FAC |
248 | |
249 | #define DMAGLOBSTATSREGDSP2 0x104FEC |
250 | #define DSP2XGPRAM_START 0x105000 |
251 | #define DSP2XGPRAM_END 0x1051FC |
252 | #define DSP2YGPRAM_START 0x105800 |
253 | #define DSP2YGPRAM_END 0x1059FC |
254 | |
255 | |
256 | |
257 | #define AUDIORINGIPDSP3_START 0x106000 |
258 | #define AUDIORINGIPDSP3_END 0x1063FC |
259 | #define AUDIORINGOPDSP3_START 0x106400 |
260 | #define AUDIORINGOPDSP3_END 0x1067FC |
261 | #define AUDPARARINGIODSP3_START 0x106800 |
262 | #define AUDPARARINGIODSP3_END 0x106BFC |
263 | #define DSP3LOCALHWREG_START 0x106C00 |
264 | #define DSP3LOCALHWREG_END 0x106C3C |
265 | #define DSP3XYRAMAGINDEX_START 0x106C40 |
266 | #define DSP3XYRAMAGINDEX_END 0x106C5C |
267 | #define DSP3XYRAMAGMDFR_START 0x106C60 |
268 | #define DSP3XYRAMAGMDFR_END 0x106C7C |
269 | #define DSP3INTCONTLVEC_START 0x106C80 |
270 | #define DSP3INTCONTLVEC_END 0x106CD8 |
271 | #define HOSTINTFPORTADDRCONTDSP3 0x106D40 |
272 | #define HOSTINTFPORTDATADSP3 0x106D44 |
273 | #define TIME0PERENBDSP3 0x106D60 |
274 | #define TIME0COUNTERDSP3 0x106D64 |
275 | #define TIME1PERENBDSP3 0x106D68 |
276 | #define TIME1COUNTERDSP3 0x106D6C |
277 | #define TIME2PERENBDSP3 0x106D70 |
278 | #define TIME2COUNTERDSP3 0x106D74 |
279 | #define TIME3PERENBDSP3 0x106D78 |
280 | #define TIME3COUNTERDSP3 0x106D7C |
281 | #define XRAMINDOPERREFNOUP_STARTDSP3 0x106D80 |
282 | #define XRAMINDOPERREFNOUP_ENDDSP3 0x106D9C |
283 | #define XRAMINDOPERREFUP_STARTDSP3 0x106DA0 |
284 | #define XRAMINDOPERREFUP_ENDDSP3 0x106DBC |
285 | #define YRAMINDOPERREFNOUP_STARTDSP3 0x106DC0 |
286 | #define YRAMINDOPERREFNOUP_ENDDSP3 0x106DDC |
287 | #define YRAMINDOPERREFUP_STARTDSP3 0x106DE0 |
288 | #define YRAMINDOPERREFUP_ENDDSP3 0x100DFC |
289 | |
290 | #define DSP3CONDCODE 0x106E00 |
291 | #define DSP3STACKFLAG 0x106E04 |
292 | #define DSP3PROGCOUNTSTACKPTREG 0x106E08 |
293 | #define DSP3PROGCOUNTSTACKDATAREG 0x106E0C |
294 | #define DSP3CURLOOPADDRREG 0x106E10 |
295 | #define DSP3CURLOOPCOUNT 0x106E14 |
296 | #define DSP3TOPLOOPCOUNTSTACK 0x106E18 |
297 | #define DSP3TOPLOOPADDRSTACK 0x106E1C |
298 | #define DSP3LOOPSTACKPTR 0x106E20 |
299 | #define DSP3STASSTACKDATAREG 0x106E24 |
300 | #define DSP3STASSTACKPTR 0x106E28 |
301 | #define DSP3PROGCOUNT 0x106E2C |
302 | #define DSP3XYRAMBASE_START 0x106EA0 |
303 | #define DSP3XYRAMBASE_END 0x106EBC |
304 | #define DSP3XYRAMLENG_START 0x106EC0 |
305 | #define DSP3XYRAMLENG_END 0x106EDC |
306 | #define SEMAPHOREREGDSP3 0x106EE0 |
307 | #define DSP3INTCONTMASKREG 0x106EE4 |
308 | #define DSP3INTCONTPENDREG 0x106EE8 |
309 | #define DSP3INTCONTSERVINT 0x106EEC |
310 | #define GPIODSP3 0x106EFC |
311 | #define DMADSPBASEADDRREG_STARTDSP3 0x106F00 |
312 | #define DMADSPBASEADDRREG_ENDDSP3 0x106F1C |
313 | #define DMAHOSTBASEADDRREG_STARTDSP3 0x106F20 |
314 | #define DMAHOSTBASEADDRREG_ENDDSP3 0x106F3C |
315 | #define DMADSPCURADDRREG_STARTDSP3 0x106F40 |
316 | #define DMADSPCURADDRREG_ENDDSP3 0x106F5C |
317 | #define DMAHOSTCURADDRREG_STARTDSP3 0x106F60 |
318 | #define DMAHOSTCURADDRREG_ENDDSP3 0x106F7C |
319 | #define DMATANXCOUNTREG_STARTDSP3 0x106F80 |
320 | #define DMATANXCOUNTREG_ENDDSP3 0x106F9C |
321 | #define DMATIMEBUGREG_STARTDSP3 0x106FA0 |
322 | #define DMATIMEBUGREG_ENDDSP3 0x106FAC |
323 | #define DMACNTLMODFREG_STARTDSP3 0x106FA0 |
324 | #define DMACNTLMODFREG_ENDDSP3 0x106FAC |
325 | |
326 | #define DMAGLOBSTATSREGDSP3 0x106FEC |
327 | #define DSP3XGPRAM_START 0x107000 |
328 | #define DSP3XGPRAM_END 0x1071FC |
329 | #define DSP3YGPRAM_START 0x107800 |
330 | #define DSP3YGPRAM_END 0x1079FC |
331 | |
332 | /* end of DSP reg definitions */ |
333 | |
334 | #define DSPAIMAP_START 0x108000 |
335 | #define DSPAIMAP_END 0x1083FC |
336 | #define DSPPIMAP_START 0x108400 |
337 | #define DSPPIMAP_END 0x1087FC |
338 | #define DSPPOMAP_START 0x108800 |
339 | #define DSPPOMAP_END 0x108BFC |
340 | #define DSPPOCTL 0x108C00 |
341 | #define TKCTL_START 0x110000 |
342 | #define TKCTL_END 0x110FFC |
343 | #define TKCC_START 0x111000 |
344 | #define TKCC_END 0x111FFC |
345 | #define TKIMAP_START 0x112000 |
346 | #define TKIMAP_END 0x112FFC |
347 | #define TKDCTR16 0x113000 |
348 | #define TKPB16 0x113004 |
349 | #define TKBS16 0x113008 |
350 | #define TKDCTR32 0x11300C |
351 | #define TKPB32 0x113010 |
352 | #define TKBS32 0x113014 |
353 | #define ICDCTR16 0x113018 |
354 | #define ITBS16 0x11301C |
355 | #define ICDCTR32 0x113020 |
356 | #define ITBS32 0x113024 |
357 | #define ITSTART 0x113028 |
358 | #define TKSQ 0x11302C |
359 | |
360 | #define TKSCCTL_START 0x114000 |
361 | #define TKSCCTL_END 0x11403C |
362 | #define TKSCADR_START 0x114100 |
363 | #define TKSCADR_END 0x11413C |
364 | #define TKSCDATAX_START 0x114800 |
365 | #define TKSCDATAX_END 0x1149FC |
366 | #define TKPCDATAX_START 0x120000 |
367 | #define TKPCDATAX_END 0x12FFFC |
368 | |
369 | #define MALSA 0x130000 |
370 | #define MAPPHA 0x130004 |
371 | #define MAPPLA 0x130008 |
372 | #define MALSB 0x130010 |
373 | #define MAPPHB 0x130014 |
374 | #define MAPPLB 0x130018 |
375 | |
376 | #define TANSPORTMAPABREGS_START 0x130020 |
377 | #define TANSPORTMAPABREGS_END 0x13A2FC |
378 | |
379 | #define PTPAHX 0x13B000 |
380 | #define PTPALX 0x13B004 |
381 | |
382 | #define TANSPPAGETABLEPHYADDR015_START 0x13B008 |
383 | #define TANSPPAGETABLEPHYADDR015_END 0x13B07C |
384 | #define TRNQADRX_START 0x13B100 |
385 | #define TRNQADRX_END 0x13B13C |
386 | #define TRNQTIMX_START 0x13B200 |
387 | #define TRNQTIMX_END 0x13B23C |
388 | #define TRNQAPARMX_START 0x13B300 |
389 | #define TRNQAPARMX_END 0x13B33C |
390 | |
391 | #define TRNQCNT 0x13B400 |
392 | #define TRNCTL 0x13B404 |
393 | #define TRNIS 0x13B408 |
394 | #define TRNCURTS 0x13B40C |
395 | |
396 | #define AMOP_START 0x140000 |
397 | #define AMOPLO 0x140000 |
398 | #define AMOPHI 0x140004 |
399 | #define AMOP_END 0x147FFC |
400 | #define PMOP_START 0x148000 |
401 | #define PMOPLO 0x148000 |
402 | #define PMOPHI 0x148004 |
403 | #define PMOP_END 0x14FFFC |
404 | #define PCURR_START 0x150000 |
405 | #define PCURR_END 0x153FFC |
406 | #define PTRAG_START 0x154000 |
407 | #define PTRAG_END 0x157FFC |
408 | #define PSR_START 0x158000 |
409 | #define PSR_END 0x15BFFC |
410 | |
411 | #define PFSTAT4SEG_START 0x160000 |
412 | #define PFSTAT4SEG_END 0x160BFC |
413 | #define PFSTAT2SEG_START 0x160C00 |
414 | #define PFSTAT2SEG_END 0x1617FC |
415 | #define PFTARG4SEG_START 0x164000 |
416 | #define PFTARG4SEG_END 0x164BFC |
417 | #define PFTARG2SEG_START 0x164C00 |
418 | #define PFTARG2SEG_END 0x1657FC |
419 | #define PFSR4SEG_START 0x168000 |
420 | #define PFSR4SEG_END 0x168BFC |
421 | #define PFSR2SEG_START 0x168C00 |
422 | #define PFSR2SEG_END 0x1697FC |
423 | #define PCURRMS4SEG_START 0x16C000 |
424 | #define PCURRMS4SEG_END 0x16CCFC |
425 | #define PCURRMS2SEG_START 0x16CC00 |
426 | #define PCURRMS2SEG_END 0x16D7FC |
427 | #define PTARGMS4SEG_START 0x170000 |
428 | #define PTARGMS4SEG_END 0x172FFC |
429 | #define PTARGMS2SEG_START 0x173000 |
430 | #define PTARGMS2SEG_END 0x1747FC |
431 | #define PSRMS4SEG_START 0x170000 |
432 | #define PSRMS4SEG_END 0x172FFC |
433 | #define PSRMS2SEG_START 0x173000 |
434 | #define PSRMS2SEG_END 0x1747FC |
435 | |
436 | #define PRING_LO_START 0x190000 |
437 | #define PRING_LO_END 0x193FFC |
438 | #define PRING_HI_START 0x194000 |
439 | #define PRING_HI_END 0x197FFC |
440 | #define PRING_LO_HI_START 0x198000 |
441 | #define PRING_LO_HI 0x198000 |
442 | #define PRING_LO_HI_END 0x19BFFC |
443 | |
444 | #define PINTFIFO 0x1A0000 |
445 | #define SRCCTL 0x1B0000 |
446 | #define SRCCCR 0x1B0004 |
447 | #define SRCIMAP 0x1B0008 |
448 | #define SRCODDC 0x1B000C |
449 | #define SRCCA 0x1B0010 |
450 | #define SRCCF 0x1B0014 |
451 | #define SRCSA 0x1B0018 |
452 | #define SRCLA 0x1B001C |
453 | #define SRCCTLSWR 0x1B0020 |
454 | |
455 | /* SRC HERE */ |
456 | #define SRCALBA 0x1B002C |
457 | #define SRCMCTL 0x1B012C |
458 | #define SRCCERR 0x1B022C |
459 | #define SRCITB 0x1B032C |
460 | #define SRCIPM 0x1B082C |
461 | #define SRCIP 0x1B102C |
462 | #define SRCENBSTAT 0x1B202C |
463 | #define SRCENBLO 0x1B212C |
464 | #define SRCENBHI 0x1B222C |
465 | #define SRCENBS 0x1B232C |
466 | #define SRCENB 0x1B282C |
467 | #define SRCENB07 0x1B282C |
468 | #define SRCENBS07 0x1B302C |
469 | |
470 | #define SRCDN0Z 0x1B0030 |
471 | #define SRCDN0Z0 0x1B0030 |
472 | #define SRCDN0Z1 0x1B0034 |
473 | #define SRCDN0Z2 0x1B0038 |
474 | #define SRCDN0Z3 0x1B003C |
475 | #define SRCDN1Z 0x1B0040 |
476 | #define SRCDN1Z0 0x1B0040 |
477 | #define SRCDN1Z1 0x1B0044 |
478 | #define SRCDN1Z2 0x1B0048 |
479 | #define SRCDN1Z3 0x1B004C |
480 | #define SRCDN1Z4 0x1B0050 |
481 | #define SRCDN1Z5 0x1B0054 |
482 | #define SRCDN1Z6 0x1B0058 |
483 | #define SRCDN1Z7 0x1B005C |
484 | #define SRCUPZ 0x1B0060 |
485 | #define SRCUPZ0 0x1B0060 |
486 | #define SRCUPZ1 0x1B0064 |
487 | #define SRCUPZ2 0x1B0068 |
488 | #define SRCUPZ3 0x1B006C |
489 | #define SRCUPZ4 0x1B0070 |
490 | #define SRCUPZ5 0x1B0074 |
491 | #define SRCUPZ6 0x1B0078 |
492 | #define SRCUPZ7 0x1B007C |
493 | #define SRCCD0 0x1B0080 |
494 | #define SRCCD1 0x1B0084 |
495 | #define SRCCD2 0x1B0088 |
496 | #define SRCCD3 0x1B008C |
497 | #define SRCCD4 0x1B0090 |
498 | #define SRCCD5 0x1B0094 |
499 | #define SRCCD6 0x1B0098 |
500 | #define SRCCD7 0x1B009C |
501 | #define SRCCD8 0x1B00A0 |
502 | #define SRCCD9 0x1B00A4 |
503 | #define SRCCDA 0x1B00A8 |
504 | #define SRCCDB 0x1B00AC |
505 | #define SRCCDC 0x1B00B0 |
506 | #define SRCCDD 0x1B00B4 |
507 | #define SRCCDE 0x1B00B8 |
508 | #define SRCCDF 0x1B00BC |
509 | #define SRCCD10 0x1B00C0 |
510 | #define SRCCD11 0x1B00C4 |
511 | #define SRCCD12 0x1B00C8 |
512 | #define SRCCD13 0x1B00CC |
513 | #define SRCCD14 0x1B00D0 |
514 | #define SRCCD15 0x1B00D4 |
515 | #define SRCCD16 0x1B00D8 |
516 | #define SRCCD17 0x1B00DC |
517 | #define SRCCD18 0x1B00E0 |
518 | #define SRCCD19 0x1B00E4 |
519 | #define SRCCD1A 0x1B00E8 |
520 | #define SRCCD1B 0x1B00EC |
521 | #define SRCCD1C 0x1B00F0 |
522 | #define SRCCD1D 0x1B00F4 |
523 | #define SRCCD1E 0x1B00F8 |
524 | #define SRCCD1F 0x1B00FC |
525 | |
526 | #define SRCCONTRBLOCK_START 0x1B0100 |
527 | #define SRCCONTRBLOCK_END 0x1BFFFC |
528 | #define FILTOP_START 0x1C0000 |
529 | #define FILTOP_END 0x1C05FC |
530 | #define FILTIMAP_START 0x1C0800 |
531 | #define FILTIMAP_END 0x1C0DFC |
532 | #define FILTZ1_START 0x1C1000 |
533 | #define FILTZ1_END 0x1C15FC |
534 | #define FILTZ2_START 0x1C1800 |
535 | #define FILTZ2_END 0x1C1DFC |
536 | #define DAOIMAP_START 0x1C5000 |
537 | #define DAOIMAP 0x1C5000 |
538 | #define DAOIMAP_END 0x1C5124 |
539 | |
540 | #define AC97D 0x1C5400 |
541 | #define AC97A 0x1C5404 |
542 | #define AC97CTL 0x1C5408 |
543 | #define I2SCTL 0x1C5420 |
544 | |
545 | #define SPOS 0x1C5440 |
546 | #define SPOSA 0x1C5440 |
547 | #define SPOSB 0x1C5444 |
548 | #define SPOSC 0x1C5448 |
549 | #define SPOSD 0x1C544C |
550 | |
551 | #define SPISA 0x1C5450 |
552 | #define SPISB 0x1C5454 |
553 | #define SPISC 0x1C5458 |
554 | #define SPISD 0x1C545C |
555 | |
556 | #define SPFSCTL 0x1C5460 |
557 | |
558 | #define SPFS0 0x1C5468 |
559 | #define SPFS1 0x1C546C |
560 | #define SPFS2 0x1C5470 |
561 | #define SPFS3 0x1C5474 |
562 | #define SPFS4 0x1C5478 |
563 | #define SPFS5 0x1C547C |
564 | |
565 | #define SPOCTL 0x1C5480 |
566 | #define SPICTL 0x1C5484 |
567 | #define SPISTS 0x1C5488 |
568 | #define SPINTP 0x1C548C |
569 | #define SPINTE 0x1C5490 |
570 | #define SPUTCTLAB 0x1C5494 |
571 | #define SPUTCTLCD 0x1C5498 |
572 | |
573 | #define SRTSPA 0x1C54C0 |
574 | #define SRTSPB 0x1C54C4 |
575 | #define SRTSPC 0x1C54C8 |
576 | #define SRTSPD 0x1C54CC |
577 | |
578 | #define SRTSCTL 0x1C54D0 |
579 | #define SRTSCTLA 0x1C54D0 |
580 | #define SRTSCTLB 0x1C54D4 |
581 | #define SRTSCTLC 0x1C54D8 |
582 | #define SRTSCTLD 0x1C54DC |
583 | |
584 | #define SRTI2S 0x1C54E0 |
585 | #define SRTICTL 0x1C54F0 |
586 | |
587 | #define WC 0x1C6000 |
588 | #define TIMR 0x1C6004 |
589 | # define TIMR_IE (1<<15) |
590 | # define TIMR_IP (1<<14) |
591 | |
592 | #define GIP 0x1C6010 |
593 | #define GIE 0x1C6014 |
594 | #define DIE 0x1C6018 |
595 | #define DIC 0x1C601C |
596 | #define GPIO 0x1C6020 |
597 | #define GPIOCTL 0x1C6024 |
598 | #define GPIP 0x1C6028 |
599 | #define GPIE 0x1C602C |
600 | #define DSPINT0 0x1C6030 |
601 | #define DSPEIOC 0x1C6034 |
602 | #define MUADAT 0x1C6040 |
603 | #define MUACMD 0x1C6044 |
604 | #define MUASTAT 0x1C6044 |
605 | #define MUBDAT 0x1C6048 |
606 | #define MUBCMD 0x1C604C |
607 | #define MUBSTAT 0x1C604C |
608 | #define UARTCMA 0x1C6050 |
609 | #define UARTCMB 0x1C6054 |
610 | #define UARTIP 0x1C6058 |
611 | #define UARTIE 0x1C605C |
612 | #define PLLCTL 0x1C6060 |
613 | #define PLLDCD 0x1C6064 |
614 | #define GCTL 0x1C6070 |
615 | #define ID0 0x1C6080 |
616 | #define ID1 0x1C6084 |
617 | #define ID2 0x1C6088 |
618 | #define ID3 0x1C608C |
619 | #define SDRCTL 0x1C7000 |
620 | |
621 | |
622 | #define I2SA_L 0x0L |
623 | #define I2SA_R 0x1L |
624 | #define I2SB_L 0x8L |
625 | #define I2SB_R 0x9L |
626 | #define I2SC_L 0x10L |
627 | #define I2SC_R 0x11L |
628 | #define I2SD_L 0x18L |
629 | #define I2SD_R 0x19L |
630 | |
631 | #endif /* CT20K1REG_H */ |
632 | |