1 | // SPDX-License-Identifier: GPL-2.0-only |
2 | /* |
3 | * Copyright (C) 2008, Creative Technology Ltd. All Rights Reserved. |
4 | * |
5 | * @File cthw20k1.c |
6 | * |
7 | * @Brief |
8 | * This file contains the implementation of hardware access methord for 20k1. |
9 | * |
10 | * @Author Liu Chun |
11 | * @Date Jun 24 2008 |
12 | */ |
13 | |
14 | #include <linux/types.h> |
15 | #include <linux/slab.h> |
16 | #include <linux/pci.h> |
17 | #include <linux/io.h> |
18 | #include <linux/string.h> |
19 | #include <linux/spinlock.h> |
20 | #include <linux/kernel.h> |
21 | #include <linux/interrupt.h> |
22 | #include <linux/delay.h> |
23 | #include "cthw20k1.h" |
24 | #include "ct20k1reg.h" |
25 | |
26 | struct hw20k1 { |
27 | struct hw hw; |
28 | spinlock_t reg_20k1_lock; |
29 | spinlock_t reg_pci_lock; |
30 | }; |
31 | |
32 | static u32 hw_read_20kx(struct hw *hw, u32 reg); |
33 | static void hw_write_20kx(struct hw *hw, u32 reg, u32 data); |
34 | static u32 hw_read_pci(struct hw *hw, u32 reg); |
35 | static void hw_write_pci(struct hw *hw, u32 reg, u32 data); |
36 | |
37 | /* |
38 | * Type definition block. |
39 | * The layout of control structures can be directly applied on 20k2 chip. |
40 | */ |
41 | |
42 | /* |
43 | * SRC control block definitions. |
44 | */ |
45 | |
46 | /* SRC resource control block */ |
47 | #define SRCCTL_STATE 0x00000007 |
48 | #define SRCCTL_BM 0x00000008 |
49 | #define SRCCTL_RSR 0x00000030 |
50 | #define SRCCTL_SF 0x000001C0 |
51 | #define SRCCTL_WR 0x00000200 |
52 | #define SRCCTL_PM 0x00000400 |
53 | #define SRCCTL_ROM 0x00001800 |
54 | #define SRCCTL_VO 0x00002000 |
55 | #define SRCCTL_ST 0x00004000 |
56 | #define SRCCTL_IE 0x00008000 |
57 | #define SRCCTL_ILSZ 0x000F0000 |
58 | #define SRCCTL_BP 0x00100000 |
59 | |
60 | #define SRCCCR_CISZ 0x000007FF |
61 | #define SRCCCR_CWA 0x001FF800 |
62 | #define SRCCCR_D 0x00200000 |
63 | #define SRCCCR_RS 0x01C00000 |
64 | #define SRCCCR_NAL 0x3E000000 |
65 | #define SRCCCR_RA 0xC0000000 |
66 | |
67 | #define SRCCA_CA 0x03FFFFFF |
68 | #define SRCCA_RS 0x1C000000 |
69 | #define SRCCA_NAL 0xE0000000 |
70 | |
71 | #define SRCSA_SA 0x03FFFFFF |
72 | |
73 | #define SRCLA_LA 0x03FFFFFF |
74 | |
75 | /* Mixer Parameter Ring ram Low and Hight register. |
76 | * Fixed-point value in 8.24 format for parameter channel */ |
77 | #define MPRLH_PITCH 0xFFFFFFFF |
78 | |
79 | /* SRC resource register dirty flags */ |
80 | union src_dirty { |
81 | struct { |
82 | u16 ctl:1; |
83 | u16 ccr:1; |
84 | u16 sa:1; |
85 | u16 la:1; |
86 | u16 ca:1; |
87 | u16 mpr:1; |
88 | u16 czbfs:1; /* Clear Z-Buffers */ |
89 | u16 rsv:9; |
90 | } bf; |
91 | u16 data; |
92 | }; |
93 | |
94 | struct src_rsc_ctrl_blk { |
95 | unsigned int ctl; |
96 | unsigned int ccr; |
97 | unsigned int ca; |
98 | unsigned int sa; |
99 | unsigned int la; |
100 | unsigned int mpr; |
101 | union src_dirty dirty; |
102 | }; |
103 | |
104 | /* SRC manager control block */ |
105 | union src_mgr_dirty { |
106 | struct { |
107 | u16 enb0:1; |
108 | u16 enb1:1; |
109 | u16 enb2:1; |
110 | u16 enb3:1; |
111 | u16 enb4:1; |
112 | u16 enb5:1; |
113 | u16 enb6:1; |
114 | u16 enb7:1; |
115 | u16 enbsa:1; |
116 | u16 rsv:7; |
117 | } bf; |
118 | u16 data; |
119 | }; |
120 | |
121 | struct src_mgr_ctrl_blk { |
122 | unsigned int enbsa; |
123 | unsigned int enb[8]; |
124 | union src_mgr_dirty dirty; |
125 | }; |
126 | |
127 | /* SRCIMP manager control block */ |
128 | #define SRCAIM_ARC 0x00000FFF |
129 | #define SRCAIM_NXT 0x00FF0000 |
130 | #define SRCAIM_SRC 0xFF000000 |
131 | |
132 | struct srcimap { |
133 | unsigned int srcaim; |
134 | unsigned int idx; |
135 | }; |
136 | |
137 | /* SRCIMP manager register dirty flags */ |
138 | union srcimp_mgr_dirty { |
139 | struct { |
140 | u16 srcimap:1; |
141 | u16 rsv:15; |
142 | } bf; |
143 | u16 data; |
144 | }; |
145 | |
146 | struct srcimp_mgr_ctrl_blk { |
147 | struct srcimap srcimap; |
148 | union srcimp_mgr_dirty dirty; |
149 | }; |
150 | |
151 | /* |
152 | * Function implementation block. |
153 | */ |
154 | |
155 | static int src_get_rsc_ctrl_blk(void **rblk) |
156 | { |
157 | struct src_rsc_ctrl_blk *blk; |
158 | |
159 | *rblk = NULL; |
160 | blk = kzalloc(size: sizeof(*blk), GFP_KERNEL); |
161 | if (!blk) |
162 | return -ENOMEM; |
163 | |
164 | *rblk = blk; |
165 | |
166 | return 0; |
167 | } |
168 | |
169 | static int src_put_rsc_ctrl_blk(void *blk) |
170 | { |
171 | kfree(objp: blk); |
172 | |
173 | return 0; |
174 | } |
175 | |
176 | static int src_set_state(void *blk, unsigned int state) |
177 | { |
178 | struct src_rsc_ctrl_blk *ctl = blk; |
179 | |
180 | set_field(data: &ctl->ctl, SRCCTL_STATE, value: state); |
181 | ctl->dirty.bf.ctl = 1; |
182 | return 0; |
183 | } |
184 | |
185 | static int src_set_bm(void *blk, unsigned int bm) |
186 | { |
187 | struct src_rsc_ctrl_blk *ctl = blk; |
188 | |
189 | set_field(data: &ctl->ctl, SRCCTL_BM, value: bm); |
190 | ctl->dirty.bf.ctl = 1; |
191 | return 0; |
192 | } |
193 | |
194 | static int src_set_rsr(void *blk, unsigned int rsr) |
195 | { |
196 | struct src_rsc_ctrl_blk *ctl = blk; |
197 | |
198 | set_field(data: &ctl->ctl, SRCCTL_RSR, value: rsr); |
199 | ctl->dirty.bf.ctl = 1; |
200 | return 0; |
201 | } |
202 | |
203 | static int src_set_sf(void *blk, unsigned int sf) |
204 | { |
205 | struct src_rsc_ctrl_blk *ctl = blk; |
206 | |
207 | set_field(data: &ctl->ctl, SRCCTL_SF, value: sf); |
208 | ctl->dirty.bf.ctl = 1; |
209 | return 0; |
210 | } |
211 | |
212 | static int src_set_wr(void *blk, unsigned int wr) |
213 | { |
214 | struct src_rsc_ctrl_blk *ctl = blk; |
215 | |
216 | set_field(data: &ctl->ctl, SRCCTL_WR, value: wr); |
217 | ctl->dirty.bf.ctl = 1; |
218 | return 0; |
219 | } |
220 | |
221 | static int src_set_pm(void *blk, unsigned int pm) |
222 | { |
223 | struct src_rsc_ctrl_blk *ctl = blk; |
224 | |
225 | set_field(data: &ctl->ctl, SRCCTL_PM, value: pm); |
226 | ctl->dirty.bf.ctl = 1; |
227 | return 0; |
228 | } |
229 | |
230 | static int src_set_rom(void *blk, unsigned int rom) |
231 | { |
232 | struct src_rsc_ctrl_blk *ctl = blk; |
233 | |
234 | set_field(data: &ctl->ctl, SRCCTL_ROM, value: rom); |
235 | ctl->dirty.bf.ctl = 1; |
236 | return 0; |
237 | } |
238 | |
239 | static int src_set_vo(void *blk, unsigned int vo) |
240 | { |
241 | struct src_rsc_ctrl_blk *ctl = blk; |
242 | |
243 | set_field(data: &ctl->ctl, SRCCTL_VO, value: vo); |
244 | ctl->dirty.bf.ctl = 1; |
245 | return 0; |
246 | } |
247 | |
248 | static int src_set_st(void *blk, unsigned int st) |
249 | { |
250 | struct src_rsc_ctrl_blk *ctl = blk; |
251 | |
252 | set_field(data: &ctl->ctl, SRCCTL_ST, value: st); |
253 | ctl->dirty.bf.ctl = 1; |
254 | return 0; |
255 | } |
256 | |
257 | static int src_set_ie(void *blk, unsigned int ie) |
258 | { |
259 | struct src_rsc_ctrl_blk *ctl = blk; |
260 | |
261 | set_field(data: &ctl->ctl, SRCCTL_IE, value: ie); |
262 | ctl->dirty.bf.ctl = 1; |
263 | return 0; |
264 | } |
265 | |
266 | static int src_set_ilsz(void *blk, unsigned int ilsz) |
267 | { |
268 | struct src_rsc_ctrl_blk *ctl = blk; |
269 | |
270 | set_field(data: &ctl->ctl, SRCCTL_ILSZ, value: ilsz); |
271 | ctl->dirty.bf.ctl = 1; |
272 | return 0; |
273 | } |
274 | |
275 | static int src_set_bp(void *blk, unsigned int bp) |
276 | { |
277 | struct src_rsc_ctrl_blk *ctl = blk; |
278 | |
279 | set_field(data: &ctl->ctl, SRCCTL_BP, value: bp); |
280 | ctl->dirty.bf.ctl = 1; |
281 | return 0; |
282 | } |
283 | |
284 | static int src_set_cisz(void *blk, unsigned int cisz) |
285 | { |
286 | struct src_rsc_ctrl_blk *ctl = blk; |
287 | |
288 | set_field(data: &ctl->ccr, SRCCCR_CISZ, value: cisz); |
289 | ctl->dirty.bf.ccr = 1; |
290 | return 0; |
291 | } |
292 | |
293 | static int src_set_ca(void *blk, unsigned int ca) |
294 | { |
295 | struct src_rsc_ctrl_blk *ctl = blk; |
296 | |
297 | set_field(data: &ctl->ca, SRCCA_CA, value: ca); |
298 | ctl->dirty.bf.ca = 1; |
299 | return 0; |
300 | } |
301 | |
302 | static int src_set_sa(void *blk, unsigned int sa) |
303 | { |
304 | struct src_rsc_ctrl_blk *ctl = blk; |
305 | |
306 | set_field(data: &ctl->sa, SRCSA_SA, value: sa); |
307 | ctl->dirty.bf.sa = 1; |
308 | return 0; |
309 | } |
310 | |
311 | static int src_set_la(void *blk, unsigned int la) |
312 | { |
313 | struct src_rsc_ctrl_blk *ctl = blk; |
314 | |
315 | set_field(data: &ctl->la, SRCLA_LA, value: la); |
316 | ctl->dirty.bf.la = 1; |
317 | return 0; |
318 | } |
319 | |
320 | static int src_set_pitch(void *blk, unsigned int pitch) |
321 | { |
322 | struct src_rsc_ctrl_blk *ctl = blk; |
323 | |
324 | set_field(data: &ctl->mpr, MPRLH_PITCH, value: pitch); |
325 | ctl->dirty.bf.mpr = 1; |
326 | return 0; |
327 | } |
328 | |
329 | static int src_set_clear_zbufs(void *blk, unsigned int clear) |
330 | { |
331 | ((struct src_rsc_ctrl_blk *)blk)->dirty.bf.czbfs = (clear ? 1 : 0); |
332 | return 0; |
333 | } |
334 | |
335 | static int src_set_dirty(void *blk, unsigned int flags) |
336 | { |
337 | ((struct src_rsc_ctrl_blk *)blk)->dirty.data = (flags & 0xffff); |
338 | return 0; |
339 | } |
340 | |
341 | static int src_set_dirty_all(void *blk) |
342 | { |
343 | ((struct src_rsc_ctrl_blk *)blk)->dirty.data = ~(0x0); |
344 | return 0; |
345 | } |
346 | |
347 | #define AR_SLOT_SIZE 4096 |
348 | #define AR_SLOT_BLOCK_SIZE 16 |
349 | #define AR_PTS_PITCH 6 |
350 | #define AR_PARAM_SRC_OFFSET 0x60 |
351 | |
352 | static unsigned int src_param_pitch_mixer(unsigned int src_idx) |
353 | { |
354 | return ((src_idx << 4) + AR_PTS_PITCH + AR_SLOT_SIZE |
355 | - AR_PARAM_SRC_OFFSET) % AR_SLOT_SIZE; |
356 | |
357 | } |
358 | |
359 | static int src_commit_write(struct hw *hw, unsigned int idx, void *blk) |
360 | { |
361 | struct src_rsc_ctrl_blk *ctl = blk; |
362 | int i; |
363 | |
364 | if (ctl->dirty.bf.czbfs) { |
365 | /* Clear Z-Buffer registers */ |
366 | for (i = 0; i < 8; i++) |
367 | hw_write_20kx(hw, SRCUPZ+idx*0x100+i*0x4, data: 0); |
368 | |
369 | for (i = 0; i < 4; i++) |
370 | hw_write_20kx(hw, SRCDN0Z+idx*0x100+i*0x4, data: 0); |
371 | |
372 | for (i = 0; i < 8; i++) |
373 | hw_write_20kx(hw, SRCDN1Z+idx*0x100+i*0x4, data: 0); |
374 | |
375 | ctl->dirty.bf.czbfs = 0; |
376 | } |
377 | if (ctl->dirty.bf.mpr) { |
378 | /* Take the parameter mixer resource in the same group as that |
379 | * the idx src is in for simplicity. Unlike src, all conjugate |
380 | * parameter mixer resources must be programmed for |
381 | * corresponding conjugate src resources. */ |
382 | unsigned int pm_idx = src_param_pitch_mixer(src_idx: idx); |
383 | hw_write_20kx(hw, PRING_LO_HI+4*pm_idx, data: ctl->mpr); |
384 | hw_write_20kx(hw, PMOPLO+8*pm_idx, data: 0x3); |
385 | hw_write_20kx(hw, PMOPHI+8*pm_idx, data: 0x0); |
386 | ctl->dirty.bf.mpr = 0; |
387 | } |
388 | if (ctl->dirty.bf.sa) { |
389 | hw_write_20kx(hw, SRCSA+idx*0x100, data: ctl->sa); |
390 | ctl->dirty.bf.sa = 0; |
391 | } |
392 | if (ctl->dirty.bf.la) { |
393 | hw_write_20kx(hw, SRCLA+idx*0x100, data: ctl->la); |
394 | ctl->dirty.bf.la = 0; |
395 | } |
396 | if (ctl->dirty.bf.ca) { |
397 | hw_write_20kx(hw, SRCCA+idx*0x100, data: ctl->ca); |
398 | ctl->dirty.bf.ca = 0; |
399 | } |
400 | |
401 | /* Write srccf register */ |
402 | hw_write_20kx(hw, SRCCF+idx*0x100, data: 0x0); |
403 | |
404 | if (ctl->dirty.bf.ccr) { |
405 | hw_write_20kx(hw, SRCCCR+idx*0x100, data: ctl->ccr); |
406 | ctl->dirty.bf.ccr = 0; |
407 | } |
408 | if (ctl->dirty.bf.ctl) { |
409 | hw_write_20kx(hw, SRCCTL+idx*0x100, data: ctl->ctl); |
410 | ctl->dirty.bf.ctl = 0; |
411 | } |
412 | |
413 | return 0; |
414 | } |
415 | |
416 | static int src_get_ca(struct hw *hw, unsigned int idx, void *blk) |
417 | { |
418 | struct src_rsc_ctrl_blk *ctl = blk; |
419 | |
420 | ctl->ca = hw_read_20kx(hw, SRCCA+idx*0x100); |
421 | ctl->dirty.bf.ca = 0; |
422 | |
423 | return get_field(data: ctl->ca, SRCCA_CA); |
424 | } |
425 | |
426 | static unsigned int src_get_dirty(void *blk) |
427 | { |
428 | return ((struct src_rsc_ctrl_blk *)blk)->dirty.data; |
429 | } |
430 | |
431 | static unsigned int src_dirty_conj_mask(void) |
432 | { |
433 | return 0x20; |
434 | } |
435 | |
436 | static int src_mgr_enbs_src(void *blk, unsigned int idx) |
437 | { |
438 | ((struct src_mgr_ctrl_blk *)blk)->enbsa = ~(0x0); |
439 | ((struct src_mgr_ctrl_blk *)blk)->dirty.bf.enbsa = 1; |
440 | ((struct src_mgr_ctrl_blk *)blk)->enb[idx/32] |= (0x1 << (idx%32)); |
441 | return 0; |
442 | } |
443 | |
444 | static int src_mgr_enb_src(void *blk, unsigned int idx) |
445 | { |
446 | ((struct src_mgr_ctrl_blk *)blk)->enb[idx/32] |= (0x1 << (idx%32)); |
447 | ((struct src_mgr_ctrl_blk *)blk)->dirty.data |= (0x1 << (idx/32)); |
448 | return 0; |
449 | } |
450 | |
451 | static int src_mgr_dsb_src(void *blk, unsigned int idx) |
452 | { |
453 | ((struct src_mgr_ctrl_blk *)blk)->enb[idx/32] &= ~(0x1 << (idx%32)); |
454 | ((struct src_mgr_ctrl_blk *)blk)->dirty.data |= (0x1 << (idx/32)); |
455 | return 0; |
456 | } |
457 | |
458 | static int src_mgr_commit_write(struct hw *hw, void *blk) |
459 | { |
460 | struct src_mgr_ctrl_blk *ctl = blk; |
461 | int i; |
462 | unsigned int ret; |
463 | |
464 | if (ctl->dirty.bf.enbsa) { |
465 | do { |
466 | ret = hw_read_20kx(hw, SRCENBSTAT); |
467 | } while (ret & 0x1); |
468 | hw_write_20kx(hw, SRCENBS, data: ctl->enbsa); |
469 | ctl->dirty.bf.enbsa = 0; |
470 | } |
471 | for (i = 0; i < 8; i++) { |
472 | if ((ctl->dirty.data & (0x1 << i))) { |
473 | hw_write_20kx(hw, SRCENB+(i*0x100), data: ctl->enb[i]); |
474 | ctl->dirty.data &= ~(0x1 << i); |
475 | } |
476 | } |
477 | |
478 | return 0; |
479 | } |
480 | |
481 | static int src_mgr_get_ctrl_blk(void **rblk) |
482 | { |
483 | struct src_mgr_ctrl_blk *blk; |
484 | |
485 | *rblk = NULL; |
486 | blk = kzalloc(size: sizeof(*blk), GFP_KERNEL); |
487 | if (!blk) |
488 | return -ENOMEM; |
489 | |
490 | *rblk = blk; |
491 | |
492 | return 0; |
493 | } |
494 | |
495 | static int src_mgr_put_ctrl_blk(void *blk) |
496 | { |
497 | kfree(objp: blk); |
498 | |
499 | return 0; |
500 | } |
501 | |
502 | static int srcimp_mgr_get_ctrl_blk(void **rblk) |
503 | { |
504 | struct srcimp_mgr_ctrl_blk *blk; |
505 | |
506 | *rblk = NULL; |
507 | blk = kzalloc(size: sizeof(*blk), GFP_KERNEL); |
508 | if (!blk) |
509 | return -ENOMEM; |
510 | |
511 | *rblk = blk; |
512 | |
513 | return 0; |
514 | } |
515 | |
516 | static int srcimp_mgr_put_ctrl_blk(void *blk) |
517 | { |
518 | kfree(objp: blk); |
519 | |
520 | return 0; |
521 | } |
522 | |
523 | static int srcimp_mgr_set_imaparc(void *blk, unsigned int slot) |
524 | { |
525 | struct srcimp_mgr_ctrl_blk *ctl = blk; |
526 | |
527 | set_field(data: &ctl->srcimap.srcaim, SRCAIM_ARC, value: slot); |
528 | ctl->dirty.bf.srcimap = 1; |
529 | return 0; |
530 | } |
531 | |
532 | static int srcimp_mgr_set_imapuser(void *blk, unsigned int user) |
533 | { |
534 | struct srcimp_mgr_ctrl_blk *ctl = blk; |
535 | |
536 | set_field(data: &ctl->srcimap.srcaim, SRCAIM_SRC, value: user); |
537 | ctl->dirty.bf.srcimap = 1; |
538 | return 0; |
539 | } |
540 | |
541 | static int srcimp_mgr_set_imapnxt(void *blk, unsigned int next) |
542 | { |
543 | struct srcimp_mgr_ctrl_blk *ctl = blk; |
544 | |
545 | set_field(data: &ctl->srcimap.srcaim, SRCAIM_NXT, value: next); |
546 | ctl->dirty.bf.srcimap = 1; |
547 | return 0; |
548 | } |
549 | |
550 | static int srcimp_mgr_set_imapaddr(void *blk, unsigned int addr) |
551 | { |
552 | struct srcimp_mgr_ctrl_blk *ctl = blk; |
553 | |
554 | ctl->srcimap.idx = addr; |
555 | ctl->dirty.bf.srcimap = 1; |
556 | return 0; |
557 | } |
558 | |
559 | static int srcimp_mgr_commit_write(struct hw *hw, void *blk) |
560 | { |
561 | struct srcimp_mgr_ctrl_blk *ctl = blk; |
562 | |
563 | if (ctl->dirty.bf.srcimap) { |
564 | hw_write_20kx(hw, SRCIMAP+ctl->srcimap.idx*0x100, |
565 | data: ctl->srcimap.srcaim); |
566 | ctl->dirty.bf.srcimap = 0; |
567 | } |
568 | |
569 | return 0; |
570 | } |
571 | |
572 | /* |
573 | * AMIXER control block definitions. |
574 | */ |
575 | |
576 | #define AMOPLO_M 0x00000003 |
577 | #define AMOPLO_X 0x0003FFF0 |
578 | #define AMOPLO_Y 0xFFFC0000 |
579 | |
580 | #define AMOPHI_SADR 0x000000FF |
581 | #define AMOPHI_SE 0x80000000 |
582 | |
583 | /* AMIXER resource register dirty flags */ |
584 | union amixer_dirty { |
585 | struct { |
586 | u16 amoplo:1; |
587 | u16 amophi:1; |
588 | u16 rsv:14; |
589 | } bf; |
590 | u16 data; |
591 | }; |
592 | |
593 | /* AMIXER resource control block */ |
594 | struct amixer_rsc_ctrl_blk { |
595 | unsigned int amoplo; |
596 | unsigned int amophi; |
597 | union amixer_dirty dirty; |
598 | }; |
599 | |
600 | static int amixer_set_mode(void *blk, unsigned int mode) |
601 | { |
602 | struct amixer_rsc_ctrl_blk *ctl = blk; |
603 | |
604 | set_field(data: &ctl->amoplo, AMOPLO_M, value: mode); |
605 | ctl->dirty.bf.amoplo = 1; |
606 | return 0; |
607 | } |
608 | |
609 | static int amixer_set_iv(void *blk, unsigned int iv) |
610 | { |
611 | /* 20k1 amixer does not have this field */ |
612 | return 0; |
613 | } |
614 | |
615 | static int amixer_set_x(void *blk, unsigned int x) |
616 | { |
617 | struct amixer_rsc_ctrl_blk *ctl = blk; |
618 | |
619 | set_field(data: &ctl->amoplo, AMOPLO_X, value: x); |
620 | ctl->dirty.bf.amoplo = 1; |
621 | return 0; |
622 | } |
623 | |
624 | static int amixer_set_y(void *blk, unsigned int y) |
625 | { |
626 | struct amixer_rsc_ctrl_blk *ctl = blk; |
627 | |
628 | set_field(data: &ctl->amoplo, AMOPLO_Y, value: y); |
629 | ctl->dirty.bf.amoplo = 1; |
630 | return 0; |
631 | } |
632 | |
633 | static int amixer_set_sadr(void *blk, unsigned int sadr) |
634 | { |
635 | struct amixer_rsc_ctrl_blk *ctl = blk; |
636 | |
637 | set_field(data: &ctl->amophi, AMOPHI_SADR, value: sadr); |
638 | ctl->dirty.bf.amophi = 1; |
639 | return 0; |
640 | } |
641 | |
642 | static int amixer_set_se(void *blk, unsigned int se) |
643 | { |
644 | struct amixer_rsc_ctrl_blk *ctl = blk; |
645 | |
646 | set_field(data: &ctl->amophi, AMOPHI_SE, value: se); |
647 | ctl->dirty.bf.amophi = 1; |
648 | return 0; |
649 | } |
650 | |
651 | static int amixer_set_dirty(void *blk, unsigned int flags) |
652 | { |
653 | ((struct amixer_rsc_ctrl_blk *)blk)->dirty.data = (flags & 0xffff); |
654 | return 0; |
655 | } |
656 | |
657 | static int amixer_set_dirty_all(void *blk) |
658 | { |
659 | ((struct amixer_rsc_ctrl_blk *)blk)->dirty.data = ~(0x0); |
660 | return 0; |
661 | } |
662 | |
663 | static int amixer_commit_write(struct hw *hw, unsigned int idx, void *blk) |
664 | { |
665 | struct amixer_rsc_ctrl_blk *ctl = blk; |
666 | |
667 | if (ctl->dirty.bf.amoplo || ctl->dirty.bf.amophi) { |
668 | hw_write_20kx(hw, AMOPLO+idx*8, data: ctl->amoplo); |
669 | ctl->dirty.bf.amoplo = 0; |
670 | hw_write_20kx(hw, AMOPHI+idx*8, data: ctl->amophi); |
671 | ctl->dirty.bf.amophi = 0; |
672 | } |
673 | |
674 | return 0; |
675 | } |
676 | |
677 | static int amixer_get_y(void *blk) |
678 | { |
679 | struct amixer_rsc_ctrl_blk *ctl = blk; |
680 | |
681 | return get_field(data: ctl->amoplo, AMOPLO_Y); |
682 | } |
683 | |
684 | static unsigned int amixer_get_dirty(void *blk) |
685 | { |
686 | return ((struct amixer_rsc_ctrl_blk *)blk)->dirty.data; |
687 | } |
688 | |
689 | static int amixer_rsc_get_ctrl_blk(void **rblk) |
690 | { |
691 | struct amixer_rsc_ctrl_blk *blk; |
692 | |
693 | *rblk = NULL; |
694 | blk = kzalloc(size: sizeof(*blk), GFP_KERNEL); |
695 | if (!blk) |
696 | return -ENOMEM; |
697 | |
698 | *rblk = blk; |
699 | |
700 | return 0; |
701 | } |
702 | |
703 | static int amixer_rsc_put_ctrl_blk(void *blk) |
704 | { |
705 | kfree(objp: blk); |
706 | |
707 | return 0; |
708 | } |
709 | |
710 | static int amixer_mgr_get_ctrl_blk(void **rblk) |
711 | { |
712 | /*amixer_mgr_ctrl_blk_t *blk;*/ |
713 | |
714 | *rblk = NULL; |
715 | /*blk = kzalloc(sizeof(*blk), GFP_KERNEL); |
716 | if (!blk) |
717 | return -ENOMEM; |
718 | |
719 | *rblk = blk;*/ |
720 | |
721 | return 0; |
722 | } |
723 | |
724 | static int amixer_mgr_put_ctrl_blk(void *blk) |
725 | { |
726 | /*kfree((amixer_mgr_ctrl_blk_t *)blk);*/ |
727 | |
728 | return 0; |
729 | } |
730 | |
731 | /* |
732 | * DAIO control block definitions. |
733 | */ |
734 | |
735 | /* Receiver Sample Rate Tracker Control register */ |
736 | #define SRTCTL_SRCR 0x000000FF |
737 | #define SRTCTL_SRCL 0x0000FF00 |
738 | #define SRTCTL_RSR 0x00030000 |
739 | #define SRTCTL_DRAT 0x000C0000 |
740 | #define SRTCTL_RLE 0x10000000 |
741 | #define SRTCTL_RLP 0x20000000 |
742 | #define SRTCTL_EC 0x40000000 |
743 | #define SRTCTL_ET 0x80000000 |
744 | |
745 | /* DAIO Receiver register dirty flags */ |
746 | union dai_dirty { |
747 | struct { |
748 | u16 srtctl:1; |
749 | u16 rsv:15; |
750 | } bf; |
751 | u16 data; |
752 | }; |
753 | |
754 | /* DAIO Receiver control block */ |
755 | struct dai_ctrl_blk { |
756 | unsigned int srtctl; |
757 | union dai_dirty dirty; |
758 | }; |
759 | |
760 | /* S/PDIF Transmitter register dirty flags */ |
761 | union dao_dirty { |
762 | struct { |
763 | u16 spos:1; |
764 | u16 rsv:15; |
765 | } bf; |
766 | u16 data; |
767 | }; |
768 | |
769 | /* S/PDIF Transmitter control block */ |
770 | struct dao_ctrl_blk { |
771 | unsigned int spos; /* S/PDIF Output Channel Status Register */ |
772 | union dao_dirty dirty; |
773 | }; |
774 | |
775 | /* Audio Input Mapper RAM */ |
776 | #define AIM_ARC 0x00000FFF |
777 | #define AIM_NXT 0x007F0000 |
778 | |
779 | struct daoimap { |
780 | unsigned int aim; |
781 | unsigned int idx; |
782 | }; |
783 | |
784 | /* I2S Transmitter/Receiver Control register */ |
785 | #define I2SCTL_EA 0x00000004 |
786 | #define I2SCTL_EI 0x00000010 |
787 | |
788 | /* S/PDIF Transmitter Control register */ |
789 | #define SPOCTL_OE 0x00000001 |
790 | #define SPOCTL_OS 0x0000000E |
791 | #define SPOCTL_RIV 0x00000010 |
792 | #define SPOCTL_LIV 0x00000020 |
793 | #define SPOCTL_SR 0x000000C0 |
794 | |
795 | /* S/PDIF Receiver Control register */ |
796 | #define SPICTL_EN 0x00000001 |
797 | #define SPICTL_I24 0x00000002 |
798 | #define SPICTL_IB 0x00000004 |
799 | #define SPICTL_SM 0x00000008 |
800 | #define SPICTL_VM 0x00000010 |
801 | |
802 | /* DAIO manager register dirty flags */ |
803 | union daio_mgr_dirty { |
804 | struct { |
805 | u32 i2soctl:4; |
806 | u32 i2sictl:4; |
807 | u32 spoctl:4; |
808 | u32 spictl:4; |
809 | u32 daoimap:1; |
810 | u32 rsv:15; |
811 | } bf; |
812 | u32 data; |
813 | }; |
814 | |
815 | /* DAIO manager control block */ |
816 | struct daio_mgr_ctrl_blk { |
817 | unsigned int i2sctl; |
818 | unsigned int spoctl; |
819 | unsigned int spictl; |
820 | struct daoimap daoimap; |
821 | union daio_mgr_dirty dirty; |
822 | }; |
823 | |
824 | static int dai_srt_set_srcr(void *blk, unsigned int src) |
825 | { |
826 | struct dai_ctrl_blk *ctl = blk; |
827 | |
828 | set_field(data: &ctl->srtctl, SRTCTL_SRCR, value: src); |
829 | ctl->dirty.bf.srtctl = 1; |
830 | return 0; |
831 | } |
832 | |
833 | static int dai_srt_set_srcl(void *blk, unsigned int src) |
834 | { |
835 | struct dai_ctrl_blk *ctl = blk; |
836 | |
837 | set_field(data: &ctl->srtctl, SRTCTL_SRCL, value: src); |
838 | ctl->dirty.bf.srtctl = 1; |
839 | return 0; |
840 | } |
841 | |
842 | static int dai_srt_set_rsr(void *blk, unsigned int rsr) |
843 | { |
844 | struct dai_ctrl_blk *ctl = blk; |
845 | |
846 | set_field(data: &ctl->srtctl, SRTCTL_RSR, value: rsr); |
847 | ctl->dirty.bf.srtctl = 1; |
848 | return 0; |
849 | } |
850 | |
851 | static int dai_srt_set_drat(void *blk, unsigned int drat) |
852 | { |
853 | struct dai_ctrl_blk *ctl = blk; |
854 | |
855 | set_field(data: &ctl->srtctl, SRTCTL_DRAT, value: drat); |
856 | ctl->dirty.bf.srtctl = 1; |
857 | return 0; |
858 | } |
859 | |
860 | static int dai_srt_set_ec(void *blk, unsigned int ec) |
861 | { |
862 | struct dai_ctrl_blk *ctl = blk; |
863 | |
864 | set_field(data: &ctl->srtctl, SRTCTL_EC, value: ec ? 1 : 0); |
865 | ctl->dirty.bf.srtctl = 1; |
866 | return 0; |
867 | } |
868 | |
869 | static int dai_srt_set_et(void *blk, unsigned int et) |
870 | { |
871 | struct dai_ctrl_blk *ctl = blk; |
872 | |
873 | set_field(data: &ctl->srtctl, SRTCTL_ET, value: et ? 1 : 0); |
874 | ctl->dirty.bf.srtctl = 1; |
875 | return 0; |
876 | } |
877 | |
878 | static int dai_commit_write(struct hw *hw, unsigned int idx, void *blk) |
879 | { |
880 | struct dai_ctrl_blk *ctl = blk; |
881 | |
882 | if (ctl->dirty.bf.srtctl) { |
883 | if (idx < 4) { |
884 | /* S/PDIF SRTs */ |
885 | hw_write_20kx(hw, SRTSCTL+0x4*idx, data: ctl->srtctl); |
886 | } else { |
887 | /* I2S SRT */ |
888 | hw_write_20kx(hw, SRTICTL, data: ctl->srtctl); |
889 | } |
890 | ctl->dirty.bf.srtctl = 0; |
891 | } |
892 | |
893 | return 0; |
894 | } |
895 | |
896 | static int dai_get_ctrl_blk(void **rblk) |
897 | { |
898 | struct dai_ctrl_blk *blk; |
899 | |
900 | *rblk = NULL; |
901 | blk = kzalloc(size: sizeof(*blk), GFP_KERNEL); |
902 | if (!blk) |
903 | return -ENOMEM; |
904 | |
905 | *rblk = blk; |
906 | |
907 | return 0; |
908 | } |
909 | |
910 | static int dai_put_ctrl_blk(void *blk) |
911 | { |
912 | kfree(objp: blk); |
913 | |
914 | return 0; |
915 | } |
916 | |
917 | static int dao_set_spos(void *blk, unsigned int spos) |
918 | { |
919 | ((struct dao_ctrl_blk *)blk)->spos = spos; |
920 | ((struct dao_ctrl_blk *)blk)->dirty.bf.spos = 1; |
921 | return 0; |
922 | } |
923 | |
924 | static int dao_commit_write(struct hw *hw, unsigned int idx, void *blk) |
925 | { |
926 | struct dao_ctrl_blk *ctl = blk; |
927 | |
928 | if (ctl->dirty.bf.spos) { |
929 | if (idx < 4) { |
930 | /* S/PDIF SPOSx */ |
931 | hw_write_20kx(hw, SPOS+0x4*idx, data: ctl->spos); |
932 | } |
933 | ctl->dirty.bf.spos = 0; |
934 | } |
935 | |
936 | return 0; |
937 | } |
938 | |
939 | static int dao_get_spos(void *blk, unsigned int *spos) |
940 | { |
941 | *spos = ((struct dao_ctrl_blk *)blk)->spos; |
942 | return 0; |
943 | } |
944 | |
945 | static int dao_get_ctrl_blk(void **rblk) |
946 | { |
947 | struct dao_ctrl_blk *blk; |
948 | |
949 | *rblk = NULL; |
950 | blk = kzalloc(size: sizeof(*blk), GFP_KERNEL); |
951 | if (!blk) |
952 | return -ENOMEM; |
953 | |
954 | *rblk = blk; |
955 | |
956 | return 0; |
957 | } |
958 | |
959 | static int dao_put_ctrl_blk(void *blk) |
960 | { |
961 | kfree(objp: blk); |
962 | |
963 | return 0; |
964 | } |
965 | |
966 | static int daio_mgr_enb_dai(void *blk, unsigned int idx) |
967 | { |
968 | struct daio_mgr_ctrl_blk *ctl = blk; |
969 | |
970 | if (idx < 4) { |
971 | /* S/PDIF input */ |
972 | set_field(data: &ctl->spictl, SPICTL_EN << (idx*8), value: 1); |
973 | ctl->dirty.bf.spictl |= (0x1 << idx); |
974 | } else { |
975 | /* I2S input */ |
976 | idx %= 4; |
977 | set_field(data: &ctl->i2sctl, I2SCTL_EI << (idx*8), value: 1); |
978 | ctl->dirty.bf.i2sictl |= (0x1 << idx); |
979 | } |
980 | return 0; |
981 | } |
982 | |
983 | static int daio_mgr_dsb_dai(void *blk, unsigned int idx) |
984 | { |
985 | struct daio_mgr_ctrl_blk *ctl = blk; |
986 | |
987 | if (idx < 4) { |
988 | /* S/PDIF input */ |
989 | set_field(data: &ctl->spictl, SPICTL_EN << (idx*8), value: 0); |
990 | ctl->dirty.bf.spictl |= (0x1 << idx); |
991 | } else { |
992 | /* I2S input */ |
993 | idx %= 4; |
994 | set_field(data: &ctl->i2sctl, I2SCTL_EI << (idx*8), value: 0); |
995 | ctl->dirty.bf.i2sictl |= (0x1 << idx); |
996 | } |
997 | return 0; |
998 | } |
999 | |
1000 | static int daio_mgr_enb_dao(void *blk, unsigned int idx) |
1001 | { |
1002 | struct daio_mgr_ctrl_blk *ctl = blk; |
1003 | |
1004 | if (idx < 4) { |
1005 | /* S/PDIF output */ |
1006 | set_field(data: &ctl->spoctl, SPOCTL_OE << (idx*8), value: 1); |
1007 | ctl->dirty.bf.spoctl |= (0x1 << idx); |
1008 | } else { |
1009 | /* I2S output */ |
1010 | idx %= 4; |
1011 | set_field(data: &ctl->i2sctl, I2SCTL_EA << (idx*8), value: 1); |
1012 | ctl->dirty.bf.i2soctl |= (0x1 << idx); |
1013 | } |
1014 | return 0; |
1015 | } |
1016 | |
1017 | static int daio_mgr_dsb_dao(void *blk, unsigned int idx) |
1018 | { |
1019 | struct daio_mgr_ctrl_blk *ctl = blk; |
1020 | |
1021 | if (idx < 4) { |
1022 | /* S/PDIF output */ |
1023 | set_field(data: &ctl->spoctl, SPOCTL_OE << (idx*8), value: 0); |
1024 | ctl->dirty.bf.spoctl |= (0x1 << idx); |
1025 | } else { |
1026 | /* I2S output */ |
1027 | idx %= 4; |
1028 | set_field(data: &ctl->i2sctl, I2SCTL_EA << (idx*8), value: 0); |
1029 | ctl->dirty.bf.i2soctl |= (0x1 << idx); |
1030 | } |
1031 | return 0; |
1032 | } |
1033 | |
1034 | static int daio_mgr_dao_init(void *blk, unsigned int idx, unsigned int conf) |
1035 | { |
1036 | struct daio_mgr_ctrl_blk *ctl = blk; |
1037 | |
1038 | if (idx < 4) { |
1039 | /* S/PDIF output */ |
1040 | switch ((conf & 0x7)) { |
1041 | case 0: |
1042 | set_field(data: &ctl->spoctl, SPOCTL_SR << (idx*8), value: 3); |
1043 | break; /* CDIF */ |
1044 | case 1: |
1045 | set_field(data: &ctl->spoctl, SPOCTL_SR << (idx*8), value: 0); |
1046 | break; |
1047 | case 2: |
1048 | set_field(data: &ctl->spoctl, SPOCTL_SR << (idx*8), value: 1); |
1049 | break; |
1050 | case 4: |
1051 | set_field(data: &ctl->spoctl, SPOCTL_SR << (idx*8), value: 2); |
1052 | break; |
1053 | default: |
1054 | break; |
1055 | } |
1056 | set_field(data: &ctl->spoctl, SPOCTL_LIV << (idx*8), |
1057 | value: (conf >> 4) & 0x1); /* Non-audio */ |
1058 | set_field(data: &ctl->spoctl, SPOCTL_RIV << (idx*8), |
1059 | value: (conf >> 4) & 0x1); /* Non-audio */ |
1060 | set_field(data: &ctl->spoctl, SPOCTL_OS << (idx*8), |
1061 | value: ((conf >> 3) & 0x1) ? 2 : 2); /* Raw */ |
1062 | |
1063 | ctl->dirty.bf.spoctl |= (0x1 << idx); |
1064 | } else { |
1065 | /* I2S output */ |
1066 | /*idx %= 4; */ |
1067 | } |
1068 | return 0; |
1069 | } |
1070 | |
1071 | static int daio_mgr_set_imaparc(void *blk, unsigned int slot) |
1072 | { |
1073 | struct daio_mgr_ctrl_blk *ctl = blk; |
1074 | |
1075 | set_field(data: &ctl->daoimap.aim, AIM_ARC, value: slot); |
1076 | ctl->dirty.bf.daoimap = 1; |
1077 | return 0; |
1078 | } |
1079 | |
1080 | static int daio_mgr_set_imapnxt(void *blk, unsigned int next) |
1081 | { |
1082 | struct daio_mgr_ctrl_blk *ctl = blk; |
1083 | |
1084 | set_field(data: &ctl->daoimap.aim, AIM_NXT, value: next); |
1085 | ctl->dirty.bf.daoimap = 1; |
1086 | return 0; |
1087 | } |
1088 | |
1089 | static int daio_mgr_set_imapaddr(void *blk, unsigned int addr) |
1090 | { |
1091 | struct daio_mgr_ctrl_blk *ctl = blk; |
1092 | |
1093 | ctl->daoimap.idx = addr; |
1094 | ctl->dirty.bf.daoimap = 1; |
1095 | return 0; |
1096 | } |
1097 | |
1098 | static int daio_mgr_commit_write(struct hw *hw, void *blk) |
1099 | { |
1100 | struct daio_mgr_ctrl_blk *ctl = blk; |
1101 | int i; |
1102 | |
1103 | if (ctl->dirty.bf.i2sictl || ctl->dirty.bf.i2soctl) { |
1104 | for (i = 0; i < 4; i++) { |
1105 | if ((ctl->dirty.bf.i2sictl & (0x1 << i))) |
1106 | ctl->dirty.bf.i2sictl &= ~(0x1 << i); |
1107 | |
1108 | if ((ctl->dirty.bf.i2soctl & (0x1 << i))) |
1109 | ctl->dirty.bf.i2soctl &= ~(0x1 << i); |
1110 | } |
1111 | hw_write_20kx(hw, I2SCTL, data: ctl->i2sctl); |
1112 | mdelay(1); |
1113 | } |
1114 | if (ctl->dirty.bf.spoctl) { |
1115 | for (i = 0; i < 4; i++) { |
1116 | if ((ctl->dirty.bf.spoctl & (0x1 << i))) |
1117 | ctl->dirty.bf.spoctl &= ~(0x1 << i); |
1118 | } |
1119 | hw_write_20kx(hw, SPOCTL, data: ctl->spoctl); |
1120 | mdelay(1); |
1121 | } |
1122 | if (ctl->dirty.bf.spictl) { |
1123 | for (i = 0; i < 4; i++) { |
1124 | if ((ctl->dirty.bf.spictl & (0x1 << i))) |
1125 | ctl->dirty.bf.spictl &= ~(0x1 << i); |
1126 | } |
1127 | hw_write_20kx(hw, SPICTL, data: ctl->spictl); |
1128 | mdelay(1); |
1129 | } |
1130 | if (ctl->dirty.bf.daoimap) { |
1131 | hw_write_20kx(hw, DAOIMAP+ctl->daoimap.idx*4, |
1132 | data: ctl->daoimap.aim); |
1133 | ctl->dirty.bf.daoimap = 0; |
1134 | } |
1135 | |
1136 | return 0; |
1137 | } |
1138 | |
1139 | static int daio_mgr_get_ctrl_blk(struct hw *hw, void **rblk) |
1140 | { |
1141 | struct daio_mgr_ctrl_blk *blk; |
1142 | |
1143 | *rblk = NULL; |
1144 | blk = kzalloc(size: sizeof(*blk), GFP_KERNEL); |
1145 | if (!blk) |
1146 | return -ENOMEM; |
1147 | |
1148 | blk->i2sctl = hw_read_20kx(hw, I2SCTL); |
1149 | blk->spoctl = hw_read_20kx(hw, SPOCTL); |
1150 | blk->spictl = hw_read_20kx(hw, SPICTL); |
1151 | |
1152 | *rblk = blk; |
1153 | |
1154 | return 0; |
1155 | } |
1156 | |
1157 | static int daio_mgr_put_ctrl_blk(void *blk) |
1158 | { |
1159 | kfree(objp: blk); |
1160 | |
1161 | return 0; |
1162 | } |
1163 | |
1164 | /* Timer interrupt */ |
1165 | static int set_timer_irq(struct hw *hw, int enable) |
1166 | { |
1167 | hw_write_20kx(hw, GIE, data: enable ? IT_INT : 0); |
1168 | return 0; |
1169 | } |
1170 | |
1171 | static int set_timer_tick(struct hw *hw, unsigned int ticks) |
1172 | { |
1173 | if (ticks) |
1174 | ticks |= TIMR_IE | TIMR_IP; |
1175 | hw_write_20kx(hw, TIMR, data: ticks); |
1176 | return 0; |
1177 | } |
1178 | |
1179 | static unsigned int get_wc(struct hw *hw) |
1180 | { |
1181 | return hw_read_20kx(hw, WC); |
1182 | } |
1183 | |
1184 | /* Card hardware initialization block */ |
1185 | struct dac_conf { |
1186 | unsigned int msr; /* master sample rate in rsrs */ |
1187 | }; |
1188 | |
1189 | struct adc_conf { |
1190 | unsigned int msr; /* master sample rate in rsrs */ |
1191 | unsigned char input; /* the input source of ADC */ |
1192 | unsigned char mic20db; /* boost mic by 20db if input is microphone */ |
1193 | }; |
1194 | |
1195 | struct daio_conf { |
1196 | unsigned int msr; /* master sample rate in rsrs */ |
1197 | }; |
1198 | |
1199 | struct trn_conf { |
1200 | unsigned long vm_pgt_phys; |
1201 | }; |
1202 | |
1203 | static int hw_daio_init(struct hw *hw, const struct daio_conf *info) |
1204 | { |
1205 | u32 i2sorg; |
1206 | u32 spdorg; |
1207 | |
1208 | /* Read I2S CTL. Keep original value. */ |
1209 | /*i2sorg = hw_read_20kx(hw, I2SCTL);*/ |
1210 | i2sorg = 0x94040404; /* enable all audio out and I2S-D input */ |
1211 | /* Program I2S with proper master sample rate and enable |
1212 | * the correct I2S channel. */ |
1213 | i2sorg &= 0xfffffffc; |
1214 | |
1215 | /* Enable S/PDIF-out-A in fixed 24-bit data |
1216 | * format and default to 48kHz. */ |
1217 | /* Disable all before doing any changes. */ |
1218 | hw_write_20kx(hw, SPOCTL, data: 0x0); |
1219 | spdorg = 0x05; |
1220 | |
1221 | switch (info->msr) { |
1222 | case 1: |
1223 | i2sorg |= 1; |
1224 | spdorg |= (0x0 << 6); |
1225 | break; |
1226 | case 2: |
1227 | i2sorg |= 2; |
1228 | spdorg |= (0x1 << 6); |
1229 | break; |
1230 | case 4: |
1231 | i2sorg |= 3; |
1232 | spdorg |= (0x2 << 6); |
1233 | break; |
1234 | default: |
1235 | i2sorg |= 1; |
1236 | break; |
1237 | } |
1238 | |
1239 | hw_write_20kx(hw, I2SCTL, data: i2sorg); |
1240 | hw_write_20kx(hw, SPOCTL, data: spdorg); |
1241 | |
1242 | /* Enable S/PDIF-in-A in fixed 24-bit data format. */ |
1243 | /* Disable all before doing any changes. */ |
1244 | hw_write_20kx(hw, SPICTL, data: 0x0); |
1245 | mdelay(1); |
1246 | spdorg = 0x0a0a0a0a; |
1247 | hw_write_20kx(hw, SPICTL, data: spdorg); |
1248 | mdelay(1); |
1249 | |
1250 | return 0; |
1251 | } |
1252 | |
1253 | /* TRANSPORT operations */ |
1254 | static int hw_trn_init(struct hw *hw, const struct trn_conf *info) |
1255 | { |
1256 | u32 trnctl; |
1257 | u32 ptp_phys_low, ptp_phys_high; |
1258 | |
1259 | /* Set up device page table */ |
1260 | if ((~0UL) == info->vm_pgt_phys) { |
1261 | dev_err(hw->card->dev, |
1262 | "Wrong device page table page address!\n" ); |
1263 | return -1; |
1264 | } |
1265 | |
1266 | trnctl = 0x13; /* 32-bit, 4k-size page */ |
1267 | ptp_phys_low = (u32)info->vm_pgt_phys; |
1268 | ptp_phys_high = upper_32_bits(info->vm_pgt_phys); |
1269 | if (sizeof(void *) == 8) /* 64bit address */ |
1270 | trnctl |= (1 << 2); |
1271 | #if 0 /* Only 4k h/w pages for simplicitiy */ |
1272 | #if PAGE_SIZE == 8192 |
1273 | trnctl |= (1<<5); |
1274 | #endif |
1275 | #endif |
1276 | hw_write_20kx(hw, PTPALX, data: ptp_phys_low); |
1277 | hw_write_20kx(hw, PTPAHX, data: ptp_phys_high); |
1278 | hw_write_20kx(hw, TRNCTL, data: trnctl); |
1279 | hw_write_20kx(hw, TRNIS, data: 0x200c01); /* really needed? */ |
1280 | |
1281 | return 0; |
1282 | } |
1283 | |
1284 | /* Card initialization */ |
1285 | #define GCTL_EAC 0x00000001 |
1286 | #define GCTL_EAI 0x00000002 |
1287 | #define GCTL_BEP 0x00000004 |
1288 | #define GCTL_BES 0x00000008 |
1289 | #define GCTL_DSP 0x00000010 |
1290 | #define GCTL_DBP 0x00000020 |
1291 | #define GCTL_ABP 0x00000040 |
1292 | #define GCTL_TBP 0x00000080 |
1293 | #define GCTL_SBP 0x00000100 |
1294 | #define GCTL_FBP 0x00000200 |
1295 | #define GCTL_XA 0x00000400 |
1296 | #define GCTL_ET 0x00000800 |
1297 | #define GCTL_PR 0x00001000 |
1298 | #define GCTL_MRL 0x00002000 |
1299 | #define GCTL_SDE 0x00004000 |
1300 | #define GCTL_SDI 0x00008000 |
1301 | #define GCTL_SM 0x00010000 |
1302 | #define GCTL_SR 0x00020000 |
1303 | #define GCTL_SD 0x00040000 |
1304 | #define GCTL_SE 0x00080000 |
1305 | #define GCTL_AID 0x00100000 |
1306 | |
1307 | static int hw_pll_init(struct hw *hw, unsigned int rsr) |
1308 | { |
1309 | unsigned int pllctl; |
1310 | int i; |
1311 | |
1312 | pllctl = (48000 == rsr) ? 0x1480a001 : 0x1480a731; |
1313 | for (i = 0; i < 3; i++) { |
1314 | if (hw_read_20kx(hw, PLLCTL) == pllctl) |
1315 | break; |
1316 | |
1317 | hw_write_20kx(hw, PLLCTL, data: pllctl); |
1318 | msleep(msecs: 40); |
1319 | } |
1320 | if (i >= 3) { |
1321 | dev_alert(hw->card->dev, "PLL initialization failed!!!\n" ); |
1322 | return -EBUSY; |
1323 | } |
1324 | |
1325 | return 0; |
1326 | } |
1327 | |
1328 | static int hw_auto_init(struct hw *hw) |
1329 | { |
1330 | unsigned int gctl; |
1331 | int i; |
1332 | |
1333 | gctl = hw_read_20kx(hw, GCTL); |
1334 | set_field(data: &gctl, GCTL_EAI, value: 0); |
1335 | hw_write_20kx(hw, GCTL, data: gctl); |
1336 | set_field(data: &gctl, GCTL_EAI, value: 1); |
1337 | hw_write_20kx(hw, GCTL, data: gctl); |
1338 | mdelay(10); |
1339 | for (i = 0; i < 400000; i++) { |
1340 | gctl = hw_read_20kx(hw, GCTL); |
1341 | if (get_field(data: gctl, GCTL_AID)) |
1342 | break; |
1343 | } |
1344 | if (!get_field(data: gctl, GCTL_AID)) { |
1345 | dev_alert(hw->card->dev, "Card Auto-init failed!!!\n" ); |
1346 | return -EBUSY; |
1347 | } |
1348 | |
1349 | return 0; |
1350 | } |
1351 | |
1352 | static int i2c_unlock(struct hw *hw) |
1353 | { |
1354 | if ((hw_read_pci(hw, reg: 0xcc) & 0xff) == 0xaa) |
1355 | return 0; |
1356 | |
1357 | hw_write_pci(hw, reg: 0xcc, data: 0x8c); |
1358 | hw_write_pci(hw, reg: 0xcc, data: 0x0e); |
1359 | if ((hw_read_pci(hw, reg: 0xcc) & 0xff) == 0xaa) |
1360 | return 0; |
1361 | |
1362 | hw_write_pci(hw, reg: 0xcc, data: 0xee); |
1363 | hw_write_pci(hw, reg: 0xcc, data: 0xaa); |
1364 | if ((hw_read_pci(hw, reg: 0xcc) & 0xff) == 0xaa) |
1365 | return 0; |
1366 | |
1367 | return -1; |
1368 | } |
1369 | |
1370 | static void i2c_lock(struct hw *hw) |
1371 | { |
1372 | if ((hw_read_pci(hw, reg: 0xcc) & 0xff) == 0xaa) |
1373 | hw_write_pci(hw, reg: 0xcc, data: 0x00); |
1374 | } |
1375 | |
1376 | static void i2c_write(struct hw *hw, u32 device, u32 addr, u32 data) |
1377 | { |
1378 | unsigned int ret; |
1379 | |
1380 | do { |
1381 | ret = hw_read_pci(hw, reg: 0xEC); |
1382 | } while (!(ret & 0x800000)); |
1383 | hw_write_pci(hw, reg: 0xE0, data: device); |
1384 | hw_write_pci(hw, reg: 0xE4, data: (data << 8) | (addr & 0xff)); |
1385 | } |
1386 | |
1387 | /* DAC operations */ |
1388 | |
1389 | static int hw_reset_dac(struct hw *hw) |
1390 | { |
1391 | u32 i; |
1392 | u16 gpioorg; |
1393 | unsigned int ret; |
1394 | |
1395 | if (i2c_unlock(hw)) |
1396 | return -1; |
1397 | |
1398 | do { |
1399 | ret = hw_read_pci(hw, reg: 0xEC); |
1400 | } while (!(ret & 0x800000)); |
1401 | hw_write_pci(hw, reg: 0xEC, data: 0x05); /* write to i2c status control */ |
1402 | |
1403 | /* To be effective, need to reset the DAC twice. */ |
1404 | for (i = 0; i < 2; i++) { |
1405 | /* set gpio */ |
1406 | msleep(msecs: 100); |
1407 | gpioorg = (u16)hw_read_20kx(hw, GPIO); |
1408 | gpioorg &= 0xfffd; |
1409 | hw_write_20kx(hw, GPIO, data: gpioorg); |
1410 | mdelay(1); |
1411 | hw_write_20kx(hw, GPIO, data: gpioorg | 0x2); |
1412 | } |
1413 | |
1414 | i2c_write(hw, device: 0x00180080, addr: 0x01, data: 0x80); |
1415 | i2c_write(hw, device: 0x00180080, addr: 0x02, data: 0x10); |
1416 | |
1417 | i2c_lock(hw); |
1418 | |
1419 | return 0; |
1420 | } |
1421 | |
1422 | static int hw_dac_init(struct hw *hw, const struct dac_conf *info) |
1423 | { |
1424 | u32 data; |
1425 | u16 gpioorg; |
1426 | unsigned int ret; |
1427 | |
1428 | if (hw->model == CTSB055X) { |
1429 | /* SB055x, unmute outputs */ |
1430 | gpioorg = (u16)hw_read_20kx(hw, GPIO); |
1431 | gpioorg &= 0xffbf; /* set GPIO6 to low */ |
1432 | gpioorg |= 2; /* set GPIO1 to high */ |
1433 | hw_write_20kx(hw, GPIO, data: gpioorg); |
1434 | return 0; |
1435 | } |
1436 | |
1437 | /* mute outputs */ |
1438 | gpioorg = (u16)hw_read_20kx(hw, GPIO); |
1439 | gpioorg &= 0xffbf; |
1440 | hw_write_20kx(hw, GPIO, data: gpioorg); |
1441 | |
1442 | hw_reset_dac(hw); |
1443 | |
1444 | if (i2c_unlock(hw)) |
1445 | return -1; |
1446 | |
1447 | hw_write_pci(hw, reg: 0xEC, data: 0x05); /* write to i2c status control */ |
1448 | do { |
1449 | ret = hw_read_pci(hw, reg: 0xEC); |
1450 | } while (!(ret & 0x800000)); |
1451 | |
1452 | switch (info->msr) { |
1453 | case 1: |
1454 | data = 0x24; |
1455 | break; |
1456 | case 2: |
1457 | data = 0x25; |
1458 | break; |
1459 | case 4: |
1460 | data = 0x26; |
1461 | break; |
1462 | default: |
1463 | data = 0x24; |
1464 | break; |
1465 | } |
1466 | |
1467 | i2c_write(hw, device: 0x00180080, addr: 0x06, data); |
1468 | i2c_write(hw, device: 0x00180080, addr: 0x09, data); |
1469 | i2c_write(hw, device: 0x00180080, addr: 0x0c, data); |
1470 | i2c_write(hw, device: 0x00180080, addr: 0x0f, data); |
1471 | |
1472 | i2c_lock(hw); |
1473 | |
1474 | /* unmute outputs */ |
1475 | gpioorg = (u16)hw_read_20kx(hw, GPIO); |
1476 | gpioorg = gpioorg | 0x40; |
1477 | hw_write_20kx(hw, GPIO, data: gpioorg); |
1478 | |
1479 | return 0; |
1480 | } |
1481 | |
1482 | /* ADC operations */ |
1483 | |
1484 | static int is_adc_input_selected_SB055x(struct hw *hw, enum ADCSRC type) |
1485 | { |
1486 | return 0; |
1487 | } |
1488 | |
1489 | static int is_adc_input_selected_SBx(struct hw *hw, enum ADCSRC type) |
1490 | { |
1491 | u32 data; |
1492 | |
1493 | data = hw_read_20kx(hw, GPIO); |
1494 | switch (type) { |
1495 | case ADC_MICIN: |
1496 | data = ((data & (0x1<<7)) && (data & (0x1<<8))); |
1497 | break; |
1498 | case ADC_LINEIN: |
1499 | data = (!(data & (0x1<<7)) && (data & (0x1<<8))); |
1500 | break; |
1501 | case ADC_NONE: /* Digital I/O */ |
1502 | data = (!(data & (0x1<<8))); |
1503 | break; |
1504 | default: |
1505 | data = 0; |
1506 | } |
1507 | return data; |
1508 | } |
1509 | |
1510 | static int is_adc_input_selected_hendrix(struct hw *hw, enum ADCSRC type) |
1511 | { |
1512 | u32 data; |
1513 | |
1514 | data = hw_read_20kx(hw, GPIO); |
1515 | switch (type) { |
1516 | case ADC_MICIN: |
1517 | data = (data & (0x1 << 7)) ? 1 : 0; |
1518 | break; |
1519 | case ADC_LINEIN: |
1520 | data = (data & (0x1 << 7)) ? 0 : 1; |
1521 | break; |
1522 | default: |
1523 | data = 0; |
1524 | } |
1525 | return data; |
1526 | } |
1527 | |
1528 | static int hw_is_adc_input_selected(struct hw *hw, enum ADCSRC type) |
1529 | { |
1530 | switch (hw->model) { |
1531 | case CTSB055X: |
1532 | return is_adc_input_selected_SB055x(hw, type); |
1533 | case CTSB073X: |
1534 | return is_adc_input_selected_hendrix(hw, type); |
1535 | case CTUAA: |
1536 | return is_adc_input_selected_hendrix(hw, type); |
1537 | default: |
1538 | return is_adc_input_selected_SBx(hw, type); |
1539 | } |
1540 | } |
1541 | |
1542 | static int |
1543 | adc_input_select_SB055x(struct hw *hw, enum ADCSRC type, unsigned char boost) |
1544 | { |
1545 | u32 data; |
1546 | |
1547 | /* |
1548 | * check and set the following GPIO bits accordingly |
1549 | * ADC_Gain = GPIO2 |
1550 | * DRM_off = GPIO3 |
1551 | * Mic_Pwr_on = GPIO7 |
1552 | * Digital_IO_Sel = GPIO8 |
1553 | * Mic_Sw = GPIO9 |
1554 | * Aux/MicLine_Sw = GPIO12 |
1555 | */ |
1556 | data = hw_read_20kx(hw, GPIO); |
1557 | data &= 0xec73; |
1558 | switch (type) { |
1559 | case ADC_MICIN: |
1560 | data |= (0x1<<7) | (0x1<<8) | (0x1<<9) ; |
1561 | data |= boost ? (0x1<<2) : 0; |
1562 | break; |
1563 | case ADC_LINEIN: |
1564 | data |= (0x1<<8); |
1565 | break; |
1566 | case ADC_AUX: |
1567 | data |= (0x1<<8) | (0x1<<12); |
1568 | break; |
1569 | case ADC_NONE: |
1570 | data |= (0x1<<12); /* set to digital */ |
1571 | break; |
1572 | default: |
1573 | return -1; |
1574 | } |
1575 | |
1576 | hw_write_20kx(hw, GPIO, data); |
1577 | |
1578 | return 0; |
1579 | } |
1580 | |
1581 | |
1582 | static int |
1583 | adc_input_select_SBx(struct hw *hw, enum ADCSRC type, unsigned char boost) |
1584 | { |
1585 | u32 data; |
1586 | u32 i2c_data; |
1587 | unsigned int ret; |
1588 | |
1589 | if (i2c_unlock(hw)) |
1590 | return -1; |
1591 | |
1592 | do { |
1593 | ret = hw_read_pci(hw, reg: 0xEC); |
1594 | } while (!(ret & 0x800000)); /* i2c ready poll */ |
1595 | /* set i2c access mode as Direct Control */ |
1596 | hw_write_pci(hw, reg: 0xEC, data: 0x05); |
1597 | |
1598 | data = hw_read_20kx(hw, GPIO); |
1599 | switch (type) { |
1600 | case ADC_MICIN: |
1601 | data |= ((0x1 << 7) | (0x1 << 8)); |
1602 | i2c_data = 0x1; /* Mic-in */ |
1603 | break; |
1604 | case ADC_LINEIN: |
1605 | data &= ~(0x1 << 7); |
1606 | data |= (0x1 << 8); |
1607 | i2c_data = 0x2; /* Line-in */ |
1608 | break; |
1609 | case ADC_NONE: |
1610 | data &= ~(0x1 << 8); |
1611 | i2c_data = 0x0; /* set to Digital */ |
1612 | break; |
1613 | default: |
1614 | i2c_lock(hw); |
1615 | return -1; |
1616 | } |
1617 | hw_write_20kx(hw, GPIO, data); |
1618 | i2c_write(hw, device: 0x001a0080, addr: 0x2a, data: i2c_data); |
1619 | if (boost) { |
1620 | i2c_write(hw, device: 0x001a0080, addr: 0x1c, data: 0xe7); /* +12dB boost */ |
1621 | i2c_write(hw, device: 0x001a0080, addr: 0x1e, data: 0xe7); /* +12dB boost */ |
1622 | } else { |
1623 | i2c_write(hw, device: 0x001a0080, addr: 0x1c, data: 0xcf); /* No boost */ |
1624 | i2c_write(hw, device: 0x001a0080, addr: 0x1e, data: 0xcf); /* No boost */ |
1625 | } |
1626 | |
1627 | i2c_lock(hw); |
1628 | |
1629 | return 0; |
1630 | } |
1631 | |
1632 | static int |
1633 | adc_input_select_hendrix(struct hw *hw, enum ADCSRC type, unsigned char boost) |
1634 | { |
1635 | u32 data; |
1636 | u32 i2c_data; |
1637 | unsigned int ret; |
1638 | |
1639 | if (i2c_unlock(hw)) |
1640 | return -1; |
1641 | |
1642 | do { |
1643 | ret = hw_read_pci(hw, reg: 0xEC); |
1644 | } while (!(ret & 0x800000)); /* i2c ready poll */ |
1645 | /* set i2c access mode as Direct Control */ |
1646 | hw_write_pci(hw, reg: 0xEC, data: 0x05); |
1647 | |
1648 | data = hw_read_20kx(hw, GPIO); |
1649 | switch (type) { |
1650 | case ADC_MICIN: |
1651 | data |= (0x1 << 7); |
1652 | i2c_data = 0x1; /* Mic-in */ |
1653 | break; |
1654 | case ADC_LINEIN: |
1655 | data &= ~(0x1 << 7); |
1656 | i2c_data = 0x2; /* Line-in */ |
1657 | break; |
1658 | default: |
1659 | i2c_lock(hw); |
1660 | return -1; |
1661 | } |
1662 | hw_write_20kx(hw, GPIO, data); |
1663 | i2c_write(hw, device: 0x001a0080, addr: 0x2a, data: i2c_data); |
1664 | if (boost) { |
1665 | i2c_write(hw, device: 0x001a0080, addr: 0x1c, data: 0xe7); /* +12dB boost */ |
1666 | i2c_write(hw, device: 0x001a0080, addr: 0x1e, data: 0xe7); /* +12dB boost */ |
1667 | } else { |
1668 | i2c_write(hw, device: 0x001a0080, addr: 0x1c, data: 0xcf); /* No boost */ |
1669 | i2c_write(hw, device: 0x001a0080, addr: 0x1e, data: 0xcf); /* No boost */ |
1670 | } |
1671 | |
1672 | i2c_lock(hw); |
1673 | |
1674 | return 0; |
1675 | } |
1676 | |
1677 | static int hw_adc_input_select(struct hw *hw, enum ADCSRC type) |
1678 | { |
1679 | int state = type == ADC_MICIN; |
1680 | |
1681 | switch (hw->model) { |
1682 | case CTSB055X: |
1683 | return adc_input_select_SB055x(hw, type, boost: state); |
1684 | case CTSB073X: |
1685 | return adc_input_select_hendrix(hw, type, boost: state); |
1686 | case CTUAA: |
1687 | return adc_input_select_hendrix(hw, type, boost: state); |
1688 | default: |
1689 | return adc_input_select_SBx(hw, type, boost: state); |
1690 | } |
1691 | } |
1692 | |
1693 | static int adc_init_SB055x(struct hw *hw, int input, int mic20db) |
1694 | { |
1695 | return adc_input_select_SB055x(hw, type: input, boost: mic20db); |
1696 | } |
1697 | |
1698 | static int adc_init_SBx(struct hw *hw, int input, int mic20db) |
1699 | { |
1700 | u16 gpioorg; |
1701 | u16 input_source; |
1702 | u32 adcdata; |
1703 | unsigned int ret; |
1704 | |
1705 | input_source = 0x100; /* default to analog */ |
1706 | switch (input) { |
1707 | case ADC_MICIN: |
1708 | adcdata = 0x1; |
1709 | input_source = 0x180; /* set GPIO7 to select Mic */ |
1710 | break; |
1711 | case ADC_LINEIN: |
1712 | adcdata = 0x2; |
1713 | break; |
1714 | case ADC_VIDEO: |
1715 | adcdata = 0x4; |
1716 | break; |
1717 | case ADC_AUX: |
1718 | adcdata = 0x8; |
1719 | break; |
1720 | case ADC_NONE: |
1721 | adcdata = 0x0; |
1722 | input_source = 0x0; /* set to Digital */ |
1723 | break; |
1724 | default: |
1725 | adcdata = 0x0; |
1726 | break; |
1727 | } |
1728 | |
1729 | if (i2c_unlock(hw)) |
1730 | return -1; |
1731 | |
1732 | do { |
1733 | ret = hw_read_pci(hw, reg: 0xEC); |
1734 | } while (!(ret & 0x800000)); /* i2c ready poll */ |
1735 | hw_write_pci(hw, reg: 0xEC, data: 0x05); /* write to i2c status control */ |
1736 | |
1737 | i2c_write(hw, device: 0x001a0080, addr: 0x0e, data: 0x08); |
1738 | i2c_write(hw, device: 0x001a0080, addr: 0x18, data: 0x0a); |
1739 | i2c_write(hw, device: 0x001a0080, addr: 0x28, data: 0x86); |
1740 | i2c_write(hw, device: 0x001a0080, addr: 0x2a, data: adcdata); |
1741 | |
1742 | if (mic20db) { |
1743 | i2c_write(hw, device: 0x001a0080, addr: 0x1c, data: 0xf7); |
1744 | i2c_write(hw, device: 0x001a0080, addr: 0x1e, data: 0xf7); |
1745 | } else { |
1746 | i2c_write(hw, device: 0x001a0080, addr: 0x1c, data: 0xcf); |
1747 | i2c_write(hw, device: 0x001a0080, addr: 0x1e, data: 0xcf); |
1748 | } |
1749 | |
1750 | if (!(hw_read_20kx(hw, ID0) & 0x100)) |
1751 | i2c_write(hw, device: 0x001a0080, addr: 0x16, data: 0x26); |
1752 | |
1753 | i2c_lock(hw); |
1754 | |
1755 | gpioorg = (u16)hw_read_20kx(hw, GPIO); |
1756 | gpioorg &= 0xfe7f; |
1757 | gpioorg |= input_source; |
1758 | hw_write_20kx(hw, GPIO, data: gpioorg); |
1759 | |
1760 | return 0; |
1761 | } |
1762 | |
1763 | static int hw_adc_init(struct hw *hw, const struct adc_conf *info) |
1764 | { |
1765 | if (hw->model == CTSB055X) |
1766 | return adc_init_SB055x(hw, input: info->input, mic20db: info->mic20db); |
1767 | else |
1768 | return adc_init_SBx(hw, input: info->input, mic20db: info->mic20db); |
1769 | } |
1770 | |
1771 | static struct capabilities hw_capabilities(struct hw *hw) |
1772 | { |
1773 | struct capabilities cap; |
1774 | |
1775 | /* SB073x and Vista compatible cards have no digit IO switch */ |
1776 | cap.digit_io_switch = !(hw->model == CTSB073X || hw->model == CTUAA); |
1777 | cap.dedicated_mic = 0; |
1778 | cap.output_switch = 0; |
1779 | cap.mic_source_switch = 0; |
1780 | |
1781 | return cap; |
1782 | } |
1783 | |
1784 | #define CTLBITS(a, b, c, d) (((a) << 24) | ((b) << 16) | ((c) << 8) | (d)) |
1785 | |
1786 | #define UAA_CFG_PWRSTATUS 0x44 |
1787 | #define UAA_CFG_SPACE_FLAG 0xA0 |
1788 | #define UAA_CORE_CHANGE 0x3FFC |
1789 | static int uaa_to_xfi(struct pci_dev *pci) |
1790 | { |
1791 | unsigned int bar0, bar1, bar2, bar3, bar4, bar5; |
1792 | unsigned int cmd, irq, cl_size, l_timer, pwr; |
1793 | unsigned int is_uaa; |
1794 | unsigned int data[4] = {0}; |
1795 | unsigned int io_base; |
1796 | void __iomem *mem_base; |
1797 | int i; |
1798 | const u32 CTLX = CTLBITS('C', 'T', 'L', 'X'); |
1799 | const u32 CTL_ = CTLBITS('C', 'T', 'L', '-'); |
1800 | const u32 CTLF = CTLBITS('C', 'T', 'L', 'F'); |
1801 | const u32 CTLi = CTLBITS('C', 'T', 'L', 'i'); |
1802 | const u32 CTLA = CTLBITS('C', 'T', 'L', 'A'); |
1803 | const u32 CTLZ = CTLBITS('C', 'T', 'L', 'Z'); |
1804 | const u32 CTLL = CTLBITS('C', 'T', 'L', 'L'); |
1805 | |
1806 | /* By default, Hendrix card UAA Bar0 should be using memory... */ |
1807 | io_base = pci_resource_start(pci, 0); |
1808 | mem_base = ioremap(offset: io_base, pci_resource_len(pci, 0)); |
1809 | if (!mem_base) |
1810 | return -ENOENT; |
1811 | |
1812 | /* Read current mode from Mode Change Register */ |
1813 | for (i = 0; i < 4; i++) |
1814 | data[i] = readl(addr: mem_base + UAA_CORE_CHANGE); |
1815 | |
1816 | /* Determine current mode... */ |
1817 | if (data[0] == CTLA) { |
1818 | is_uaa = ((data[1] == CTLZ && data[2] == CTLL |
1819 | && data[3] == CTLA) || (data[1] == CTLA |
1820 | && data[2] == CTLZ && data[3] == CTLL)); |
1821 | } else if (data[0] == CTLZ) { |
1822 | is_uaa = (data[1] == CTLL |
1823 | && data[2] == CTLA && data[3] == CTLA); |
1824 | } else if (data[0] == CTLL) { |
1825 | is_uaa = (data[1] == CTLA |
1826 | && data[2] == CTLA && data[3] == CTLZ); |
1827 | } else { |
1828 | is_uaa = 0; |
1829 | } |
1830 | |
1831 | if (!is_uaa) { |
1832 | /* Not in UAA mode currently. Return directly. */ |
1833 | iounmap(addr: mem_base); |
1834 | return 0; |
1835 | } |
1836 | |
1837 | pci_read_config_dword(dev: pci, PCI_BASE_ADDRESS_0, val: &bar0); |
1838 | pci_read_config_dword(dev: pci, PCI_BASE_ADDRESS_1, val: &bar1); |
1839 | pci_read_config_dword(dev: pci, PCI_BASE_ADDRESS_2, val: &bar2); |
1840 | pci_read_config_dword(dev: pci, PCI_BASE_ADDRESS_3, val: &bar3); |
1841 | pci_read_config_dword(dev: pci, PCI_BASE_ADDRESS_4, val: &bar4); |
1842 | pci_read_config_dword(dev: pci, PCI_BASE_ADDRESS_5, val: &bar5); |
1843 | pci_read_config_dword(dev: pci, PCI_INTERRUPT_LINE, val: &irq); |
1844 | pci_read_config_dword(dev: pci, PCI_CACHE_LINE_SIZE, val: &cl_size); |
1845 | pci_read_config_dword(dev: pci, PCI_LATENCY_TIMER, val: &l_timer); |
1846 | pci_read_config_dword(dev: pci, UAA_CFG_PWRSTATUS, val: &pwr); |
1847 | pci_read_config_dword(dev: pci, PCI_COMMAND, val: &cmd); |
1848 | |
1849 | /* Set up X-Fi core PCI configuration space. */ |
1850 | /* Switch to X-Fi config space with BAR0 exposed. */ |
1851 | pci_write_config_dword(dev: pci, UAA_CFG_SPACE_FLAG, val: 0x87654321); |
1852 | /* Copy UAA's BAR5 into X-Fi BAR0 */ |
1853 | pci_write_config_dword(dev: pci, PCI_BASE_ADDRESS_0, val: bar5); |
1854 | /* Switch to X-Fi config space without BAR0 exposed. */ |
1855 | pci_write_config_dword(dev: pci, UAA_CFG_SPACE_FLAG, val: 0x12345678); |
1856 | pci_write_config_dword(dev: pci, PCI_BASE_ADDRESS_1, val: bar1); |
1857 | pci_write_config_dword(dev: pci, PCI_BASE_ADDRESS_2, val: bar2); |
1858 | pci_write_config_dword(dev: pci, PCI_BASE_ADDRESS_3, val: bar3); |
1859 | pci_write_config_dword(dev: pci, PCI_BASE_ADDRESS_4, val: bar4); |
1860 | pci_write_config_dword(dev: pci, PCI_INTERRUPT_LINE, val: irq); |
1861 | pci_write_config_dword(dev: pci, PCI_CACHE_LINE_SIZE, val: cl_size); |
1862 | pci_write_config_dword(dev: pci, PCI_LATENCY_TIMER, val: l_timer); |
1863 | pci_write_config_dword(dev: pci, UAA_CFG_PWRSTATUS, val: pwr); |
1864 | pci_write_config_dword(dev: pci, PCI_COMMAND, val: cmd); |
1865 | |
1866 | /* Switch to X-Fi mode */ |
1867 | writel(val: CTLX, addr: (mem_base + UAA_CORE_CHANGE)); |
1868 | writel(val: CTL_, addr: (mem_base + UAA_CORE_CHANGE)); |
1869 | writel(val: CTLF, addr: (mem_base + UAA_CORE_CHANGE)); |
1870 | writel(val: CTLi, addr: (mem_base + UAA_CORE_CHANGE)); |
1871 | |
1872 | iounmap(addr: mem_base); |
1873 | |
1874 | return 0; |
1875 | } |
1876 | |
1877 | static irqreturn_t ct_20k1_interrupt(int irq, void *dev_id) |
1878 | { |
1879 | struct hw *hw = dev_id; |
1880 | unsigned int status; |
1881 | |
1882 | status = hw_read_20kx(hw, GIP); |
1883 | if (!status) |
1884 | return IRQ_NONE; |
1885 | |
1886 | if (hw->irq_callback) |
1887 | hw->irq_callback(hw->irq_callback_data, status); |
1888 | |
1889 | hw_write_20kx(hw, GIP, data: status); |
1890 | return IRQ_HANDLED; |
1891 | } |
1892 | |
1893 | static int hw_card_start(struct hw *hw) |
1894 | { |
1895 | int err; |
1896 | struct pci_dev *pci = hw->pci; |
1897 | const unsigned int dma_bits = BITS_PER_LONG; |
1898 | |
1899 | err = pci_enable_device(dev: pci); |
1900 | if (err < 0) |
1901 | return err; |
1902 | |
1903 | /* Set DMA transfer mask */ |
1904 | if (dma_set_mask_and_coherent(dev: &pci->dev, DMA_BIT_MASK(dma_bits))) |
1905 | dma_set_mask_and_coherent(dev: &pci->dev, DMA_BIT_MASK(32)); |
1906 | |
1907 | if (!hw->io_base) { |
1908 | err = pci_request_regions(pci, "XFi" ); |
1909 | if (err < 0) |
1910 | goto error1; |
1911 | |
1912 | if (hw->model == CTUAA) |
1913 | hw->io_base = pci_resource_start(pci, 5); |
1914 | else |
1915 | hw->io_base = pci_resource_start(pci, 0); |
1916 | |
1917 | } |
1918 | |
1919 | /* Switch to X-Fi mode from UAA mode if needed */ |
1920 | if (hw->model == CTUAA) { |
1921 | err = uaa_to_xfi(pci); |
1922 | if (err) |
1923 | goto error2; |
1924 | |
1925 | } |
1926 | |
1927 | if (hw->irq < 0) { |
1928 | err = request_irq(irq: pci->irq, handler: ct_20k1_interrupt, IRQF_SHARED, |
1929 | KBUILD_MODNAME, dev: hw); |
1930 | if (err < 0) { |
1931 | dev_err(hw->card->dev, |
1932 | "XFi: Cannot get irq %d\n" , pci->irq); |
1933 | goto error2; |
1934 | } |
1935 | hw->irq = pci->irq; |
1936 | hw->card->sync_irq = hw->irq; |
1937 | } |
1938 | |
1939 | pci_set_master(dev: pci); |
1940 | |
1941 | return 0; |
1942 | |
1943 | error2: |
1944 | pci_release_regions(pci); |
1945 | hw->io_base = 0; |
1946 | error1: |
1947 | pci_disable_device(dev: pci); |
1948 | return err; |
1949 | } |
1950 | |
1951 | static int hw_card_stop(struct hw *hw) |
1952 | { |
1953 | unsigned int data; |
1954 | |
1955 | /* disable transport bus master and queueing of request */ |
1956 | hw_write_20kx(hw, TRNCTL, data: 0x00); |
1957 | |
1958 | /* disable pll */ |
1959 | data = hw_read_20kx(hw, PLLCTL); |
1960 | hw_write_20kx(hw, PLLCTL, data: (data & (~(0x0F<<12)))); |
1961 | |
1962 | return 0; |
1963 | } |
1964 | |
1965 | static int hw_card_shutdown(struct hw *hw) |
1966 | { |
1967 | if (hw->irq >= 0) |
1968 | free_irq(hw->irq, hw); |
1969 | |
1970 | hw->irq = -1; |
1971 | iounmap(addr: hw->mem_base); |
1972 | hw->mem_base = NULL; |
1973 | |
1974 | if (hw->io_base) |
1975 | pci_release_regions(hw->pci); |
1976 | |
1977 | hw->io_base = 0; |
1978 | |
1979 | pci_disable_device(dev: hw->pci); |
1980 | |
1981 | return 0; |
1982 | } |
1983 | |
1984 | static int hw_card_init(struct hw *hw, struct card_conf *info) |
1985 | { |
1986 | int err; |
1987 | unsigned int gctl; |
1988 | u32 data; |
1989 | struct dac_conf dac_info = {0}; |
1990 | struct adc_conf adc_info = {0}; |
1991 | struct daio_conf daio_info = {0}; |
1992 | struct trn_conf trn_info = {0}; |
1993 | |
1994 | /* Get PCI io port base address and do Hendrix switch if needed. */ |
1995 | err = hw_card_start(hw); |
1996 | if (err) |
1997 | return err; |
1998 | |
1999 | /* PLL init */ |
2000 | err = hw_pll_init(hw, rsr: info->rsr); |
2001 | if (err < 0) |
2002 | return err; |
2003 | |
2004 | /* kick off auto-init */ |
2005 | err = hw_auto_init(hw); |
2006 | if (err < 0) |
2007 | return err; |
2008 | |
2009 | /* Enable audio ring */ |
2010 | gctl = hw_read_20kx(hw, GCTL); |
2011 | set_field(data: &gctl, GCTL_EAC, value: 1); |
2012 | set_field(data: &gctl, GCTL_DBP, value: 1); |
2013 | set_field(data: &gctl, GCTL_TBP, value: 1); |
2014 | set_field(data: &gctl, GCTL_FBP, value: 1); |
2015 | set_field(data: &gctl, GCTL_ET, value: 1); |
2016 | hw_write_20kx(hw, GCTL, data: gctl); |
2017 | mdelay(10); |
2018 | |
2019 | /* Reset all global pending interrupts */ |
2020 | hw_write_20kx(hw, GIE, data: 0); |
2021 | /* Reset all SRC pending interrupts */ |
2022 | hw_write_20kx(hw, SRCIP, data: 0); |
2023 | msleep(msecs: 30); |
2024 | |
2025 | /* Detect the card ID and configure GPIO accordingly. */ |
2026 | switch (hw->model) { |
2027 | case CTSB055X: |
2028 | hw_write_20kx(hw, GPIOCTL, data: 0x13fe); |
2029 | break; |
2030 | case CTSB073X: |
2031 | hw_write_20kx(hw, GPIOCTL, data: 0x00e6); |
2032 | break; |
2033 | case CTUAA: |
2034 | hw_write_20kx(hw, GPIOCTL, data: 0x00c2); |
2035 | break; |
2036 | default: |
2037 | hw_write_20kx(hw, GPIOCTL, data: 0x01e6); |
2038 | break; |
2039 | } |
2040 | |
2041 | trn_info.vm_pgt_phys = info->vm_pgt_phys; |
2042 | err = hw_trn_init(hw, info: &trn_info); |
2043 | if (err < 0) |
2044 | return err; |
2045 | |
2046 | daio_info.msr = info->msr; |
2047 | err = hw_daio_init(hw, info: &daio_info); |
2048 | if (err < 0) |
2049 | return err; |
2050 | |
2051 | dac_info.msr = info->msr; |
2052 | err = hw_dac_init(hw, info: &dac_info); |
2053 | if (err < 0) |
2054 | return err; |
2055 | |
2056 | adc_info.msr = info->msr; |
2057 | adc_info.input = ADC_LINEIN; |
2058 | adc_info.mic20db = 0; |
2059 | err = hw_adc_init(hw, info: &adc_info); |
2060 | if (err < 0) |
2061 | return err; |
2062 | |
2063 | data = hw_read_20kx(hw, SRCMCTL); |
2064 | data |= 0x1; /* Enables input from the audio ring */ |
2065 | hw_write_20kx(hw, SRCMCTL, data); |
2066 | |
2067 | return 0; |
2068 | } |
2069 | |
2070 | #ifdef CONFIG_PM_SLEEP |
2071 | static int hw_suspend(struct hw *hw) |
2072 | { |
2073 | struct pci_dev *pci = hw->pci; |
2074 | |
2075 | hw_card_stop(hw); |
2076 | |
2077 | if (hw->model == CTUAA) { |
2078 | /* Switch to UAA config space. */ |
2079 | pci_write_config_dword(dev: pci, UAA_CFG_SPACE_FLAG, val: 0x0); |
2080 | } |
2081 | |
2082 | return 0; |
2083 | } |
2084 | |
2085 | static int hw_resume(struct hw *hw, struct card_conf *info) |
2086 | { |
2087 | /* Re-initialize card hardware. */ |
2088 | return hw_card_init(hw, info); |
2089 | } |
2090 | #endif |
2091 | |
2092 | static u32 hw_read_20kx(struct hw *hw, u32 reg) |
2093 | { |
2094 | u32 value; |
2095 | unsigned long flags; |
2096 | |
2097 | spin_lock_irqsave( |
2098 | &container_of(hw, struct hw20k1, hw)->reg_20k1_lock, flags); |
2099 | outl(value: reg, port: hw->io_base + 0x0); |
2100 | value = inl(port: hw->io_base + 0x4); |
2101 | spin_unlock_irqrestore( |
2102 | lock: &container_of(hw, struct hw20k1, hw)->reg_20k1_lock, flags); |
2103 | |
2104 | return value; |
2105 | } |
2106 | |
2107 | static void hw_write_20kx(struct hw *hw, u32 reg, u32 data) |
2108 | { |
2109 | unsigned long flags; |
2110 | |
2111 | spin_lock_irqsave( |
2112 | &container_of(hw, struct hw20k1, hw)->reg_20k1_lock, flags); |
2113 | outl(value: reg, port: hw->io_base + 0x0); |
2114 | outl(value: data, port: hw->io_base + 0x4); |
2115 | spin_unlock_irqrestore( |
2116 | lock: &container_of(hw, struct hw20k1, hw)->reg_20k1_lock, flags); |
2117 | |
2118 | } |
2119 | |
2120 | static u32 hw_read_pci(struct hw *hw, u32 reg) |
2121 | { |
2122 | u32 value; |
2123 | unsigned long flags; |
2124 | |
2125 | spin_lock_irqsave( |
2126 | &container_of(hw, struct hw20k1, hw)->reg_pci_lock, flags); |
2127 | outl(value: reg, port: hw->io_base + 0x10); |
2128 | value = inl(port: hw->io_base + 0x14); |
2129 | spin_unlock_irqrestore( |
2130 | lock: &container_of(hw, struct hw20k1, hw)->reg_pci_lock, flags); |
2131 | |
2132 | return value; |
2133 | } |
2134 | |
2135 | static void hw_write_pci(struct hw *hw, u32 reg, u32 data) |
2136 | { |
2137 | unsigned long flags; |
2138 | |
2139 | spin_lock_irqsave( |
2140 | &container_of(hw, struct hw20k1, hw)->reg_pci_lock, flags); |
2141 | outl(value: reg, port: hw->io_base + 0x10); |
2142 | outl(value: data, port: hw->io_base + 0x14); |
2143 | spin_unlock_irqrestore( |
2144 | lock: &container_of(hw, struct hw20k1, hw)->reg_pci_lock, flags); |
2145 | } |
2146 | |
2147 | static const struct hw ct20k1_preset = { |
2148 | .irq = -1, |
2149 | |
2150 | .card_init = hw_card_init, |
2151 | .card_stop = hw_card_stop, |
2152 | .pll_init = hw_pll_init, |
2153 | .is_adc_source_selected = hw_is_adc_input_selected, |
2154 | .select_adc_source = hw_adc_input_select, |
2155 | .capabilities = hw_capabilities, |
2156 | #ifdef CONFIG_PM_SLEEP |
2157 | .suspend = hw_suspend, |
2158 | .resume = hw_resume, |
2159 | #endif |
2160 | |
2161 | .src_rsc_get_ctrl_blk = src_get_rsc_ctrl_blk, |
2162 | .src_rsc_put_ctrl_blk = src_put_rsc_ctrl_blk, |
2163 | .src_mgr_get_ctrl_blk = src_mgr_get_ctrl_blk, |
2164 | .src_mgr_put_ctrl_blk = src_mgr_put_ctrl_blk, |
2165 | .src_set_state = src_set_state, |
2166 | .src_set_bm = src_set_bm, |
2167 | .src_set_rsr = src_set_rsr, |
2168 | .src_set_sf = src_set_sf, |
2169 | .src_set_wr = src_set_wr, |
2170 | .src_set_pm = src_set_pm, |
2171 | .src_set_rom = src_set_rom, |
2172 | .src_set_vo = src_set_vo, |
2173 | .src_set_st = src_set_st, |
2174 | .src_set_ie = src_set_ie, |
2175 | .src_set_ilsz = src_set_ilsz, |
2176 | .src_set_bp = src_set_bp, |
2177 | .src_set_cisz = src_set_cisz, |
2178 | .src_set_ca = src_set_ca, |
2179 | .src_set_sa = src_set_sa, |
2180 | .src_set_la = src_set_la, |
2181 | .src_set_pitch = src_set_pitch, |
2182 | .src_set_dirty = src_set_dirty, |
2183 | .src_set_clear_zbufs = src_set_clear_zbufs, |
2184 | .src_set_dirty_all = src_set_dirty_all, |
2185 | .src_commit_write = src_commit_write, |
2186 | .src_get_ca = src_get_ca, |
2187 | .src_get_dirty = src_get_dirty, |
2188 | .src_dirty_conj_mask = src_dirty_conj_mask, |
2189 | .src_mgr_enbs_src = src_mgr_enbs_src, |
2190 | .src_mgr_enb_src = src_mgr_enb_src, |
2191 | .src_mgr_dsb_src = src_mgr_dsb_src, |
2192 | .src_mgr_commit_write = src_mgr_commit_write, |
2193 | |
2194 | .srcimp_mgr_get_ctrl_blk = srcimp_mgr_get_ctrl_blk, |
2195 | .srcimp_mgr_put_ctrl_blk = srcimp_mgr_put_ctrl_blk, |
2196 | .srcimp_mgr_set_imaparc = srcimp_mgr_set_imaparc, |
2197 | .srcimp_mgr_set_imapuser = srcimp_mgr_set_imapuser, |
2198 | .srcimp_mgr_set_imapnxt = srcimp_mgr_set_imapnxt, |
2199 | .srcimp_mgr_set_imapaddr = srcimp_mgr_set_imapaddr, |
2200 | .srcimp_mgr_commit_write = srcimp_mgr_commit_write, |
2201 | |
2202 | .amixer_rsc_get_ctrl_blk = amixer_rsc_get_ctrl_blk, |
2203 | .amixer_rsc_put_ctrl_blk = amixer_rsc_put_ctrl_blk, |
2204 | .amixer_mgr_get_ctrl_blk = amixer_mgr_get_ctrl_blk, |
2205 | .amixer_mgr_put_ctrl_blk = amixer_mgr_put_ctrl_blk, |
2206 | .amixer_set_mode = amixer_set_mode, |
2207 | .amixer_set_iv = amixer_set_iv, |
2208 | .amixer_set_x = amixer_set_x, |
2209 | .amixer_set_y = amixer_set_y, |
2210 | .amixer_set_sadr = amixer_set_sadr, |
2211 | .amixer_set_se = amixer_set_se, |
2212 | .amixer_set_dirty = amixer_set_dirty, |
2213 | .amixer_set_dirty_all = amixer_set_dirty_all, |
2214 | .amixer_commit_write = amixer_commit_write, |
2215 | .amixer_get_y = amixer_get_y, |
2216 | .amixer_get_dirty = amixer_get_dirty, |
2217 | |
2218 | .dai_get_ctrl_blk = dai_get_ctrl_blk, |
2219 | .dai_put_ctrl_blk = dai_put_ctrl_blk, |
2220 | .dai_srt_set_srco = dai_srt_set_srcr, |
2221 | .dai_srt_set_srcm = dai_srt_set_srcl, |
2222 | .dai_srt_set_rsr = dai_srt_set_rsr, |
2223 | .dai_srt_set_drat = dai_srt_set_drat, |
2224 | .dai_srt_set_ec = dai_srt_set_ec, |
2225 | .dai_srt_set_et = dai_srt_set_et, |
2226 | .dai_commit_write = dai_commit_write, |
2227 | |
2228 | .dao_get_ctrl_blk = dao_get_ctrl_blk, |
2229 | .dao_put_ctrl_blk = dao_put_ctrl_blk, |
2230 | .dao_set_spos = dao_set_spos, |
2231 | .dao_commit_write = dao_commit_write, |
2232 | .dao_get_spos = dao_get_spos, |
2233 | |
2234 | .daio_mgr_get_ctrl_blk = daio_mgr_get_ctrl_blk, |
2235 | .daio_mgr_put_ctrl_blk = daio_mgr_put_ctrl_blk, |
2236 | .daio_mgr_enb_dai = daio_mgr_enb_dai, |
2237 | .daio_mgr_dsb_dai = daio_mgr_dsb_dai, |
2238 | .daio_mgr_enb_dao = daio_mgr_enb_dao, |
2239 | .daio_mgr_dsb_dao = daio_mgr_dsb_dao, |
2240 | .daio_mgr_dao_init = daio_mgr_dao_init, |
2241 | .daio_mgr_set_imaparc = daio_mgr_set_imaparc, |
2242 | .daio_mgr_set_imapnxt = daio_mgr_set_imapnxt, |
2243 | .daio_mgr_set_imapaddr = daio_mgr_set_imapaddr, |
2244 | .daio_mgr_commit_write = daio_mgr_commit_write, |
2245 | |
2246 | .set_timer_irq = set_timer_irq, |
2247 | .set_timer_tick = set_timer_tick, |
2248 | .get_wc = get_wc, |
2249 | }; |
2250 | |
2251 | int create_20k1_hw_obj(struct hw **rhw) |
2252 | { |
2253 | struct hw20k1 *hw20k1; |
2254 | |
2255 | *rhw = NULL; |
2256 | hw20k1 = kzalloc(size: sizeof(*hw20k1), GFP_KERNEL); |
2257 | if (!hw20k1) |
2258 | return -ENOMEM; |
2259 | |
2260 | spin_lock_init(&hw20k1->reg_20k1_lock); |
2261 | spin_lock_init(&hw20k1->reg_pci_lock); |
2262 | |
2263 | hw20k1->hw = ct20k1_preset; |
2264 | |
2265 | *rhw = &hw20k1->hw; |
2266 | |
2267 | return 0; |
2268 | } |
2269 | |
2270 | int destroy_20k1_hw_obj(struct hw *hw) |
2271 | { |
2272 | if (hw->io_base) |
2273 | hw_card_shutdown(hw); |
2274 | |
2275 | kfree(container_of(hw, struct hw20k1, hw)); |
2276 | return 0; |
2277 | } |
2278 | |