1 | /* SPDX-License-Identifier: GPL-2.0-or-later */ |
2 | /* |
3 | * Driver for Digigram VX222 PCI soundcards |
4 | * |
5 | * Copyright (c) 2002 by Takashi Iwai <tiwai@suse.de> |
6 | */ |
7 | |
8 | #ifndef __VX222_H |
9 | #define __VX222_H |
10 | |
11 | #include <sound/vx_core.h> |
12 | |
13 | struct snd_vx222 { |
14 | |
15 | struct vx_core core; |
16 | |
17 | /* h/w config; for PLX and for DSP */ |
18 | struct pci_dev *pci; |
19 | unsigned long port[2]; |
20 | |
21 | unsigned int regCDSP; /* current CDSP register */ |
22 | unsigned int regCFG; /* current CFG register */ |
23 | unsigned int regSELMIC; /* current SELMIC reg. (for VX222 Mic) */ |
24 | |
25 | int input_level[2]; /* input level for vx222 mic */ |
26 | int mic_level; /* mic level for vx222 mic */ |
27 | }; |
28 | |
29 | #define to_vx222(x) container_of(x, struct snd_vx222, core) |
30 | |
31 | /* we use a lookup table with 148 values, see vx_mixer.c */ |
32 | #define VX2_AKM_LEVEL_MAX 0x93 |
33 | |
34 | extern const struct snd_vx_ops vx222_ops; |
35 | extern const struct snd_vx_ops vx222_old_ops; |
36 | |
37 | /* Offset of registers with base equal to portDSP. */ |
38 | #define VX_RESET_DMA_REGISTER_OFFSET 0x00000008 |
39 | |
40 | /* Constants used to access the INTCSR register. */ |
41 | #define VX_INTCSR_VALUE 0x00000001 |
42 | #define VX_PCI_INTERRUPT_MASK 0x00000040 |
43 | |
44 | /* Constants used to access the CDSP register (0x20). */ |
45 | #define VX_CDSP_TEST1_MASK 0x00000080 |
46 | #define VX_CDSP_TOR1_MASK 0x00000040 |
47 | #define VX_CDSP_TOR2_MASK 0x00000020 |
48 | #define VX_CDSP_RESERVED0_0_MASK 0x00000010 |
49 | #define VX_CDSP_CODEC_RESET_MASK 0x00000008 |
50 | #define VX_CDSP_VALID_IRQ_MASK 0x00000004 |
51 | #define VX_CDSP_TEST0_MASK 0x00000002 |
52 | #define VX_CDSP_DSP_RESET_MASK 0x00000001 |
53 | |
54 | #define VX_CDSP_GPIO_OUT_MASK 0x00000060 |
55 | #define VX_GPIO_OUT_BIT_OFFSET 5 // transform output to bit 0 and 1 |
56 | |
57 | /* Constants used to access the CFG register (0x24). */ |
58 | #define VX_CFG_SYNCDSP_MASK 0x00000080 |
59 | #define VX_CFG_RESERVED0_0_MASK 0x00000040 |
60 | #define VX_CFG_RESERVED1_0_MASK 0x00000020 |
61 | #define VX_CFG_RESERVED2_0_MASK 0x00000010 |
62 | #define VX_CFG_DATAIN_SEL_MASK 0x00000008 // 0 (ana), 1 (UER) |
63 | #define VX_CFG_RESERVED3_0_MASK 0x00000004 |
64 | #define VX_CFG_RESERVED4_0_MASK 0x00000002 |
65 | #define VX_CFG_CLOCKIN_SEL_MASK 0x00000001 // 0 (internal), 1 (AES/EBU) |
66 | |
67 | /* Constants used to access the STATUS register (0x30). */ |
68 | #define VX_STATUS_DATA_XICOR_MASK 0x00000080 |
69 | #define VX_STATUS_VAL_TEST1_MASK 0x00000040 |
70 | #define VX_STATUS_VAL_TEST0_MASK 0x00000020 |
71 | #define VX_STATUS_RESERVED0_MASK 0x00000010 |
72 | #define VX_STATUS_VAL_TOR1_MASK 0x00000008 |
73 | #define VX_STATUS_VAL_TOR0_MASK 0x00000004 |
74 | #define VX_STATUS_LEVEL_IN_MASK 0x00000002 // 6 dBu (0), 22 dBu (1) |
75 | #define VX_STATUS_MEMIRQ_MASK 0x00000001 |
76 | |
77 | #define VX_STATUS_GPIO_IN_MASK 0x0000000C |
78 | #define VX_GPIO_IN_BIT_OFFSET 0 // leave input as bit 2 and 3 |
79 | |
80 | /* Constants used to access the MICRO INPUT SELECT register (0x40). */ |
81 | #define MICRO_SELECT_INPUT_NORM 0x00 |
82 | #define MICRO_SELECT_INPUT_MUTE 0x01 |
83 | #define MICRO_SELECT_INPUT_LIMIT 0x02 |
84 | #define MICRO_SELECT_INPUT_MASK 0x03 |
85 | |
86 | #define MICRO_SELECT_PREAMPLI_G_0 0x00 |
87 | #define MICRO_SELECT_PREAMPLI_G_1 0x04 |
88 | #define MICRO_SELECT_PREAMPLI_G_2 0x08 |
89 | #define MICRO_SELECT_PREAMPLI_G_3 0x0C |
90 | #define MICRO_SELECT_PREAMPLI_MASK 0x0C |
91 | #define MICRO_SELECT_PREAMPLI_OFFSET 2 |
92 | |
93 | #define MICRO_SELECT_RAISE_COMPR 0x10 |
94 | |
95 | #define MICRO_SELECT_NOISE_T_52DB 0x00 |
96 | #define MICRO_SELECT_NOISE_T_42DB 0x20 |
97 | #define MICRO_SELECT_NOISE_T_32DB 0x40 |
98 | #define MICRO_SELECT_NOISE_T_MASK 0x60 |
99 | |
100 | #define MICRO_SELECT_PHANTOM_ALIM 0x80 |
101 | |
102 | |
103 | #endif /* __VX222_H */ |
104 | |