1 | // SPDX-License-Identifier: GPL-2.0-or-later |
2 | /* |
3 | * Driver for Digigram VX222 V2/Mic soundcards |
4 | * |
5 | * VX222-specific low-level routines |
6 | * |
7 | * Copyright (c) 2002 by Takashi Iwai <tiwai@suse.de> |
8 | */ |
9 | |
10 | #include <linux/delay.h> |
11 | #include <linux/device.h> |
12 | #include <linux/firmware.h> |
13 | #include <linux/mutex.h> |
14 | #include <linux/io.h> |
15 | |
16 | #include <sound/core.h> |
17 | #include <sound/control.h> |
18 | #include <sound/tlv.h> |
19 | #include "vx222.h" |
20 | |
21 | |
22 | static const int vx2_reg_offset[VX_REG_MAX] = { |
23 | [VX_ICR] = 0x00, |
24 | [VX_CVR] = 0x04, |
25 | [VX_ISR] = 0x08, |
26 | [VX_IVR] = 0x0c, |
27 | [VX_RXH] = 0x14, |
28 | [VX_RXM] = 0x18, |
29 | [VX_RXL] = 0x1c, |
30 | [VX_DMA] = 0x10, |
31 | [VX_CDSP] = 0x20, |
32 | [VX_CFG] = 0x24, |
33 | [VX_RUER] = 0x28, |
34 | [VX_DATA] = 0x2c, |
35 | [VX_STATUS] = 0x30, |
36 | [VX_LOFREQ] = 0x34, |
37 | [VX_HIFREQ] = 0x38, |
38 | [VX_CSUER] = 0x3c, |
39 | [VX_SELMIC] = 0x40, |
40 | [VX_COMPOT] = 0x44, // Write: POTENTIOMETER ; Read: COMPRESSION LEVEL activate |
41 | [VX_SCOMPR] = 0x48, // Read: COMPRESSION THRESHOLD activate |
42 | [VX_GLIMIT] = 0x4c, // Read: LEVEL LIMITATION activate |
43 | [VX_INTCSR] = 0x4c, // VX_INTCSR_REGISTER_OFFSET |
44 | [VX_CNTRL] = 0x50, // VX_CNTRL_REGISTER_OFFSET |
45 | [VX_GPIOC] = 0x54, // VX_GPIOC (new with PLX9030) |
46 | }; |
47 | |
48 | static const int vx2_reg_index[VX_REG_MAX] = { |
49 | [VX_ICR] = 1, |
50 | [VX_CVR] = 1, |
51 | [VX_ISR] = 1, |
52 | [VX_IVR] = 1, |
53 | [VX_RXH] = 1, |
54 | [VX_RXM] = 1, |
55 | [VX_RXL] = 1, |
56 | [VX_DMA] = 1, |
57 | [VX_CDSP] = 1, |
58 | [VX_CFG] = 1, |
59 | [VX_RUER] = 1, |
60 | [VX_DATA] = 1, |
61 | [VX_STATUS] = 1, |
62 | [VX_LOFREQ] = 1, |
63 | [VX_HIFREQ] = 1, |
64 | [VX_CSUER] = 1, |
65 | [VX_SELMIC] = 1, |
66 | [VX_COMPOT] = 1, |
67 | [VX_SCOMPR] = 1, |
68 | [VX_GLIMIT] = 1, |
69 | [VX_INTCSR] = 0, /* on the PLX */ |
70 | [VX_CNTRL] = 0, /* on the PLX */ |
71 | [VX_GPIOC] = 0, /* on the PLX */ |
72 | }; |
73 | |
74 | static inline unsigned long vx2_reg_addr(struct vx_core *_chip, int reg) |
75 | { |
76 | struct snd_vx222 *chip = to_vx222(_chip); |
77 | return chip->port[vx2_reg_index[reg]] + vx2_reg_offset[reg]; |
78 | } |
79 | |
80 | /** |
81 | * vx2_inb - read a byte from the register |
82 | * @chip: VX core instance |
83 | * @offset: register enum |
84 | */ |
85 | static unsigned char vx2_inb(struct vx_core *chip, int offset) |
86 | { |
87 | return inb(port: vx2_reg_addr(chip: chip, reg: offset)); |
88 | } |
89 | |
90 | /** |
91 | * vx2_outb - write a byte on the register |
92 | * @chip: VX core instance |
93 | * @offset: the register offset |
94 | * @val: the value to write |
95 | */ |
96 | static void vx2_outb(struct vx_core *chip, int offset, unsigned char val) |
97 | { |
98 | outb(value: val, port: vx2_reg_addr(chip: chip, reg: offset)); |
99 | /* |
100 | dev_dbg(chip->card->dev, "outb: %x -> %x\n", val, vx2_reg_addr(chip, offset)); |
101 | */ |
102 | } |
103 | |
104 | /** |
105 | * vx2_inl - read a 32bit word from the register |
106 | * @chip: VX core instance |
107 | * @offset: register enum |
108 | */ |
109 | static unsigned int vx2_inl(struct vx_core *chip, int offset) |
110 | { |
111 | return inl(port: vx2_reg_addr(chip: chip, reg: offset)); |
112 | } |
113 | |
114 | /** |
115 | * vx2_outl - write a 32bit word on the register |
116 | * @chip: VX core instance |
117 | * @offset: the register enum |
118 | * @val: the value to write |
119 | */ |
120 | static void vx2_outl(struct vx_core *chip, int offset, unsigned int val) |
121 | { |
122 | /* |
123 | dev_dbg(chip->card->dev, "outl: %x -> %x\n", val, vx2_reg_addr(chip, offset)); |
124 | */ |
125 | outl(value: val, port: vx2_reg_addr(chip: chip, reg: offset)); |
126 | } |
127 | |
128 | /* |
129 | * redefine macros to call directly |
130 | */ |
131 | #undef vx_inb |
132 | #define vx_inb(chip,reg) vx2_inb((struct vx_core*)(chip), VX_##reg) |
133 | #undef vx_outb |
134 | #define vx_outb(chip,reg,val) vx2_outb((struct vx_core*)(chip), VX_##reg, val) |
135 | #undef vx_inl |
136 | #define vx_inl(chip,reg) vx2_inl((struct vx_core*)(chip), VX_##reg) |
137 | #undef vx_outl |
138 | #define vx_outl(chip,reg,val) vx2_outl((struct vx_core*)(chip), VX_##reg, val) |
139 | |
140 | |
141 | /* |
142 | * vx_reset_dsp - reset the DSP |
143 | */ |
144 | |
145 | #define XX_DSP_RESET_WAIT_TIME 2 /* ms */ |
146 | |
147 | static void vx2_reset_dsp(struct vx_core *_chip) |
148 | { |
149 | struct snd_vx222 *chip = to_vx222(_chip); |
150 | |
151 | /* set the reset dsp bit to 0 */ |
152 | vx_outl(chip, CDSP, chip->regCDSP & ~VX_CDSP_DSP_RESET_MASK); |
153 | |
154 | mdelay(XX_DSP_RESET_WAIT_TIME); |
155 | |
156 | chip->regCDSP |= VX_CDSP_DSP_RESET_MASK; |
157 | /* set the reset dsp bit to 1 */ |
158 | vx_outl(chip, CDSP, chip->regCDSP); |
159 | } |
160 | |
161 | |
162 | static int vx2_test_xilinx(struct vx_core *_chip) |
163 | { |
164 | struct snd_vx222 *chip = to_vx222(_chip); |
165 | unsigned int data; |
166 | |
167 | dev_dbg(_chip->card->dev, "testing xilinx...\n" ); |
168 | /* This test uses several write/read sequences on TEST0 and TEST1 bits |
169 | * to figure out whever or not the xilinx was correctly loaded |
170 | */ |
171 | |
172 | /* We write 1 on CDSP.TEST0. We should get 0 on STATUS.TEST0. */ |
173 | vx_outl(chip, CDSP, chip->regCDSP | VX_CDSP_TEST0_MASK); |
174 | vx_inl(chip, ISR); |
175 | data = vx_inl(chip, STATUS); |
176 | if ((data & VX_STATUS_VAL_TEST0_MASK) == VX_STATUS_VAL_TEST0_MASK) { |
177 | dev_dbg(_chip->card->dev, "bad!\n" ); |
178 | return -ENODEV; |
179 | } |
180 | |
181 | /* We write 0 on CDSP.TEST0. We should get 1 on STATUS.TEST0. */ |
182 | vx_outl(chip, CDSP, chip->regCDSP & ~VX_CDSP_TEST0_MASK); |
183 | vx_inl(chip, ISR); |
184 | data = vx_inl(chip, STATUS); |
185 | if (! (data & VX_STATUS_VAL_TEST0_MASK)) { |
186 | dev_dbg(_chip->card->dev, "bad! #2\n" ); |
187 | return -ENODEV; |
188 | } |
189 | |
190 | if (_chip->type == VX_TYPE_BOARD) { |
191 | /* not implemented on VX_2_BOARDS */ |
192 | /* We write 1 on CDSP.TEST1. We should get 0 on STATUS.TEST1. */ |
193 | vx_outl(chip, CDSP, chip->regCDSP | VX_CDSP_TEST1_MASK); |
194 | vx_inl(chip, ISR); |
195 | data = vx_inl(chip, STATUS); |
196 | if ((data & VX_STATUS_VAL_TEST1_MASK) == VX_STATUS_VAL_TEST1_MASK) { |
197 | dev_dbg(_chip->card->dev, "bad! #3\n" ); |
198 | return -ENODEV; |
199 | } |
200 | |
201 | /* We write 0 on CDSP.TEST1. We should get 1 on STATUS.TEST1. */ |
202 | vx_outl(chip, CDSP, chip->regCDSP & ~VX_CDSP_TEST1_MASK); |
203 | vx_inl(chip, ISR); |
204 | data = vx_inl(chip, STATUS); |
205 | if (! (data & VX_STATUS_VAL_TEST1_MASK)) { |
206 | dev_dbg(_chip->card->dev, "bad! #4\n" ); |
207 | return -ENODEV; |
208 | } |
209 | } |
210 | dev_dbg(_chip->card->dev, "ok, xilinx fine.\n" ); |
211 | return 0; |
212 | } |
213 | |
214 | |
215 | /** |
216 | * vx2_setup_pseudo_dma - set up the pseudo dma read/write mode. |
217 | * @chip: VX core instance |
218 | * @do_write: 0 = read, 1 = set up for DMA write |
219 | */ |
220 | static void vx2_setup_pseudo_dma(struct vx_core *chip, int do_write) |
221 | { |
222 | /* Interrupt mode and HREQ pin enabled for host transmit data transfers |
223 | * (in case of the use of the pseudo-dma facility). |
224 | */ |
225 | vx_outl(chip, ICR, do_write ? ICR_TREQ : ICR_RREQ); |
226 | |
227 | /* Reset the pseudo-dma register (in case of the use of the |
228 | * pseudo-dma facility). |
229 | */ |
230 | vx_outl(chip, RESET_DMA, 0); |
231 | } |
232 | |
233 | /* |
234 | * vx_release_pseudo_dma - disable the pseudo-DMA mode |
235 | */ |
236 | static inline void vx2_release_pseudo_dma(struct vx_core *chip) |
237 | { |
238 | /* HREQ pin disabled. */ |
239 | vx_outl(chip, ICR, 0); |
240 | } |
241 | |
242 | |
243 | |
244 | /* pseudo-dma write */ |
245 | static void vx2_dma_write(struct vx_core *chip, struct snd_pcm_runtime *runtime, |
246 | struct vx_pipe *pipe, int count) |
247 | { |
248 | unsigned long port = vx2_reg_addr(chip: chip, reg: VX_DMA); |
249 | int offset = pipe->hw_ptr; |
250 | u32 *addr = (u32 *)(runtime->dma_area + offset); |
251 | |
252 | if (snd_BUG_ON(count % 4)) |
253 | return; |
254 | |
255 | vx2_setup_pseudo_dma(chip, do_write: 1); |
256 | |
257 | /* Transfer using pseudo-dma. |
258 | */ |
259 | if (offset + count >= pipe->buffer_bytes) { |
260 | int length = pipe->buffer_bytes - offset; |
261 | count -= length; |
262 | length >>= 2; /* in 32bit words */ |
263 | /* Transfer using pseudo-dma. */ |
264 | for (; length > 0; length--) { |
265 | outl(value: *addr, port); |
266 | addr++; |
267 | } |
268 | addr = (u32 *)runtime->dma_area; |
269 | pipe->hw_ptr = 0; |
270 | } |
271 | pipe->hw_ptr += count; |
272 | count >>= 2; /* in 32bit words */ |
273 | /* Transfer using pseudo-dma. */ |
274 | for (; count > 0; count--) { |
275 | outl(value: *addr, port); |
276 | addr++; |
277 | } |
278 | |
279 | vx2_release_pseudo_dma(chip); |
280 | } |
281 | |
282 | |
283 | /* pseudo dma read */ |
284 | static void vx2_dma_read(struct vx_core *chip, struct snd_pcm_runtime *runtime, |
285 | struct vx_pipe *pipe, int count) |
286 | { |
287 | int offset = pipe->hw_ptr; |
288 | u32 *addr = (u32 *)(runtime->dma_area + offset); |
289 | unsigned long port = vx2_reg_addr(chip: chip, reg: VX_DMA); |
290 | |
291 | if (snd_BUG_ON(count % 4)) |
292 | return; |
293 | |
294 | vx2_setup_pseudo_dma(chip, do_write: 0); |
295 | /* Transfer using pseudo-dma. |
296 | */ |
297 | if (offset + count >= pipe->buffer_bytes) { |
298 | int length = pipe->buffer_bytes - offset; |
299 | count -= length; |
300 | length >>= 2; /* in 32bit words */ |
301 | /* Transfer using pseudo-dma. */ |
302 | for (; length > 0; length--) |
303 | *addr++ = inl(port); |
304 | addr = (u32 *)runtime->dma_area; |
305 | pipe->hw_ptr = 0; |
306 | } |
307 | pipe->hw_ptr += count; |
308 | count >>= 2; /* in 32bit words */ |
309 | /* Transfer using pseudo-dma. */ |
310 | for (; count > 0; count--) |
311 | *addr++ = inl(port); |
312 | |
313 | vx2_release_pseudo_dma(chip); |
314 | } |
315 | |
316 | #define VX_XILINX_RESET_MASK 0x40000000 |
317 | #define VX_USERBIT0_MASK 0x00000004 |
318 | #define VX_USERBIT1_MASK 0x00000020 |
319 | #define VX_CNTRL_REGISTER_VALUE 0x00172012 |
320 | |
321 | /* |
322 | * transfer counts bits to PLX |
323 | */ |
324 | static int put_xilinx_data(struct vx_core *chip, unsigned int port, unsigned int counts, unsigned char data) |
325 | { |
326 | unsigned int i; |
327 | |
328 | for (i = 0; i < counts; i++) { |
329 | unsigned int val; |
330 | |
331 | /* set the clock bit to 0. */ |
332 | val = VX_CNTRL_REGISTER_VALUE & ~VX_USERBIT0_MASK; |
333 | vx2_outl(chip, offset: port, val); |
334 | vx2_inl(chip, offset: port); |
335 | udelay(1); |
336 | |
337 | if (data & (1 << i)) |
338 | val |= VX_USERBIT1_MASK; |
339 | else |
340 | val &= ~VX_USERBIT1_MASK; |
341 | vx2_outl(chip, offset: port, val); |
342 | vx2_inl(chip, offset: port); |
343 | |
344 | /* set the clock bit to 1. */ |
345 | val |= VX_USERBIT0_MASK; |
346 | vx2_outl(chip, offset: port, val); |
347 | vx2_inl(chip, offset: port); |
348 | udelay(1); |
349 | } |
350 | return 0; |
351 | } |
352 | |
353 | /* |
354 | * load the xilinx image |
355 | */ |
356 | static int vx2_load_xilinx_binary(struct vx_core *chip, const struct firmware *xilinx) |
357 | { |
358 | unsigned int i; |
359 | unsigned int port; |
360 | const unsigned char *image; |
361 | |
362 | /* XILINX reset (wait at least 1 millisecond between reset on and off). */ |
363 | vx_outl(chip, CNTRL, VX_CNTRL_REGISTER_VALUE | VX_XILINX_RESET_MASK); |
364 | vx_inl(chip, CNTRL); |
365 | msleep(msecs: 10); |
366 | vx_outl(chip, CNTRL, VX_CNTRL_REGISTER_VALUE); |
367 | vx_inl(chip, CNTRL); |
368 | msleep(msecs: 10); |
369 | |
370 | if (chip->type == VX_TYPE_BOARD) |
371 | port = VX_CNTRL; |
372 | else |
373 | port = VX_GPIOC; /* VX222 V2 and VX222_MIC_BOARD with new PLX9030 use this register */ |
374 | |
375 | image = xilinx->data; |
376 | for (i = 0; i < xilinx->size; i++, image++) { |
377 | if (put_xilinx_data(chip, port, counts: 8, data: *image) < 0) |
378 | return -EINVAL; |
379 | /* don't take too much time in this loop... */ |
380 | cond_resched(); |
381 | } |
382 | put_xilinx_data(chip, port, counts: 4, data: 0xff); /* end signature */ |
383 | |
384 | msleep(msecs: 200); |
385 | |
386 | /* test after loading (is buggy with VX222) */ |
387 | if (chip->type != VX_TYPE_BOARD) { |
388 | /* Test if load successful: test bit 8 of register GPIOC (VX222: use CNTRL) ! */ |
389 | i = vx_inl(chip, GPIOC); |
390 | if (i & 0x0100) |
391 | return 0; |
392 | dev_err(chip->card->dev, |
393 | "xilinx test failed after load, GPIOC=0x%x\n" , i); |
394 | return -EINVAL; |
395 | } |
396 | |
397 | return 0; |
398 | } |
399 | |
400 | |
401 | /* |
402 | * load the boot/dsp images |
403 | */ |
404 | static int vx2_load_dsp(struct vx_core *vx, int index, const struct firmware *dsp) |
405 | { |
406 | int err; |
407 | |
408 | switch (index) { |
409 | case 1: |
410 | /* xilinx image */ |
411 | err = vx2_load_xilinx_binary(chip: vx, xilinx: dsp); |
412 | if (err < 0) |
413 | return err; |
414 | err = vx2_test_xilinx(chip: vx); |
415 | if (err < 0) |
416 | return err; |
417 | return 0; |
418 | case 2: |
419 | /* DSP boot */ |
420 | return snd_vx_dsp_boot(chip: vx, dsp); |
421 | case 3: |
422 | /* DSP image */ |
423 | return snd_vx_dsp_load(chip: vx, dsp); |
424 | default: |
425 | snd_BUG(); |
426 | return -EINVAL; |
427 | } |
428 | } |
429 | |
430 | |
431 | /* |
432 | * vx_test_and_ack - test and acknowledge interrupt |
433 | * |
434 | * called from irq hander, too |
435 | * |
436 | * spinlock held! |
437 | */ |
438 | static int vx2_test_and_ack(struct vx_core *chip) |
439 | { |
440 | /* not booted yet? */ |
441 | if (! (chip->chip_status & VX_STAT_XILINX_LOADED)) |
442 | return -ENXIO; |
443 | |
444 | if (! (vx_inl(chip, STATUS) & VX_STATUS_MEMIRQ_MASK)) |
445 | return -EIO; |
446 | |
447 | /* ok, interrupts generated, now ack it */ |
448 | /* set ACQUIT bit up and down */ |
449 | vx_outl(chip, STATUS, 0); |
450 | /* useless read just to spend some time and maintain |
451 | * the ACQUIT signal up for a while ( a bus cycle ) |
452 | */ |
453 | vx_inl(chip, STATUS); |
454 | /* ack */ |
455 | vx_outl(chip, STATUS, VX_STATUS_MEMIRQ_MASK); |
456 | /* useless read just to spend some time and maintain |
457 | * the ACQUIT signal up for a while ( a bus cycle ) */ |
458 | vx_inl(chip, STATUS); |
459 | /* clear */ |
460 | vx_outl(chip, STATUS, 0); |
461 | |
462 | return 0; |
463 | } |
464 | |
465 | |
466 | /* |
467 | * vx_validate_irq - enable/disable IRQ |
468 | */ |
469 | static void vx2_validate_irq(struct vx_core *_chip, int enable) |
470 | { |
471 | struct snd_vx222 *chip = to_vx222(_chip); |
472 | |
473 | /* Set the interrupt enable bit to 1 in CDSP register */ |
474 | if (enable) { |
475 | /* Set the PCI interrupt enable bit to 1.*/ |
476 | vx_outl(chip, INTCSR, VX_INTCSR_VALUE|VX_PCI_INTERRUPT_MASK); |
477 | chip->regCDSP |= VX_CDSP_VALID_IRQ_MASK; |
478 | } else { |
479 | /* Set the PCI interrupt enable bit to 0. */ |
480 | vx_outl(chip, INTCSR, VX_INTCSR_VALUE&~VX_PCI_INTERRUPT_MASK); |
481 | chip->regCDSP &= ~VX_CDSP_VALID_IRQ_MASK; |
482 | } |
483 | vx_outl(chip, CDSP, chip->regCDSP); |
484 | } |
485 | |
486 | |
487 | /* |
488 | * write an AKM codec data (24bit) |
489 | */ |
490 | static void vx2_write_codec_reg(struct vx_core *chip, unsigned int data) |
491 | { |
492 | unsigned int i; |
493 | |
494 | vx_inl(chip, HIFREQ); |
495 | |
496 | /* We have to send 24 bits (3 x 8 bits). Start with most signif. Bit */ |
497 | for (i = 0; i < 24; i++, data <<= 1) |
498 | vx_outl(chip, DATA, ((data & 0x800000) ? VX_DATA_CODEC_MASK : 0)); |
499 | /* Terminate access to codec registers */ |
500 | vx_inl(chip, RUER); |
501 | } |
502 | |
503 | |
504 | #define AKM_CODEC_POWER_CONTROL_CMD 0xA007 |
505 | #define AKM_CODEC_RESET_ON_CMD 0xA100 |
506 | #define AKM_CODEC_RESET_OFF_CMD 0xA103 |
507 | #define AKM_CODEC_CLOCK_FORMAT_CMD 0xA240 |
508 | #define AKM_CODEC_MUTE_CMD 0xA38D |
509 | #define AKM_CODEC_UNMUTE_CMD 0xA30D |
510 | #define AKM_CODEC_LEFT_LEVEL_CMD 0xA400 |
511 | #define AKM_CODEC_RIGHT_LEVEL_CMD 0xA500 |
512 | |
513 | static const u8 vx2_akm_gains_lut[VX2_AKM_LEVEL_MAX+1] = { |
514 | 0x7f, // [000] = +0.000 dB -> AKM(0x7f) = +0.000 dB error(+0.000 dB) |
515 | 0x7d, // [001] = -0.500 dB -> AKM(0x7d) = -0.572 dB error(-0.072 dB) |
516 | 0x7c, // [002] = -1.000 dB -> AKM(0x7c) = -0.873 dB error(+0.127 dB) |
517 | 0x7a, // [003] = -1.500 dB -> AKM(0x7a) = -1.508 dB error(-0.008 dB) |
518 | 0x79, // [004] = -2.000 dB -> AKM(0x79) = -1.844 dB error(+0.156 dB) |
519 | 0x77, // [005] = -2.500 dB -> AKM(0x77) = -2.557 dB error(-0.057 dB) |
520 | 0x76, // [006] = -3.000 dB -> AKM(0x76) = -2.937 dB error(+0.063 dB) |
521 | 0x75, // [007] = -3.500 dB -> AKM(0x75) = -3.334 dB error(+0.166 dB) |
522 | 0x73, // [008] = -4.000 dB -> AKM(0x73) = -4.188 dB error(-0.188 dB) |
523 | 0x72, // [009] = -4.500 dB -> AKM(0x72) = -4.648 dB error(-0.148 dB) |
524 | 0x71, // [010] = -5.000 dB -> AKM(0x71) = -5.134 dB error(-0.134 dB) |
525 | 0x70, // [011] = -5.500 dB -> AKM(0x70) = -5.649 dB error(-0.149 dB) |
526 | 0x6f, // [012] = -6.000 dB -> AKM(0x6f) = -6.056 dB error(-0.056 dB) |
527 | 0x6d, // [013] = -6.500 dB -> AKM(0x6d) = -6.631 dB error(-0.131 dB) |
528 | 0x6c, // [014] = -7.000 dB -> AKM(0x6c) = -6.933 dB error(+0.067 dB) |
529 | 0x6a, // [015] = -7.500 dB -> AKM(0x6a) = -7.571 dB error(-0.071 dB) |
530 | 0x69, // [016] = -8.000 dB -> AKM(0x69) = -7.909 dB error(+0.091 dB) |
531 | 0x67, // [017] = -8.500 dB -> AKM(0x67) = -8.626 dB error(-0.126 dB) |
532 | 0x66, // [018] = -9.000 dB -> AKM(0x66) = -9.008 dB error(-0.008 dB) |
533 | 0x65, // [019] = -9.500 dB -> AKM(0x65) = -9.407 dB error(+0.093 dB) |
534 | 0x64, // [020] = -10.000 dB -> AKM(0x64) = -9.826 dB error(+0.174 dB) |
535 | 0x62, // [021] = -10.500 dB -> AKM(0x62) = -10.730 dB error(-0.230 dB) |
536 | 0x61, // [022] = -11.000 dB -> AKM(0x61) = -11.219 dB error(-0.219 dB) |
537 | 0x60, // [023] = -11.500 dB -> AKM(0x60) = -11.738 dB error(-0.238 dB) |
538 | 0x5f, // [024] = -12.000 dB -> AKM(0x5f) = -12.149 dB error(-0.149 dB) |
539 | 0x5e, // [025] = -12.500 dB -> AKM(0x5e) = -12.434 dB error(+0.066 dB) |
540 | 0x5c, // [026] = -13.000 dB -> AKM(0x5c) = -13.033 dB error(-0.033 dB) |
541 | 0x5b, // [027] = -13.500 dB -> AKM(0x5b) = -13.350 dB error(+0.150 dB) |
542 | 0x59, // [028] = -14.000 dB -> AKM(0x59) = -14.018 dB error(-0.018 dB) |
543 | 0x58, // [029] = -14.500 dB -> AKM(0x58) = -14.373 dB error(+0.127 dB) |
544 | 0x56, // [030] = -15.000 dB -> AKM(0x56) = -15.130 dB error(-0.130 dB) |
545 | 0x55, // [031] = -15.500 dB -> AKM(0x55) = -15.534 dB error(-0.034 dB) |
546 | 0x54, // [032] = -16.000 dB -> AKM(0x54) = -15.958 dB error(+0.042 dB) |
547 | 0x53, // [033] = -16.500 dB -> AKM(0x53) = -16.404 dB error(+0.096 dB) |
548 | 0x52, // [034] = -17.000 dB -> AKM(0x52) = -16.874 dB error(+0.126 dB) |
549 | 0x51, // [035] = -17.500 dB -> AKM(0x51) = -17.371 dB error(+0.129 dB) |
550 | 0x50, // [036] = -18.000 dB -> AKM(0x50) = -17.898 dB error(+0.102 dB) |
551 | 0x4e, // [037] = -18.500 dB -> AKM(0x4e) = -18.605 dB error(-0.105 dB) |
552 | 0x4d, // [038] = -19.000 dB -> AKM(0x4d) = -18.905 dB error(+0.095 dB) |
553 | 0x4b, // [039] = -19.500 dB -> AKM(0x4b) = -19.538 dB error(-0.038 dB) |
554 | 0x4a, // [040] = -20.000 dB -> AKM(0x4a) = -19.872 dB error(+0.128 dB) |
555 | 0x48, // [041] = -20.500 dB -> AKM(0x48) = -20.583 dB error(-0.083 dB) |
556 | 0x47, // [042] = -21.000 dB -> AKM(0x47) = -20.961 dB error(+0.039 dB) |
557 | 0x46, // [043] = -21.500 dB -> AKM(0x46) = -21.356 dB error(+0.144 dB) |
558 | 0x44, // [044] = -22.000 dB -> AKM(0x44) = -22.206 dB error(-0.206 dB) |
559 | 0x43, // [045] = -22.500 dB -> AKM(0x43) = -22.664 dB error(-0.164 dB) |
560 | 0x42, // [046] = -23.000 dB -> AKM(0x42) = -23.147 dB error(-0.147 dB) |
561 | 0x41, // [047] = -23.500 dB -> AKM(0x41) = -23.659 dB error(-0.159 dB) |
562 | 0x40, // [048] = -24.000 dB -> AKM(0x40) = -24.203 dB error(-0.203 dB) |
563 | 0x3f, // [049] = -24.500 dB -> AKM(0x3f) = -24.635 dB error(-0.135 dB) |
564 | 0x3e, // [050] = -25.000 dB -> AKM(0x3e) = -24.935 dB error(+0.065 dB) |
565 | 0x3c, // [051] = -25.500 dB -> AKM(0x3c) = -25.569 dB error(-0.069 dB) |
566 | 0x3b, // [052] = -26.000 dB -> AKM(0x3b) = -25.904 dB error(+0.096 dB) |
567 | 0x39, // [053] = -26.500 dB -> AKM(0x39) = -26.615 dB error(-0.115 dB) |
568 | 0x38, // [054] = -27.000 dB -> AKM(0x38) = -26.994 dB error(+0.006 dB) |
569 | 0x37, // [055] = -27.500 dB -> AKM(0x37) = -27.390 dB error(+0.110 dB) |
570 | 0x36, // [056] = -28.000 dB -> AKM(0x36) = -27.804 dB error(+0.196 dB) |
571 | 0x34, // [057] = -28.500 dB -> AKM(0x34) = -28.699 dB error(-0.199 dB) |
572 | 0x33, // [058] = -29.000 dB -> AKM(0x33) = -29.183 dB error(-0.183 dB) |
573 | 0x32, // [059] = -29.500 dB -> AKM(0x32) = -29.696 dB error(-0.196 dB) |
574 | 0x31, // [060] = -30.000 dB -> AKM(0x31) = -30.241 dB error(-0.241 dB) |
575 | 0x31, // [061] = -30.500 dB -> AKM(0x31) = -30.241 dB error(+0.259 dB) |
576 | 0x30, // [062] = -31.000 dB -> AKM(0x30) = -30.823 dB error(+0.177 dB) |
577 | 0x2e, // [063] = -31.500 dB -> AKM(0x2e) = -31.610 dB error(-0.110 dB) |
578 | 0x2d, // [064] = -32.000 dB -> AKM(0x2d) = -31.945 dB error(+0.055 dB) |
579 | 0x2b, // [065] = -32.500 dB -> AKM(0x2b) = -32.659 dB error(-0.159 dB) |
580 | 0x2a, // [066] = -33.000 dB -> AKM(0x2a) = -33.038 dB error(-0.038 dB) |
581 | 0x29, // [067] = -33.500 dB -> AKM(0x29) = -33.435 dB error(+0.065 dB) |
582 | 0x28, // [068] = -34.000 dB -> AKM(0x28) = -33.852 dB error(+0.148 dB) |
583 | 0x27, // [069] = -34.500 dB -> AKM(0x27) = -34.289 dB error(+0.211 dB) |
584 | 0x25, // [070] = -35.000 dB -> AKM(0x25) = -35.235 dB error(-0.235 dB) |
585 | 0x24, // [071] = -35.500 dB -> AKM(0x24) = -35.750 dB error(-0.250 dB) |
586 | 0x24, // [072] = -36.000 dB -> AKM(0x24) = -35.750 dB error(+0.250 dB) |
587 | 0x23, // [073] = -36.500 dB -> AKM(0x23) = -36.297 dB error(+0.203 dB) |
588 | 0x22, // [074] = -37.000 dB -> AKM(0x22) = -36.881 dB error(+0.119 dB) |
589 | 0x21, // [075] = -37.500 dB -> AKM(0x21) = -37.508 dB error(-0.008 dB) |
590 | 0x20, // [076] = -38.000 dB -> AKM(0x20) = -38.183 dB error(-0.183 dB) |
591 | 0x1f, // [077] = -38.500 dB -> AKM(0x1f) = -38.726 dB error(-0.226 dB) |
592 | 0x1e, // [078] = -39.000 dB -> AKM(0x1e) = -39.108 dB error(-0.108 dB) |
593 | 0x1d, // [079] = -39.500 dB -> AKM(0x1d) = -39.507 dB error(-0.007 dB) |
594 | 0x1c, // [080] = -40.000 dB -> AKM(0x1c) = -39.926 dB error(+0.074 dB) |
595 | 0x1b, // [081] = -40.500 dB -> AKM(0x1b) = -40.366 dB error(+0.134 dB) |
596 | 0x1a, // [082] = -41.000 dB -> AKM(0x1a) = -40.829 dB error(+0.171 dB) |
597 | 0x19, // [083] = -41.500 dB -> AKM(0x19) = -41.318 dB error(+0.182 dB) |
598 | 0x18, // [084] = -42.000 dB -> AKM(0x18) = -41.837 dB error(+0.163 dB) |
599 | 0x17, // [085] = -42.500 dB -> AKM(0x17) = -42.389 dB error(+0.111 dB) |
600 | 0x16, // [086] = -43.000 dB -> AKM(0x16) = -42.978 dB error(+0.022 dB) |
601 | 0x15, // [087] = -43.500 dB -> AKM(0x15) = -43.610 dB error(-0.110 dB) |
602 | 0x14, // [088] = -44.000 dB -> AKM(0x14) = -44.291 dB error(-0.291 dB) |
603 | 0x14, // [089] = -44.500 dB -> AKM(0x14) = -44.291 dB error(+0.209 dB) |
604 | 0x13, // [090] = -45.000 dB -> AKM(0x13) = -45.031 dB error(-0.031 dB) |
605 | 0x12, // [091] = -45.500 dB -> AKM(0x12) = -45.840 dB error(-0.340 dB) |
606 | 0x12, // [092] = -46.000 dB -> AKM(0x12) = -45.840 dB error(+0.160 dB) |
607 | 0x11, // [093] = -46.500 dB -> AKM(0x11) = -46.731 dB error(-0.231 dB) |
608 | 0x11, // [094] = -47.000 dB -> AKM(0x11) = -46.731 dB error(+0.269 dB) |
609 | 0x10, // [095] = -47.500 dB -> AKM(0x10) = -47.725 dB error(-0.225 dB) |
610 | 0x10, // [096] = -48.000 dB -> AKM(0x10) = -47.725 dB error(+0.275 dB) |
611 | 0x0f, // [097] = -48.500 dB -> AKM(0x0f) = -48.553 dB error(-0.053 dB) |
612 | 0x0e, // [098] = -49.000 dB -> AKM(0x0e) = -49.152 dB error(-0.152 dB) |
613 | 0x0d, // [099] = -49.500 dB -> AKM(0x0d) = -49.796 dB error(-0.296 dB) |
614 | 0x0d, // [100] = -50.000 dB -> AKM(0x0d) = -49.796 dB error(+0.204 dB) |
615 | 0x0c, // [101] = -50.500 dB -> AKM(0x0c) = -50.491 dB error(+0.009 dB) |
616 | 0x0b, // [102] = -51.000 dB -> AKM(0x0b) = -51.247 dB error(-0.247 dB) |
617 | 0x0b, // [103] = -51.500 dB -> AKM(0x0b) = -51.247 dB error(+0.253 dB) |
618 | 0x0a, // [104] = -52.000 dB -> AKM(0x0a) = -52.075 dB error(-0.075 dB) |
619 | 0x0a, // [105] = -52.500 dB -> AKM(0x0a) = -52.075 dB error(+0.425 dB) |
620 | 0x09, // [106] = -53.000 dB -> AKM(0x09) = -52.990 dB error(+0.010 dB) |
621 | 0x09, // [107] = -53.500 dB -> AKM(0x09) = -52.990 dB error(+0.510 dB) |
622 | 0x08, // [108] = -54.000 dB -> AKM(0x08) = -54.013 dB error(-0.013 dB) |
623 | 0x08, // [109] = -54.500 dB -> AKM(0x08) = -54.013 dB error(+0.487 dB) |
624 | 0x07, // [110] = -55.000 dB -> AKM(0x07) = -55.173 dB error(-0.173 dB) |
625 | 0x07, // [111] = -55.500 dB -> AKM(0x07) = -55.173 dB error(+0.327 dB) |
626 | 0x06, // [112] = -56.000 dB -> AKM(0x06) = -56.512 dB error(-0.512 dB) |
627 | 0x06, // [113] = -56.500 dB -> AKM(0x06) = -56.512 dB error(-0.012 dB) |
628 | 0x06, // [114] = -57.000 dB -> AKM(0x06) = -56.512 dB error(+0.488 dB) |
629 | 0x05, // [115] = -57.500 dB -> AKM(0x05) = -58.095 dB error(-0.595 dB) |
630 | 0x05, // [116] = -58.000 dB -> AKM(0x05) = -58.095 dB error(-0.095 dB) |
631 | 0x05, // [117] = -58.500 dB -> AKM(0x05) = -58.095 dB error(+0.405 dB) |
632 | 0x05, // [118] = -59.000 dB -> AKM(0x05) = -58.095 dB error(+0.905 dB) |
633 | 0x04, // [119] = -59.500 dB -> AKM(0x04) = -60.034 dB error(-0.534 dB) |
634 | 0x04, // [120] = -60.000 dB -> AKM(0x04) = -60.034 dB error(-0.034 dB) |
635 | 0x04, // [121] = -60.500 dB -> AKM(0x04) = -60.034 dB error(+0.466 dB) |
636 | 0x04, // [122] = -61.000 dB -> AKM(0x04) = -60.034 dB error(+0.966 dB) |
637 | 0x03, // [123] = -61.500 dB -> AKM(0x03) = -62.532 dB error(-1.032 dB) |
638 | 0x03, // [124] = -62.000 dB -> AKM(0x03) = -62.532 dB error(-0.532 dB) |
639 | 0x03, // [125] = -62.500 dB -> AKM(0x03) = -62.532 dB error(-0.032 dB) |
640 | 0x03, // [126] = -63.000 dB -> AKM(0x03) = -62.532 dB error(+0.468 dB) |
641 | 0x03, // [127] = -63.500 dB -> AKM(0x03) = -62.532 dB error(+0.968 dB) |
642 | 0x03, // [128] = -64.000 dB -> AKM(0x03) = -62.532 dB error(+1.468 dB) |
643 | 0x02, // [129] = -64.500 dB -> AKM(0x02) = -66.054 dB error(-1.554 dB) |
644 | 0x02, // [130] = -65.000 dB -> AKM(0x02) = -66.054 dB error(-1.054 dB) |
645 | 0x02, // [131] = -65.500 dB -> AKM(0x02) = -66.054 dB error(-0.554 dB) |
646 | 0x02, // [132] = -66.000 dB -> AKM(0x02) = -66.054 dB error(-0.054 dB) |
647 | 0x02, // [133] = -66.500 dB -> AKM(0x02) = -66.054 dB error(+0.446 dB) |
648 | 0x02, // [134] = -67.000 dB -> AKM(0x02) = -66.054 dB error(+0.946 dB) |
649 | 0x02, // [135] = -67.500 dB -> AKM(0x02) = -66.054 dB error(+1.446 dB) |
650 | 0x02, // [136] = -68.000 dB -> AKM(0x02) = -66.054 dB error(+1.946 dB) |
651 | 0x02, // [137] = -68.500 dB -> AKM(0x02) = -66.054 dB error(+2.446 dB) |
652 | 0x02, // [138] = -69.000 dB -> AKM(0x02) = -66.054 dB error(+2.946 dB) |
653 | 0x01, // [139] = -69.500 dB -> AKM(0x01) = -72.075 dB error(-2.575 dB) |
654 | 0x01, // [140] = -70.000 dB -> AKM(0x01) = -72.075 dB error(-2.075 dB) |
655 | 0x01, // [141] = -70.500 dB -> AKM(0x01) = -72.075 dB error(-1.575 dB) |
656 | 0x01, // [142] = -71.000 dB -> AKM(0x01) = -72.075 dB error(-1.075 dB) |
657 | 0x01, // [143] = -71.500 dB -> AKM(0x01) = -72.075 dB error(-0.575 dB) |
658 | 0x01, // [144] = -72.000 dB -> AKM(0x01) = -72.075 dB error(-0.075 dB) |
659 | 0x01, // [145] = -72.500 dB -> AKM(0x01) = -72.075 dB error(+0.425 dB) |
660 | 0x01, // [146] = -73.000 dB -> AKM(0x01) = -72.075 dB error(+0.925 dB) |
661 | 0x00}; // [147] = -73.500 dB -> AKM(0x00) = mute error(+infini) |
662 | |
663 | /* |
664 | * pseudo-codec write entry |
665 | */ |
666 | static void vx2_write_akm(struct vx_core *chip, int reg, unsigned int data) |
667 | { |
668 | unsigned int val; |
669 | |
670 | if (reg == XX_CODEC_DAC_CONTROL_REGISTER) { |
671 | vx2_write_codec_reg(chip, data: data ? AKM_CODEC_MUTE_CMD : AKM_CODEC_UNMUTE_CMD); |
672 | return; |
673 | } |
674 | |
675 | /* `data' is a value between 0x0 and VX2_AKM_LEVEL_MAX = 0x093, in the case of the AKM codecs, we need |
676 | a look up table, as there is no linear matching between the driver codec values |
677 | and the real dBu value |
678 | */ |
679 | if (snd_BUG_ON(data >= sizeof(vx2_akm_gains_lut))) |
680 | return; |
681 | |
682 | switch (reg) { |
683 | case XX_CODEC_LEVEL_LEFT_REGISTER: |
684 | val = AKM_CODEC_LEFT_LEVEL_CMD; |
685 | break; |
686 | case XX_CODEC_LEVEL_RIGHT_REGISTER: |
687 | val = AKM_CODEC_RIGHT_LEVEL_CMD; |
688 | break; |
689 | default: |
690 | snd_BUG(); |
691 | return; |
692 | } |
693 | val |= vx2_akm_gains_lut[data]; |
694 | |
695 | vx2_write_codec_reg(chip, data: val); |
696 | } |
697 | |
698 | |
699 | /* |
700 | * write codec bit for old VX222 board |
701 | */ |
702 | static void vx2_old_write_codec_bit(struct vx_core *chip, int codec, unsigned int data) |
703 | { |
704 | int i; |
705 | |
706 | /* activate access to codec registers */ |
707 | vx_inl(chip, HIFREQ); |
708 | |
709 | for (i = 0; i < 24; i++, data <<= 1) |
710 | vx_outl(chip, DATA, ((data & 0x800000) ? VX_DATA_CODEC_MASK : 0)); |
711 | |
712 | /* Terminate access to codec registers */ |
713 | vx_inl(chip, RUER); |
714 | } |
715 | |
716 | |
717 | /* |
718 | * reset codec bit |
719 | */ |
720 | static void vx2_reset_codec(struct vx_core *_chip) |
721 | { |
722 | struct snd_vx222 *chip = to_vx222(_chip); |
723 | |
724 | /* Set the reset CODEC bit to 0. */ |
725 | vx_outl(chip, CDSP, chip->regCDSP &~ VX_CDSP_CODEC_RESET_MASK); |
726 | vx_inl(chip, CDSP); |
727 | msleep(msecs: 10); |
728 | /* Set the reset CODEC bit to 1. */ |
729 | chip->regCDSP |= VX_CDSP_CODEC_RESET_MASK; |
730 | vx_outl(chip, CDSP, chip->regCDSP); |
731 | vx_inl(chip, CDSP); |
732 | if (_chip->type == VX_TYPE_BOARD) { |
733 | msleep(msecs: 1); |
734 | return; |
735 | } |
736 | |
737 | msleep(msecs: 5); /* additionnel wait time for AKM's */ |
738 | |
739 | vx2_write_codec_reg(chip: _chip, AKM_CODEC_POWER_CONTROL_CMD); /* DAC power up, ADC power up, Vref power down */ |
740 | |
741 | vx2_write_codec_reg(chip: _chip, AKM_CODEC_CLOCK_FORMAT_CMD); /* default */ |
742 | vx2_write_codec_reg(chip: _chip, AKM_CODEC_MUTE_CMD); /* Mute = ON ,Deemphasis = OFF */ |
743 | vx2_write_codec_reg(chip: _chip, AKM_CODEC_RESET_OFF_CMD); /* DAC and ADC normal operation */ |
744 | |
745 | if (_chip->type == VX_TYPE_MIC) { |
746 | /* set up the micro input selector */ |
747 | chip->regSELMIC = MICRO_SELECT_INPUT_NORM | |
748 | MICRO_SELECT_PREAMPLI_G_0 | |
749 | MICRO_SELECT_NOISE_T_52DB; |
750 | |
751 | /* reset phantom power supply */ |
752 | chip->regSELMIC &= ~MICRO_SELECT_PHANTOM_ALIM; |
753 | |
754 | vx_outl(_chip, SELMIC, chip->regSELMIC); |
755 | } |
756 | } |
757 | |
758 | |
759 | /* |
760 | * change the audio source |
761 | */ |
762 | static void vx2_change_audio_source(struct vx_core *_chip, int src) |
763 | { |
764 | struct snd_vx222 *chip = to_vx222(_chip); |
765 | |
766 | switch (src) { |
767 | case VX_AUDIO_SRC_DIGITAL: |
768 | chip->regCFG |= VX_CFG_DATAIN_SEL_MASK; |
769 | break; |
770 | default: |
771 | chip->regCFG &= ~VX_CFG_DATAIN_SEL_MASK; |
772 | break; |
773 | } |
774 | vx_outl(chip, CFG, chip->regCFG); |
775 | } |
776 | |
777 | |
778 | /* |
779 | * set the clock source |
780 | */ |
781 | static void vx2_set_clock_source(struct vx_core *_chip, int source) |
782 | { |
783 | struct snd_vx222 *chip = to_vx222(_chip); |
784 | |
785 | if (source == INTERNAL_QUARTZ) |
786 | chip->regCFG &= ~VX_CFG_CLOCKIN_SEL_MASK; |
787 | else |
788 | chip->regCFG |= VX_CFG_CLOCKIN_SEL_MASK; |
789 | vx_outl(chip, CFG, chip->regCFG); |
790 | } |
791 | |
792 | /* |
793 | * reset the board |
794 | */ |
795 | static void vx2_reset_board(struct vx_core *_chip, int cold_reset) |
796 | { |
797 | struct snd_vx222 *chip = to_vx222(_chip); |
798 | |
799 | /* initialize the register values */ |
800 | chip->regCDSP = VX_CDSP_CODEC_RESET_MASK | VX_CDSP_DSP_RESET_MASK ; |
801 | chip->regCFG = 0; |
802 | } |
803 | |
804 | |
805 | |
806 | /* |
807 | * input level controls for VX222 Mic |
808 | */ |
809 | |
810 | /* Micro level is specified to be adjustable from -96dB to 63 dB (board coded 0x00 ... 318), |
811 | * 318 = 210 + 36 + 36 + 36 (210 = +9dB variable) (3 * 36 = 3 steps of 18dB pre ampli) |
812 | * as we will mute if less than -110dB, so let's simply use line input coded levels and add constant offset ! |
813 | */ |
814 | #define V2_MICRO_LEVEL_RANGE (318 - 255) |
815 | |
816 | static void vx2_set_input_level(struct snd_vx222 *chip) |
817 | { |
818 | int i, miclevel, preamp; |
819 | unsigned int data; |
820 | |
821 | miclevel = chip->mic_level; |
822 | miclevel += V2_MICRO_LEVEL_RANGE; /* add 318 - 0xff */ |
823 | preamp = 0; |
824 | while (miclevel > 210) { /* limitation to +9dB of 3310 real gain */ |
825 | preamp++; /* raise pre ampli + 18dB */ |
826 | miclevel -= (18 * 2); /* lower level 18 dB (*2 because of 0.5 dB steps !) */ |
827 | } |
828 | if (snd_BUG_ON(preamp >= 4)) |
829 | return; |
830 | |
831 | /* set pre-amp level */ |
832 | chip->regSELMIC &= ~MICRO_SELECT_PREAMPLI_MASK; |
833 | chip->regSELMIC |= (preamp << MICRO_SELECT_PREAMPLI_OFFSET) & MICRO_SELECT_PREAMPLI_MASK; |
834 | vx_outl(chip, SELMIC, chip->regSELMIC); |
835 | |
836 | data = (unsigned int)miclevel << 16 | |
837 | (unsigned int)chip->input_level[1] << 8 | |
838 | (unsigned int)chip->input_level[0]; |
839 | vx_inl(chip, DATA); /* Activate input level programming */ |
840 | |
841 | /* We have to send 32 bits (4 x 8 bits) */ |
842 | for (i = 0; i < 32; i++, data <<= 1) |
843 | vx_outl(chip, DATA, ((data & 0x80000000) ? VX_DATA_CODEC_MASK : 0)); |
844 | |
845 | vx_inl(chip, RUER); /* Terminate input level programming */ |
846 | } |
847 | |
848 | |
849 | #define MIC_LEVEL_MAX 0xff |
850 | |
851 | static const DECLARE_TLV_DB_SCALE(db_scale_mic, -6450, 50, 0); |
852 | |
853 | /* |
854 | * controls API for input levels |
855 | */ |
856 | |
857 | /* input levels */ |
858 | static int vx_input_level_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo) |
859 | { |
860 | uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; |
861 | uinfo->count = 2; |
862 | uinfo->value.integer.min = 0; |
863 | uinfo->value.integer.max = MIC_LEVEL_MAX; |
864 | return 0; |
865 | } |
866 | |
867 | static int vx_input_level_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) |
868 | { |
869 | struct vx_core *_chip = snd_kcontrol_chip(kcontrol); |
870 | struct snd_vx222 *chip = to_vx222(_chip); |
871 | mutex_lock(&_chip->mixer_mutex); |
872 | ucontrol->value.integer.value[0] = chip->input_level[0]; |
873 | ucontrol->value.integer.value[1] = chip->input_level[1]; |
874 | mutex_unlock(lock: &_chip->mixer_mutex); |
875 | return 0; |
876 | } |
877 | |
878 | static int vx_input_level_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) |
879 | { |
880 | struct vx_core *_chip = snd_kcontrol_chip(kcontrol); |
881 | struct snd_vx222 *chip = to_vx222(_chip); |
882 | if (ucontrol->value.integer.value[0] < 0 || |
883 | ucontrol->value.integer.value[0] > MIC_LEVEL_MAX) |
884 | return -EINVAL; |
885 | if (ucontrol->value.integer.value[1] < 0 || |
886 | ucontrol->value.integer.value[1] > MIC_LEVEL_MAX) |
887 | return -EINVAL; |
888 | mutex_lock(&_chip->mixer_mutex); |
889 | if (chip->input_level[0] != ucontrol->value.integer.value[0] || |
890 | chip->input_level[1] != ucontrol->value.integer.value[1]) { |
891 | chip->input_level[0] = ucontrol->value.integer.value[0]; |
892 | chip->input_level[1] = ucontrol->value.integer.value[1]; |
893 | vx2_set_input_level(chip); |
894 | mutex_unlock(lock: &_chip->mixer_mutex); |
895 | return 1; |
896 | } |
897 | mutex_unlock(lock: &_chip->mixer_mutex); |
898 | return 0; |
899 | } |
900 | |
901 | /* mic level */ |
902 | static int vx_mic_level_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo) |
903 | { |
904 | uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; |
905 | uinfo->count = 1; |
906 | uinfo->value.integer.min = 0; |
907 | uinfo->value.integer.max = MIC_LEVEL_MAX; |
908 | return 0; |
909 | } |
910 | |
911 | static int vx_mic_level_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) |
912 | { |
913 | struct vx_core *_chip = snd_kcontrol_chip(kcontrol); |
914 | struct snd_vx222 *chip = to_vx222(_chip); |
915 | ucontrol->value.integer.value[0] = chip->mic_level; |
916 | return 0; |
917 | } |
918 | |
919 | static int vx_mic_level_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) |
920 | { |
921 | struct vx_core *_chip = snd_kcontrol_chip(kcontrol); |
922 | struct snd_vx222 *chip = to_vx222(_chip); |
923 | if (ucontrol->value.integer.value[0] < 0 || |
924 | ucontrol->value.integer.value[0] > MIC_LEVEL_MAX) |
925 | return -EINVAL; |
926 | mutex_lock(&_chip->mixer_mutex); |
927 | if (chip->mic_level != ucontrol->value.integer.value[0]) { |
928 | chip->mic_level = ucontrol->value.integer.value[0]; |
929 | vx2_set_input_level(chip); |
930 | mutex_unlock(lock: &_chip->mixer_mutex); |
931 | return 1; |
932 | } |
933 | mutex_unlock(lock: &_chip->mixer_mutex); |
934 | return 0; |
935 | } |
936 | |
937 | static const struct snd_kcontrol_new vx_control_input_level = { |
938 | .iface = SNDRV_CTL_ELEM_IFACE_MIXER, |
939 | .access = (SNDRV_CTL_ELEM_ACCESS_READWRITE | |
940 | SNDRV_CTL_ELEM_ACCESS_TLV_READ), |
941 | .name = "Capture Volume" , |
942 | .info = vx_input_level_info, |
943 | .get = vx_input_level_get, |
944 | .put = vx_input_level_put, |
945 | .tlv = { .p = db_scale_mic }, |
946 | }; |
947 | |
948 | static const struct snd_kcontrol_new vx_control_mic_level = { |
949 | .iface = SNDRV_CTL_ELEM_IFACE_MIXER, |
950 | .access = (SNDRV_CTL_ELEM_ACCESS_READWRITE | |
951 | SNDRV_CTL_ELEM_ACCESS_TLV_READ), |
952 | .name = "Mic Capture Volume" , |
953 | .info = vx_mic_level_info, |
954 | .get = vx_mic_level_get, |
955 | .put = vx_mic_level_put, |
956 | .tlv = { .p = db_scale_mic }, |
957 | }; |
958 | |
959 | /* |
960 | * FIXME: compressor/limiter implementation is missing yet... |
961 | */ |
962 | |
963 | static int vx2_add_mic_controls(struct vx_core *_chip) |
964 | { |
965 | struct snd_vx222 *chip = to_vx222(_chip); |
966 | int err; |
967 | |
968 | if (_chip->type != VX_TYPE_MIC) |
969 | return 0; |
970 | |
971 | /* mute input levels */ |
972 | chip->input_level[0] = chip->input_level[1] = 0; |
973 | chip->mic_level = 0; |
974 | vx2_set_input_level(chip); |
975 | |
976 | /* controls */ |
977 | err = snd_ctl_add(card: _chip->card, kcontrol: snd_ctl_new1(kcontrolnew: &vx_control_input_level, private_data: chip)); |
978 | if (err < 0) |
979 | return err; |
980 | err = snd_ctl_add(card: _chip->card, kcontrol: snd_ctl_new1(kcontrolnew: &vx_control_mic_level, private_data: chip)); |
981 | if (err < 0) |
982 | return err; |
983 | |
984 | return 0; |
985 | } |
986 | |
987 | |
988 | /* |
989 | * callbacks |
990 | */ |
991 | const struct snd_vx_ops vx222_ops = { |
992 | .in8 = vx2_inb, |
993 | .in32 = vx2_inl, |
994 | .out8 = vx2_outb, |
995 | .out32 = vx2_outl, |
996 | .test_and_ack = vx2_test_and_ack, |
997 | .validate_irq = vx2_validate_irq, |
998 | .akm_write = vx2_write_akm, |
999 | .reset_codec = vx2_reset_codec, |
1000 | .change_audio_source = vx2_change_audio_source, |
1001 | .set_clock_source = vx2_set_clock_source, |
1002 | .load_dsp = vx2_load_dsp, |
1003 | .reset_dsp = vx2_reset_dsp, |
1004 | .reset_board = vx2_reset_board, |
1005 | .dma_write = vx2_dma_write, |
1006 | .dma_read = vx2_dma_read, |
1007 | .add_controls = vx2_add_mic_controls, |
1008 | }; |
1009 | |
1010 | /* for old VX222 board */ |
1011 | const struct snd_vx_ops vx222_old_ops = { |
1012 | .in8 = vx2_inb, |
1013 | .in32 = vx2_inl, |
1014 | .out8 = vx2_outb, |
1015 | .out32 = vx2_outl, |
1016 | .test_and_ack = vx2_test_and_ack, |
1017 | .validate_irq = vx2_validate_irq, |
1018 | .write_codec = vx2_old_write_codec_bit, |
1019 | .reset_codec = vx2_reset_codec, |
1020 | .change_audio_source = vx2_change_audio_source, |
1021 | .set_clock_source = vx2_set_clock_source, |
1022 | .load_dsp = vx2_load_dsp, |
1023 | .reset_dsp = vx2_reset_dsp, |
1024 | .reset_board = vx2_reset_board, |
1025 | .dma_write = vx2_dma_write, |
1026 | .dma_read = vx2_dma_read, |
1027 | }; |
1028 | |
1029 | |