1 | // SPDX-License-Identifier: GPL-2.0-only |
2 | /* |
3 | * Driver for Atmel I2S controller |
4 | * |
5 | * Copyright (C) 2015 Atmel Corporation |
6 | * |
7 | * Author: Cyrille Pitchen <cyrille.pitchen@atmel.com> |
8 | */ |
9 | |
10 | #include <linux/init.h> |
11 | #include <linux/module.h> |
12 | #include <linux/device.h> |
13 | #include <linux/slab.h> |
14 | #include <linux/delay.h> |
15 | #include <linux/io.h> |
16 | #include <linux/clk.h> |
17 | #include <linux/mfd/syscon.h> |
18 | |
19 | #include <sound/core.h> |
20 | #include <sound/pcm.h> |
21 | #include <sound/pcm_params.h> |
22 | #include <sound/initval.h> |
23 | #include <sound/soc.h> |
24 | #include <sound/dmaengine_pcm.h> |
25 | |
26 | #define ATMEL_I2SC_MAX_TDM_CHANNELS 8 |
27 | |
28 | /* |
29 | * ---- I2S Controller Register map ---- |
30 | */ |
31 | #define ATMEL_I2SC_CR 0x0000 /* Control Register */ |
32 | #define ATMEL_I2SC_MR 0x0004 /* Mode Register */ |
33 | #define ATMEL_I2SC_SR 0x0008 /* Status Register */ |
34 | #define ATMEL_I2SC_SCR 0x000c /* Status Clear Register */ |
35 | #define ATMEL_I2SC_SSR 0x0010 /* Status Set Register */ |
36 | #define ATMEL_I2SC_IER 0x0014 /* Interrupt Enable Register */ |
37 | #define ATMEL_I2SC_IDR 0x0018 /* Interrupt Disable Register */ |
38 | #define ATMEL_I2SC_IMR 0x001c /* Interrupt Mask Register */ |
39 | #define ATMEL_I2SC_RHR 0x0020 /* Receiver Holding Register */ |
40 | #define ATMEL_I2SC_THR 0x0024 /* Transmitter Holding Register */ |
41 | #define ATMEL_I2SC_VERSION 0x0028 /* Version Register */ |
42 | |
43 | /* |
44 | * ---- Control Register (Write-only) ---- |
45 | */ |
46 | #define ATMEL_I2SC_CR_RXEN BIT(0) /* Receiver Enable */ |
47 | #define ATMEL_I2SC_CR_RXDIS BIT(1) /* Receiver Disable */ |
48 | #define ATMEL_I2SC_CR_CKEN BIT(2) /* Clock Enable */ |
49 | #define ATMEL_I2SC_CR_CKDIS BIT(3) /* Clock Disable */ |
50 | #define ATMEL_I2SC_CR_TXEN BIT(4) /* Transmitter Enable */ |
51 | #define ATMEL_I2SC_CR_TXDIS BIT(5) /* Transmitter Disable */ |
52 | #define ATMEL_I2SC_CR_SWRST BIT(7) /* Software Reset */ |
53 | |
54 | /* |
55 | * ---- Mode Register (Read/Write) ---- |
56 | */ |
57 | #define ATMEL_I2SC_MR_MODE_MASK GENMASK(0, 0) |
58 | #define ATMEL_I2SC_MR_MODE_SLAVE (0 << 0) |
59 | #define ATMEL_I2SC_MR_MODE_MASTER (1 << 0) |
60 | |
61 | #define ATMEL_I2SC_MR_DATALENGTH_MASK GENMASK(4, 2) |
62 | #define ATMEL_I2SC_MR_DATALENGTH_32_BITS (0 << 2) |
63 | #define ATMEL_I2SC_MR_DATALENGTH_24_BITS (1 << 2) |
64 | #define ATMEL_I2SC_MR_DATALENGTH_20_BITS (2 << 2) |
65 | #define ATMEL_I2SC_MR_DATALENGTH_18_BITS (3 << 2) |
66 | #define ATMEL_I2SC_MR_DATALENGTH_16_BITS (4 << 2) |
67 | #define ATMEL_I2SC_MR_DATALENGTH_16_BITS_COMPACT (5 << 2) |
68 | #define ATMEL_I2SC_MR_DATALENGTH_8_BITS (6 << 2) |
69 | #define ATMEL_I2SC_MR_DATALENGTH_8_BITS_COMPACT (7 << 2) |
70 | |
71 | #define ATMEL_I2SC_MR_FORMAT_MASK GENMASK(7, 6) |
72 | #define ATMEL_I2SC_MR_FORMAT_I2S (0 << 6) |
73 | #define ATMEL_I2SC_MR_FORMAT_LJ (1 << 6) /* Left Justified */ |
74 | #define ATMEL_I2SC_MR_FORMAT_TDM (2 << 6) |
75 | #define ATMEL_I2SC_MR_FORMAT_TDMLJ (3 << 6) |
76 | |
77 | /* Left audio samples duplicated to right audio channel */ |
78 | #define ATMEL_I2SC_MR_RXMONO BIT(8) |
79 | |
80 | /* Receiver uses one DMA channel ... */ |
81 | #define ATMEL_I2SC_MR_RXDMA_MASK GENMASK(9, 9) |
82 | #define ATMEL_I2SC_MR_RXDMA_SINGLE (0 << 9) /* for all audio channels */ |
83 | #define ATMEL_I2SC_MR_RXDMA_MULTIPLE (1 << 9) /* per audio channel */ |
84 | |
85 | /* I2SDO output of I2SC is internally connected to I2SDI input */ |
86 | #define ATMEL_I2SC_MR_RXLOOP BIT(10) |
87 | |
88 | /* Left audio samples duplicated to right audio channel */ |
89 | #define ATMEL_I2SC_MR_TXMONO BIT(12) |
90 | |
91 | /* Transmitter uses one DMA channel ... */ |
92 | #define ATMEL_I2SC_MR_TXDMA_MASK GENMASK(13, 13) |
93 | #define ATMEL_I2SC_MR_TXDMA_SINGLE (0 << 13) /* for all audio channels */ |
94 | #define ATMEL_I2SC_MR_TXDME_MULTIPLE (1 << 13) /* per audio channel */ |
95 | |
96 | /* x sample transmitted when underrun */ |
97 | #define ATMEL_I2SC_MR_TXSAME_MASK GENMASK(14, 14) |
98 | #define ATMEL_I2SC_MR_TXSAME_ZERO (0 << 14) /* Zero sample */ |
99 | #define ATMEL_I2SC_MR_TXSAME_PREVIOUS (1 << 14) /* Previous sample */ |
100 | |
101 | /* Audio Clock to I2SC Master Clock ratio */ |
102 | #define ATMEL_I2SC_MR_IMCKDIV_MASK GENMASK(21, 16) |
103 | #define ATMEL_I2SC_MR_IMCKDIV(div) \ |
104 | (((div) << 16) & ATMEL_I2SC_MR_IMCKDIV_MASK) |
105 | |
106 | /* Master Clock to fs ratio */ |
107 | #define ATMEL_I2SC_MR_IMCKFS_MASK GENMASK(29, 24) |
108 | #define ATMEL_I2SC_MR_IMCKFS(fs) \ |
109 | (((fs) << 24) & ATMEL_I2SC_MR_IMCKFS_MASK) |
110 | |
111 | /* Master Clock mode */ |
112 | #define ATMEL_I2SC_MR_IMCKMODE_MASK GENMASK(30, 30) |
113 | /* 0: No master clock generated (selected clock drives I2SCK pin) */ |
114 | #define ATMEL_I2SC_MR_IMCKMODE_I2SCK (0 << 30) |
115 | /* 1: master clock generated (internally generated clock drives I2SMCK pin) */ |
116 | #define ATMEL_I2SC_MR_IMCKMODE_I2SMCK (1 << 30) |
117 | |
118 | /* Slot Width */ |
119 | /* 0: slot is 32 bits wide for DATALENGTH = 18/20/24 bits. */ |
120 | /* 1: slot is 24 bits wide for DATALENGTH = 18/20/24 bits. */ |
121 | #define ATMEL_I2SC_MR_IWS BIT(31) |
122 | |
123 | /* |
124 | * ---- Status Registers ---- |
125 | */ |
126 | #define ATMEL_I2SC_SR_RXEN BIT(0) /* Receiver Enabled */ |
127 | #define ATMEL_I2SC_SR_RXRDY BIT(1) /* Receive Ready */ |
128 | #define ATMEL_I2SC_SR_RXOR BIT(2) /* Receive Overrun */ |
129 | |
130 | #define ATMEL_I2SC_SR_TXEN BIT(4) /* Transmitter Enabled */ |
131 | #define ATMEL_I2SC_SR_TXRDY BIT(5) /* Transmit Ready */ |
132 | #define ATMEL_I2SC_SR_TXUR BIT(6) /* Transmit Underrun */ |
133 | |
134 | /* Receive Overrun Channel */ |
135 | #define ATMEL_I2SC_SR_RXORCH_MASK GENMASK(15, 8) |
136 | #define ATMEL_I2SC_SR_RXORCH(ch) (1 << (((ch) & 0x7) + 8)) |
137 | |
138 | /* Transmit Underrun Channel */ |
139 | #define ATMEL_I2SC_SR_TXURCH_MASK GENMASK(27, 20) |
140 | #define ATMEL_I2SC_SR_TXURCH(ch) (1 << (((ch) & 0x7) + 20)) |
141 | |
142 | /* |
143 | * ---- Interrupt Enable/Disable/Mask Registers ---- |
144 | */ |
145 | #define ATMEL_I2SC_INT_RXRDY ATMEL_I2SC_SR_RXRDY |
146 | #define ATMEL_I2SC_INT_RXOR ATMEL_I2SC_SR_RXOR |
147 | #define ATMEL_I2SC_INT_TXRDY ATMEL_I2SC_SR_TXRDY |
148 | #define ATMEL_I2SC_INT_TXUR ATMEL_I2SC_SR_TXUR |
149 | |
150 | static const struct regmap_config atmel_i2s_regmap_config = { |
151 | .reg_bits = 32, |
152 | .reg_stride = 4, |
153 | .val_bits = 32, |
154 | .max_register = ATMEL_I2SC_VERSION, |
155 | }; |
156 | |
157 | struct atmel_i2s_gck_param { |
158 | int fs; |
159 | unsigned long mck; |
160 | int imckdiv; |
161 | int imckfs; |
162 | }; |
163 | |
164 | #define I2S_MCK_12M288 12288000UL |
165 | #define I2S_MCK_11M2896 11289600UL |
166 | #define I2S_MCK_6M144 6144000UL |
167 | |
168 | /* mck = (32 * (imckfs+1) / (imckdiv+1)) * fs */ |
169 | static const struct atmel_i2s_gck_param gck_params[] = { |
170 | /* mck = 6.144Mhz */ |
171 | { 8000, I2S_MCK_6M144, 1, 47}, /* mck = 768 fs */ |
172 | |
173 | /* mck = 12.288MHz */ |
174 | { 16000, I2S_MCK_12M288, 1, 47}, /* mck = 768 fs */ |
175 | { 24000, I2S_MCK_12M288, 3, 63}, /* mck = 512 fs */ |
176 | { 32000, I2S_MCK_12M288, 3, 47}, /* mck = 384 fs */ |
177 | { 48000, I2S_MCK_12M288, 7, 63}, /* mck = 256 fs */ |
178 | { 64000, I2S_MCK_12M288, 7, 47}, /* mck = 192 fs */ |
179 | { 96000, I2S_MCK_12M288, 7, 31}, /* mck = 128 fs */ |
180 | {192000, I2S_MCK_12M288, 7, 15}, /* mck = 64 fs */ |
181 | |
182 | /* mck = 11.2896MHz */ |
183 | { 11025, I2S_MCK_11M2896, 1, 63}, /* mck = 1024 fs */ |
184 | { 22050, I2S_MCK_11M2896, 3, 63}, /* mck = 512 fs */ |
185 | { 44100, I2S_MCK_11M2896, 7, 63}, /* mck = 256 fs */ |
186 | { 88200, I2S_MCK_11M2896, 7, 31}, /* mck = 128 fs */ |
187 | {176400, I2S_MCK_11M2896, 7, 15}, /* mck = 64 fs */ |
188 | }; |
189 | |
190 | struct atmel_i2s_dev; |
191 | |
192 | struct atmel_i2s_caps { |
193 | int (*mck_init)(struct atmel_i2s_dev *, struct device_node *np); |
194 | }; |
195 | |
196 | struct atmel_i2s_dev { |
197 | struct device *dev; |
198 | struct regmap *regmap; |
199 | struct clk *pclk; |
200 | struct clk *gclk; |
201 | struct snd_dmaengine_dai_dma_data playback; |
202 | struct snd_dmaengine_dai_dma_data capture; |
203 | unsigned int fmt; |
204 | const struct atmel_i2s_gck_param *gck_param; |
205 | const struct atmel_i2s_caps *caps; |
206 | int clk_use_no; |
207 | }; |
208 | |
209 | static irqreturn_t atmel_i2s_interrupt(int irq, void *dev_id) |
210 | { |
211 | struct atmel_i2s_dev *dev = dev_id; |
212 | unsigned int sr, imr, pending, ch, mask; |
213 | irqreturn_t ret = IRQ_NONE; |
214 | |
215 | regmap_read(map: dev->regmap, ATMEL_I2SC_SR, val: &sr); |
216 | regmap_read(map: dev->regmap, ATMEL_I2SC_IMR, val: &imr); |
217 | pending = sr & imr; |
218 | |
219 | if (!pending) |
220 | return IRQ_NONE; |
221 | |
222 | if (pending & ATMEL_I2SC_INT_RXOR) { |
223 | mask = ATMEL_I2SC_SR_RXOR; |
224 | |
225 | for (ch = 0; ch < ATMEL_I2SC_MAX_TDM_CHANNELS; ++ch) { |
226 | if (sr & ATMEL_I2SC_SR_RXORCH(ch)) { |
227 | mask |= ATMEL_I2SC_SR_RXORCH(ch); |
228 | dev_err(dev->dev, |
229 | "RX overrun on channel %d\n" , ch); |
230 | } |
231 | } |
232 | regmap_write(map: dev->regmap, ATMEL_I2SC_SCR, val: mask); |
233 | ret = IRQ_HANDLED; |
234 | } |
235 | |
236 | if (pending & ATMEL_I2SC_INT_TXUR) { |
237 | mask = ATMEL_I2SC_SR_TXUR; |
238 | |
239 | for (ch = 0; ch < ATMEL_I2SC_MAX_TDM_CHANNELS; ++ch) { |
240 | if (sr & ATMEL_I2SC_SR_TXURCH(ch)) { |
241 | mask |= ATMEL_I2SC_SR_TXURCH(ch); |
242 | dev_err(dev->dev, |
243 | "TX underrun on channel %d\n" , ch); |
244 | } |
245 | } |
246 | regmap_write(map: dev->regmap, ATMEL_I2SC_SCR, val: mask); |
247 | ret = IRQ_HANDLED; |
248 | } |
249 | |
250 | return ret; |
251 | } |
252 | |
253 | #define ATMEL_I2S_RATES SNDRV_PCM_RATE_8000_192000 |
254 | |
255 | #define ATMEL_I2S_FORMATS (SNDRV_PCM_FMTBIT_S8 | \ |
256 | SNDRV_PCM_FMTBIT_S16_LE | \ |
257 | SNDRV_PCM_FMTBIT_S18_3LE | \ |
258 | SNDRV_PCM_FMTBIT_S20_3LE | \ |
259 | SNDRV_PCM_FMTBIT_S24_3LE | \ |
260 | SNDRV_PCM_FMTBIT_S24_LE | \ |
261 | SNDRV_PCM_FMTBIT_S32_LE) |
262 | |
263 | static int atmel_i2s_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt) |
264 | { |
265 | struct atmel_i2s_dev *dev = snd_soc_dai_get_drvdata(dai); |
266 | |
267 | dev->fmt = fmt; |
268 | return 0; |
269 | } |
270 | |
271 | static int atmel_i2s_prepare(struct snd_pcm_substream *substream, |
272 | struct snd_soc_dai *dai) |
273 | { |
274 | struct atmel_i2s_dev *dev = snd_soc_dai_get_drvdata(dai); |
275 | bool is_playback = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK); |
276 | unsigned int rhr, sr = 0; |
277 | |
278 | if (is_playback) { |
279 | regmap_read(map: dev->regmap, ATMEL_I2SC_SR, val: &sr); |
280 | if (sr & ATMEL_I2SC_SR_RXRDY) { |
281 | /* |
282 | * The RX Ready flag should not be set. However if here, |
283 | * we flush (read) the Receive Holding Register to start |
284 | * from a clean state. |
285 | */ |
286 | dev_dbg(dev->dev, "RXRDY is set\n" ); |
287 | regmap_read(map: dev->regmap, ATMEL_I2SC_RHR, val: &rhr); |
288 | } |
289 | } |
290 | |
291 | return 0; |
292 | } |
293 | |
294 | static int atmel_i2s_get_gck_param(struct atmel_i2s_dev *dev, int fs) |
295 | { |
296 | int i, best; |
297 | |
298 | if (!dev->gclk) { |
299 | dev_err(dev->dev, "cannot generate the I2S Master Clock\n" ); |
300 | return -EINVAL; |
301 | } |
302 | |
303 | /* |
304 | * Find the best possible settings to generate the I2S Master Clock |
305 | * from the PLL Audio. |
306 | */ |
307 | dev->gck_param = NULL; |
308 | best = INT_MAX; |
309 | for (i = 0; i < ARRAY_SIZE(gck_params); ++i) { |
310 | const struct atmel_i2s_gck_param *gck_param = &gck_params[i]; |
311 | int val = abs(fs - gck_param->fs); |
312 | |
313 | if (val < best) { |
314 | best = val; |
315 | dev->gck_param = gck_param; |
316 | } |
317 | } |
318 | |
319 | return 0; |
320 | } |
321 | |
322 | static int atmel_i2s_hw_params(struct snd_pcm_substream *substream, |
323 | struct snd_pcm_hw_params *params, |
324 | struct snd_soc_dai *dai) |
325 | { |
326 | struct atmel_i2s_dev *dev = snd_soc_dai_get_drvdata(dai); |
327 | bool is_playback = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK); |
328 | unsigned int mr = 0, mr_mask; |
329 | int ret; |
330 | |
331 | mr_mask = ATMEL_I2SC_MR_FORMAT_MASK | ATMEL_I2SC_MR_MODE_MASK | |
332 | ATMEL_I2SC_MR_DATALENGTH_MASK; |
333 | if (is_playback) |
334 | mr_mask |= ATMEL_I2SC_MR_TXMONO; |
335 | else |
336 | mr_mask |= ATMEL_I2SC_MR_RXMONO; |
337 | |
338 | switch (dev->fmt & SND_SOC_DAIFMT_FORMAT_MASK) { |
339 | case SND_SOC_DAIFMT_I2S: |
340 | mr |= ATMEL_I2SC_MR_FORMAT_I2S; |
341 | break; |
342 | |
343 | default: |
344 | dev_err(dev->dev, "unsupported bus format\n" ); |
345 | return -EINVAL; |
346 | } |
347 | |
348 | switch (dev->fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) { |
349 | case SND_SOC_DAIFMT_BP_FP: |
350 | /* codec is slave, so cpu is master */ |
351 | mr |= ATMEL_I2SC_MR_MODE_MASTER; |
352 | ret = atmel_i2s_get_gck_param(dev, fs: params_rate(p: params)); |
353 | if (ret) |
354 | return ret; |
355 | break; |
356 | |
357 | case SND_SOC_DAIFMT_BC_FC: |
358 | /* codec is master, so cpu is slave */ |
359 | mr |= ATMEL_I2SC_MR_MODE_SLAVE; |
360 | dev->gck_param = NULL; |
361 | break; |
362 | |
363 | default: |
364 | dev_err(dev->dev, "unsupported master/slave mode\n" ); |
365 | return -EINVAL; |
366 | } |
367 | |
368 | switch (params_channels(p: params)) { |
369 | case 1: |
370 | if (is_playback) |
371 | mr |= ATMEL_I2SC_MR_TXMONO; |
372 | else |
373 | mr |= ATMEL_I2SC_MR_RXMONO; |
374 | break; |
375 | case 2: |
376 | break; |
377 | default: |
378 | dev_err(dev->dev, "unsupported number of audio channels\n" ); |
379 | return -EINVAL; |
380 | } |
381 | |
382 | switch (params_format(p: params)) { |
383 | case SNDRV_PCM_FORMAT_S8: |
384 | mr |= ATMEL_I2SC_MR_DATALENGTH_8_BITS; |
385 | break; |
386 | |
387 | case SNDRV_PCM_FORMAT_S16_LE: |
388 | mr |= ATMEL_I2SC_MR_DATALENGTH_16_BITS; |
389 | break; |
390 | |
391 | case SNDRV_PCM_FORMAT_S18_3LE: |
392 | mr |= ATMEL_I2SC_MR_DATALENGTH_18_BITS | ATMEL_I2SC_MR_IWS; |
393 | break; |
394 | |
395 | case SNDRV_PCM_FORMAT_S20_3LE: |
396 | mr |= ATMEL_I2SC_MR_DATALENGTH_20_BITS | ATMEL_I2SC_MR_IWS; |
397 | break; |
398 | |
399 | case SNDRV_PCM_FORMAT_S24_3LE: |
400 | mr |= ATMEL_I2SC_MR_DATALENGTH_24_BITS | ATMEL_I2SC_MR_IWS; |
401 | break; |
402 | |
403 | case SNDRV_PCM_FORMAT_S24_LE: |
404 | mr |= ATMEL_I2SC_MR_DATALENGTH_24_BITS; |
405 | break; |
406 | |
407 | case SNDRV_PCM_FORMAT_S32_LE: |
408 | mr |= ATMEL_I2SC_MR_DATALENGTH_32_BITS; |
409 | break; |
410 | |
411 | default: |
412 | dev_err(dev->dev, "unsupported size/endianness for audio samples\n" ); |
413 | return -EINVAL; |
414 | } |
415 | |
416 | return regmap_update_bits(map: dev->regmap, ATMEL_I2SC_MR, mask: mr_mask, val: mr); |
417 | } |
418 | |
419 | static int atmel_i2s_switch_mck_generator(struct atmel_i2s_dev *dev, |
420 | bool enabled) |
421 | { |
422 | unsigned int mr, mr_mask; |
423 | unsigned long gclk_rate; |
424 | int ret; |
425 | |
426 | mr = 0; |
427 | mr_mask = (ATMEL_I2SC_MR_IMCKDIV_MASK | |
428 | ATMEL_I2SC_MR_IMCKFS_MASK | |
429 | ATMEL_I2SC_MR_IMCKMODE_MASK); |
430 | |
431 | if (!enabled) { |
432 | /* Disable the I2S Master Clock generator. */ |
433 | ret = regmap_write(map: dev->regmap, ATMEL_I2SC_CR, |
434 | ATMEL_I2SC_CR_CKDIS); |
435 | if (ret) |
436 | return ret; |
437 | |
438 | /* Reset the I2S Master Clock generator settings. */ |
439 | ret = regmap_update_bits(map: dev->regmap, ATMEL_I2SC_MR, |
440 | mask: mr_mask, val: mr); |
441 | if (ret) |
442 | return ret; |
443 | |
444 | /* Disable/unprepare the PMC generated clock. */ |
445 | clk_disable_unprepare(clk: dev->gclk); |
446 | |
447 | return 0; |
448 | } |
449 | |
450 | if (!dev->gck_param) |
451 | return -EINVAL; |
452 | |
453 | gclk_rate = dev->gck_param->mck * (dev->gck_param->imckdiv + 1); |
454 | |
455 | ret = clk_set_rate(clk: dev->gclk, rate: gclk_rate); |
456 | if (ret) |
457 | return ret; |
458 | |
459 | ret = clk_prepare_enable(clk: dev->gclk); |
460 | if (ret) |
461 | return ret; |
462 | |
463 | /* Update the Mode Register to generate the I2S Master Clock. */ |
464 | mr |= ATMEL_I2SC_MR_IMCKDIV(dev->gck_param->imckdiv); |
465 | mr |= ATMEL_I2SC_MR_IMCKFS(dev->gck_param->imckfs); |
466 | mr |= ATMEL_I2SC_MR_IMCKMODE_I2SMCK; |
467 | ret = regmap_update_bits(map: dev->regmap, ATMEL_I2SC_MR, mask: mr_mask, val: mr); |
468 | if (ret) |
469 | return ret; |
470 | |
471 | /* Finally enable the I2S Master Clock generator. */ |
472 | return regmap_write(map: dev->regmap, ATMEL_I2SC_CR, |
473 | ATMEL_I2SC_CR_CKEN); |
474 | } |
475 | |
476 | static int atmel_i2s_trigger(struct snd_pcm_substream *substream, int cmd, |
477 | struct snd_soc_dai *dai) |
478 | { |
479 | struct atmel_i2s_dev *dev = snd_soc_dai_get_drvdata(dai); |
480 | bool is_playback = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK); |
481 | bool is_master, mck_enabled; |
482 | unsigned int cr, mr; |
483 | int err; |
484 | |
485 | switch (cmd) { |
486 | case SNDRV_PCM_TRIGGER_START: |
487 | case SNDRV_PCM_TRIGGER_RESUME: |
488 | case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: |
489 | cr = is_playback ? ATMEL_I2SC_CR_TXEN : ATMEL_I2SC_CR_RXEN; |
490 | mck_enabled = true; |
491 | break; |
492 | case SNDRV_PCM_TRIGGER_STOP: |
493 | case SNDRV_PCM_TRIGGER_SUSPEND: |
494 | case SNDRV_PCM_TRIGGER_PAUSE_PUSH: |
495 | cr = is_playback ? ATMEL_I2SC_CR_TXDIS : ATMEL_I2SC_CR_RXDIS; |
496 | mck_enabled = false; |
497 | break; |
498 | default: |
499 | return -EINVAL; |
500 | } |
501 | |
502 | /* Read the Mode Register to retrieve the master/slave state. */ |
503 | err = regmap_read(map: dev->regmap, ATMEL_I2SC_MR, val: &mr); |
504 | if (err) |
505 | return err; |
506 | is_master = (mr & ATMEL_I2SC_MR_MODE_MASK) == ATMEL_I2SC_MR_MODE_MASTER; |
507 | |
508 | /* If master starts, enable the audio clock. */ |
509 | if (is_master && mck_enabled) { |
510 | if (!dev->clk_use_no) { |
511 | err = atmel_i2s_switch_mck_generator(dev, enabled: true); |
512 | if (err) |
513 | return err; |
514 | } |
515 | dev->clk_use_no++; |
516 | } |
517 | |
518 | err = regmap_write(map: dev->regmap, ATMEL_I2SC_CR, val: cr); |
519 | if (err) |
520 | return err; |
521 | |
522 | /* If master stops, disable the audio clock. */ |
523 | if (is_master && !mck_enabled) { |
524 | if (dev->clk_use_no == 1) { |
525 | err = atmel_i2s_switch_mck_generator(dev, enabled: false); |
526 | if (err) |
527 | return err; |
528 | } |
529 | dev->clk_use_no--; |
530 | } |
531 | |
532 | return err; |
533 | } |
534 | |
535 | static int atmel_i2s_dai_probe(struct snd_soc_dai *dai) |
536 | { |
537 | struct atmel_i2s_dev *dev = snd_soc_dai_get_drvdata(dai); |
538 | |
539 | snd_soc_dai_init_dma_data(dai, playback: &dev->playback, capture: &dev->capture); |
540 | return 0; |
541 | } |
542 | |
543 | static const struct snd_soc_dai_ops atmel_i2s_dai_ops = { |
544 | .probe = atmel_i2s_dai_probe, |
545 | .prepare = atmel_i2s_prepare, |
546 | .trigger = atmel_i2s_trigger, |
547 | .hw_params = atmel_i2s_hw_params, |
548 | .set_fmt = atmel_i2s_set_dai_fmt, |
549 | }; |
550 | |
551 | static struct snd_soc_dai_driver atmel_i2s_dai = { |
552 | .playback = { |
553 | .channels_min = 1, |
554 | .channels_max = 2, |
555 | .rates = ATMEL_I2S_RATES, |
556 | .formats = ATMEL_I2S_FORMATS, |
557 | }, |
558 | .capture = { |
559 | .channels_min = 1, |
560 | .channels_max = 2, |
561 | .rates = ATMEL_I2S_RATES, |
562 | .formats = ATMEL_I2S_FORMATS, |
563 | }, |
564 | .ops = &atmel_i2s_dai_ops, |
565 | .symmetric_rate = 1, |
566 | .symmetric_sample_bits = 1, |
567 | }; |
568 | |
569 | static const struct snd_soc_component_driver atmel_i2s_component = { |
570 | .name = "atmel-i2s" , |
571 | .legacy_dai_naming = 1, |
572 | }; |
573 | |
574 | static int atmel_i2s_sama5d2_mck_init(struct atmel_i2s_dev *dev, |
575 | struct device_node *np) |
576 | { |
577 | struct clk *muxclk; |
578 | int err; |
579 | |
580 | if (!dev->gclk) |
581 | return 0; |
582 | |
583 | /* muxclk is optional, so we return error for probe defer only */ |
584 | muxclk = devm_clk_get(dev: dev->dev, id: "muxclk" ); |
585 | if (IS_ERR(ptr: muxclk)) { |
586 | err = PTR_ERR(ptr: muxclk); |
587 | if (err == -EPROBE_DEFER) |
588 | return -EPROBE_DEFER; |
589 | dev_dbg(dev->dev, |
590 | "failed to get the I2S clock control: %d\n" , err); |
591 | return 0; |
592 | } |
593 | |
594 | return clk_set_parent(clk: muxclk, parent: dev->gclk); |
595 | } |
596 | |
597 | static const struct atmel_i2s_caps atmel_i2s_sama5d2_caps = { |
598 | .mck_init = atmel_i2s_sama5d2_mck_init, |
599 | }; |
600 | |
601 | static const struct of_device_id atmel_i2s_dt_ids[] = { |
602 | { |
603 | .compatible = "atmel,sama5d2-i2s" , |
604 | .data = (void *)&atmel_i2s_sama5d2_caps, |
605 | }, |
606 | |
607 | { /* sentinel */ } |
608 | }; |
609 | |
610 | MODULE_DEVICE_TABLE(of, atmel_i2s_dt_ids); |
611 | |
612 | static int atmel_i2s_probe(struct platform_device *pdev) |
613 | { |
614 | struct device_node *np = pdev->dev.of_node; |
615 | const struct of_device_id *match; |
616 | struct atmel_i2s_dev *dev; |
617 | struct resource *mem; |
618 | struct regmap *regmap; |
619 | void __iomem *base; |
620 | int irq; |
621 | int err; |
622 | unsigned int pcm_flags = 0; |
623 | unsigned int version; |
624 | |
625 | /* Get memory for driver data. */ |
626 | dev = devm_kzalloc(dev: &pdev->dev, size: sizeof(*dev), GFP_KERNEL); |
627 | if (!dev) |
628 | return -ENOMEM; |
629 | |
630 | /* Get hardware capabilities. */ |
631 | match = of_match_node(matches: atmel_i2s_dt_ids, node: np); |
632 | if (match) |
633 | dev->caps = match->data; |
634 | |
635 | /* Map I/O registers. */ |
636 | base = devm_platform_get_and_ioremap_resource(pdev, index: 0, res: &mem); |
637 | if (IS_ERR(ptr: base)) |
638 | return PTR_ERR(ptr: base); |
639 | |
640 | regmap = devm_regmap_init_mmio(&pdev->dev, base, |
641 | &atmel_i2s_regmap_config); |
642 | if (IS_ERR(ptr: regmap)) |
643 | return PTR_ERR(ptr: regmap); |
644 | |
645 | /* Request IRQ. */ |
646 | irq = platform_get_irq(pdev, 0); |
647 | if (irq < 0) |
648 | return irq; |
649 | |
650 | err = devm_request_irq(dev: &pdev->dev, irq, handler: atmel_i2s_interrupt, irqflags: 0, |
651 | devname: dev_name(dev: &pdev->dev), dev_id: dev); |
652 | if (err) |
653 | return err; |
654 | |
655 | /* Get the peripheral clock. */ |
656 | dev->pclk = devm_clk_get(dev: &pdev->dev, id: "pclk" ); |
657 | if (IS_ERR(ptr: dev->pclk)) { |
658 | err = PTR_ERR(ptr: dev->pclk); |
659 | dev_err(&pdev->dev, |
660 | "failed to get the peripheral clock: %d\n" , err); |
661 | return err; |
662 | } |
663 | |
664 | /* Get audio clock to generate the I2S Master Clock (I2S_MCK) */ |
665 | dev->gclk = devm_clk_get(dev: &pdev->dev, id: "gclk" ); |
666 | if (IS_ERR(ptr: dev->gclk)) { |
667 | if (PTR_ERR(ptr: dev->gclk) == -EPROBE_DEFER) |
668 | return -EPROBE_DEFER; |
669 | /* Master Mode not supported */ |
670 | dev->gclk = NULL; |
671 | } |
672 | dev->dev = &pdev->dev; |
673 | dev->regmap = regmap; |
674 | platform_set_drvdata(pdev, data: dev); |
675 | |
676 | /* Do hardware specific settings to initialize I2S_MCK generator */ |
677 | if (dev->caps && dev->caps->mck_init) { |
678 | err = dev->caps->mck_init(dev, np); |
679 | if (err) |
680 | return err; |
681 | } |
682 | |
683 | /* Enable the peripheral clock. */ |
684 | err = clk_prepare_enable(clk: dev->pclk); |
685 | if (err) |
686 | return err; |
687 | |
688 | /* Get IP version. */ |
689 | regmap_read(map: dev->regmap, ATMEL_I2SC_VERSION, val: &version); |
690 | dev_info(&pdev->dev, "hw version: %#x\n" , version); |
691 | |
692 | /* Enable error interrupts. */ |
693 | regmap_write(map: dev->regmap, ATMEL_I2SC_IER, |
694 | ATMEL_I2SC_INT_RXOR | ATMEL_I2SC_INT_TXUR); |
695 | |
696 | err = devm_snd_soc_register_component(dev: &pdev->dev, |
697 | component_driver: &atmel_i2s_component, |
698 | dai_drv: &atmel_i2s_dai, num_dai: 1); |
699 | if (err) { |
700 | dev_err(&pdev->dev, "failed to register DAI: %d\n" , err); |
701 | clk_disable_unprepare(clk: dev->pclk); |
702 | return err; |
703 | } |
704 | |
705 | /* Prepare DMA config. */ |
706 | dev->playback.addr = (dma_addr_t)mem->start + ATMEL_I2SC_THR; |
707 | dev->playback.maxburst = 1; |
708 | dev->capture.addr = (dma_addr_t)mem->start + ATMEL_I2SC_RHR; |
709 | dev->capture.maxburst = 1; |
710 | |
711 | if (of_property_match_string(np, propname: "dma-names" , string: "rx-tx" ) == 0) |
712 | pcm_flags |= SND_DMAENGINE_PCM_FLAG_HALF_DUPLEX; |
713 | err = devm_snd_dmaengine_pcm_register(dev: &pdev->dev, NULL, flags: pcm_flags); |
714 | if (err) { |
715 | dev_err(&pdev->dev, "failed to register PCM: %d\n" , err); |
716 | clk_disable_unprepare(clk: dev->pclk); |
717 | return err; |
718 | } |
719 | |
720 | return 0; |
721 | } |
722 | |
723 | static void atmel_i2s_remove(struct platform_device *pdev) |
724 | { |
725 | struct atmel_i2s_dev *dev = platform_get_drvdata(pdev); |
726 | |
727 | clk_disable_unprepare(clk: dev->pclk); |
728 | } |
729 | |
730 | static struct platform_driver atmel_i2s_driver = { |
731 | .driver = { |
732 | .name = "atmel_i2s" , |
733 | .of_match_table = atmel_i2s_dt_ids, |
734 | }, |
735 | .probe = atmel_i2s_probe, |
736 | .remove_new = atmel_i2s_remove, |
737 | }; |
738 | module_platform_driver(atmel_i2s_driver); |
739 | |
740 | MODULE_DESCRIPTION("Atmel I2S Controller driver" ); |
741 | MODULE_AUTHOR("Cyrille Pitchen <cyrille.pitchen@atmel.com>" ); |
742 | MODULE_LICENSE("GPL v2" ); |
743 | |