| 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
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| 2 | /* Copyright (c) 2020 Maxim Integrated */ |
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| 3 | |
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| 4 | #ifndef _MAX98373_SDW_H |
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| 5 | #define _MAX98373_SDW_H |
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| 6 | |
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| 7 | #include "max98373.h" |
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| 8 | |
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| 9 | /* SoundWire Slave Control Port (SCP) */ |
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| 10 | #define MAX98373_R0040_SCP_INIT_STAT_1 0x0040 |
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| 11 | #define MAX98373_R0041_SCP_INIT_MASK_1 0x0041 |
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| 12 | #define MAX98373_R0042_SCP_INIT_STAT_2 0x0042 |
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| 13 | #define MAX98373_R0044_SCP_CTRL 0x0044 |
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| 14 | #define MAX98373_R0045_SCP_SYSTEM_CTRL 0x0045 |
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| 15 | #define MAX98373_R0046_SCP_DEV_NUMBER 0x0046 |
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| 16 | #define MAX98373_R0050_SCP_DEV_ID_0 0x0050 |
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| 17 | #define MAX98373_R0051_SCP_DEV_ID_1 0x0051 |
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| 18 | #define MAX98373_R0052_SCP_DEV_ID_2 0x0052 |
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| 19 | #define MAX98373_R0053_SCP_DEV_ID_3 0x0053 |
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| 20 | #define MAX98373_R0054_SCP_DEV_ID_4 0x0054 |
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| 21 | #define MAX98373_R0055_SCP_DEV_ID_5 0x0055 |
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| 22 | #define MAX98373_R0060_SCP_FRAME_CTLR 0x0060 |
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| 23 | #define MAX98373_R0070_SCP_FRAME_CTLR 0x0070 |
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| 24 | |
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| 25 | /* SoundWire Device Data Port (DP) */ |
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| 26 | /* Data Port 1 Registers */ |
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| 27 | #define MAX98373_R0100_DP1_INIT_STAT 0x0100 |
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| 28 | #define MAX98373_R0101_DP1_INIT_MASK 0x0101 |
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| 29 | #define MAX98373_R0102_DP1_PORT_CTRL 0x0102 |
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| 30 | #define MAX98373_R0103_DP1_BLOCK_CTRL_1 0x0103 |
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| 31 | #define MAX98373_R0104_DP1_PREPARE_STATUS 0x0104 |
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| 32 | #define MAX98373_R0105_DP1_PREPARE_CTRL 0x0105 |
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| 33 | /* Data Port 1 Bank 0 Registers */ |
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| 34 | #define MAX98373_R0120_DP1_CHANNEL_EN 0x0120 |
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| 35 | #define MAX98373_R0122_DP1_SAMPLE_CTRL1 0x0122 |
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| 36 | #define MAX98373_R0123_DP1_SAMPLE_CTRL2 0x0123 |
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| 37 | #define MAX98373_R0124_DP1_OFFSET_CTRL1 0x0124 |
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| 38 | #define MAX98373_R0125_DP1_OFFSET_CTRL2 0x0125 |
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| 39 | #define MAX98373_R0126_DP1_HCTRL 0x0126 |
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| 40 | #define MAX98373_R0127_DP1_BLOCK_CTRL3 0x0127 |
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| 41 | /* Data Port 1 Bank 1 Registers */ |
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| 42 | #define MAX98373_R0130_DP1_CHANNEL_EN 0x0130 |
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| 43 | #define MAX98373_R0132_DP1_SAMPLE_CTRL1 0x0132 |
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| 44 | #define MAX98373_R0133_DP1_SAMPLE_CTRL2 0x0133 |
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| 45 | #define MAX98373_R0134_DP1_OFFSET_CTRL1 0x0134 |
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| 46 | #define MAX98373_R0135_DP1_OFFSET_CTRL2 0x0135 |
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| 47 | #define MAX98373_R0136_DP1_HCTRL 0x0136 |
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| 48 | #define MAX98373_R0137_DP1_BLOCK_CTRL3 0x0137 |
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| 49 | /* Data Port 3 Registers */ |
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| 50 | #define MAX98373_R0300_DP3_INIT_STAT 0x0300 |
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| 51 | #define MAX98373_R0301_DP3_INIT_MASK 0x0301 |
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| 52 | #define MAX98373_R0302_DP3_PORT_CTRL 0x0302 |
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| 53 | #define MAX98373_R0303_DP3_BLOCK_CTRL_1 0x0303 |
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| 54 | #define MAX98373_R0304_DP3_PREPARE_STATUS 0x0304 |
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| 55 | #define MAX98373_R0305_DP3_PREPARE_CTRL 0x0305 |
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| 56 | /* Data Port 3 Bank 0 Registers */ |
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| 57 | #define MAX98373_R0320_DP3_CHANNEL_EN 0x0320 |
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| 58 | #define MAX98373_R0322_DP3_SAMPLE_CTRL1 0x0322 |
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| 59 | #define MAX98373_R0323_DP3_SAMPLE_CTRL2 0x0323 |
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| 60 | #define MAX98373_R0324_DP3_OFFSET_CTRL1 0x0324 |
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| 61 | #define MAX98373_R0325_DP3_OFFSET_CTRL2 0x0325 |
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| 62 | #define MAX98373_R0326_DP3_HCTRL 0x0326 |
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| 63 | #define MAX98373_R0327_DP3_BLOCK_CTRL3 0x0327 |
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| 64 | /* Data Port 3 Bank 1 Registers */ |
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| 65 | #define MAX98373_R0330_DP3_CHANNEL_EN 0x0330 |
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| 66 | #define MAX98373_R0332_DP3_SAMPLE_CTRL1 0x0332 |
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| 67 | #define MAX98373_R0333_DP3_SAMPLE_CTRL2 0x0333 |
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| 68 | #define MAX98373_R0334_DP3_OFFSET_CTRL1 0x0334 |
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| 69 | #define MAX98373_R0335_DP3_OFFSET_CTRL2 0x0335 |
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| 70 | #define MAX98373_R0336_DP3_HCTRL 0x0336 |
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| 71 | #define MAX98373_R0337_DP3_BLOCK_CTRL3 0x0337 |
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| 72 | #endif |
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| 73 | |
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