1 | // SPDX-License-Identifier: GPL-2.0-only |
2 | // Copyright (c) 2020, Maxim Integrated |
3 | |
4 | #include <linux/acpi.h> |
5 | #include <linux/delay.h> |
6 | #include <linux/module.h> |
7 | #include <linux/mod_devicetable.h> |
8 | #include <linux/pm_runtime.h> |
9 | #include <linux/regmap.h> |
10 | #include <linux/slab.h> |
11 | #include <sound/pcm.h> |
12 | #include <sound/pcm_params.h> |
13 | #include <sound/sdw.h> |
14 | #include <sound/soc.h> |
15 | #include <sound/tlv.h> |
16 | #include <linux/of.h> |
17 | #include <linux/soundwire/sdw.h> |
18 | #include <linux/soundwire/sdw_type.h> |
19 | #include <linux/soundwire/sdw_registers.h> |
20 | #include "max98373.h" |
21 | #include "max98373-sdw.h" |
22 | |
23 | static const u32 max98373_sdw_cache_reg[] = { |
24 | MAX98373_R2054_MEAS_ADC_PVDD_CH_READBACK, |
25 | MAX98373_R2055_MEAS_ADC_THERM_CH_READBACK, |
26 | MAX98373_R20B6_BDE_CUR_STATE_READBACK, |
27 | }; |
28 | |
29 | static struct reg_default max98373_reg[] = { |
30 | {MAX98373_R0040_SCP_INIT_STAT_1, 0x00}, |
31 | {MAX98373_R0041_SCP_INIT_MASK_1, 0x00}, |
32 | {MAX98373_R0042_SCP_INIT_STAT_2, 0x00}, |
33 | {MAX98373_R0044_SCP_CTRL, 0x00}, |
34 | {MAX98373_R0045_SCP_SYSTEM_CTRL, 0x00}, |
35 | {MAX98373_R0046_SCP_DEV_NUMBER, 0x00}, |
36 | {MAX98373_R0050_SCP_DEV_ID_0, 0x21}, |
37 | {MAX98373_R0051_SCP_DEV_ID_1, 0x01}, |
38 | {MAX98373_R0052_SCP_DEV_ID_2, 0x9F}, |
39 | {MAX98373_R0053_SCP_DEV_ID_3, 0x87}, |
40 | {MAX98373_R0054_SCP_DEV_ID_4, 0x08}, |
41 | {MAX98373_R0055_SCP_DEV_ID_5, 0x00}, |
42 | {MAX98373_R0060_SCP_FRAME_CTLR, 0x00}, |
43 | {MAX98373_R0070_SCP_FRAME_CTLR, 0x00}, |
44 | {MAX98373_R0100_DP1_INIT_STAT, 0x00}, |
45 | {MAX98373_R0101_DP1_INIT_MASK, 0x00}, |
46 | {MAX98373_R0102_DP1_PORT_CTRL, 0x00}, |
47 | {MAX98373_R0103_DP1_BLOCK_CTRL_1, 0x00}, |
48 | {MAX98373_R0104_DP1_PREPARE_STATUS, 0x00}, |
49 | {MAX98373_R0105_DP1_PREPARE_CTRL, 0x00}, |
50 | {MAX98373_R0120_DP1_CHANNEL_EN, 0x00}, |
51 | {MAX98373_R0122_DP1_SAMPLE_CTRL1, 0x00}, |
52 | {MAX98373_R0123_DP1_SAMPLE_CTRL2, 0x00}, |
53 | {MAX98373_R0124_DP1_OFFSET_CTRL1, 0x00}, |
54 | {MAX98373_R0125_DP1_OFFSET_CTRL2, 0x00}, |
55 | {MAX98373_R0126_DP1_HCTRL, 0x00}, |
56 | {MAX98373_R0127_DP1_BLOCK_CTRL3, 0x00}, |
57 | {MAX98373_R0130_DP1_CHANNEL_EN, 0x00}, |
58 | {MAX98373_R0132_DP1_SAMPLE_CTRL1, 0x00}, |
59 | {MAX98373_R0133_DP1_SAMPLE_CTRL2, 0x00}, |
60 | {MAX98373_R0134_DP1_OFFSET_CTRL1, 0x00}, |
61 | {MAX98373_R0135_DP1_OFFSET_CTRL2, 0x00}, |
62 | {MAX98373_R0136_DP1_HCTRL, 0x0136}, |
63 | {MAX98373_R0137_DP1_BLOCK_CTRL3, 0x00}, |
64 | {MAX98373_R0300_DP3_INIT_STAT, 0x00}, |
65 | {MAX98373_R0301_DP3_INIT_MASK, 0x00}, |
66 | {MAX98373_R0302_DP3_PORT_CTRL, 0x00}, |
67 | {MAX98373_R0303_DP3_BLOCK_CTRL_1, 0x00}, |
68 | {MAX98373_R0304_DP3_PREPARE_STATUS, 0x00}, |
69 | {MAX98373_R0305_DP3_PREPARE_CTRL, 0x00}, |
70 | {MAX98373_R0320_DP3_CHANNEL_EN, 0x00}, |
71 | {MAX98373_R0322_DP3_SAMPLE_CTRL1, 0x00}, |
72 | {MAX98373_R0323_DP3_SAMPLE_CTRL2, 0x00}, |
73 | {MAX98373_R0324_DP3_OFFSET_CTRL1, 0x00}, |
74 | {MAX98373_R0325_DP3_OFFSET_CTRL2, 0x00}, |
75 | {MAX98373_R0326_DP3_HCTRL, 0x00}, |
76 | {MAX98373_R0327_DP3_BLOCK_CTRL3, 0x00}, |
77 | {MAX98373_R0330_DP3_CHANNEL_EN, 0x00}, |
78 | {MAX98373_R0332_DP3_SAMPLE_CTRL1, 0x00}, |
79 | {MAX98373_R0333_DP3_SAMPLE_CTRL2, 0x00}, |
80 | {MAX98373_R0334_DP3_OFFSET_CTRL1, 0x00}, |
81 | {MAX98373_R0335_DP3_OFFSET_CTRL2, 0x00}, |
82 | {MAX98373_R0336_DP3_HCTRL, 0x00}, |
83 | {MAX98373_R0337_DP3_BLOCK_CTRL3, 0x00}, |
84 | {MAX98373_R2000_SW_RESET, 0x00}, |
85 | {MAX98373_R2001_INT_RAW1, 0x00}, |
86 | {MAX98373_R2002_INT_RAW2, 0x00}, |
87 | {MAX98373_R2003_INT_RAW3, 0x00}, |
88 | {MAX98373_R2004_INT_STATE1, 0x00}, |
89 | {MAX98373_R2005_INT_STATE2, 0x00}, |
90 | {MAX98373_R2006_INT_STATE3, 0x00}, |
91 | {MAX98373_R2007_INT_FLAG1, 0x00}, |
92 | {MAX98373_R2008_INT_FLAG2, 0x00}, |
93 | {MAX98373_R2009_INT_FLAG3, 0x00}, |
94 | {MAX98373_R200A_INT_EN1, 0x00}, |
95 | {MAX98373_R200B_INT_EN2, 0x00}, |
96 | {MAX98373_R200C_INT_EN3, 0x00}, |
97 | {MAX98373_R200D_INT_FLAG_CLR1, 0x00}, |
98 | {MAX98373_R200E_INT_FLAG_CLR2, 0x00}, |
99 | {MAX98373_R200F_INT_FLAG_CLR3, 0x00}, |
100 | {MAX98373_R2010_IRQ_CTRL, 0x00}, |
101 | {MAX98373_R2014_THERM_WARN_THRESH, 0x10}, |
102 | {MAX98373_R2015_THERM_SHDN_THRESH, 0x27}, |
103 | {MAX98373_R2016_THERM_HYSTERESIS, 0x01}, |
104 | {MAX98373_R2017_THERM_FOLDBACK_SET, 0xC0}, |
105 | {MAX98373_R2018_THERM_FOLDBACK_EN, 0x00}, |
106 | {MAX98373_R201E_PIN_DRIVE_STRENGTH, 0x55}, |
107 | {MAX98373_R2020_PCM_TX_HIZ_EN_1, 0xFE}, |
108 | {MAX98373_R2021_PCM_TX_HIZ_EN_2, 0xFF}, |
109 | {MAX98373_R2022_PCM_TX_SRC_1, 0x00}, |
110 | {MAX98373_R2023_PCM_TX_SRC_2, 0x00}, |
111 | {MAX98373_R2024_PCM_DATA_FMT_CFG, 0xC0}, |
112 | {MAX98373_R2025_AUDIO_IF_MODE, 0x00}, |
113 | {MAX98373_R2026_PCM_CLOCK_RATIO, 0x04}, |
114 | {MAX98373_R2027_PCM_SR_SETUP_1, 0x08}, |
115 | {MAX98373_R2028_PCM_SR_SETUP_2, 0x88}, |
116 | {MAX98373_R2029_PCM_TO_SPK_MONO_MIX_1, 0x00}, |
117 | {MAX98373_R202A_PCM_TO_SPK_MONO_MIX_2, 0x00}, |
118 | {MAX98373_R202B_PCM_RX_EN, 0x00}, |
119 | {MAX98373_R202C_PCM_TX_EN, 0x00}, |
120 | {MAX98373_R202E_ICC_RX_CH_EN_1, 0x00}, |
121 | {MAX98373_R202F_ICC_RX_CH_EN_2, 0x00}, |
122 | {MAX98373_R2030_ICC_TX_HIZ_EN_1, 0xFF}, |
123 | {MAX98373_R2031_ICC_TX_HIZ_EN_2, 0xFF}, |
124 | {MAX98373_R2032_ICC_LINK_EN_CFG, 0x30}, |
125 | {MAX98373_R2034_ICC_TX_CNTL, 0x00}, |
126 | {MAX98373_R2035_ICC_TX_EN, 0x00}, |
127 | {MAX98373_R2036_SOUNDWIRE_CTRL, 0x05}, |
128 | {MAX98373_R203D_AMP_DIG_VOL_CTRL, 0x00}, |
129 | {MAX98373_R203E_AMP_PATH_GAIN, 0x08}, |
130 | {MAX98373_R203F_AMP_DSP_CFG, 0x02}, |
131 | {MAX98373_R2040_TONE_GEN_CFG, 0x00}, |
132 | {MAX98373_R2041_AMP_CFG, 0x03}, |
133 | {MAX98373_R2042_AMP_EDGE_RATE_CFG, 0x00}, |
134 | {MAX98373_R2043_AMP_EN, 0x00}, |
135 | {MAX98373_R2046_IV_SENSE_ADC_DSP_CFG, 0x04}, |
136 | {MAX98373_R2047_IV_SENSE_ADC_EN, 0x00}, |
137 | {MAX98373_R2051_MEAS_ADC_SAMPLING_RATE, 0x00}, |
138 | {MAX98373_R2052_MEAS_ADC_PVDD_FLT_CFG, 0x00}, |
139 | {MAX98373_R2053_MEAS_ADC_THERM_FLT_CFG, 0x00}, |
140 | {MAX98373_R2054_MEAS_ADC_PVDD_CH_READBACK, 0x00}, |
141 | {MAX98373_R2055_MEAS_ADC_THERM_CH_READBACK, 0x00}, |
142 | {MAX98373_R2056_MEAS_ADC_PVDD_CH_EN, 0x00}, |
143 | {MAX98373_R2090_BDE_LVL_HOLD, 0x00}, |
144 | {MAX98373_R2091_BDE_GAIN_ATK_REL_RATE, 0x00}, |
145 | {MAX98373_R2092_BDE_CLIPPER_MODE, 0x00}, |
146 | {MAX98373_R2097_BDE_L1_THRESH, 0x00}, |
147 | {MAX98373_R2098_BDE_L2_THRESH, 0x00}, |
148 | {MAX98373_R2099_BDE_L3_THRESH, 0x00}, |
149 | {MAX98373_R209A_BDE_L4_THRESH, 0x00}, |
150 | {MAX98373_R209B_BDE_THRESH_HYST, 0x00}, |
151 | {MAX98373_R20A8_BDE_L1_CFG_1, 0x00}, |
152 | {MAX98373_R20A9_BDE_L1_CFG_2, 0x00}, |
153 | {MAX98373_R20AA_BDE_L1_CFG_3, 0x00}, |
154 | {MAX98373_R20AB_BDE_L2_CFG_1, 0x00}, |
155 | {MAX98373_R20AC_BDE_L2_CFG_2, 0x00}, |
156 | {MAX98373_R20AD_BDE_L2_CFG_3, 0x00}, |
157 | {MAX98373_R20AE_BDE_L3_CFG_1, 0x00}, |
158 | {MAX98373_R20AF_BDE_L3_CFG_2, 0x00}, |
159 | {MAX98373_R20B0_BDE_L3_CFG_3, 0x00}, |
160 | {MAX98373_R20B1_BDE_L4_CFG_1, 0x00}, |
161 | {MAX98373_R20B2_BDE_L4_CFG_2, 0x00}, |
162 | {MAX98373_R20B3_BDE_L4_CFG_3, 0x00}, |
163 | {MAX98373_R20B4_BDE_INFINITE_HOLD_RELEASE, 0x00}, |
164 | {MAX98373_R20B5_BDE_EN, 0x00}, |
165 | {MAX98373_R20B6_BDE_CUR_STATE_READBACK, 0x00}, |
166 | {MAX98373_R20D1_DHT_CFG, 0x01}, |
167 | {MAX98373_R20D2_DHT_ATTACK_CFG, 0x02}, |
168 | {MAX98373_R20D3_DHT_RELEASE_CFG, 0x03}, |
169 | {MAX98373_R20D4_DHT_EN, 0x00}, |
170 | {MAX98373_R20E0_LIMITER_THRESH_CFG, 0x00}, |
171 | {MAX98373_R20E1_LIMITER_ATK_REL_RATES, 0x00}, |
172 | {MAX98373_R20E2_LIMITER_EN, 0x00}, |
173 | {MAX98373_R20FE_DEVICE_AUTO_RESTART_CFG, 0x00}, |
174 | {MAX98373_R20FF_GLOBAL_SHDN, 0x00}, |
175 | {MAX98373_R21FF_REV_ID, 0x42}, |
176 | }; |
177 | |
178 | static bool max98373_readable_register(struct device *dev, unsigned int reg) |
179 | { |
180 | switch (reg) { |
181 | case MAX98373_R21FF_REV_ID: |
182 | case MAX98373_R2010_IRQ_CTRL: |
183 | /* SoundWire Control Port Registers */ |
184 | case MAX98373_R0040_SCP_INIT_STAT_1 ... MAX98373_R0070_SCP_FRAME_CTLR: |
185 | /* Soundwire Data Port 1 Registers */ |
186 | case MAX98373_R0100_DP1_INIT_STAT ... MAX98373_R0137_DP1_BLOCK_CTRL3: |
187 | /* Soundwire Data Port 3 Registers */ |
188 | case MAX98373_R0300_DP3_INIT_STAT ... MAX98373_R0337_DP3_BLOCK_CTRL3: |
189 | case MAX98373_R2000_SW_RESET ... MAX98373_R200C_INT_EN3: |
190 | case MAX98373_R2014_THERM_WARN_THRESH |
191 | ... MAX98373_R2018_THERM_FOLDBACK_EN: |
192 | case MAX98373_R201E_PIN_DRIVE_STRENGTH |
193 | ... MAX98373_R2036_SOUNDWIRE_CTRL: |
194 | case MAX98373_R203D_AMP_DIG_VOL_CTRL ... MAX98373_R2043_AMP_EN: |
195 | case MAX98373_R2046_IV_SENSE_ADC_DSP_CFG |
196 | ... MAX98373_R2047_IV_SENSE_ADC_EN: |
197 | case MAX98373_R2051_MEAS_ADC_SAMPLING_RATE |
198 | ... MAX98373_R2056_MEAS_ADC_PVDD_CH_EN: |
199 | case MAX98373_R2090_BDE_LVL_HOLD ... MAX98373_R2092_BDE_CLIPPER_MODE: |
200 | case MAX98373_R2097_BDE_L1_THRESH |
201 | ... MAX98373_R209B_BDE_THRESH_HYST: |
202 | case MAX98373_R20A8_BDE_L1_CFG_1 ... MAX98373_R20B3_BDE_L4_CFG_3: |
203 | case MAX98373_R20B5_BDE_EN ... MAX98373_R20B6_BDE_CUR_STATE_READBACK: |
204 | case MAX98373_R20D1_DHT_CFG ... MAX98373_R20D4_DHT_EN: |
205 | case MAX98373_R20E0_LIMITER_THRESH_CFG ... MAX98373_R20E2_LIMITER_EN: |
206 | case MAX98373_R20FE_DEVICE_AUTO_RESTART_CFG |
207 | ... MAX98373_R20FF_GLOBAL_SHDN: |
208 | return true; |
209 | default: |
210 | return false; |
211 | } |
212 | }; |
213 | |
214 | static bool max98373_volatile_reg(struct device *dev, unsigned int reg) |
215 | { |
216 | switch (reg) { |
217 | case MAX98373_R2054_MEAS_ADC_PVDD_CH_READBACK: |
218 | case MAX98373_R2055_MEAS_ADC_THERM_CH_READBACK: |
219 | case MAX98373_R20B6_BDE_CUR_STATE_READBACK: |
220 | case MAX98373_R20FF_GLOBAL_SHDN: |
221 | case MAX98373_R21FF_REV_ID: |
222 | /* SoundWire Control Port Registers */ |
223 | case MAX98373_R0040_SCP_INIT_STAT_1 ... MAX98373_R0070_SCP_FRAME_CTLR: |
224 | /* Soundwire Data Port 1 Registers */ |
225 | case MAX98373_R0100_DP1_INIT_STAT ... MAX98373_R0137_DP1_BLOCK_CTRL3: |
226 | /* Soundwire Data Port 3 Registers */ |
227 | case MAX98373_R0300_DP3_INIT_STAT ... MAX98373_R0337_DP3_BLOCK_CTRL3: |
228 | case MAX98373_R2000_SW_RESET ... MAX98373_R2009_INT_FLAG3: |
229 | return true; |
230 | default: |
231 | return false; |
232 | } |
233 | } |
234 | |
235 | static const struct regmap_config max98373_sdw_regmap = { |
236 | .reg_bits = 32, |
237 | .val_bits = 8, |
238 | .max_register = MAX98373_R21FF_REV_ID, |
239 | .reg_defaults = max98373_reg, |
240 | .num_reg_defaults = ARRAY_SIZE(max98373_reg), |
241 | .readable_reg = max98373_readable_register, |
242 | .volatile_reg = max98373_volatile_reg, |
243 | .cache_type = REGCACHE_RBTREE, |
244 | .use_single_read = true, |
245 | .use_single_write = true, |
246 | }; |
247 | |
248 | /* Power management functions and structure */ |
249 | static __maybe_unused int max98373_suspend(struct device *dev) |
250 | { |
251 | struct max98373_priv *max98373 = dev_get_drvdata(dev); |
252 | int i; |
253 | |
254 | /* cache feedback register values before suspend */ |
255 | for (i = 0; i < max98373->cache_num; i++) |
256 | regmap_read(map: max98373->regmap, reg: max98373->cache[i].reg, val: &max98373->cache[i].val); |
257 | |
258 | regcache_cache_only(map: max98373->regmap, enable: true); |
259 | |
260 | return 0; |
261 | } |
262 | |
263 | #define MAX98373_PROBE_TIMEOUT 5000 |
264 | |
265 | static __maybe_unused int max98373_resume(struct device *dev) |
266 | { |
267 | struct sdw_slave *slave = dev_to_sdw_dev(dev); |
268 | struct max98373_priv *max98373 = dev_get_drvdata(dev); |
269 | unsigned long time; |
270 | |
271 | if (!max98373->first_hw_init) |
272 | return 0; |
273 | |
274 | if (!slave->unattach_request) |
275 | goto regmap_sync; |
276 | |
277 | time = wait_for_completion_timeout(x: &slave->initialization_complete, |
278 | timeout: msecs_to_jiffies(MAX98373_PROBE_TIMEOUT)); |
279 | if (!time) { |
280 | dev_err(dev, "Initialization not complete, timed out\n" ); |
281 | sdw_show_ping_status(bus: slave->bus, sync_delay: true); |
282 | |
283 | return -ETIMEDOUT; |
284 | } |
285 | |
286 | regmap_sync: |
287 | slave->unattach_request = 0; |
288 | regcache_cache_only(map: max98373->regmap, enable: false); |
289 | regcache_sync(map: max98373->regmap); |
290 | |
291 | return 0; |
292 | } |
293 | |
294 | static const struct dev_pm_ops max98373_pm = { |
295 | SET_SYSTEM_SLEEP_PM_OPS(max98373_suspend, max98373_resume) |
296 | SET_RUNTIME_PM_OPS(max98373_suspend, max98373_resume, NULL) |
297 | }; |
298 | |
299 | static int max98373_read_prop(struct sdw_slave *slave) |
300 | { |
301 | struct sdw_slave_prop *prop = &slave->prop; |
302 | int nval, i; |
303 | u32 bit; |
304 | unsigned long addr; |
305 | struct sdw_dpn_prop *dpn; |
306 | |
307 | prop->scp_int1_mask = SDW_SCP_INT1_BUS_CLASH | SDW_SCP_INT1_PARITY; |
308 | |
309 | /* BITMAP: 00001000 Dataport 3 is active */ |
310 | prop->source_ports = BIT(3); |
311 | /* BITMAP: 00000010 Dataport 1 is active */ |
312 | prop->sink_ports = BIT(1); |
313 | prop->paging_support = true; |
314 | prop->clk_stop_timeout = 20; |
315 | |
316 | nval = hweight32(prop->source_ports); |
317 | prop->src_dpn_prop = devm_kcalloc(dev: &slave->dev, n: nval, |
318 | size: sizeof(*prop->src_dpn_prop), |
319 | GFP_KERNEL); |
320 | if (!prop->src_dpn_prop) |
321 | return -ENOMEM; |
322 | |
323 | i = 0; |
324 | dpn = prop->src_dpn_prop; |
325 | addr = prop->source_ports; |
326 | for_each_set_bit(bit, &addr, 32) { |
327 | dpn[i].num = bit; |
328 | dpn[i].type = SDW_DPN_FULL; |
329 | dpn[i].simple_ch_prep_sm = true; |
330 | dpn[i].ch_prep_timeout = 10; |
331 | i++; |
332 | } |
333 | |
334 | /* do this again for sink now */ |
335 | nval = hweight32(prop->sink_ports); |
336 | prop->sink_dpn_prop = devm_kcalloc(dev: &slave->dev, n: nval, |
337 | size: sizeof(*prop->sink_dpn_prop), |
338 | GFP_KERNEL); |
339 | if (!prop->sink_dpn_prop) |
340 | return -ENOMEM; |
341 | |
342 | i = 0; |
343 | dpn = prop->sink_dpn_prop; |
344 | addr = prop->sink_ports; |
345 | for_each_set_bit(bit, &addr, 32) { |
346 | dpn[i].num = bit; |
347 | dpn[i].type = SDW_DPN_FULL; |
348 | dpn[i].simple_ch_prep_sm = true; |
349 | dpn[i].ch_prep_timeout = 10; |
350 | i++; |
351 | } |
352 | |
353 | /* set the timeout values */ |
354 | prop->clk_stop_timeout = 20; |
355 | |
356 | return 0; |
357 | } |
358 | |
359 | static int max98373_io_init(struct sdw_slave *slave) |
360 | { |
361 | struct device *dev = &slave->dev; |
362 | struct max98373_priv *max98373 = dev_get_drvdata(dev); |
363 | |
364 | regcache_cache_only(map: max98373->regmap, enable: false); |
365 | if (max98373->first_hw_init) |
366 | regcache_cache_bypass(map: max98373->regmap, enable: true); |
367 | |
368 | /* |
369 | * PM runtime status is marked as 'active' only when a Slave reports as Attached |
370 | */ |
371 | if (!max98373->first_hw_init) |
372 | /* update count of parent 'active' children */ |
373 | pm_runtime_set_active(dev); |
374 | |
375 | pm_runtime_get_noresume(dev); |
376 | |
377 | /* Software Reset */ |
378 | max98373_reset(max98373, dev); |
379 | |
380 | /* Set soundwire mode */ |
381 | regmap_write(map: max98373->regmap, MAX98373_R2025_AUDIO_IF_MODE, val: 3); |
382 | /* Enable ADC */ |
383 | regmap_write(map: max98373->regmap, MAX98373_R2047_IV_SENSE_ADC_EN, val: 3); |
384 | /* Set default Soundwire clock */ |
385 | regmap_write(map: max98373->regmap, MAX98373_R2036_SOUNDWIRE_CTRL, val: 5); |
386 | /* Set default sampling rate for speaker and IVDAC */ |
387 | regmap_write(map: max98373->regmap, MAX98373_R2028_PCM_SR_SETUP_2, val: 0x88); |
388 | /* IV default slot configuration */ |
389 | regmap_write(map: max98373->regmap, |
390 | MAX98373_R2020_PCM_TX_HIZ_EN_1, |
391 | val: 0xFF); |
392 | regmap_write(map: max98373->regmap, |
393 | MAX98373_R2021_PCM_TX_HIZ_EN_2, |
394 | val: 0xFF); |
395 | /* L/R mix configuration */ |
396 | regmap_write(map: max98373->regmap, |
397 | MAX98373_R2029_PCM_TO_SPK_MONO_MIX_1, |
398 | val: 0x80); |
399 | regmap_write(map: max98373->regmap, |
400 | MAX98373_R202A_PCM_TO_SPK_MONO_MIX_2, |
401 | val: 0x1); |
402 | /* Enable DC blocker */ |
403 | regmap_write(map: max98373->regmap, |
404 | MAX98373_R203F_AMP_DSP_CFG, |
405 | val: 0x3); |
406 | /* Enable IMON VMON DC blocker */ |
407 | regmap_write(map: max98373->regmap, |
408 | MAX98373_R2046_IV_SENSE_ADC_DSP_CFG, |
409 | val: 0x7); |
410 | /* voltage, current slot configuration */ |
411 | regmap_write(map: max98373->regmap, |
412 | MAX98373_R2022_PCM_TX_SRC_1, |
413 | val: (max98373->i_slot << MAX98373_PCM_TX_CH_SRC_A_I_SHIFT | |
414 | max98373->v_slot) & 0xFF); |
415 | if (max98373->v_slot < 8) |
416 | regmap_update_bits(map: max98373->regmap, |
417 | MAX98373_R2020_PCM_TX_HIZ_EN_1, |
418 | mask: 1 << max98373->v_slot, val: 0); |
419 | else |
420 | regmap_update_bits(map: max98373->regmap, |
421 | MAX98373_R2021_PCM_TX_HIZ_EN_2, |
422 | mask: 1 << (max98373->v_slot - 8), val: 0); |
423 | |
424 | if (max98373->i_slot < 8) |
425 | regmap_update_bits(map: max98373->regmap, |
426 | MAX98373_R2020_PCM_TX_HIZ_EN_1, |
427 | mask: 1 << max98373->i_slot, val: 0); |
428 | else |
429 | regmap_update_bits(map: max98373->regmap, |
430 | MAX98373_R2021_PCM_TX_HIZ_EN_2, |
431 | mask: 1 << (max98373->i_slot - 8), val: 0); |
432 | |
433 | /* speaker feedback slot configuration */ |
434 | regmap_write(map: max98373->regmap, |
435 | MAX98373_R2023_PCM_TX_SRC_2, |
436 | val: max98373->spkfb_slot & 0xFF); |
437 | |
438 | /* Set interleave mode */ |
439 | if (max98373->interleave_mode) |
440 | regmap_update_bits(map: max98373->regmap, |
441 | MAX98373_R2024_PCM_DATA_FMT_CFG, |
442 | MAX98373_PCM_TX_CH_INTERLEAVE_MASK, |
443 | MAX98373_PCM_TX_CH_INTERLEAVE_MASK); |
444 | |
445 | /* Speaker enable */ |
446 | regmap_update_bits(map: max98373->regmap, |
447 | MAX98373_R2043_AMP_EN, |
448 | MAX98373_SPK_EN_MASK, val: 1); |
449 | |
450 | regmap_write(map: max98373->regmap, MAX98373_R20B5_BDE_EN, val: 1); |
451 | regmap_write(map: max98373->regmap, MAX98373_R20E2_LIMITER_EN, val: 1); |
452 | |
453 | if (max98373->first_hw_init) { |
454 | regcache_cache_bypass(map: max98373->regmap, enable: false); |
455 | regcache_mark_dirty(map: max98373->regmap); |
456 | } |
457 | |
458 | max98373->first_hw_init = true; |
459 | max98373->hw_init = true; |
460 | |
461 | pm_runtime_mark_last_busy(dev); |
462 | pm_runtime_put_autosuspend(dev); |
463 | |
464 | return 0; |
465 | } |
466 | |
467 | static int max98373_clock_calculate(struct sdw_slave *slave, |
468 | unsigned int clk_freq) |
469 | { |
470 | int x, y; |
471 | static const int max98373_clk_family[] = { |
472 | 7680000, 8400000, 9600000, 11289600, |
473 | 12000000, 12288000, 13000000 |
474 | }; |
475 | |
476 | for (x = 0; x < 4; x++) |
477 | for (y = 0; y < ARRAY_SIZE(max98373_clk_family); y++) |
478 | if (clk_freq == (max98373_clk_family[y] >> x)) |
479 | return (x << 3) + y; |
480 | |
481 | /* Set default clock (12.288 Mhz) if the value is not in the list */ |
482 | dev_err(&slave->dev, "Requested clock not found. (clk_freq = %d)\n" , |
483 | clk_freq); |
484 | return 0x5; |
485 | } |
486 | |
487 | static int max98373_clock_config(struct sdw_slave *slave, |
488 | struct sdw_bus_params *params) |
489 | { |
490 | struct device *dev = &slave->dev; |
491 | struct max98373_priv *max98373 = dev_get_drvdata(dev); |
492 | unsigned int clk_freq, value; |
493 | |
494 | clk_freq = (params->curr_dr_freq >> 1); |
495 | |
496 | /* |
497 | * Select the proper value for the register based on the |
498 | * requested clock. If the value is not in the list, |
499 | * use reasonable default - 12.288 Mhz |
500 | */ |
501 | value = max98373_clock_calculate(slave, clk_freq); |
502 | |
503 | /* SWCLK */ |
504 | regmap_write(map: max98373->regmap, MAX98373_R2036_SOUNDWIRE_CTRL, val: value); |
505 | |
506 | /* The default Sampling Rate value for IV is 48KHz*/ |
507 | regmap_write(map: max98373->regmap, MAX98373_R2028_PCM_SR_SETUP_2, val: 0x88); |
508 | |
509 | return 0; |
510 | } |
511 | |
512 | #define MAX98373_RATES SNDRV_PCM_RATE_8000_96000 |
513 | #define MAX98373_FORMATS (SNDRV_PCM_FMTBIT_S32_LE) |
514 | |
515 | static int max98373_sdw_dai_hw_params(struct snd_pcm_substream *substream, |
516 | struct snd_pcm_hw_params *params, |
517 | struct snd_soc_dai *dai) |
518 | { |
519 | struct snd_soc_component *component = dai->component; |
520 | struct max98373_priv *max98373 = |
521 | snd_soc_component_get_drvdata(c: component); |
522 | struct sdw_stream_config stream_config = {0}; |
523 | struct sdw_port_config port_config = {0}; |
524 | struct sdw_stream_runtime *sdw_stream; |
525 | int ret, chan_sz, sampling_rate; |
526 | |
527 | sdw_stream = snd_soc_dai_get_dma_data(dai, substream); |
528 | |
529 | if (!sdw_stream) |
530 | return -EINVAL; |
531 | |
532 | if (!max98373->slave) |
533 | return -EINVAL; |
534 | |
535 | snd_sdw_params_to_config(substream, params, stream_config: &stream_config, port_config: &port_config); |
536 | |
537 | if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { |
538 | port_config.num = 1; |
539 | |
540 | if (max98373->slot) { |
541 | stream_config.ch_count = max98373->slot; |
542 | port_config.ch_mask = max98373->rx_mask; |
543 | } |
544 | } else { |
545 | port_config.num = 3; |
546 | |
547 | /* only IV are supported by capture */ |
548 | stream_config.ch_count = 2; |
549 | port_config.ch_mask = GENMASK((int)stream_config.ch_count - 1, 0); |
550 | } |
551 | |
552 | ret = sdw_stream_add_slave(slave: max98373->slave, stream_config: &stream_config, |
553 | port_config: &port_config, num_ports: 1, stream: sdw_stream); |
554 | if (ret) { |
555 | dev_err(dai->dev, "Unable to configure port\n" ); |
556 | return ret; |
557 | } |
558 | |
559 | if (params_channels(p: params) > 16) { |
560 | dev_err(component->dev, "Unsupported channels %d\n" , |
561 | params_channels(params)); |
562 | return -EINVAL; |
563 | } |
564 | |
565 | /* Channel size configuration */ |
566 | switch (snd_pcm_format_width(format: params_format(p: params))) { |
567 | case 16: |
568 | chan_sz = MAX98373_PCM_MODE_CFG_CHANSZ_16; |
569 | break; |
570 | case 24: |
571 | chan_sz = MAX98373_PCM_MODE_CFG_CHANSZ_24; |
572 | break; |
573 | case 32: |
574 | chan_sz = MAX98373_PCM_MODE_CFG_CHANSZ_32; |
575 | break; |
576 | default: |
577 | dev_err(component->dev, "Channel size unsupported %d\n" , |
578 | params_format(params)); |
579 | return -EINVAL; |
580 | } |
581 | |
582 | max98373->ch_size = snd_pcm_format_width(format: params_format(p: params)); |
583 | |
584 | regmap_update_bits(map: max98373->regmap, |
585 | MAX98373_R2024_PCM_DATA_FMT_CFG, |
586 | MAX98373_PCM_MODE_CFG_CHANSZ_MASK, val: chan_sz); |
587 | |
588 | dev_dbg(component->dev, "Format supported %d" , params_format(params)); |
589 | |
590 | /* Sampling rate configuration */ |
591 | switch (params_rate(p: params)) { |
592 | case 8000: |
593 | sampling_rate = MAX98373_PCM_SR_SET1_SR_8000; |
594 | break; |
595 | case 11025: |
596 | sampling_rate = MAX98373_PCM_SR_SET1_SR_11025; |
597 | break; |
598 | case 12000: |
599 | sampling_rate = MAX98373_PCM_SR_SET1_SR_12000; |
600 | break; |
601 | case 16000: |
602 | sampling_rate = MAX98373_PCM_SR_SET1_SR_16000; |
603 | break; |
604 | case 22050: |
605 | sampling_rate = MAX98373_PCM_SR_SET1_SR_22050; |
606 | break; |
607 | case 24000: |
608 | sampling_rate = MAX98373_PCM_SR_SET1_SR_24000; |
609 | break; |
610 | case 32000: |
611 | sampling_rate = MAX98373_PCM_SR_SET1_SR_32000; |
612 | break; |
613 | case 44100: |
614 | sampling_rate = MAX98373_PCM_SR_SET1_SR_44100; |
615 | break; |
616 | case 48000: |
617 | sampling_rate = MAX98373_PCM_SR_SET1_SR_48000; |
618 | break; |
619 | case 88200: |
620 | sampling_rate = MAX98373_PCM_SR_SET1_SR_88200; |
621 | break; |
622 | case 96000: |
623 | sampling_rate = MAX98373_PCM_SR_SET1_SR_96000; |
624 | break; |
625 | default: |
626 | dev_err(component->dev, "Rate %d is not supported\n" , |
627 | params_rate(params)); |
628 | return -EINVAL; |
629 | } |
630 | |
631 | /* set correct sampling frequency */ |
632 | regmap_update_bits(map: max98373->regmap, |
633 | MAX98373_R2028_PCM_SR_SETUP_2, |
634 | MAX98373_PCM_SR_SET2_SR_MASK, |
635 | val: sampling_rate << MAX98373_PCM_SR_SET2_SR_SHIFT); |
636 | |
637 | /* set sampling rate of IV */ |
638 | regmap_update_bits(map: max98373->regmap, |
639 | MAX98373_R2028_PCM_SR_SETUP_2, |
640 | MAX98373_PCM_SR_SET2_IVADC_SR_MASK, |
641 | val: sampling_rate); |
642 | |
643 | return 0; |
644 | } |
645 | |
646 | static int max98373_pcm_hw_free(struct snd_pcm_substream *substream, |
647 | struct snd_soc_dai *dai) |
648 | { |
649 | struct snd_soc_component *component = dai->component; |
650 | struct max98373_priv *max98373 = |
651 | snd_soc_component_get_drvdata(c: component); |
652 | struct sdw_stream_runtime *sdw_stream = |
653 | snd_soc_dai_get_dma_data(dai, substream); |
654 | |
655 | if (!max98373->slave) |
656 | return -EINVAL; |
657 | |
658 | sdw_stream_remove_slave(slave: max98373->slave, stream: sdw_stream); |
659 | return 0; |
660 | } |
661 | |
662 | static int max98373_set_sdw_stream(struct snd_soc_dai *dai, |
663 | void *sdw_stream, int direction) |
664 | { |
665 | snd_soc_dai_dma_data_set(dai, stream: direction, data: sdw_stream); |
666 | |
667 | return 0; |
668 | } |
669 | |
670 | static void max98373_shutdown(struct snd_pcm_substream *substream, |
671 | struct snd_soc_dai *dai) |
672 | { |
673 | snd_soc_dai_set_dma_data(dai, substream, NULL); |
674 | } |
675 | |
676 | static int max98373_sdw_set_tdm_slot(struct snd_soc_dai *dai, |
677 | unsigned int tx_mask, |
678 | unsigned int rx_mask, |
679 | int slots, int slot_width) |
680 | { |
681 | struct snd_soc_component *component = dai->component; |
682 | struct max98373_priv *max98373 = |
683 | snd_soc_component_get_drvdata(c: component); |
684 | |
685 | /* tx_mask is unused since it's irrelevant for I/V feedback */ |
686 | if (tx_mask) |
687 | return -EINVAL; |
688 | |
689 | if (!rx_mask && !slots && !slot_width) |
690 | max98373->tdm_mode = false; |
691 | else |
692 | max98373->tdm_mode = true; |
693 | |
694 | max98373->rx_mask = rx_mask; |
695 | max98373->slot = slots; |
696 | |
697 | return 0; |
698 | } |
699 | |
700 | static const struct snd_soc_dai_ops max98373_dai_sdw_ops = { |
701 | .hw_params = max98373_sdw_dai_hw_params, |
702 | .hw_free = max98373_pcm_hw_free, |
703 | .set_stream = max98373_set_sdw_stream, |
704 | .shutdown = max98373_shutdown, |
705 | .set_tdm_slot = max98373_sdw_set_tdm_slot, |
706 | }; |
707 | |
708 | static struct snd_soc_dai_driver max98373_sdw_dai[] = { |
709 | { |
710 | .name = "max98373-aif1" , |
711 | .playback = { |
712 | .stream_name = "HiFi Playback" , |
713 | .channels_min = 1, |
714 | .channels_max = 2, |
715 | .rates = MAX98373_RATES, |
716 | .formats = MAX98373_FORMATS, |
717 | }, |
718 | .capture = { |
719 | .stream_name = "HiFi Capture" , |
720 | .channels_min = 1, |
721 | .channels_max = 2, |
722 | .rates = MAX98373_RATES, |
723 | .formats = MAX98373_FORMATS, |
724 | }, |
725 | .ops = &max98373_dai_sdw_ops, |
726 | } |
727 | }; |
728 | |
729 | static int max98373_init(struct sdw_slave *slave, struct regmap *regmap) |
730 | { |
731 | struct max98373_priv *max98373; |
732 | int ret; |
733 | int i; |
734 | struct device *dev = &slave->dev; |
735 | |
736 | /* Allocate and assign private driver data structure */ |
737 | max98373 = devm_kzalloc(dev, size: sizeof(*max98373), GFP_KERNEL); |
738 | if (!max98373) |
739 | return -ENOMEM; |
740 | |
741 | dev_set_drvdata(dev, data: max98373); |
742 | max98373->regmap = regmap; |
743 | max98373->slave = slave; |
744 | |
745 | regcache_cache_only(map: max98373->regmap, enable: true); |
746 | |
747 | max98373->cache_num = ARRAY_SIZE(max98373_sdw_cache_reg); |
748 | max98373->cache = devm_kcalloc(dev, n: max98373->cache_num, |
749 | size: sizeof(*max98373->cache), |
750 | GFP_KERNEL); |
751 | if (!max98373->cache) |
752 | return -ENOMEM; |
753 | |
754 | for (i = 0; i < max98373->cache_num; i++) |
755 | max98373->cache[i].reg = max98373_sdw_cache_reg[i]; |
756 | |
757 | /* Read voltage and slot configuration */ |
758 | max98373_slot_config(dev, max98373); |
759 | |
760 | max98373->hw_init = false; |
761 | max98373->first_hw_init = false; |
762 | |
763 | /* codec registration */ |
764 | ret = devm_snd_soc_register_component(dev, component_driver: &soc_codec_dev_max98373_sdw, |
765 | dai_drv: max98373_sdw_dai, |
766 | ARRAY_SIZE(max98373_sdw_dai)); |
767 | if (ret < 0) { |
768 | dev_err(dev, "Failed to register codec: %d\n" , ret); |
769 | return ret; |
770 | } |
771 | |
772 | /* set autosuspend parameters */ |
773 | pm_runtime_set_autosuspend_delay(dev, delay: 3000); |
774 | pm_runtime_use_autosuspend(dev); |
775 | |
776 | /* make sure the device does not suspend immediately */ |
777 | pm_runtime_mark_last_busy(dev); |
778 | |
779 | pm_runtime_enable(dev); |
780 | |
781 | /* important note: the device is NOT tagged as 'active' and will remain |
782 | * 'suspended' until the hardware is enumerated/initialized. This is required |
783 | * to make sure the ASoC framework use of pm_runtime_get_sync() does not silently |
784 | * fail with -EACCESS because of race conditions between card creation and enumeration |
785 | */ |
786 | |
787 | return 0; |
788 | } |
789 | |
790 | static int max98373_update_status(struct sdw_slave *slave, |
791 | enum sdw_slave_status status) |
792 | { |
793 | struct max98373_priv *max98373 = dev_get_drvdata(dev: &slave->dev); |
794 | |
795 | if (status == SDW_SLAVE_UNATTACHED) |
796 | max98373->hw_init = false; |
797 | |
798 | /* |
799 | * Perform initialization only if slave status is SDW_SLAVE_ATTACHED |
800 | */ |
801 | if (max98373->hw_init || status != SDW_SLAVE_ATTACHED) |
802 | return 0; |
803 | |
804 | /* perform I/O transfers required for Slave initialization */ |
805 | return max98373_io_init(slave); |
806 | } |
807 | |
808 | static int max98373_bus_config(struct sdw_slave *slave, |
809 | struct sdw_bus_params *params) |
810 | { |
811 | int ret; |
812 | |
813 | ret = max98373_clock_config(slave, params); |
814 | if (ret < 0) |
815 | dev_err(&slave->dev, "Invalid clk config" ); |
816 | |
817 | return ret; |
818 | } |
819 | |
820 | /* |
821 | * slave_ops: callbacks for get_clock_stop_mode, clock_stop and |
822 | * port_prep are not defined for now |
823 | */ |
824 | static const struct sdw_slave_ops max98373_slave_ops = { |
825 | .read_prop = max98373_read_prop, |
826 | .update_status = max98373_update_status, |
827 | .bus_config = max98373_bus_config, |
828 | }; |
829 | |
830 | static int max98373_sdw_probe(struct sdw_slave *slave, |
831 | const struct sdw_device_id *id) |
832 | { |
833 | struct regmap *regmap; |
834 | |
835 | /* Regmap Initialization */ |
836 | regmap = devm_regmap_init_sdw(slave, &max98373_sdw_regmap); |
837 | if (IS_ERR(ptr: regmap)) |
838 | return PTR_ERR(ptr: regmap); |
839 | |
840 | return max98373_init(slave, regmap); |
841 | } |
842 | |
843 | static int max98373_sdw_remove(struct sdw_slave *slave) |
844 | { |
845 | pm_runtime_disable(dev: &slave->dev); |
846 | |
847 | return 0; |
848 | } |
849 | |
850 | #if defined(CONFIG_OF) |
851 | static const struct of_device_id max98373_of_match[] = { |
852 | { .compatible = "maxim,max98373" , }, |
853 | {}, |
854 | }; |
855 | MODULE_DEVICE_TABLE(of, max98373_of_match); |
856 | #endif |
857 | |
858 | #ifdef CONFIG_ACPI |
859 | static const struct acpi_device_id max98373_acpi_match[] = { |
860 | { "MX98373" , 0 }, |
861 | {}, |
862 | }; |
863 | MODULE_DEVICE_TABLE(acpi, max98373_acpi_match); |
864 | #endif |
865 | |
866 | static const struct sdw_device_id max98373_id[] = { |
867 | SDW_SLAVE_ENTRY(0x019F, 0x8373, 0), |
868 | {}, |
869 | }; |
870 | MODULE_DEVICE_TABLE(sdw, max98373_id); |
871 | |
872 | static struct sdw_driver max98373_sdw_driver = { |
873 | .driver = { |
874 | .name = "max98373" , |
875 | .owner = THIS_MODULE, |
876 | .of_match_table = of_match_ptr(max98373_of_match), |
877 | .acpi_match_table = ACPI_PTR(max98373_acpi_match), |
878 | .pm = &max98373_pm, |
879 | }, |
880 | .probe = max98373_sdw_probe, |
881 | .remove = max98373_sdw_remove, |
882 | .ops = &max98373_slave_ops, |
883 | .id_table = max98373_id, |
884 | }; |
885 | |
886 | module_sdw_driver(max98373_sdw_driver); |
887 | |
888 | MODULE_DESCRIPTION("ASoC MAX98373 driver SDW" ); |
889 | MODULE_AUTHOR("Oleg Sherbakov <oleg.sherbakov@maximintegrated.com>" ); |
890 | MODULE_LICENSE("GPL v2" ); |
891 | |