1 | // SPDX-License-Identifier: GPL-2.0-only |
2 | /* |
3 | * Driver for the PCM512x CODECs |
4 | * |
5 | * Author: Mark Brown <broonie@kernel.org> |
6 | * Copyright 2014 Linaro Ltd |
7 | */ |
8 | |
9 | |
10 | #include <linux/init.h> |
11 | #include <linux/module.h> |
12 | #include <linux/clk.h> |
13 | #include <linux/kernel.h> |
14 | #include <linux/pm_runtime.h> |
15 | #include <linux/regmap.h> |
16 | #include <linux/regulator/consumer.h> |
17 | #include <linux/gcd.h> |
18 | #include <sound/soc.h> |
19 | #include <sound/soc-dapm.h> |
20 | #include <sound/pcm_params.h> |
21 | #include <sound/tlv.h> |
22 | |
23 | #include "pcm512x.h" |
24 | |
25 | #define PCM512x_NUM_SUPPLIES 3 |
26 | static const char * const pcm512x_supply_names[PCM512x_NUM_SUPPLIES] = { |
27 | "AVDD" , |
28 | "DVDD" , |
29 | "CPVDD" , |
30 | }; |
31 | |
32 | struct pcm512x_priv { |
33 | struct regmap *regmap; |
34 | struct clk *sclk; |
35 | struct regulator_bulk_data supplies[PCM512x_NUM_SUPPLIES]; |
36 | struct notifier_block supply_nb[PCM512x_NUM_SUPPLIES]; |
37 | int fmt; |
38 | int pll_in; |
39 | int pll_out; |
40 | int pll_r; |
41 | int pll_j; |
42 | int pll_d; |
43 | int pll_p; |
44 | unsigned long real_pll; |
45 | unsigned long overclock_pll; |
46 | unsigned long overclock_dac; |
47 | unsigned long overclock_dsp; |
48 | int mute; |
49 | struct mutex mutex; |
50 | unsigned int bclk_ratio; |
51 | int force_pll_on; |
52 | }; |
53 | |
54 | /* |
55 | * We can't use the same notifier block for more than one supply and |
56 | * there's no way I can see to get from a callback to the caller |
57 | * except container_of(). |
58 | */ |
59 | #define PCM512x_REGULATOR_EVENT(n) \ |
60 | static int pcm512x_regulator_event_##n(struct notifier_block *nb, \ |
61 | unsigned long event, void *data) \ |
62 | { \ |
63 | struct pcm512x_priv *pcm512x = container_of(nb, struct pcm512x_priv, \ |
64 | supply_nb[n]); \ |
65 | if (event & REGULATOR_EVENT_DISABLE) { \ |
66 | regcache_mark_dirty(pcm512x->regmap); \ |
67 | regcache_cache_only(pcm512x->regmap, true); \ |
68 | } \ |
69 | return 0; \ |
70 | } |
71 | |
72 | PCM512x_REGULATOR_EVENT(0) |
73 | PCM512x_REGULATOR_EVENT(1) |
74 | PCM512x_REGULATOR_EVENT(2) |
75 | |
76 | static const struct reg_default pcm512x_reg_defaults[] = { |
77 | { PCM512x_RESET, 0x00 }, |
78 | { PCM512x_POWER, 0x00 }, |
79 | { PCM512x_MUTE, 0x00 }, |
80 | { PCM512x_DSP, 0x00 }, |
81 | { PCM512x_PLL_REF, 0x00 }, |
82 | { PCM512x_DAC_REF, 0x00 }, |
83 | { PCM512x_DAC_ROUTING, 0x11 }, |
84 | { PCM512x_DSP_PROGRAM, 0x01 }, |
85 | { PCM512x_CLKDET, 0x00 }, |
86 | { PCM512x_AUTO_MUTE, 0x00 }, |
87 | { PCM512x_ERROR_DETECT, 0x00 }, |
88 | { PCM512x_DIGITAL_VOLUME_1, 0x00 }, |
89 | { PCM512x_DIGITAL_VOLUME_2, 0x30 }, |
90 | { PCM512x_DIGITAL_VOLUME_3, 0x30 }, |
91 | { PCM512x_DIGITAL_MUTE_1, 0x22 }, |
92 | { PCM512x_DIGITAL_MUTE_2, 0x00 }, |
93 | { PCM512x_DIGITAL_MUTE_3, 0x07 }, |
94 | { PCM512x_OUTPUT_AMPLITUDE, 0x00 }, |
95 | { PCM512x_ANALOG_GAIN_CTRL, 0x00 }, |
96 | { PCM512x_UNDERVOLTAGE_PROT, 0x00 }, |
97 | { PCM512x_ANALOG_MUTE_CTRL, 0x00 }, |
98 | { PCM512x_ANALOG_GAIN_BOOST, 0x00 }, |
99 | { PCM512x_VCOM_CTRL_1, 0x00 }, |
100 | { PCM512x_VCOM_CTRL_2, 0x01 }, |
101 | { PCM512x_BCLK_LRCLK_CFG, 0x00 }, |
102 | { PCM512x_MASTER_MODE, 0x7c }, |
103 | { PCM512x_GPIO_DACIN, 0x00 }, |
104 | { PCM512x_GPIO_PLLIN, 0x00 }, |
105 | { PCM512x_SYNCHRONIZE, 0x10 }, |
106 | { PCM512x_PLL_COEFF_0, 0x00 }, |
107 | { PCM512x_PLL_COEFF_1, 0x00 }, |
108 | { PCM512x_PLL_COEFF_2, 0x00 }, |
109 | { PCM512x_PLL_COEFF_3, 0x00 }, |
110 | { PCM512x_PLL_COEFF_4, 0x00 }, |
111 | { PCM512x_DSP_CLKDIV, 0x00 }, |
112 | { PCM512x_DAC_CLKDIV, 0x00 }, |
113 | { PCM512x_NCP_CLKDIV, 0x00 }, |
114 | { PCM512x_OSR_CLKDIV, 0x00 }, |
115 | { PCM512x_MASTER_CLKDIV_1, 0x00 }, |
116 | { PCM512x_MASTER_CLKDIV_2, 0x00 }, |
117 | { PCM512x_FS_SPEED_MODE, 0x00 }, |
118 | { PCM512x_IDAC_1, 0x01 }, |
119 | { PCM512x_IDAC_2, 0x00 }, |
120 | { PCM512x_I2S_1, 0x02 }, |
121 | { PCM512x_I2S_2, 0x00 }, |
122 | }; |
123 | |
124 | static bool pcm512x_readable(struct device *dev, unsigned int reg) |
125 | { |
126 | switch (reg) { |
127 | case PCM512x_RESET: |
128 | case PCM512x_POWER: |
129 | case PCM512x_MUTE: |
130 | case PCM512x_PLL_EN: |
131 | case PCM512x_SPI_MISO_FUNCTION: |
132 | case PCM512x_DSP: |
133 | case PCM512x_GPIO_EN: |
134 | case PCM512x_BCLK_LRCLK_CFG: |
135 | case PCM512x_DSP_GPIO_INPUT: |
136 | case PCM512x_MASTER_MODE: |
137 | case PCM512x_PLL_REF: |
138 | case PCM512x_DAC_REF: |
139 | case PCM512x_GPIO_DACIN: |
140 | case PCM512x_GPIO_PLLIN: |
141 | case PCM512x_SYNCHRONIZE: |
142 | case PCM512x_PLL_COEFF_0: |
143 | case PCM512x_PLL_COEFF_1: |
144 | case PCM512x_PLL_COEFF_2: |
145 | case PCM512x_PLL_COEFF_3: |
146 | case PCM512x_PLL_COEFF_4: |
147 | case PCM512x_DSP_CLKDIV: |
148 | case PCM512x_DAC_CLKDIV: |
149 | case PCM512x_NCP_CLKDIV: |
150 | case PCM512x_OSR_CLKDIV: |
151 | case PCM512x_MASTER_CLKDIV_1: |
152 | case PCM512x_MASTER_CLKDIV_2: |
153 | case PCM512x_FS_SPEED_MODE: |
154 | case PCM512x_IDAC_1: |
155 | case PCM512x_IDAC_2: |
156 | case PCM512x_ERROR_DETECT: |
157 | case PCM512x_I2S_1: |
158 | case PCM512x_I2S_2: |
159 | case PCM512x_DAC_ROUTING: |
160 | case PCM512x_DSP_PROGRAM: |
161 | case PCM512x_CLKDET: |
162 | case PCM512x_AUTO_MUTE: |
163 | case PCM512x_DIGITAL_VOLUME_1: |
164 | case PCM512x_DIGITAL_VOLUME_2: |
165 | case PCM512x_DIGITAL_VOLUME_3: |
166 | case PCM512x_DIGITAL_MUTE_1: |
167 | case PCM512x_DIGITAL_MUTE_2: |
168 | case PCM512x_DIGITAL_MUTE_3: |
169 | case PCM512x_GPIO_OUTPUT_1: |
170 | case PCM512x_GPIO_OUTPUT_2: |
171 | case PCM512x_GPIO_OUTPUT_3: |
172 | case PCM512x_GPIO_OUTPUT_4: |
173 | case PCM512x_GPIO_OUTPUT_5: |
174 | case PCM512x_GPIO_OUTPUT_6: |
175 | case PCM512x_GPIO_CONTROL_1: |
176 | case PCM512x_GPIO_CONTROL_2: |
177 | case PCM512x_OVERFLOW: |
178 | case PCM512x_RATE_DET_1: |
179 | case PCM512x_RATE_DET_2: |
180 | case PCM512x_RATE_DET_3: |
181 | case PCM512x_RATE_DET_4: |
182 | case PCM512x_CLOCK_STATUS: |
183 | case PCM512x_ANALOG_MUTE_DET: |
184 | case PCM512x_GPIN: |
185 | case PCM512x_DIGITAL_MUTE_DET: |
186 | case PCM512x_OUTPUT_AMPLITUDE: |
187 | case PCM512x_ANALOG_GAIN_CTRL: |
188 | case PCM512x_UNDERVOLTAGE_PROT: |
189 | case PCM512x_ANALOG_MUTE_CTRL: |
190 | case PCM512x_ANALOG_GAIN_BOOST: |
191 | case PCM512x_VCOM_CTRL_1: |
192 | case PCM512x_VCOM_CTRL_2: |
193 | case PCM512x_CRAM_CTRL: |
194 | case PCM512x_FLEX_A: |
195 | case PCM512x_FLEX_B: |
196 | return true; |
197 | default: |
198 | /* There are 256 raw register addresses */ |
199 | return reg < 0xff; |
200 | } |
201 | } |
202 | |
203 | static bool pcm512x_volatile(struct device *dev, unsigned int reg) |
204 | { |
205 | switch (reg) { |
206 | case PCM512x_PLL_EN: |
207 | case PCM512x_OVERFLOW: |
208 | case PCM512x_RATE_DET_1: |
209 | case PCM512x_RATE_DET_2: |
210 | case PCM512x_RATE_DET_3: |
211 | case PCM512x_RATE_DET_4: |
212 | case PCM512x_CLOCK_STATUS: |
213 | case PCM512x_ANALOG_MUTE_DET: |
214 | case PCM512x_GPIN: |
215 | case PCM512x_DIGITAL_MUTE_DET: |
216 | case PCM512x_CRAM_CTRL: |
217 | return true; |
218 | default: |
219 | /* There are 256 raw register addresses */ |
220 | return reg < 0xff; |
221 | } |
222 | } |
223 | |
224 | static int pcm512x_overclock_pll_get(struct snd_kcontrol *kcontrol, |
225 | struct snd_ctl_elem_value *ucontrol) |
226 | { |
227 | struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); |
228 | struct pcm512x_priv *pcm512x = snd_soc_component_get_drvdata(c: component); |
229 | |
230 | ucontrol->value.integer.value[0] = pcm512x->overclock_pll; |
231 | return 0; |
232 | } |
233 | |
234 | static int pcm512x_overclock_pll_put(struct snd_kcontrol *kcontrol, |
235 | struct snd_ctl_elem_value *ucontrol) |
236 | { |
237 | struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); |
238 | struct pcm512x_priv *pcm512x = snd_soc_component_get_drvdata(c: component); |
239 | |
240 | switch (snd_soc_component_get_bias_level(component)) { |
241 | case SND_SOC_BIAS_OFF: |
242 | case SND_SOC_BIAS_STANDBY: |
243 | break; |
244 | default: |
245 | return -EBUSY; |
246 | } |
247 | |
248 | pcm512x->overclock_pll = ucontrol->value.integer.value[0]; |
249 | return 0; |
250 | } |
251 | |
252 | static int pcm512x_overclock_dsp_get(struct snd_kcontrol *kcontrol, |
253 | struct snd_ctl_elem_value *ucontrol) |
254 | { |
255 | struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); |
256 | struct pcm512x_priv *pcm512x = snd_soc_component_get_drvdata(c: component); |
257 | |
258 | ucontrol->value.integer.value[0] = pcm512x->overclock_dsp; |
259 | return 0; |
260 | } |
261 | |
262 | static int pcm512x_overclock_dsp_put(struct snd_kcontrol *kcontrol, |
263 | struct snd_ctl_elem_value *ucontrol) |
264 | { |
265 | struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); |
266 | struct pcm512x_priv *pcm512x = snd_soc_component_get_drvdata(c: component); |
267 | |
268 | switch (snd_soc_component_get_bias_level(component)) { |
269 | case SND_SOC_BIAS_OFF: |
270 | case SND_SOC_BIAS_STANDBY: |
271 | break; |
272 | default: |
273 | return -EBUSY; |
274 | } |
275 | |
276 | pcm512x->overclock_dsp = ucontrol->value.integer.value[0]; |
277 | return 0; |
278 | } |
279 | |
280 | static int pcm512x_overclock_dac_get(struct snd_kcontrol *kcontrol, |
281 | struct snd_ctl_elem_value *ucontrol) |
282 | { |
283 | struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); |
284 | struct pcm512x_priv *pcm512x = snd_soc_component_get_drvdata(c: component); |
285 | |
286 | ucontrol->value.integer.value[0] = pcm512x->overclock_dac; |
287 | return 0; |
288 | } |
289 | |
290 | static int pcm512x_overclock_dac_put(struct snd_kcontrol *kcontrol, |
291 | struct snd_ctl_elem_value *ucontrol) |
292 | { |
293 | struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); |
294 | struct pcm512x_priv *pcm512x = snd_soc_component_get_drvdata(c: component); |
295 | |
296 | switch (snd_soc_component_get_bias_level(component)) { |
297 | case SND_SOC_BIAS_OFF: |
298 | case SND_SOC_BIAS_STANDBY: |
299 | break; |
300 | default: |
301 | return -EBUSY; |
302 | } |
303 | |
304 | pcm512x->overclock_dac = ucontrol->value.integer.value[0]; |
305 | return 0; |
306 | } |
307 | |
308 | static const DECLARE_TLV_DB_SCALE(digital_tlv, -10350, 50, 1); |
309 | static const DECLARE_TLV_DB_SCALE(analog_tlv, -600, 600, 0); |
310 | static const DECLARE_TLV_DB_SCALE(boost_tlv, 0, 80, 0); |
311 | |
312 | static const char * const pcm512x_dsp_program_texts[] = { |
313 | "FIR interpolation with de-emphasis" , |
314 | "Low latency IIR with de-emphasis" , |
315 | "High attenuation with de-emphasis" , |
316 | "Fixed process flow" , |
317 | "Ringing-less low latency FIR" , |
318 | }; |
319 | |
320 | static const unsigned int pcm512x_dsp_program_values[] = { |
321 | 1, |
322 | 2, |
323 | 3, |
324 | 5, |
325 | 7, |
326 | }; |
327 | |
328 | static SOC_VALUE_ENUM_SINGLE_DECL(pcm512x_dsp_program, |
329 | PCM512x_DSP_PROGRAM, 0, 0x1f, |
330 | pcm512x_dsp_program_texts, |
331 | pcm512x_dsp_program_values); |
332 | |
333 | static const char * const pcm512x_clk_missing_text[] = { |
334 | "1s" , "2s" , "3s" , "4s" , "5s" , "6s" , "7s" , "8s" |
335 | }; |
336 | |
337 | static const struct soc_enum pcm512x_clk_missing = |
338 | SOC_ENUM_SINGLE(PCM512x_CLKDET, 0, 8, pcm512x_clk_missing_text); |
339 | |
340 | static const char * const pcm512x_autom_text[] = { |
341 | "21ms" , "106ms" , "213ms" , "533ms" , "1.07s" , "2.13s" , "5.33s" , "10.66s" |
342 | }; |
343 | |
344 | static const struct soc_enum pcm512x_autom_l = |
345 | SOC_ENUM_SINGLE(PCM512x_AUTO_MUTE, PCM512x_ATML_SHIFT, 8, |
346 | pcm512x_autom_text); |
347 | |
348 | static const struct soc_enum pcm512x_autom_r = |
349 | SOC_ENUM_SINGLE(PCM512x_AUTO_MUTE, PCM512x_ATMR_SHIFT, 8, |
350 | pcm512x_autom_text); |
351 | |
352 | static const char * const pcm512x_ramp_rate_text[] = { |
353 | "1 sample/update" , "2 samples/update" , "4 samples/update" , |
354 | "Immediate" |
355 | }; |
356 | |
357 | static const struct soc_enum pcm512x_vndf = |
358 | SOC_ENUM_SINGLE(PCM512x_DIGITAL_MUTE_1, PCM512x_VNDF_SHIFT, 4, |
359 | pcm512x_ramp_rate_text); |
360 | |
361 | static const struct soc_enum pcm512x_vnuf = |
362 | SOC_ENUM_SINGLE(PCM512x_DIGITAL_MUTE_1, PCM512x_VNUF_SHIFT, 4, |
363 | pcm512x_ramp_rate_text); |
364 | |
365 | static const struct soc_enum pcm512x_vedf = |
366 | SOC_ENUM_SINGLE(PCM512x_DIGITAL_MUTE_2, PCM512x_VEDF_SHIFT, 4, |
367 | pcm512x_ramp_rate_text); |
368 | |
369 | static const char * const pcm512x_ramp_step_text[] = { |
370 | "4dB/step" , "2dB/step" , "1dB/step" , "0.5dB/step" |
371 | }; |
372 | |
373 | static const struct soc_enum pcm512x_vnds = |
374 | SOC_ENUM_SINGLE(PCM512x_DIGITAL_MUTE_1, PCM512x_VNDS_SHIFT, 4, |
375 | pcm512x_ramp_step_text); |
376 | |
377 | static const struct soc_enum pcm512x_vnus = |
378 | SOC_ENUM_SINGLE(PCM512x_DIGITAL_MUTE_1, PCM512x_VNUS_SHIFT, 4, |
379 | pcm512x_ramp_step_text); |
380 | |
381 | static const struct soc_enum pcm512x_veds = |
382 | SOC_ENUM_SINGLE(PCM512x_DIGITAL_MUTE_2, PCM512x_VEDS_SHIFT, 4, |
383 | pcm512x_ramp_step_text); |
384 | |
385 | static int pcm512x_update_mute(struct pcm512x_priv *pcm512x) |
386 | { |
387 | return regmap_update_bits( |
388 | map: pcm512x->regmap, PCM512x_MUTE, PCM512x_RQML | PCM512x_RQMR, |
389 | val: (!!(pcm512x->mute & 0x5) << PCM512x_RQML_SHIFT) |
390 | | (!!(pcm512x->mute & 0x3) << PCM512x_RQMR_SHIFT)); |
391 | } |
392 | |
393 | static int pcm512x_digital_playback_switch_get(struct snd_kcontrol *kcontrol, |
394 | struct snd_ctl_elem_value *ucontrol) |
395 | { |
396 | struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); |
397 | struct pcm512x_priv *pcm512x = snd_soc_component_get_drvdata(c: component); |
398 | |
399 | mutex_lock(&pcm512x->mutex); |
400 | ucontrol->value.integer.value[0] = !(pcm512x->mute & 0x4); |
401 | ucontrol->value.integer.value[1] = !(pcm512x->mute & 0x2); |
402 | mutex_unlock(lock: &pcm512x->mutex); |
403 | |
404 | return 0; |
405 | } |
406 | |
407 | static int pcm512x_digital_playback_switch_put(struct snd_kcontrol *kcontrol, |
408 | struct snd_ctl_elem_value *ucontrol) |
409 | { |
410 | struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); |
411 | struct pcm512x_priv *pcm512x = snd_soc_component_get_drvdata(c: component); |
412 | int ret, changed = 0; |
413 | |
414 | mutex_lock(&pcm512x->mutex); |
415 | |
416 | if ((pcm512x->mute & 0x4) == (ucontrol->value.integer.value[0] << 2)) { |
417 | pcm512x->mute ^= 0x4; |
418 | changed = 1; |
419 | } |
420 | if ((pcm512x->mute & 0x2) == (ucontrol->value.integer.value[1] << 1)) { |
421 | pcm512x->mute ^= 0x2; |
422 | changed = 1; |
423 | } |
424 | |
425 | if (changed) { |
426 | ret = pcm512x_update_mute(pcm512x); |
427 | if (ret != 0) { |
428 | dev_err(component->dev, |
429 | "Failed to update digital mute: %d\n" , ret); |
430 | mutex_unlock(lock: &pcm512x->mutex); |
431 | return ret; |
432 | } |
433 | } |
434 | |
435 | mutex_unlock(lock: &pcm512x->mutex); |
436 | |
437 | return changed; |
438 | } |
439 | |
440 | static const struct snd_kcontrol_new pcm512x_controls[] = { |
441 | SOC_DOUBLE_R_TLV("Digital Playback Volume" , PCM512x_DIGITAL_VOLUME_2, |
442 | PCM512x_DIGITAL_VOLUME_3, 0, 255, 1, digital_tlv), |
443 | SOC_DOUBLE_TLV("Analogue Playback Volume" , PCM512x_ANALOG_GAIN_CTRL, |
444 | PCM512x_LAGN_SHIFT, PCM512x_RAGN_SHIFT, 1, 1, analog_tlv), |
445 | SOC_DOUBLE_TLV("Analogue Playback Boost Volume" , PCM512x_ANALOG_GAIN_BOOST, |
446 | PCM512x_AGBL_SHIFT, PCM512x_AGBR_SHIFT, 1, 0, boost_tlv), |
447 | { |
448 | .iface = SNDRV_CTL_ELEM_IFACE_MIXER, |
449 | .name = "Digital Playback Switch" , |
450 | .index = 0, |
451 | .access = SNDRV_CTL_ELEM_ACCESS_READWRITE, |
452 | .info = snd_ctl_boolean_stereo_info, |
453 | .get = pcm512x_digital_playback_switch_get, |
454 | .put = pcm512x_digital_playback_switch_put |
455 | }, |
456 | |
457 | SOC_SINGLE("Deemphasis Switch" , PCM512x_DSP, PCM512x_DEMP_SHIFT, 1, 1), |
458 | SOC_ENUM("DSP Program" , pcm512x_dsp_program), |
459 | |
460 | SOC_ENUM("Clock Missing Period" , pcm512x_clk_missing), |
461 | SOC_ENUM("Auto Mute Time Left" , pcm512x_autom_l), |
462 | SOC_ENUM("Auto Mute Time Right" , pcm512x_autom_r), |
463 | SOC_SINGLE("Auto Mute Mono Switch" , PCM512x_DIGITAL_MUTE_3, |
464 | PCM512x_ACTL_SHIFT, 1, 0), |
465 | SOC_DOUBLE("Auto Mute Switch" , PCM512x_DIGITAL_MUTE_3, PCM512x_AMLE_SHIFT, |
466 | PCM512x_AMRE_SHIFT, 1, 0), |
467 | |
468 | SOC_ENUM("Volume Ramp Down Rate" , pcm512x_vndf), |
469 | SOC_ENUM("Volume Ramp Down Step" , pcm512x_vnds), |
470 | SOC_ENUM("Volume Ramp Up Rate" , pcm512x_vnuf), |
471 | SOC_ENUM("Volume Ramp Up Step" , pcm512x_vnus), |
472 | SOC_ENUM("Volume Ramp Down Emergency Rate" , pcm512x_vedf), |
473 | SOC_ENUM("Volume Ramp Down Emergency Step" , pcm512x_veds), |
474 | |
475 | SOC_SINGLE_EXT("Max Overclock PLL" , SND_SOC_NOPM, 0, 20, 0, |
476 | pcm512x_overclock_pll_get, pcm512x_overclock_pll_put), |
477 | SOC_SINGLE_EXT("Max Overclock DSP" , SND_SOC_NOPM, 0, 40, 0, |
478 | pcm512x_overclock_dsp_get, pcm512x_overclock_dsp_put), |
479 | SOC_SINGLE_EXT("Max Overclock DAC" , SND_SOC_NOPM, 0, 40, 0, |
480 | pcm512x_overclock_dac_get, pcm512x_overclock_dac_put), |
481 | }; |
482 | |
483 | static const struct snd_soc_dapm_widget pcm512x_dapm_widgets[] = { |
484 | SND_SOC_DAPM_DAC("DACL" , NULL, SND_SOC_NOPM, 0, 0), |
485 | SND_SOC_DAPM_DAC("DACR" , NULL, SND_SOC_NOPM, 0, 0), |
486 | |
487 | SND_SOC_DAPM_OUTPUT("OUTL" ), |
488 | SND_SOC_DAPM_OUTPUT("OUTR" ), |
489 | }; |
490 | |
491 | static const struct snd_soc_dapm_route pcm512x_dapm_routes[] = { |
492 | { "DACL" , NULL, "Playback" }, |
493 | { "DACR" , NULL, "Playback" }, |
494 | |
495 | { "OUTL" , NULL, "DACL" }, |
496 | { "OUTR" , NULL, "DACR" }, |
497 | }; |
498 | |
499 | static unsigned long pcm512x_pll_max(struct pcm512x_priv *pcm512x) |
500 | { |
501 | return 25000000 + 25000000 * pcm512x->overclock_pll / 100; |
502 | } |
503 | |
504 | static unsigned long pcm512x_dsp_max(struct pcm512x_priv *pcm512x) |
505 | { |
506 | return 50000000 + 50000000 * pcm512x->overclock_dsp / 100; |
507 | } |
508 | |
509 | static unsigned long pcm512x_dac_max(struct pcm512x_priv *pcm512x, |
510 | unsigned long rate) |
511 | { |
512 | return rate + rate * pcm512x->overclock_dac / 100; |
513 | } |
514 | |
515 | static unsigned long pcm512x_sck_max(struct pcm512x_priv *pcm512x) |
516 | { |
517 | if (!pcm512x->pll_out) |
518 | return 25000000; |
519 | return pcm512x_pll_max(pcm512x); |
520 | } |
521 | |
522 | static unsigned long pcm512x_ncp_target(struct pcm512x_priv *pcm512x, |
523 | unsigned long dac_rate) |
524 | { |
525 | /* |
526 | * If the DAC is not actually overclocked, use the good old |
527 | * NCP target rate... |
528 | */ |
529 | if (dac_rate <= 6144000) |
530 | return 1536000; |
531 | /* |
532 | * ...but if the DAC is in fact overclocked, bump the NCP target |
533 | * rate to get the recommended dividers even when overclocking. |
534 | */ |
535 | return pcm512x_dac_max(pcm512x, rate: 1536000); |
536 | } |
537 | |
538 | static const u32 pcm512x_dai_rates[] = { |
539 | 8000, 11025, 16000, 22050, 32000, 44100, 48000, 64000, |
540 | 88200, 96000, 176400, 192000, 384000, |
541 | }; |
542 | |
543 | static const struct snd_pcm_hw_constraint_list constraints_slave = { |
544 | .count = ARRAY_SIZE(pcm512x_dai_rates), |
545 | .list = pcm512x_dai_rates, |
546 | }; |
547 | |
548 | static int pcm512x_hw_rule_rate(struct snd_pcm_hw_params *params, |
549 | struct snd_pcm_hw_rule *rule) |
550 | { |
551 | struct pcm512x_priv *pcm512x = rule->private; |
552 | struct snd_interval ranges[2]; |
553 | int frame_size; |
554 | |
555 | frame_size = snd_soc_params_to_frame_size(params); |
556 | if (frame_size < 0) |
557 | return frame_size; |
558 | |
559 | switch (frame_size) { |
560 | case 32: |
561 | /* No hole when the frame size is 32. */ |
562 | return 0; |
563 | case 48: |
564 | case 64: |
565 | /* There is only one hole in the range of supported |
566 | * rates, but it moves with the frame size. |
567 | */ |
568 | memset(ranges, 0, sizeof(ranges)); |
569 | ranges[0].min = 8000; |
570 | ranges[0].max = pcm512x_sck_max(pcm512x) / frame_size / 2; |
571 | ranges[1].min = DIV_ROUND_UP(16000000, frame_size); |
572 | ranges[1].max = 384000; |
573 | break; |
574 | default: |
575 | return -EINVAL; |
576 | } |
577 | |
578 | return snd_interval_ranges(i: hw_param_interval(params, var: rule->var), |
579 | ARRAY_SIZE(ranges), list: ranges, mask: 0); |
580 | } |
581 | |
582 | static int pcm512x_dai_startup_master(struct snd_pcm_substream *substream, |
583 | struct snd_soc_dai *dai) |
584 | { |
585 | struct snd_soc_component *component = dai->component; |
586 | struct pcm512x_priv *pcm512x = snd_soc_component_get_drvdata(c: component); |
587 | struct device *dev = dai->dev; |
588 | struct snd_pcm_hw_constraint_ratnums *constraints_no_pll; |
589 | struct snd_ratnum *rats_no_pll; |
590 | |
591 | if (IS_ERR(ptr: pcm512x->sclk)) { |
592 | dev_err(dev, "Need SCLK for master mode: %ld\n" , |
593 | PTR_ERR(pcm512x->sclk)); |
594 | return PTR_ERR(ptr: pcm512x->sclk); |
595 | } |
596 | |
597 | if (pcm512x->pll_out) |
598 | return snd_pcm_hw_rule_add(runtime: substream->runtime, cond: 0, |
599 | SNDRV_PCM_HW_PARAM_RATE, |
600 | func: pcm512x_hw_rule_rate, |
601 | private: pcm512x, |
602 | SNDRV_PCM_HW_PARAM_FRAME_BITS, |
603 | SNDRV_PCM_HW_PARAM_CHANNELS, -1); |
604 | |
605 | constraints_no_pll = devm_kzalloc(dev, size: sizeof(*constraints_no_pll), |
606 | GFP_KERNEL); |
607 | if (!constraints_no_pll) |
608 | return -ENOMEM; |
609 | constraints_no_pll->nrats = 1; |
610 | rats_no_pll = devm_kzalloc(dev, size: sizeof(*rats_no_pll), GFP_KERNEL); |
611 | if (!rats_no_pll) |
612 | return -ENOMEM; |
613 | constraints_no_pll->rats = rats_no_pll; |
614 | rats_no_pll->num = clk_get_rate(clk: pcm512x->sclk) / 64; |
615 | rats_no_pll->den_min = 1; |
616 | rats_no_pll->den_max = 128; |
617 | rats_no_pll->den_step = 1; |
618 | |
619 | return snd_pcm_hw_constraint_ratnums(runtime: substream->runtime, cond: 0, |
620 | SNDRV_PCM_HW_PARAM_RATE, |
621 | r: constraints_no_pll); |
622 | } |
623 | |
624 | static int pcm512x_dai_startup_slave(struct snd_pcm_substream *substream, |
625 | struct snd_soc_dai *dai) |
626 | { |
627 | struct snd_soc_component *component = dai->component; |
628 | struct pcm512x_priv *pcm512x = snd_soc_component_get_drvdata(c: component); |
629 | struct device *dev = dai->dev; |
630 | struct regmap *regmap = pcm512x->regmap; |
631 | |
632 | if (IS_ERR(ptr: pcm512x->sclk)) { |
633 | dev_info(dev, "No SCLK, using BCLK: %ld\n" , |
634 | PTR_ERR(pcm512x->sclk)); |
635 | |
636 | /* Disable reporting of missing SCLK as an error */ |
637 | regmap_update_bits(map: regmap, PCM512x_ERROR_DETECT, |
638 | PCM512x_IDCH, PCM512x_IDCH); |
639 | |
640 | /* Switch PLL input to BCLK */ |
641 | regmap_update_bits(map: regmap, PCM512x_PLL_REF, |
642 | PCM512x_SREF, PCM512x_SREF_BCK); |
643 | } |
644 | |
645 | return snd_pcm_hw_constraint_list(runtime: substream->runtime, cond: 0, |
646 | SNDRV_PCM_HW_PARAM_RATE, |
647 | l: &constraints_slave); |
648 | } |
649 | |
650 | static int pcm512x_dai_startup(struct snd_pcm_substream *substream, |
651 | struct snd_soc_dai *dai) |
652 | { |
653 | struct snd_soc_component *component = dai->component; |
654 | struct pcm512x_priv *pcm512x = snd_soc_component_get_drvdata(c: component); |
655 | |
656 | switch (pcm512x->fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) { |
657 | case SND_SOC_DAIFMT_CBP_CFP: |
658 | case SND_SOC_DAIFMT_CBP_CFC: |
659 | return pcm512x_dai_startup_master(substream, dai); |
660 | |
661 | case SND_SOC_DAIFMT_CBC_CFC: |
662 | return pcm512x_dai_startup_slave(substream, dai); |
663 | |
664 | default: |
665 | return -EINVAL; |
666 | } |
667 | } |
668 | |
669 | static int pcm512x_set_bias_level(struct snd_soc_component *component, |
670 | enum snd_soc_bias_level level) |
671 | { |
672 | struct pcm512x_priv *pcm512x = dev_get_drvdata(dev: component->dev); |
673 | int ret; |
674 | |
675 | switch (level) { |
676 | case SND_SOC_BIAS_ON: |
677 | case SND_SOC_BIAS_PREPARE: |
678 | break; |
679 | |
680 | case SND_SOC_BIAS_STANDBY: |
681 | ret = regmap_update_bits(map: pcm512x->regmap, PCM512x_POWER, |
682 | PCM512x_RQST, val: 0); |
683 | if (ret != 0) { |
684 | dev_err(component->dev, "Failed to remove standby: %d\n" , |
685 | ret); |
686 | return ret; |
687 | } |
688 | break; |
689 | |
690 | case SND_SOC_BIAS_OFF: |
691 | ret = regmap_update_bits(map: pcm512x->regmap, PCM512x_POWER, |
692 | PCM512x_RQST, PCM512x_RQST); |
693 | if (ret != 0) { |
694 | dev_err(component->dev, "Failed to request standby: %d\n" , |
695 | ret); |
696 | return ret; |
697 | } |
698 | break; |
699 | } |
700 | |
701 | return 0; |
702 | } |
703 | |
704 | static unsigned long pcm512x_find_sck(struct snd_soc_dai *dai, |
705 | unsigned long bclk_rate) |
706 | { |
707 | struct device *dev = dai->dev; |
708 | struct snd_soc_component *component = dai->component; |
709 | struct pcm512x_priv *pcm512x = snd_soc_component_get_drvdata(c: component); |
710 | unsigned long sck_rate; |
711 | int pow2; |
712 | |
713 | /* 64 MHz <= pll_rate <= 100 MHz, VREF mode */ |
714 | /* 16 MHz <= sck_rate <= 25 MHz, VREF mode */ |
715 | |
716 | /* select sck_rate as a multiple of bclk_rate but still with |
717 | * as many factors of 2 as possible, as that makes it easier |
718 | * to find a fast DAC rate |
719 | */ |
720 | pow2 = 1 << fls(x: (pcm512x_pll_max(pcm512x) - 16000000) / bclk_rate); |
721 | for (; pow2; pow2 >>= 1) { |
722 | sck_rate = rounddown(pcm512x_pll_max(pcm512x), |
723 | bclk_rate * pow2); |
724 | if (sck_rate >= 16000000) |
725 | break; |
726 | } |
727 | if (!pow2) { |
728 | dev_err(dev, "Impossible to generate a suitable SCK\n" ); |
729 | return 0; |
730 | } |
731 | |
732 | dev_dbg(dev, "sck_rate %lu\n" , sck_rate); |
733 | return sck_rate; |
734 | } |
735 | |
736 | /* pll_rate = pllin_rate * R * J.D / P |
737 | * 1 <= R <= 16 |
738 | * 1 <= J <= 63 |
739 | * 0 <= D <= 9999 |
740 | * 1 <= P <= 15 |
741 | * 64 MHz <= pll_rate <= 100 MHz |
742 | * if D == 0 |
743 | * 1 MHz <= pllin_rate / P <= 20 MHz |
744 | * else if D > 0 |
745 | * 6.667 MHz <= pllin_rate / P <= 20 MHz |
746 | * 4 <= J <= 11 |
747 | * R = 1 |
748 | */ |
749 | static int pcm512x_find_pll_coeff(struct snd_soc_dai *dai, |
750 | unsigned long pllin_rate, |
751 | unsigned long pll_rate) |
752 | { |
753 | struct device *dev = dai->dev; |
754 | struct snd_soc_component *component = dai->component; |
755 | struct pcm512x_priv *pcm512x = snd_soc_component_get_drvdata(c: component); |
756 | unsigned long common; |
757 | int R, J, D, P; |
758 | unsigned long K; /* 10000 * J.D */ |
759 | unsigned long num; |
760 | unsigned long den; |
761 | |
762 | common = gcd(a: pll_rate, b: pllin_rate); |
763 | dev_dbg(dev, "pll %lu pllin %lu common %lu\n" , |
764 | pll_rate, pllin_rate, common); |
765 | num = pll_rate / common; |
766 | den = pllin_rate / common; |
767 | |
768 | /* pllin_rate / P (or here, den) cannot be greater than 20 MHz */ |
769 | if (pllin_rate / den > 20000000 && num < 8) { |
770 | num *= DIV_ROUND_UP(pllin_rate / den, 20000000); |
771 | den *= DIV_ROUND_UP(pllin_rate / den, 20000000); |
772 | } |
773 | dev_dbg(dev, "num / den = %lu / %lu\n" , num, den); |
774 | |
775 | P = den; |
776 | if (den <= 15 && num <= 16 * 63 |
777 | && 1000000 <= pllin_rate / P && pllin_rate / P <= 20000000) { |
778 | /* Try the case with D = 0 */ |
779 | D = 0; |
780 | /* factor 'num' into J and R, such that R <= 16 and J <= 63 */ |
781 | for (R = 16; R; R--) { |
782 | if (num % R) |
783 | continue; |
784 | J = num / R; |
785 | if (J == 0 || J > 63) |
786 | continue; |
787 | |
788 | dev_dbg(dev, "R * J / P = %d * %d / %d\n" , R, J, P); |
789 | pcm512x->real_pll = pll_rate; |
790 | goto done; |
791 | } |
792 | /* no luck */ |
793 | } |
794 | |
795 | R = 1; |
796 | |
797 | if (num > 0xffffffffUL / 10000) |
798 | goto fallback; |
799 | |
800 | /* Try to find an exact pll_rate using the D > 0 case */ |
801 | common = gcd(a: 10000 * num, b: den); |
802 | num = 10000 * num / common; |
803 | den /= common; |
804 | dev_dbg(dev, "num %lu den %lu common %lu\n" , num, den, common); |
805 | |
806 | for (P = den; P <= 15; P++) { |
807 | if (pllin_rate / P < 6667000 || 200000000 < pllin_rate / P) |
808 | continue; |
809 | if (num * P % den) |
810 | continue; |
811 | K = num * P / den; |
812 | /* J == 12 is ok if D == 0 */ |
813 | if (K < 40000 || K > 120000) |
814 | continue; |
815 | |
816 | J = K / 10000; |
817 | D = K % 10000; |
818 | dev_dbg(dev, "J.D / P = %d.%04d / %d\n" , J, D, P); |
819 | pcm512x->real_pll = pll_rate; |
820 | goto done; |
821 | } |
822 | |
823 | /* Fall back to an approximate pll_rate */ |
824 | |
825 | fallback: |
826 | /* find smallest possible P */ |
827 | P = DIV_ROUND_UP(pllin_rate, 20000000); |
828 | if (!P) |
829 | P = 1; |
830 | else if (P > 15) { |
831 | dev_err(dev, "Need a slower clock as pll-input\n" ); |
832 | return -EINVAL; |
833 | } |
834 | if (pllin_rate / P < 6667000) { |
835 | dev_err(dev, "Need a faster clock as pll-input\n" ); |
836 | return -EINVAL; |
837 | } |
838 | K = DIV_ROUND_CLOSEST_ULL(10000ULL * pll_rate * P, pllin_rate); |
839 | if (K < 40000) |
840 | K = 40000; |
841 | /* J == 12 is ok if D == 0 */ |
842 | if (K > 120000) |
843 | K = 120000; |
844 | J = K / 10000; |
845 | D = K % 10000; |
846 | dev_dbg(dev, "J.D / P ~ %d.%04d / %d\n" , J, D, P); |
847 | pcm512x->real_pll = DIV_ROUND_DOWN_ULL((u64)K * pllin_rate, 10000 * P); |
848 | |
849 | done: |
850 | pcm512x->pll_r = R; |
851 | pcm512x->pll_j = J; |
852 | pcm512x->pll_d = D; |
853 | pcm512x->pll_p = P; |
854 | return 0; |
855 | } |
856 | |
857 | static unsigned long pcm512x_pllin_dac_rate(struct snd_soc_dai *dai, |
858 | unsigned long osr_rate, |
859 | unsigned long pllin_rate) |
860 | { |
861 | struct snd_soc_component *component = dai->component; |
862 | struct pcm512x_priv *pcm512x = snd_soc_component_get_drvdata(c: component); |
863 | unsigned long dac_rate; |
864 | |
865 | if (!pcm512x->pll_out) |
866 | return 0; /* no PLL to bypass, force SCK as DAC input */ |
867 | |
868 | if (pllin_rate % osr_rate) |
869 | return 0; /* futile, quit early */ |
870 | |
871 | /* run DAC no faster than 6144000 Hz */ |
872 | for (dac_rate = rounddown(pcm512x_dac_max(pcm512x, 6144000), osr_rate); |
873 | dac_rate; |
874 | dac_rate -= osr_rate) { |
875 | |
876 | if (pllin_rate / dac_rate > 128) |
877 | return 0; /* DAC divider would be too big */ |
878 | |
879 | if (!(pllin_rate % dac_rate)) |
880 | return dac_rate; |
881 | |
882 | dac_rate -= osr_rate; |
883 | } |
884 | |
885 | return 0; |
886 | } |
887 | |
888 | static int pcm512x_set_dividers(struct snd_soc_dai *dai, |
889 | struct snd_pcm_hw_params *params) |
890 | { |
891 | struct device *dev = dai->dev; |
892 | struct snd_soc_component *component = dai->component; |
893 | struct pcm512x_priv *pcm512x = snd_soc_component_get_drvdata(c: component); |
894 | unsigned long pllin_rate = 0; |
895 | unsigned long pll_rate; |
896 | unsigned long sck_rate; |
897 | unsigned long mck_rate; |
898 | unsigned long bclk_rate; |
899 | unsigned long sample_rate; |
900 | unsigned long osr_rate; |
901 | unsigned long dacsrc_rate; |
902 | int bclk_div; |
903 | int lrclk_div; |
904 | int dsp_div; |
905 | int dac_div; |
906 | unsigned long dac_rate; |
907 | int ncp_div; |
908 | int osr_div; |
909 | int ret; |
910 | int idac; |
911 | int fssp; |
912 | int gpio; |
913 | |
914 | if (pcm512x->bclk_ratio > 0) { |
915 | lrclk_div = pcm512x->bclk_ratio; |
916 | } else { |
917 | lrclk_div = snd_soc_params_to_frame_size(params); |
918 | |
919 | if (lrclk_div == 0) { |
920 | dev_err(dev, "No LRCLK?\n" ); |
921 | return -EINVAL; |
922 | } |
923 | } |
924 | |
925 | if (!pcm512x->pll_out) { |
926 | sck_rate = clk_get_rate(clk: pcm512x->sclk); |
927 | bclk_rate = params_rate(p: params) * lrclk_div; |
928 | bclk_div = DIV_ROUND_CLOSEST(sck_rate, bclk_rate); |
929 | |
930 | mck_rate = sck_rate; |
931 | } else { |
932 | ret = snd_soc_params_to_bclk(parms: params); |
933 | if (ret < 0) { |
934 | dev_err(dev, "Failed to find suitable BCLK: %d\n" , ret); |
935 | return ret; |
936 | } |
937 | if (ret == 0) { |
938 | dev_err(dev, "No BCLK?\n" ); |
939 | return -EINVAL; |
940 | } |
941 | bclk_rate = ret; |
942 | |
943 | pllin_rate = clk_get_rate(clk: pcm512x->sclk); |
944 | |
945 | sck_rate = pcm512x_find_sck(dai, bclk_rate); |
946 | if (!sck_rate) |
947 | return -EINVAL; |
948 | pll_rate = 4 * sck_rate; |
949 | |
950 | ret = pcm512x_find_pll_coeff(dai, pllin_rate, pll_rate); |
951 | if (ret != 0) |
952 | return ret; |
953 | |
954 | ret = regmap_write(map: pcm512x->regmap, |
955 | PCM512x_PLL_COEFF_0, val: pcm512x->pll_p - 1); |
956 | if (ret != 0) { |
957 | dev_err(dev, "Failed to write PLL P: %d\n" , ret); |
958 | return ret; |
959 | } |
960 | |
961 | ret = regmap_write(map: pcm512x->regmap, |
962 | PCM512x_PLL_COEFF_1, val: pcm512x->pll_j); |
963 | if (ret != 0) { |
964 | dev_err(dev, "Failed to write PLL J: %d\n" , ret); |
965 | return ret; |
966 | } |
967 | |
968 | ret = regmap_write(map: pcm512x->regmap, |
969 | PCM512x_PLL_COEFF_2, val: pcm512x->pll_d >> 8); |
970 | if (ret != 0) { |
971 | dev_err(dev, "Failed to write PLL D msb: %d\n" , ret); |
972 | return ret; |
973 | } |
974 | |
975 | ret = regmap_write(map: pcm512x->regmap, |
976 | PCM512x_PLL_COEFF_3, val: pcm512x->pll_d & 0xff); |
977 | if (ret != 0) { |
978 | dev_err(dev, "Failed to write PLL D lsb: %d\n" , ret); |
979 | return ret; |
980 | } |
981 | |
982 | ret = regmap_write(map: pcm512x->regmap, |
983 | PCM512x_PLL_COEFF_4, val: pcm512x->pll_r - 1); |
984 | if (ret != 0) { |
985 | dev_err(dev, "Failed to write PLL R: %d\n" , ret); |
986 | return ret; |
987 | } |
988 | |
989 | mck_rate = pcm512x->real_pll; |
990 | |
991 | bclk_div = DIV_ROUND_CLOSEST(sck_rate, bclk_rate); |
992 | } |
993 | |
994 | if (bclk_div > 128) { |
995 | dev_err(dev, "Failed to find BCLK divider\n" ); |
996 | return -EINVAL; |
997 | } |
998 | |
999 | /* the actual rate */ |
1000 | sample_rate = sck_rate / bclk_div / lrclk_div; |
1001 | osr_rate = 16 * sample_rate; |
1002 | |
1003 | /* run DSP no faster than 50 MHz */ |
1004 | dsp_div = mck_rate > pcm512x_dsp_max(pcm512x) ? 2 : 1; |
1005 | |
1006 | dac_rate = pcm512x_pllin_dac_rate(dai, osr_rate, pllin_rate); |
1007 | if (dac_rate) { |
1008 | /* the desired clock rate is "compatible" with the pll input |
1009 | * clock, so use that clock as dac input instead of the pll |
1010 | * output clock since the pll will introduce jitter and thus |
1011 | * noise. |
1012 | */ |
1013 | dev_dbg(dev, "using pll input as dac input\n" ); |
1014 | ret = regmap_update_bits(map: pcm512x->regmap, PCM512x_DAC_REF, |
1015 | PCM512x_SDAC, PCM512x_SDAC_GPIO); |
1016 | if (ret != 0) { |
1017 | dev_err(component->dev, |
1018 | "Failed to set gpio as dacref: %d\n" , ret); |
1019 | return ret; |
1020 | } |
1021 | |
1022 | gpio = PCM512x_GREF_GPIO1 + pcm512x->pll_in - 1; |
1023 | ret = regmap_update_bits(map: pcm512x->regmap, PCM512x_GPIO_DACIN, |
1024 | PCM512x_GREF, val: gpio); |
1025 | if (ret != 0) { |
1026 | dev_err(component->dev, |
1027 | "Failed to set gpio %d as dacin: %d\n" , |
1028 | pcm512x->pll_in, ret); |
1029 | return ret; |
1030 | } |
1031 | |
1032 | dacsrc_rate = pllin_rate; |
1033 | } else { |
1034 | /* run DAC no faster than 6144000 Hz */ |
1035 | unsigned long dac_mul = pcm512x_dac_max(pcm512x, rate: 6144000) |
1036 | / osr_rate; |
1037 | unsigned long sck_mul = sck_rate / osr_rate; |
1038 | |
1039 | for (; dac_mul; dac_mul--) { |
1040 | if (!(sck_mul % dac_mul)) |
1041 | break; |
1042 | } |
1043 | if (!dac_mul) { |
1044 | dev_err(dev, "Failed to find DAC rate\n" ); |
1045 | return -EINVAL; |
1046 | } |
1047 | |
1048 | dac_rate = dac_mul * osr_rate; |
1049 | dev_dbg(dev, "dac_rate %lu sample_rate %lu\n" , |
1050 | dac_rate, sample_rate); |
1051 | |
1052 | ret = regmap_update_bits(map: pcm512x->regmap, PCM512x_DAC_REF, |
1053 | PCM512x_SDAC, PCM512x_SDAC_SCK); |
1054 | if (ret != 0) { |
1055 | dev_err(component->dev, |
1056 | "Failed to set sck as dacref: %d\n" , ret); |
1057 | return ret; |
1058 | } |
1059 | |
1060 | dacsrc_rate = sck_rate; |
1061 | } |
1062 | |
1063 | osr_div = DIV_ROUND_CLOSEST(dac_rate, osr_rate); |
1064 | if (osr_div > 128) { |
1065 | dev_err(dev, "Failed to find OSR divider\n" ); |
1066 | return -EINVAL; |
1067 | } |
1068 | |
1069 | dac_div = DIV_ROUND_CLOSEST(dacsrc_rate, dac_rate); |
1070 | if (dac_div > 128) { |
1071 | dev_err(dev, "Failed to find DAC divider\n" ); |
1072 | return -EINVAL; |
1073 | } |
1074 | dac_rate = dacsrc_rate / dac_div; |
1075 | |
1076 | ncp_div = DIV_ROUND_CLOSEST(dac_rate, |
1077 | pcm512x_ncp_target(pcm512x, dac_rate)); |
1078 | if (ncp_div > 128 || dac_rate / ncp_div > 2048000) { |
1079 | /* run NCP no faster than 2048000 Hz, but why? */ |
1080 | ncp_div = DIV_ROUND_UP(dac_rate, 2048000); |
1081 | if (ncp_div > 128) { |
1082 | dev_err(dev, "Failed to find NCP divider\n" ); |
1083 | return -EINVAL; |
1084 | } |
1085 | } |
1086 | |
1087 | idac = mck_rate / (dsp_div * sample_rate); |
1088 | |
1089 | ret = regmap_write(map: pcm512x->regmap, PCM512x_DSP_CLKDIV, val: dsp_div - 1); |
1090 | if (ret != 0) { |
1091 | dev_err(dev, "Failed to write DSP divider: %d\n" , ret); |
1092 | return ret; |
1093 | } |
1094 | |
1095 | ret = regmap_write(map: pcm512x->regmap, PCM512x_DAC_CLKDIV, val: dac_div - 1); |
1096 | if (ret != 0) { |
1097 | dev_err(dev, "Failed to write DAC divider: %d\n" , ret); |
1098 | return ret; |
1099 | } |
1100 | |
1101 | ret = regmap_write(map: pcm512x->regmap, PCM512x_NCP_CLKDIV, val: ncp_div - 1); |
1102 | if (ret != 0) { |
1103 | dev_err(dev, "Failed to write NCP divider: %d\n" , ret); |
1104 | return ret; |
1105 | } |
1106 | |
1107 | ret = regmap_write(map: pcm512x->regmap, PCM512x_OSR_CLKDIV, val: osr_div - 1); |
1108 | if (ret != 0) { |
1109 | dev_err(dev, "Failed to write OSR divider: %d\n" , ret); |
1110 | return ret; |
1111 | } |
1112 | |
1113 | ret = regmap_write(map: pcm512x->regmap, |
1114 | PCM512x_MASTER_CLKDIV_1, val: bclk_div - 1); |
1115 | if (ret != 0) { |
1116 | dev_err(dev, "Failed to write BCLK divider: %d\n" , ret); |
1117 | return ret; |
1118 | } |
1119 | |
1120 | ret = regmap_write(map: pcm512x->regmap, |
1121 | PCM512x_MASTER_CLKDIV_2, val: lrclk_div - 1); |
1122 | if (ret != 0) { |
1123 | dev_err(dev, "Failed to write LRCLK divider: %d\n" , ret); |
1124 | return ret; |
1125 | } |
1126 | |
1127 | ret = regmap_write(map: pcm512x->regmap, PCM512x_IDAC_1, val: idac >> 8); |
1128 | if (ret != 0) { |
1129 | dev_err(dev, "Failed to write IDAC msb divider: %d\n" , ret); |
1130 | return ret; |
1131 | } |
1132 | |
1133 | ret = regmap_write(map: pcm512x->regmap, PCM512x_IDAC_2, val: idac & 0xff); |
1134 | if (ret != 0) { |
1135 | dev_err(dev, "Failed to write IDAC lsb divider: %d\n" , ret); |
1136 | return ret; |
1137 | } |
1138 | |
1139 | if (sample_rate <= pcm512x_dac_max(pcm512x, rate: 48000)) |
1140 | fssp = PCM512x_FSSP_48KHZ; |
1141 | else if (sample_rate <= pcm512x_dac_max(pcm512x, rate: 96000)) |
1142 | fssp = PCM512x_FSSP_96KHZ; |
1143 | else if (sample_rate <= pcm512x_dac_max(pcm512x, rate: 192000)) |
1144 | fssp = PCM512x_FSSP_192KHZ; |
1145 | else |
1146 | fssp = PCM512x_FSSP_384KHZ; |
1147 | ret = regmap_update_bits(map: pcm512x->regmap, PCM512x_FS_SPEED_MODE, |
1148 | PCM512x_FSSP, val: fssp); |
1149 | if (ret != 0) { |
1150 | dev_err(component->dev, "Failed to set fs speed: %d\n" , ret); |
1151 | return ret; |
1152 | } |
1153 | |
1154 | dev_dbg(component->dev, "DSP divider %d\n" , dsp_div); |
1155 | dev_dbg(component->dev, "DAC divider %d\n" , dac_div); |
1156 | dev_dbg(component->dev, "NCP divider %d\n" , ncp_div); |
1157 | dev_dbg(component->dev, "OSR divider %d\n" , osr_div); |
1158 | dev_dbg(component->dev, "BCK divider %d\n" , bclk_div); |
1159 | dev_dbg(component->dev, "LRCK divider %d\n" , lrclk_div); |
1160 | dev_dbg(component->dev, "IDAC %d\n" , idac); |
1161 | dev_dbg(component->dev, "1<<FSSP %d\n" , 1 << fssp); |
1162 | |
1163 | return 0; |
1164 | } |
1165 | |
1166 | static int pcm512x_hw_params(struct snd_pcm_substream *substream, |
1167 | struct snd_pcm_hw_params *params, |
1168 | struct snd_soc_dai *dai) |
1169 | { |
1170 | struct snd_soc_component *component = dai->component; |
1171 | struct pcm512x_priv *pcm512x = snd_soc_component_get_drvdata(c: component); |
1172 | int alen; |
1173 | int gpio; |
1174 | int ret; |
1175 | |
1176 | dev_dbg(component->dev, "hw_params %u Hz, %u channels\n" , |
1177 | params_rate(params), |
1178 | params_channels(params)); |
1179 | |
1180 | switch (params_width(p: params)) { |
1181 | case 16: |
1182 | alen = PCM512x_ALEN_16; |
1183 | break; |
1184 | case 20: |
1185 | alen = PCM512x_ALEN_20; |
1186 | break; |
1187 | case 24: |
1188 | alen = PCM512x_ALEN_24; |
1189 | break; |
1190 | case 32: |
1191 | alen = PCM512x_ALEN_32; |
1192 | break; |
1193 | default: |
1194 | dev_err(component->dev, "Bad frame size: %d\n" , |
1195 | params_width(params)); |
1196 | return -EINVAL; |
1197 | } |
1198 | |
1199 | ret = regmap_update_bits(map: pcm512x->regmap, PCM512x_I2S_1, |
1200 | PCM512x_ALEN, val: alen); |
1201 | if (ret != 0) { |
1202 | dev_err(component->dev, "Failed to set frame size: %d\n" , ret); |
1203 | return ret; |
1204 | } |
1205 | |
1206 | if ((pcm512x->fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) == |
1207 | SND_SOC_DAIFMT_CBC_CFC) { |
1208 | ret = regmap_update_bits(map: pcm512x->regmap, PCM512x_ERROR_DETECT, |
1209 | PCM512x_DCAS, val: 0); |
1210 | if (ret != 0) { |
1211 | dev_err(component->dev, |
1212 | "Failed to enable clock divider autoset: %d\n" , |
1213 | ret); |
1214 | return ret; |
1215 | } |
1216 | goto skip_pll; |
1217 | } |
1218 | |
1219 | if (pcm512x->pll_out) { |
1220 | ret = regmap_write(map: pcm512x->regmap, PCM512x_FLEX_A, val: 0x11); |
1221 | if (ret != 0) { |
1222 | dev_err(component->dev, "Failed to set FLEX_A: %d\n" , ret); |
1223 | return ret; |
1224 | } |
1225 | |
1226 | ret = regmap_write(map: pcm512x->regmap, PCM512x_FLEX_B, val: 0xff); |
1227 | if (ret != 0) { |
1228 | dev_err(component->dev, "Failed to set FLEX_B: %d\n" , ret); |
1229 | return ret; |
1230 | } |
1231 | |
1232 | ret = regmap_update_bits(map: pcm512x->regmap, PCM512x_ERROR_DETECT, |
1233 | PCM512x_IDFS | PCM512x_IDBK |
1234 | | PCM512x_IDSK | PCM512x_IDCH |
1235 | | PCM512x_IDCM | PCM512x_DCAS |
1236 | | PCM512x_IPLK, |
1237 | PCM512x_IDFS | PCM512x_IDBK |
1238 | | PCM512x_IDSK | PCM512x_IDCH |
1239 | | PCM512x_DCAS); |
1240 | if (ret != 0) { |
1241 | dev_err(component->dev, |
1242 | "Failed to ignore auto-clock failures: %d\n" , |
1243 | ret); |
1244 | return ret; |
1245 | } |
1246 | } else { |
1247 | ret = regmap_update_bits(map: pcm512x->regmap, PCM512x_ERROR_DETECT, |
1248 | PCM512x_IDFS | PCM512x_IDBK |
1249 | | PCM512x_IDSK | PCM512x_IDCH |
1250 | | PCM512x_IDCM | PCM512x_DCAS |
1251 | | PCM512x_IPLK, |
1252 | PCM512x_IDFS | PCM512x_IDBK |
1253 | | PCM512x_IDSK | PCM512x_IDCH |
1254 | | PCM512x_DCAS | PCM512x_IPLK); |
1255 | if (ret != 0) { |
1256 | dev_err(component->dev, |
1257 | "Failed to ignore auto-clock failures: %d\n" , |
1258 | ret); |
1259 | return ret; |
1260 | } |
1261 | |
1262 | if (!pcm512x->force_pll_on) { |
1263 | ret = regmap_update_bits(map: pcm512x->regmap, |
1264 | PCM512x_PLL_EN, PCM512x_PLLE, val: 0); |
1265 | } else { |
1266 | /* provide minimum PLL config for TAS575x clocking |
1267 | * and leave PLL enabled |
1268 | */ |
1269 | ret = regmap_write(map: pcm512x->regmap, |
1270 | PCM512x_PLL_COEFF_0, val: 0x01); |
1271 | if (ret != 0) { |
1272 | dev_err(component->dev, |
1273 | "Failed to set pll coefficient: %d\n" , ret); |
1274 | return ret; |
1275 | } |
1276 | ret = regmap_write(map: pcm512x->regmap, |
1277 | PCM512x_PLL_COEFF_1, val: 0x04); |
1278 | if (ret != 0) { |
1279 | dev_err(component->dev, |
1280 | "Failed to set pll coefficient: %d\n" , ret); |
1281 | return ret; |
1282 | } |
1283 | ret = regmap_write(map: pcm512x->regmap, |
1284 | PCM512x_PLL_EN, val: 0x01); |
1285 | dev_dbg(component->dev, "Enabling PLL for TAS575x\n" ); |
1286 | } |
1287 | |
1288 | if (ret != 0) { |
1289 | dev_err(component->dev, "Failed to set pll mode: %d\n" , ret); |
1290 | return ret; |
1291 | } |
1292 | } |
1293 | |
1294 | ret = pcm512x_set_dividers(dai, params); |
1295 | if (ret != 0) |
1296 | return ret; |
1297 | |
1298 | if (pcm512x->pll_out) { |
1299 | ret = regmap_update_bits(map: pcm512x->regmap, PCM512x_PLL_REF, |
1300 | PCM512x_SREF, PCM512x_SREF_GPIO); |
1301 | if (ret != 0) { |
1302 | dev_err(component->dev, |
1303 | "Failed to set gpio as pllref: %d\n" , ret); |
1304 | return ret; |
1305 | } |
1306 | |
1307 | gpio = PCM512x_GREF_GPIO1 + pcm512x->pll_in - 1; |
1308 | ret = regmap_update_bits(map: pcm512x->regmap, PCM512x_GPIO_PLLIN, |
1309 | PCM512x_GREF, val: gpio); |
1310 | if (ret != 0) { |
1311 | dev_err(component->dev, |
1312 | "Failed to set gpio %d as pllin: %d\n" , |
1313 | pcm512x->pll_in, ret); |
1314 | return ret; |
1315 | } |
1316 | |
1317 | ret = regmap_update_bits(map: pcm512x->regmap, PCM512x_PLL_EN, |
1318 | PCM512x_PLLE, PCM512x_PLLE); |
1319 | if (ret != 0) { |
1320 | dev_err(component->dev, "Failed to enable pll: %d\n" , ret); |
1321 | return ret; |
1322 | } |
1323 | |
1324 | gpio = PCM512x_G1OE << (pcm512x->pll_out - 1); |
1325 | ret = regmap_update_bits(map: pcm512x->regmap, PCM512x_GPIO_EN, |
1326 | mask: gpio, val: gpio); |
1327 | if (ret != 0) { |
1328 | dev_err(component->dev, "Failed to enable gpio %d: %d\n" , |
1329 | pcm512x->pll_out, ret); |
1330 | return ret; |
1331 | } |
1332 | |
1333 | gpio = PCM512x_GPIO_OUTPUT_1 + pcm512x->pll_out - 1; |
1334 | ret = regmap_update_bits(map: pcm512x->regmap, reg: gpio, |
1335 | PCM512x_GxSL, PCM512x_GxSL_PLLCK); |
1336 | if (ret != 0) { |
1337 | dev_err(component->dev, "Failed to output pll on %d: %d\n" , |
1338 | ret, pcm512x->pll_out); |
1339 | return ret; |
1340 | } |
1341 | } |
1342 | |
1343 | ret = regmap_update_bits(map: pcm512x->regmap, PCM512x_SYNCHRONIZE, |
1344 | PCM512x_RQSY, PCM512x_RQSY_HALT); |
1345 | if (ret != 0) { |
1346 | dev_err(component->dev, "Failed to halt clocks: %d\n" , ret); |
1347 | return ret; |
1348 | } |
1349 | |
1350 | ret = regmap_update_bits(map: pcm512x->regmap, PCM512x_SYNCHRONIZE, |
1351 | PCM512x_RQSY, PCM512x_RQSY_RESUME); |
1352 | if (ret != 0) { |
1353 | dev_err(component->dev, "Failed to resume clocks: %d\n" , ret); |
1354 | return ret; |
1355 | } |
1356 | |
1357 | skip_pll: |
1358 | return 0; |
1359 | } |
1360 | |
1361 | static int pcm512x_set_fmt(struct snd_soc_dai *dai, unsigned int fmt) |
1362 | { |
1363 | struct snd_soc_component *component = dai->component; |
1364 | struct pcm512x_priv *pcm512x = snd_soc_component_get_drvdata(c: component); |
1365 | int afmt; |
1366 | int offset = 0; |
1367 | int clock_output; |
1368 | int provider_mode; |
1369 | int ret; |
1370 | |
1371 | switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) { |
1372 | case SND_SOC_DAIFMT_CBC_CFC: |
1373 | clock_output = 0; |
1374 | provider_mode = 0; |
1375 | break; |
1376 | case SND_SOC_DAIFMT_CBP_CFP: |
1377 | clock_output = PCM512x_BCKO | PCM512x_LRKO; |
1378 | provider_mode = PCM512x_RLRK | PCM512x_RBCK; |
1379 | break; |
1380 | case SND_SOC_DAIFMT_CBP_CFC: |
1381 | clock_output = PCM512x_BCKO; |
1382 | provider_mode = PCM512x_RBCK; |
1383 | break; |
1384 | default: |
1385 | return -EINVAL; |
1386 | } |
1387 | |
1388 | ret = regmap_update_bits(map: pcm512x->regmap, PCM512x_BCLK_LRCLK_CFG, |
1389 | PCM512x_BCKP | PCM512x_BCKO | PCM512x_LRKO, |
1390 | val: clock_output); |
1391 | if (ret != 0) { |
1392 | dev_err(component->dev, "Failed to enable clock output: %d\n" , ret); |
1393 | return ret; |
1394 | } |
1395 | |
1396 | ret = regmap_update_bits(map: pcm512x->regmap, PCM512x_MASTER_MODE, |
1397 | PCM512x_RLRK | PCM512x_RBCK, |
1398 | val: provider_mode); |
1399 | if (ret != 0) { |
1400 | dev_err(component->dev, "Failed to enable provider mode: %d\n" , ret); |
1401 | return ret; |
1402 | } |
1403 | |
1404 | switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { |
1405 | case SND_SOC_DAIFMT_I2S: |
1406 | afmt = PCM512x_AFMT_I2S; |
1407 | break; |
1408 | case SND_SOC_DAIFMT_RIGHT_J: |
1409 | afmt = PCM512x_AFMT_RTJ; |
1410 | break; |
1411 | case SND_SOC_DAIFMT_LEFT_J: |
1412 | afmt = PCM512x_AFMT_LTJ; |
1413 | break; |
1414 | case SND_SOC_DAIFMT_DSP_A: |
1415 | offset = 1; |
1416 | fallthrough; |
1417 | case SND_SOC_DAIFMT_DSP_B: |
1418 | afmt = PCM512x_AFMT_DSP; |
1419 | break; |
1420 | default: |
1421 | dev_err(component->dev, "unsupported DAI format: 0x%x\n" , |
1422 | pcm512x->fmt); |
1423 | return -EINVAL; |
1424 | } |
1425 | |
1426 | ret = regmap_update_bits(map: pcm512x->regmap, PCM512x_I2S_1, |
1427 | PCM512x_AFMT, val: afmt); |
1428 | if (ret != 0) { |
1429 | dev_err(component->dev, "Failed to set data format: %d\n" , ret); |
1430 | return ret; |
1431 | } |
1432 | |
1433 | ret = regmap_update_bits(map: pcm512x->regmap, PCM512x_I2S_2, |
1434 | mask: 0xFF, val: offset); |
1435 | if (ret != 0) { |
1436 | dev_err(component->dev, "Failed to set data offset: %d\n" , ret); |
1437 | return ret; |
1438 | } |
1439 | |
1440 | pcm512x->fmt = fmt; |
1441 | |
1442 | return 0; |
1443 | } |
1444 | |
1445 | static int pcm512x_set_bclk_ratio(struct snd_soc_dai *dai, unsigned int ratio) |
1446 | { |
1447 | struct snd_soc_component *component = dai->component; |
1448 | struct pcm512x_priv *pcm512x = snd_soc_component_get_drvdata(c: component); |
1449 | |
1450 | if (ratio > 256) |
1451 | return -EINVAL; |
1452 | |
1453 | pcm512x->bclk_ratio = ratio; |
1454 | |
1455 | return 0; |
1456 | } |
1457 | |
1458 | static int pcm512x_mute(struct snd_soc_dai *dai, int mute, int direction) |
1459 | { |
1460 | struct snd_soc_component *component = dai->component; |
1461 | struct pcm512x_priv *pcm512x = snd_soc_component_get_drvdata(c: component); |
1462 | int ret; |
1463 | unsigned int mute_det; |
1464 | |
1465 | mutex_lock(&pcm512x->mutex); |
1466 | |
1467 | if (mute) { |
1468 | pcm512x->mute |= 0x1; |
1469 | ret = regmap_update_bits(map: pcm512x->regmap, PCM512x_MUTE, |
1470 | PCM512x_RQML | PCM512x_RQMR, |
1471 | PCM512x_RQML | PCM512x_RQMR); |
1472 | if (ret != 0) { |
1473 | dev_err(component->dev, |
1474 | "Failed to set digital mute: %d\n" , ret); |
1475 | goto unlock; |
1476 | } |
1477 | |
1478 | regmap_read_poll_timeout(pcm512x->regmap, |
1479 | PCM512x_ANALOG_MUTE_DET, |
1480 | mute_det, (mute_det & 0x3) == 0, |
1481 | 200, 10000); |
1482 | } else { |
1483 | pcm512x->mute &= ~0x1; |
1484 | ret = pcm512x_update_mute(pcm512x); |
1485 | if (ret != 0) { |
1486 | dev_err(component->dev, |
1487 | "Failed to update digital mute: %d\n" , ret); |
1488 | goto unlock; |
1489 | } |
1490 | |
1491 | regmap_read_poll_timeout(pcm512x->regmap, |
1492 | PCM512x_ANALOG_MUTE_DET, |
1493 | mute_det, |
1494 | (mute_det & 0x3) |
1495 | == ((~pcm512x->mute >> 1) & 0x3), |
1496 | 200, 10000); |
1497 | } |
1498 | |
1499 | unlock: |
1500 | mutex_unlock(lock: &pcm512x->mutex); |
1501 | |
1502 | return ret; |
1503 | } |
1504 | |
1505 | static const struct snd_soc_dai_ops pcm512x_dai_ops = { |
1506 | .startup = pcm512x_dai_startup, |
1507 | .hw_params = pcm512x_hw_params, |
1508 | .set_fmt = pcm512x_set_fmt, |
1509 | .mute_stream = pcm512x_mute, |
1510 | .set_bclk_ratio = pcm512x_set_bclk_ratio, |
1511 | .no_capture_mute = 1, |
1512 | }; |
1513 | |
1514 | static struct snd_soc_dai_driver pcm512x_dai = { |
1515 | .name = "pcm512x-hifi" , |
1516 | .playback = { |
1517 | .stream_name = "Playback" , |
1518 | .channels_min = 2, |
1519 | .channels_max = 2, |
1520 | .rates = SNDRV_PCM_RATE_CONTINUOUS, |
1521 | .rate_min = 8000, |
1522 | .rate_max = 384000, |
1523 | .formats = SNDRV_PCM_FMTBIT_S16_LE | |
1524 | SNDRV_PCM_FMTBIT_S24_LE | |
1525 | SNDRV_PCM_FMTBIT_S32_LE |
1526 | }, |
1527 | .ops = &pcm512x_dai_ops, |
1528 | }; |
1529 | |
1530 | static const struct snd_soc_component_driver pcm512x_component_driver = { |
1531 | .set_bias_level = pcm512x_set_bias_level, |
1532 | .controls = pcm512x_controls, |
1533 | .num_controls = ARRAY_SIZE(pcm512x_controls), |
1534 | .dapm_widgets = pcm512x_dapm_widgets, |
1535 | .num_dapm_widgets = ARRAY_SIZE(pcm512x_dapm_widgets), |
1536 | .dapm_routes = pcm512x_dapm_routes, |
1537 | .num_dapm_routes = ARRAY_SIZE(pcm512x_dapm_routes), |
1538 | .use_pmdown_time = 1, |
1539 | .endianness = 1, |
1540 | }; |
1541 | |
1542 | static const struct regmap_range_cfg pcm512x_range = { |
1543 | .name = "Pages" , .range_min = PCM512x_VIRT_BASE, |
1544 | .range_max = PCM512x_MAX_REGISTER, |
1545 | .selector_reg = PCM512x_PAGE, |
1546 | .selector_mask = 0xff, |
1547 | .window_start = 0, .window_len = 0x100, |
1548 | }; |
1549 | |
1550 | const struct regmap_config pcm512x_regmap = { |
1551 | .reg_bits = 8, |
1552 | .val_bits = 8, |
1553 | |
1554 | .readable_reg = pcm512x_readable, |
1555 | .volatile_reg = pcm512x_volatile, |
1556 | |
1557 | .ranges = &pcm512x_range, |
1558 | .num_ranges = 1, |
1559 | |
1560 | .max_register = PCM512x_MAX_REGISTER, |
1561 | .reg_defaults = pcm512x_reg_defaults, |
1562 | .num_reg_defaults = ARRAY_SIZE(pcm512x_reg_defaults), |
1563 | .cache_type = REGCACHE_RBTREE, |
1564 | }; |
1565 | EXPORT_SYMBOL_GPL(pcm512x_regmap); |
1566 | |
1567 | int pcm512x_probe(struct device *dev, struct regmap *regmap) |
1568 | { |
1569 | struct pcm512x_priv *pcm512x; |
1570 | int i, ret; |
1571 | |
1572 | pcm512x = devm_kzalloc(dev, size: sizeof(struct pcm512x_priv), GFP_KERNEL); |
1573 | if (!pcm512x) |
1574 | return -ENOMEM; |
1575 | |
1576 | mutex_init(&pcm512x->mutex); |
1577 | |
1578 | dev_set_drvdata(dev, data: pcm512x); |
1579 | pcm512x->regmap = regmap; |
1580 | |
1581 | for (i = 0; i < ARRAY_SIZE(pcm512x->supplies); i++) |
1582 | pcm512x->supplies[i].supply = pcm512x_supply_names[i]; |
1583 | |
1584 | ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(pcm512x->supplies), |
1585 | consumers: pcm512x->supplies); |
1586 | if (ret != 0) { |
1587 | dev_err(dev, "Failed to get supplies: %d\n" , ret); |
1588 | return ret; |
1589 | } |
1590 | |
1591 | pcm512x->supply_nb[0].notifier_call = pcm512x_regulator_event_0; |
1592 | pcm512x->supply_nb[1].notifier_call = pcm512x_regulator_event_1; |
1593 | pcm512x->supply_nb[2].notifier_call = pcm512x_regulator_event_2; |
1594 | |
1595 | for (i = 0; i < ARRAY_SIZE(pcm512x->supplies); i++) { |
1596 | ret = devm_regulator_register_notifier( |
1597 | regulator: pcm512x->supplies[i].consumer, |
1598 | nb: &pcm512x->supply_nb[i]); |
1599 | if (ret != 0) { |
1600 | dev_err(dev, |
1601 | "Failed to register regulator notifier: %d\n" , |
1602 | ret); |
1603 | } |
1604 | } |
1605 | |
1606 | ret = regulator_bulk_enable(ARRAY_SIZE(pcm512x->supplies), |
1607 | consumers: pcm512x->supplies); |
1608 | if (ret != 0) { |
1609 | dev_err(dev, "Failed to enable supplies: %d\n" , ret); |
1610 | return ret; |
1611 | } |
1612 | |
1613 | /* Reset the device, verifying I/O in the process for I2C */ |
1614 | ret = regmap_write(map: regmap, PCM512x_RESET, |
1615 | PCM512x_RSTM | PCM512x_RSTR); |
1616 | if (ret != 0) { |
1617 | dev_err(dev, "Failed to reset device: %d\n" , ret); |
1618 | goto err; |
1619 | } |
1620 | |
1621 | ret = regmap_write(map: regmap, PCM512x_RESET, val: 0); |
1622 | if (ret != 0) { |
1623 | dev_err(dev, "Failed to reset device: %d\n" , ret); |
1624 | goto err; |
1625 | } |
1626 | |
1627 | pcm512x->sclk = devm_clk_get(dev, NULL); |
1628 | if (PTR_ERR(ptr: pcm512x->sclk) == -EPROBE_DEFER) { |
1629 | ret = -EPROBE_DEFER; |
1630 | goto err; |
1631 | } |
1632 | if (!IS_ERR(ptr: pcm512x->sclk)) { |
1633 | ret = clk_prepare_enable(clk: pcm512x->sclk); |
1634 | if (ret != 0) { |
1635 | dev_err(dev, "Failed to enable SCLK: %d\n" , ret); |
1636 | goto err; |
1637 | } |
1638 | } |
1639 | |
1640 | /* Default to standby mode */ |
1641 | ret = regmap_update_bits(map: pcm512x->regmap, PCM512x_POWER, |
1642 | PCM512x_RQST, PCM512x_RQST); |
1643 | if (ret != 0) { |
1644 | dev_err(dev, "Failed to request standby: %d\n" , |
1645 | ret); |
1646 | goto err_clk; |
1647 | } |
1648 | |
1649 | pm_runtime_set_active(dev); |
1650 | pm_runtime_enable(dev); |
1651 | pm_runtime_idle(dev); |
1652 | |
1653 | #ifdef CONFIG_OF |
1654 | if (dev->of_node) { |
1655 | const struct device_node *np = dev->of_node; |
1656 | u32 val; |
1657 | |
1658 | if (of_property_read_u32(np, propname: "pll-in" , out_value: &val) >= 0) { |
1659 | if (val > 6) { |
1660 | dev_err(dev, "Invalid pll-in\n" ); |
1661 | ret = -EINVAL; |
1662 | goto err_pm; |
1663 | } |
1664 | pcm512x->pll_in = val; |
1665 | } |
1666 | |
1667 | if (of_property_read_u32(np, propname: "pll-out" , out_value: &val) >= 0) { |
1668 | if (val > 6) { |
1669 | dev_err(dev, "Invalid pll-out\n" ); |
1670 | ret = -EINVAL; |
1671 | goto err_pm; |
1672 | } |
1673 | pcm512x->pll_out = val; |
1674 | } |
1675 | |
1676 | if (!pcm512x->pll_in != !pcm512x->pll_out) { |
1677 | dev_err(dev, |
1678 | "Error: both pll-in and pll-out, or none\n" ); |
1679 | ret = -EINVAL; |
1680 | goto err_pm; |
1681 | } |
1682 | if (pcm512x->pll_in && pcm512x->pll_in == pcm512x->pll_out) { |
1683 | dev_err(dev, "Error: pll-in == pll-out\n" ); |
1684 | ret = -EINVAL; |
1685 | goto err_pm; |
1686 | } |
1687 | |
1688 | if (!strcmp(np->name, "tas5756" ) || |
1689 | !strcmp(np->name, "tas5754" )) |
1690 | pcm512x->force_pll_on = 1; |
1691 | dev_dbg(dev, "Device ID: %s\n" , np->name); |
1692 | } |
1693 | #endif |
1694 | |
1695 | ret = devm_snd_soc_register_component(dev, component_driver: &pcm512x_component_driver, |
1696 | dai_drv: &pcm512x_dai, num_dai: 1); |
1697 | if (ret != 0) { |
1698 | dev_err(dev, "Failed to register CODEC: %d\n" , ret); |
1699 | goto err_pm; |
1700 | } |
1701 | |
1702 | return 0; |
1703 | |
1704 | err_pm: |
1705 | pm_runtime_disable(dev); |
1706 | err_clk: |
1707 | if (!IS_ERR(ptr: pcm512x->sclk)) |
1708 | clk_disable_unprepare(clk: pcm512x->sclk); |
1709 | err: |
1710 | regulator_bulk_disable(ARRAY_SIZE(pcm512x->supplies), |
1711 | consumers: pcm512x->supplies); |
1712 | return ret; |
1713 | } |
1714 | EXPORT_SYMBOL_GPL(pcm512x_probe); |
1715 | |
1716 | void pcm512x_remove(struct device *dev) |
1717 | { |
1718 | struct pcm512x_priv *pcm512x = dev_get_drvdata(dev); |
1719 | |
1720 | pm_runtime_disable(dev); |
1721 | if (!IS_ERR(ptr: pcm512x->sclk)) |
1722 | clk_disable_unprepare(clk: pcm512x->sclk); |
1723 | regulator_bulk_disable(ARRAY_SIZE(pcm512x->supplies), |
1724 | consumers: pcm512x->supplies); |
1725 | } |
1726 | EXPORT_SYMBOL_GPL(pcm512x_remove); |
1727 | |
1728 | #ifdef CONFIG_PM |
1729 | static int pcm512x_suspend(struct device *dev) |
1730 | { |
1731 | struct pcm512x_priv *pcm512x = dev_get_drvdata(dev); |
1732 | int ret; |
1733 | |
1734 | ret = regmap_update_bits(map: pcm512x->regmap, PCM512x_POWER, |
1735 | PCM512x_RQPD, PCM512x_RQPD); |
1736 | if (ret != 0) { |
1737 | dev_err(dev, "Failed to request power down: %d\n" , ret); |
1738 | return ret; |
1739 | } |
1740 | |
1741 | ret = regulator_bulk_disable(ARRAY_SIZE(pcm512x->supplies), |
1742 | consumers: pcm512x->supplies); |
1743 | if (ret != 0) { |
1744 | dev_err(dev, "Failed to disable supplies: %d\n" , ret); |
1745 | return ret; |
1746 | } |
1747 | |
1748 | if (!IS_ERR(ptr: pcm512x->sclk)) |
1749 | clk_disable_unprepare(clk: pcm512x->sclk); |
1750 | |
1751 | return 0; |
1752 | } |
1753 | |
1754 | static int pcm512x_resume(struct device *dev) |
1755 | { |
1756 | struct pcm512x_priv *pcm512x = dev_get_drvdata(dev); |
1757 | int ret; |
1758 | |
1759 | if (!IS_ERR(ptr: pcm512x->sclk)) { |
1760 | ret = clk_prepare_enable(clk: pcm512x->sclk); |
1761 | if (ret != 0) { |
1762 | dev_err(dev, "Failed to enable SCLK: %d\n" , ret); |
1763 | return ret; |
1764 | } |
1765 | } |
1766 | |
1767 | ret = regulator_bulk_enable(ARRAY_SIZE(pcm512x->supplies), |
1768 | consumers: pcm512x->supplies); |
1769 | if (ret != 0) { |
1770 | dev_err(dev, "Failed to enable supplies: %d\n" , ret); |
1771 | return ret; |
1772 | } |
1773 | |
1774 | regcache_cache_only(map: pcm512x->regmap, enable: false); |
1775 | ret = regcache_sync(map: pcm512x->regmap); |
1776 | if (ret != 0) { |
1777 | dev_err(dev, "Failed to sync cache: %d\n" , ret); |
1778 | return ret; |
1779 | } |
1780 | |
1781 | ret = regmap_update_bits(map: pcm512x->regmap, PCM512x_POWER, |
1782 | PCM512x_RQPD, val: 0); |
1783 | if (ret != 0) { |
1784 | dev_err(dev, "Failed to remove power down: %d\n" , ret); |
1785 | return ret; |
1786 | } |
1787 | |
1788 | return 0; |
1789 | } |
1790 | #endif |
1791 | |
1792 | const struct dev_pm_ops pcm512x_pm_ops = { |
1793 | SET_RUNTIME_PM_OPS(pcm512x_suspend, pcm512x_resume, NULL) |
1794 | }; |
1795 | EXPORT_SYMBOL_GPL(pcm512x_pm_ops); |
1796 | |
1797 | MODULE_DESCRIPTION("ASoC PCM512x codec driver" ); |
1798 | MODULE_AUTHOR("Mark Brown <broonie@kernel.org>" ); |
1799 | MODULE_LICENSE("GPL v2" ); |
1800 | |