1 | // SPDX-License-Identifier: GPL-2.0-only |
2 | // |
3 | // rt1316-sdw.c -- rt1316 SDCA ALSA SoC amplifier audio driver |
4 | // |
5 | // Copyright(c) 2021 Realtek Semiconductor Corp. |
6 | // |
7 | // |
8 | #include <linux/delay.h> |
9 | #include <linux/device.h> |
10 | #include <linux/pm_runtime.h> |
11 | #include <linux/mod_devicetable.h> |
12 | #include <linux/module.h> |
13 | #include <linux/regmap.h> |
14 | #include <sound/core.h> |
15 | #include <sound/pcm.h> |
16 | #include <sound/pcm_params.h> |
17 | #include <sound/sdw.h> |
18 | #include <sound/soc-dapm.h> |
19 | #include <sound/initval.h> |
20 | #include "rt1316-sdw.h" |
21 | |
22 | static const struct reg_default rt1316_reg_defaults[] = { |
23 | { 0x3004, 0x00 }, |
24 | { 0x3005, 0x00 }, |
25 | { 0x3206, 0x00 }, |
26 | { 0xc001, 0x00 }, |
27 | { 0xc002, 0x00 }, |
28 | { 0xc003, 0x00 }, |
29 | { 0xc004, 0x00 }, |
30 | { 0xc005, 0x00 }, |
31 | { 0xc006, 0x00 }, |
32 | { 0xc007, 0x00 }, |
33 | { 0xc008, 0x00 }, |
34 | { 0xc009, 0x00 }, |
35 | { 0xc00a, 0x00 }, |
36 | { 0xc00b, 0x00 }, |
37 | { 0xc00c, 0x00 }, |
38 | { 0xc00d, 0x00 }, |
39 | { 0xc00e, 0x00 }, |
40 | { 0xc00f, 0x00 }, |
41 | { 0xc010, 0xa5 }, |
42 | { 0xc011, 0x00 }, |
43 | { 0xc012, 0xff }, |
44 | { 0xc013, 0xff }, |
45 | { 0xc014, 0x40 }, |
46 | { 0xc015, 0x00 }, |
47 | { 0xc016, 0x00 }, |
48 | { 0xc017, 0x00 }, |
49 | { 0xc605, 0x30 }, |
50 | { 0xc700, 0x0a }, |
51 | { 0xc701, 0xaa }, |
52 | { 0xc702, 0x1a }, |
53 | { 0xc703, 0x0a }, |
54 | { 0xc710, 0x80 }, |
55 | { 0xc711, 0x00 }, |
56 | { 0xc712, 0x3e }, |
57 | { 0xc713, 0x80 }, |
58 | { 0xc714, 0x80 }, |
59 | { 0xc715, 0x06 }, |
60 | { 0xd101, 0x00 }, |
61 | { 0xd102, 0x30 }, |
62 | { 0xd103, 0x00 }, |
63 | { SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1316_SDCA_ENT_UDMPU21, RT1316_SDCA_CTL_UDMPU_CLUSTER, 0), 0x00 }, |
64 | { SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1316_SDCA_ENT_FU21, RT1316_SDCA_CTL_FU_MUTE, CH_L), 0x01 }, |
65 | { SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1316_SDCA_ENT_FU21, RT1316_SDCA_CTL_FU_MUTE, CH_R), 0x01 }, |
66 | { SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1316_SDCA_ENT_XU24, RT1316_SDCA_CTL_BYPASS, 0), 0x01 }, |
67 | { SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1316_SDCA_ENT_PDE23, RT1316_SDCA_CTL_REQ_POWER_STATE, 0), 0x03 }, |
68 | { SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1316_SDCA_ENT_PDE22, RT1316_SDCA_CTL_REQ_POWER_STATE, 0), 0x03 }, |
69 | { SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1316_SDCA_ENT_PDE24, RT1316_SDCA_CTL_REQ_POWER_STATE, 0), 0x03 }, |
70 | }; |
71 | |
72 | static const struct reg_sequence rt1316_blind_write[] = { |
73 | { 0xc710, 0x17 }, |
74 | { 0xc711, 0x80 }, |
75 | { 0xc712, 0x26 }, |
76 | { 0xc713, 0x06 }, |
77 | { 0xc714, 0x80 }, |
78 | { 0xc715, 0x06 }, |
79 | { 0xc702, 0x0a }, |
80 | { 0xc703, 0x0a }, |
81 | { 0xc001, 0x45 }, |
82 | { 0xc003, 0x00 }, |
83 | { 0xc004, 0x11 }, |
84 | { 0xc005, 0x00 }, |
85 | { 0xc006, 0x00 }, |
86 | { 0xc106, 0x00 }, |
87 | { 0xc007, 0x11 }, |
88 | { 0xc008, 0x11 }, |
89 | { 0xc009, 0x00 }, |
90 | |
91 | { 0x2f0a, 0x00 }, |
92 | { 0xd101, 0xf0 }, |
93 | { 0xd103, 0x9b }, |
94 | { 0x2f36, 0x8e }, |
95 | { 0x3206, 0x80 }, |
96 | { 0x3211, 0x0b }, |
97 | { 0x3216, 0x06 }, |
98 | { 0xc614, 0x20 }, |
99 | { 0xc615, 0x0a }, |
100 | { 0xc616, 0x02 }, |
101 | { 0xc617, 0x00 }, |
102 | { 0xc60b, 0x10 }, |
103 | { 0xc60e, 0x05 }, |
104 | { 0xc102, 0x00 }, |
105 | { 0xc090, 0xb0 }, |
106 | { 0xc00f, 0x01 }, |
107 | { 0xc09c, 0x7b }, |
108 | |
109 | { 0xc602, 0x07 }, |
110 | { 0xc603, 0x07 }, |
111 | { 0xc0a3, 0x71 }, |
112 | { 0xc00b, 0x30 }, |
113 | { 0xc093, 0x80 }, |
114 | { 0xc09d, 0x80 }, |
115 | { 0xc0b0, 0x77 }, |
116 | { 0xc010, 0xa5 }, |
117 | { 0xc050, 0x83 }, |
118 | { 0x2f55, 0x03 }, |
119 | { 0x3217, 0xb5 }, |
120 | { 0x3202, 0x02 }, |
121 | |
122 | { SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1316_SDCA_ENT_XU24, RT1316_SDCA_CTL_BYPASS, 0), 0x00 }, |
123 | |
124 | /* for IV sense */ |
125 | { 0x2232, 0x80 }, |
126 | { 0xc0b0, 0x77 }, |
127 | { 0xc011, 0x00 }, |
128 | { 0xc020, 0x00 }, |
129 | { 0xc023, 0x00 }, |
130 | { 0x3101, 0x00 }, |
131 | { 0x3004, 0xa0 }, |
132 | { 0x3005, 0xb1 }, |
133 | { 0xc007, 0x11 }, |
134 | { 0xc008, 0x11 }, |
135 | { 0xc009, 0x00 }, |
136 | { 0xc022, 0xd6 }, |
137 | { 0xc025, 0xd6 }, |
138 | |
139 | { 0xd001, 0x03 }, |
140 | { 0xd002, 0xbf }, |
141 | { 0xd003, 0x03 }, |
142 | { 0xd004, 0xbf }, |
143 | }; |
144 | |
145 | static bool rt1316_readable_register(struct device *dev, unsigned int reg) |
146 | { |
147 | switch (reg) { |
148 | case 0x2f0a: |
149 | case 0x2f36: |
150 | case 0x3203 ... 0x320e: |
151 | case 0xc000 ... 0xc7b4: |
152 | case 0xcf00 ... 0xcf03: |
153 | case 0xd101 ... 0xd103: |
154 | case SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1316_SDCA_ENT_UDMPU21, RT1316_SDCA_CTL_UDMPU_CLUSTER, 0): |
155 | case SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1316_SDCA_ENT_FU21, RT1316_SDCA_CTL_FU_MUTE, CH_L): |
156 | case SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1316_SDCA_ENT_FU21, RT1316_SDCA_CTL_FU_MUTE, CH_R): |
157 | case SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1316_SDCA_ENT_PDE23, RT1316_SDCA_CTL_REQ_POWER_STATE, 0): |
158 | case SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1316_SDCA_ENT_PDE27, RT1316_SDCA_CTL_REQ_POWER_STATE, 0): |
159 | case SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1316_SDCA_ENT_PDE22, RT1316_SDCA_CTL_REQ_POWER_STATE, 0): |
160 | case SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1316_SDCA_ENT_PDE24, RT1316_SDCA_CTL_REQ_POWER_STATE, 0): |
161 | return true; |
162 | default: |
163 | return false; |
164 | } |
165 | } |
166 | |
167 | static bool rt1316_volatile_register(struct device *dev, unsigned int reg) |
168 | { |
169 | switch (reg) { |
170 | case 0xc000: |
171 | case 0xc093: |
172 | case 0xc09d: |
173 | case 0xc0a3: |
174 | case 0xc201: |
175 | case 0xc427 ... 0xc428: |
176 | case 0xd102: |
177 | return true; |
178 | default: |
179 | return false; |
180 | } |
181 | } |
182 | |
183 | static const struct regmap_config rt1316_sdw_regmap = { |
184 | .reg_bits = 32, |
185 | .val_bits = 8, |
186 | .readable_reg = rt1316_readable_register, |
187 | .volatile_reg = rt1316_volatile_register, |
188 | .max_register = 0x4108ffff, |
189 | .reg_defaults = rt1316_reg_defaults, |
190 | .num_reg_defaults = ARRAY_SIZE(rt1316_reg_defaults), |
191 | .cache_type = REGCACHE_MAPLE, |
192 | .use_single_read = true, |
193 | .use_single_write = true, |
194 | }; |
195 | |
196 | static int rt1316_read_prop(struct sdw_slave *slave) |
197 | { |
198 | struct sdw_slave_prop *prop = &slave->prop; |
199 | int nval; |
200 | int i, j; |
201 | u32 bit; |
202 | unsigned long addr; |
203 | struct sdw_dpn_prop *dpn; |
204 | |
205 | prop->scp_int1_mask = SDW_SCP_INT1_BUS_CLASH | SDW_SCP_INT1_PARITY; |
206 | prop->quirks = SDW_SLAVE_QUIRKS_INVALID_INITIAL_PARITY; |
207 | |
208 | prop->paging_support = true; |
209 | |
210 | /* first we need to allocate memory for set bits in port lists */ |
211 | prop->source_ports = 0x04; /* BITMAP: 00000100 */ |
212 | prop->sink_ports = 0x2; /* BITMAP: 00000010 */ |
213 | |
214 | nval = hweight32(prop->source_ports); |
215 | prop->src_dpn_prop = devm_kcalloc(dev: &slave->dev, n: nval, |
216 | size: sizeof(*prop->src_dpn_prop), GFP_KERNEL); |
217 | if (!prop->src_dpn_prop) |
218 | return -ENOMEM; |
219 | |
220 | i = 0; |
221 | dpn = prop->src_dpn_prop; |
222 | addr = prop->source_ports; |
223 | for_each_set_bit(bit, &addr, 32) { |
224 | dpn[i].num = bit; |
225 | dpn[i].type = SDW_DPN_FULL; |
226 | dpn[i].simple_ch_prep_sm = true; |
227 | dpn[i].ch_prep_timeout = 10; |
228 | i++; |
229 | } |
230 | |
231 | /* do this again for sink now */ |
232 | nval = hweight32(prop->sink_ports); |
233 | prop->sink_dpn_prop = devm_kcalloc(dev: &slave->dev, n: nval, |
234 | size: sizeof(*prop->sink_dpn_prop), GFP_KERNEL); |
235 | if (!prop->sink_dpn_prop) |
236 | return -ENOMEM; |
237 | |
238 | j = 0; |
239 | dpn = prop->sink_dpn_prop; |
240 | addr = prop->sink_ports; |
241 | for_each_set_bit(bit, &addr, 32) { |
242 | dpn[j].num = bit; |
243 | dpn[j].type = SDW_DPN_FULL; |
244 | dpn[j].simple_ch_prep_sm = true; |
245 | dpn[j].ch_prep_timeout = 10; |
246 | j++; |
247 | } |
248 | |
249 | /* set the timeout values */ |
250 | prop->clk_stop_timeout = 20; |
251 | |
252 | dev_dbg(&slave->dev, "%s\n" , __func__); |
253 | |
254 | return 0; |
255 | } |
256 | |
257 | static void rt1316_apply_bq_params(struct rt1316_sdw_priv *rt1316) |
258 | { |
259 | unsigned int i, reg, data; |
260 | |
261 | for (i = 0; i < rt1316->bq_params_cnt; i += 3) { |
262 | reg = rt1316->bq_params[i] | (rt1316->bq_params[i + 1] << 8); |
263 | data = rt1316->bq_params[i + 2]; |
264 | regmap_write(map: rt1316->regmap, reg, val: data); |
265 | } |
266 | } |
267 | |
268 | static int rt1316_io_init(struct device *dev, struct sdw_slave *slave) |
269 | { |
270 | struct rt1316_sdw_priv *rt1316 = dev_get_drvdata(dev); |
271 | |
272 | if (rt1316->hw_init) |
273 | return 0; |
274 | |
275 | regcache_cache_only(map: rt1316->regmap, enable: false); |
276 | if (rt1316->first_hw_init) { |
277 | regcache_cache_bypass(map: rt1316->regmap, enable: true); |
278 | } else { |
279 | /* |
280 | * PM runtime status is marked as 'active' only when a Slave reports as Attached |
281 | */ |
282 | |
283 | /* update count of parent 'active' children */ |
284 | pm_runtime_set_active(dev: &slave->dev); |
285 | } |
286 | |
287 | pm_runtime_get_noresume(dev: &slave->dev); |
288 | |
289 | /* sw reset */ |
290 | regmap_write(map: rt1316->regmap, reg: 0xc000, val: 0x02); |
291 | |
292 | /* initial settings - blind write */ |
293 | regmap_multi_reg_write(map: rt1316->regmap, regs: rt1316_blind_write, |
294 | ARRAY_SIZE(rt1316_blind_write)); |
295 | |
296 | if (rt1316->first_hw_init) { |
297 | regcache_cache_bypass(map: rt1316->regmap, enable: false); |
298 | regcache_mark_dirty(map: rt1316->regmap); |
299 | } else |
300 | rt1316->first_hw_init = true; |
301 | |
302 | /* Mark Slave initialization complete */ |
303 | rt1316->hw_init = true; |
304 | |
305 | pm_runtime_mark_last_busy(dev: &slave->dev); |
306 | pm_runtime_put_autosuspend(dev: &slave->dev); |
307 | |
308 | dev_dbg(&slave->dev, "%s hw_init complete\n" , __func__); |
309 | return 0; |
310 | } |
311 | |
312 | static int rt1316_update_status(struct sdw_slave *slave, |
313 | enum sdw_slave_status status) |
314 | { |
315 | struct rt1316_sdw_priv *rt1316 = dev_get_drvdata(dev: &slave->dev); |
316 | |
317 | if (status == SDW_SLAVE_UNATTACHED) |
318 | rt1316->hw_init = false; |
319 | |
320 | /* |
321 | * Perform initialization only if slave status is present and |
322 | * hw_init flag is false |
323 | */ |
324 | if (rt1316->hw_init || status != SDW_SLAVE_ATTACHED) |
325 | return 0; |
326 | |
327 | /* perform I/O transfers required for Slave initialization */ |
328 | return rt1316_io_init(dev: &slave->dev, slave); |
329 | } |
330 | |
331 | static int rt1316_classd_event(struct snd_soc_dapm_widget *w, |
332 | struct snd_kcontrol *kcontrol, int event) |
333 | { |
334 | struct snd_soc_component *component = |
335 | snd_soc_dapm_to_component(dapm: w->dapm); |
336 | struct rt1316_sdw_priv *rt1316 = snd_soc_component_get_drvdata(c: component); |
337 | unsigned char ps0 = 0x0, ps3 = 0x3; |
338 | |
339 | switch (event) { |
340 | case SND_SOC_DAPM_POST_PMU: |
341 | regmap_write(map: rt1316->regmap, |
342 | SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1316_SDCA_ENT_PDE23, |
343 | RT1316_SDCA_CTL_REQ_POWER_STATE, 0), |
344 | val: ps0); |
345 | regmap_write(map: rt1316->regmap, |
346 | SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1316_SDCA_ENT_PDE27, |
347 | RT1316_SDCA_CTL_REQ_POWER_STATE, 0), |
348 | val: ps0); |
349 | regmap_write(map: rt1316->regmap, |
350 | SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1316_SDCA_ENT_PDE22, |
351 | RT1316_SDCA_CTL_REQ_POWER_STATE, 0), |
352 | val: ps0); |
353 | break; |
354 | case SND_SOC_DAPM_PRE_PMD: |
355 | regmap_write(map: rt1316->regmap, |
356 | SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1316_SDCA_ENT_PDE23, |
357 | RT1316_SDCA_CTL_REQ_POWER_STATE, 0), |
358 | val: ps3); |
359 | regmap_write(map: rt1316->regmap, |
360 | SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1316_SDCA_ENT_PDE27, |
361 | RT1316_SDCA_CTL_REQ_POWER_STATE, 0), |
362 | val: ps3); |
363 | regmap_write(map: rt1316->regmap, |
364 | SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1316_SDCA_ENT_PDE22, |
365 | RT1316_SDCA_CTL_REQ_POWER_STATE, 0), |
366 | val: ps3); |
367 | break; |
368 | |
369 | default: |
370 | break; |
371 | } |
372 | |
373 | return 0; |
374 | } |
375 | |
376 | static int rt1316_pde24_event(struct snd_soc_dapm_widget *w, |
377 | struct snd_kcontrol *kcontrol, int event) |
378 | { |
379 | struct snd_soc_component *component = |
380 | snd_soc_dapm_to_component(dapm: w->dapm); |
381 | struct rt1316_sdw_priv *rt1316 = snd_soc_component_get_drvdata(c: component); |
382 | unsigned char ps0 = 0x0, ps3 = 0x3; |
383 | |
384 | switch (event) { |
385 | case SND_SOC_DAPM_POST_PMU: |
386 | regmap_write(map: rt1316->regmap, |
387 | SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1316_SDCA_ENT_PDE24, |
388 | RT1316_SDCA_CTL_REQ_POWER_STATE, 0), |
389 | val: ps0); |
390 | break; |
391 | case SND_SOC_DAPM_PRE_PMD: |
392 | regmap_write(map: rt1316->regmap, |
393 | SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1316_SDCA_ENT_PDE24, |
394 | RT1316_SDCA_CTL_REQ_POWER_STATE, 0), |
395 | val: ps3); |
396 | break; |
397 | } |
398 | return 0; |
399 | } |
400 | |
401 | static const char * const rt1316_rx_data_ch_select[] = { |
402 | "L,R" , |
403 | "L,L" , |
404 | "L,R" , |
405 | "L,L+R" , |
406 | "R,L" , |
407 | "R,R" , |
408 | "R,L+R" , |
409 | "L+R,L" , |
410 | "L+R,R" , |
411 | "L+R,L+R" , |
412 | }; |
413 | |
414 | static SOC_ENUM_SINGLE_DECL(rt1316_rx_data_ch_enum, |
415 | SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1316_SDCA_ENT_UDMPU21, RT1316_SDCA_CTL_UDMPU_CLUSTER, 0), 0, |
416 | rt1316_rx_data_ch_select); |
417 | |
418 | static const char * const rt1316_dac_output_vol_select[] = { |
419 | "immediately" , |
420 | "zero crossing" , |
421 | "zero crossing with soft ramp" , |
422 | }; |
423 | |
424 | static SOC_ENUM_SINGLE_DECL(rt1316_dac_vol_ctl_enum, |
425 | 0xc010, 6, rt1316_dac_output_vol_select); |
426 | |
427 | static const struct snd_kcontrol_new rt1316_snd_controls[] = { |
428 | |
429 | /* I2S Data Channel Selection */ |
430 | SOC_ENUM("RX Channel Select" , rt1316_rx_data_ch_enum), |
431 | |
432 | /* XU24 Bypass Control */ |
433 | SOC_SINGLE("XU24 Bypass Switch" , |
434 | SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1316_SDCA_ENT_XU24, RT1316_SDCA_CTL_BYPASS, 0), 0, 1, 0), |
435 | |
436 | /* Left/Right IV tag */ |
437 | SOC_SINGLE("Left V Tag Select" , 0x3004, 0, 7, 0), |
438 | SOC_SINGLE("Left I Tag Select" , 0x3004, 4, 7, 0), |
439 | SOC_SINGLE("Right V Tag Select" , 0x3005, 0, 7, 0), |
440 | SOC_SINGLE("Right I Tag Select" , 0x3005, 4, 7, 0), |
441 | |
442 | /* IV mixer Control */ |
443 | SOC_DOUBLE("Isense Mixer Switch" , 0xc605, 2, 0, 1, 1), |
444 | SOC_DOUBLE("Vsense Mixer Switch" , 0xc605, 3, 1, 1, 1), |
445 | |
446 | /* DAC Output Volume Control */ |
447 | SOC_ENUM("DAC Output Vol Control" , rt1316_dac_vol_ctl_enum), |
448 | }; |
449 | |
450 | static const struct snd_kcontrol_new rt1316_sto_dac = |
451 | SOC_DAPM_DOUBLE_R("Switch" , |
452 | SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1316_SDCA_ENT_FU21, RT1316_SDCA_CTL_FU_MUTE, CH_L), |
453 | SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1316_SDCA_ENT_FU21, RT1316_SDCA_CTL_FU_MUTE, CH_R), |
454 | 0, 1, 1); |
455 | |
456 | static const struct snd_soc_dapm_widget rt1316_dapm_widgets[] = { |
457 | /* Audio Interface */ |
458 | SND_SOC_DAPM_AIF_IN("DP1RX" , "DP1 Playback" , 0, SND_SOC_NOPM, 0, 0), |
459 | SND_SOC_DAPM_AIF_OUT("DP2TX" , "DP2 Capture" , 0, SND_SOC_NOPM, 0, 0), |
460 | |
461 | /* Digital Interface */ |
462 | SND_SOC_DAPM_SWITCH("DAC" , SND_SOC_NOPM, 0, 0, &rt1316_sto_dac), |
463 | |
464 | /* Output Lines */ |
465 | SND_SOC_DAPM_PGA_E("CLASS D" , SND_SOC_NOPM, 0, 0, NULL, 0, |
466 | rt1316_classd_event, |
467 | SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU), |
468 | SND_SOC_DAPM_OUTPUT("SPOL" ), |
469 | SND_SOC_DAPM_OUTPUT("SPOR" ), |
470 | |
471 | SND_SOC_DAPM_SUPPLY("PDE 24" , SND_SOC_NOPM, 0, 0, |
472 | rt1316_pde24_event, |
473 | SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), |
474 | SND_SOC_DAPM_PGA("I Sense" , SND_SOC_NOPM, 0, 0, NULL, 0), |
475 | SND_SOC_DAPM_PGA("V Sense" , SND_SOC_NOPM, 0, 0, NULL, 0), |
476 | SND_SOC_DAPM_SIGGEN("I Gen" ), |
477 | SND_SOC_DAPM_SIGGEN("V Gen" ), |
478 | }; |
479 | |
480 | static const struct snd_soc_dapm_route rt1316_dapm_routes[] = { |
481 | { "DAC" , "Switch" , "DP1RX" }, |
482 | { "CLASS D" , NULL, "DAC" }, |
483 | { "SPOL" , NULL, "CLASS D" }, |
484 | { "SPOR" , NULL, "CLASS D" }, |
485 | |
486 | { "I Sense" , NULL, "I Gen" }, |
487 | { "V Sense" , NULL, "V Gen" }, |
488 | { "I Sense" , NULL, "PDE 24" }, |
489 | { "V Sense" , NULL, "PDE 24" }, |
490 | { "DP2TX" , NULL, "I Sense" }, |
491 | { "DP2TX" , NULL, "V Sense" }, |
492 | }; |
493 | |
494 | static int rt1316_set_sdw_stream(struct snd_soc_dai *dai, void *sdw_stream, |
495 | int direction) |
496 | { |
497 | snd_soc_dai_dma_data_set(dai, stream: direction, data: sdw_stream); |
498 | |
499 | return 0; |
500 | } |
501 | |
502 | static void rt1316_sdw_shutdown(struct snd_pcm_substream *substream, |
503 | struct snd_soc_dai *dai) |
504 | { |
505 | snd_soc_dai_set_dma_data(dai, substream, NULL); |
506 | } |
507 | |
508 | static int rt1316_sdw_hw_params(struct snd_pcm_substream *substream, |
509 | struct snd_pcm_hw_params *params, struct snd_soc_dai *dai) |
510 | { |
511 | struct snd_soc_component *component = dai->component; |
512 | struct rt1316_sdw_priv *rt1316 = |
513 | snd_soc_component_get_drvdata(c: component); |
514 | struct sdw_stream_config stream_config = {0}; |
515 | struct sdw_port_config port_config = {0}; |
516 | struct sdw_stream_runtime *sdw_stream; |
517 | int retval; |
518 | |
519 | dev_dbg(dai->dev, "%s %s" , __func__, dai->name); |
520 | sdw_stream = snd_soc_dai_get_dma_data(dai, substream); |
521 | |
522 | if (!sdw_stream) |
523 | return -EINVAL; |
524 | |
525 | if (!rt1316->sdw_slave) |
526 | return -EINVAL; |
527 | |
528 | /* SoundWire specific configuration */ |
529 | snd_sdw_params_to_config(substream, params, stream_config: &stream_config, port_config: &port_config); |
530 | |
531 | /* port 1 for playback */ |
532 | if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) |
533 | port_config.num = 1; |
534 | else |
535 | port_config.num = 2; |
536 | |
537 | retval = sdw_stream_add_slave(slave: rt1316->sdw_slave, stream_config: &stream_config, |
538 | port_config: &port_config, num_ports: 1, stream: sdw_stream); |
539 | if (retval) { |
540 | dev_err(dai->dev, "%s: Unable to configure port\n" , __func__); |
541 | return retval; |
542 | } |
543 | |
544 | return 0; |
545 | } |
546 | |
547 | static int rt1316_sdw_pcm_hw_free(struct snd_pcm_substream *substream, |
548 | struct snd_soc_dai *dai) |
549 | { |
550 | struct snd_soc_component *component = dai->component; |
551 | struct rt1316_sdw_priv *rt1316 = |
552 | snd_soc_component_get_drvdata(c: component); |
553 | struct sdw_stream_runtime *sdw_stream = |
554 | snd_soc_dai_get_dma_data(dai, substream); |
555 | |
556 | if (!rt1316->sdw_slave) |
557 | return -EINVAL; |
558 | |
559 | sdw_stream_remove_slave(slave: rt1316->sdw_slave, stream: sdw_stream); |
560 | return 0; |
561 | } |
562 | |
563 | /* |
564 | * slave_ops: callbacks for get_clock_stop_mode, clock_stop and |
565 | * port_prep are not defined for now |
566 | */ |
567 | static const struct sdw_slave_ops rt1316_slave_ops = { |
568 | .read_prop = rt1316_read_prop, |
569 | .update_status = rt1316_update_status, |
570 | }; |
571 | |
572 | static int rt1316_sdw_parse_dt(struct rt1316_sdw_priv *rt1316, struct device *dev) |
573 | { |
574 | int ret = 0; |
575 | |
576 | device_property_read_u32(dev, propname: "realtek,bq-params-cnt" , val: &rt1316->bq_params_cnt); |
577 | if (rt1316->bq_params_cnt) { |
578 | rt1316->bq_params = devm_kzalloc(dev, size: rt1316->bq_params_cnt, GFP_KERNEL); |
579 | if (!rt1316->bq_params) { |
580 | dev_err(dev, "%s: Could not allocate bq_params memory\n" , __func__); |
581 | ret = -ENOMEM; |
582 | } else { |
583 | ret = device_property_read_u8_array(dev, propname: "realtek,bq-params" , val: rt1316->bq_params, nval: rt1316->bq_params_cnt); |
584 | if (ret < 0) |
585 | dev_err(dev, "%s: Could not read list of realtek,bq-params\n" , __func__); |
586 | } |
587 | } |
588 | |
589 | dev_dbg(dev, "bq_params_cnt=%d\n" , rt1316->bq_params_cnt); |
590 | return ret; |
591 | } |
592 | |
593 | static int rt1316_sdw_component_probe(struct snd_soc_component *component) |
594 | { |
595 | struct rt1316_sdw_priv *rt1316 = snd_soc_component_get_drvdata(c: component); |
596 | int ret; |
597 | |
598 | rt1316->component = component; |
599 | rt1316_sdw_parse_dt(rt1316, dev: &rt1316->sdw_slave->dev); |
600 | |
601 | if (!rt1316->first_hw_init) |
602 | return 0; |
603 | |
604 | ret = pm_runtime_resume(dev: component->dev); |
605 | if (ret < 0 && ret != -EACCES) |
606 | return ret; |
607 | |
608 | /* apply BQ params */ |
609 | rt1316_apply_bq_params(rt1316); |
610 | |
611 | return 0; |
612 | } |
613 | |
614 | static const struct snd_soc_component_driver soc_component_sdw_rt1316 = { |
615 | .probe = rt1316_sdw_component_probe, |
616 | .controls = rt1316_snd_controls, |
617 | .num_controls = ARRAY_SIZE(rt1316_snd_controls), |
618 | .dapm_widgets = rt1316_dapm_widgets, |
619 | .num_dapm_widgets = ARRAY_SIZE(rt1316_dapm_widgets), |
620 | .dapm_routes = rt1316_dapm_routes, |
621 | .num_dapm_routes = ARRAY_SIZE(rt1316_dapm_routes), |
622 | .endianness = 1, |
623 | }; |
624 | |
625 | static const struct snd_soc_dai_ops rt1316_aif_dai_ops = { |
626 | .hw_params = rt1316_sdw_hw_params, |
627 | .hw_free = rt1316_sdw_pcm_hw_free, |
628 | .set_stream = rt1316_set_sdw_stream, |
629 | .shutdown = rt1316_sdw_shutdown, |
630 | }; |
631 | |
632 | #define RT1316_STEREO_RATES SNDRV_PCM_RATE_48000 |
633 | #define RT1316_FORMATS (SNDRV_PCM_FMTBIT_S20_3LE | SNDRV_PCM_FMTBIT_S16_LE | \ |
634 | SNDRV_PCM_FMTBIT_S24_LE) |
635 | |
636 | static struct snd_soc_dai_driver rt1316_sdw_dai[] = { |
637 | { |
638 | .name = "rt1316-aif" , |
639 | .playback = { |
640 | .stream_name = "DP1 Playback" , |
641 | .channels_min = 1, |
642 | .channels_max = 2, |
643 | .rates = RT1316_STEREO_RATES, |
644 | .formats = RT1316_FORMATS, |
645 | }, |
646 | .capture = { |
647 | .stream_name = "DP2 Capture" , |
648 | .channels_min = 1, |
649 | .channels_max = 2, |
650 | .rates = RT1316_STEREO_RATES, |
651 | .formats = RT1316_FORMATS, |
652 | }, |
653 | .ops = &rt1316_aif_dai_ops, |
654 | }, |
655 | }; |
656 | |
657 | static int rt1316_sdw_init(struct device *dev, struct regmap *regmap, |
658 | struct sdw_slave *slave) |
659 | { |
660 | struct rt1316_sdw_priv *rt1316; |
661 | int ret; |
662 | |
663 | rt1316 = devm_kzalloc(dev, size: sizeof(*rt1316), GFP_KERNEL); |
664 | if (!rt1316) |
665 | return -ENOMEM; |
666 | |
667 | dev_set_drvdata(dev, data: rt1316); |
668 | rt1316->sdw_slave = slave; |
669 | rt1316->regmap = regmap; |
670 | |
671 | regcache_cache_only(map: rt1316->regmap, enable: true); |
672 | |
673 | /* |
674 | * Mark hw_init to false |
675 | * HW init will be performed when device reports present |
676 | */ |
677 | rt1316->hw_init = false; |
678 | rt1316->first_hw_init = false; |
679 | |
680 | ret = devm_snd_soc_register_component(dev, |
681 | component_driver: &soc_component_sdw_rt1316, |
682 | dai_drv: rt1316_sdw_dai, |
683 | ARRAY_SIZE(rt1316_sdw_dai)); |
684 | if (ret < 0) |
685 | return ret; |
686 | |
687 | /* set autosuspend parameters */ |
688 | pm_runtime_set_autosuspend_delay(dev, delay: 3000); |
689 | pm_runtime_use_autosuspend(dev); |
690 | |
691 | /* make sure the device does not suspend immediately */ |
692 | pm_runtime_mark_last_busy(dev); |
693 | |
694 | pm_runtime_enable(dev); |
695 | |
696 | /* important note: the device is NOT tagged as 'active' and will remain |
697 | * 'suspended' until the hardware is enumerated/initialized. This is required |
698 | * to make sure the ASoC framework use of pm_runtime_get_sync() does not silently |
699 | * fail with -EACCESS because of race conditions between card creation and enumeration |
700 | */ |
701 | |
702 | dev_dbg(dev, "%s\n" , __func__); |
703 | |
704 | return 0; |
705 | } |
706 | |
707 | static int rt1316_sdw_probe(struct sdw_slave *slave, |
708 | const struct sdw_device_id *id) |
709 | { |
710 | struct regmap *regmap; |
711 | |
712 | /* Regmap Initialization */ |
713 | regmap = devm_regmap_init_sdw(slave, &rt1316_sdw_regmap); |
714 | if (IS_ERR(ptr: regmap)) |
715 | return PTR_ERR(ptr: regmap); |
716 | |
717 | return rt1316_sdw_init(dev: &slave->dev, regmap, slave); |
718 | } |
719 | |
720 | static int rt1316_sdw_remove(struct sdw_slave *slave) |
721 | { |
722 | pm_runtime_disable(dev: &slave->dev); |
723 | |
724 | return 0; |
725 | } |
726 | |
727 | static const struct sdw_device_id rt1316_id[] = { |
728 | SDW_SLAVE_ENTRY_EXT(0x025d, 0x1316, 0x3, 0x1, 0), |
729 | {}, |
730 | }; |
731 | MODULE_DEVICE_TABLE(sdw, rt1316_id); |
732 | |
733 | static int __maybe_unused rt1316_dev_suspend(struct device *dev) |
734 | { |
735 | struct rt1316_sdw_priv *rt1316 = dev_get_drvdata(dev); |
736 | |
737 | if (!rt1316->hw_init) |
738 | return 0; |
739 | |
740 | regcache_cache_only(map: rt1316->regmap, enable: true); |
741 | |
742 | return 0; |
743 | } |
744 | |
745 | #define RT1316_PROBE_TIMEOUT 5000 |
746 | |
747 | static int __maybe_unused rt1316_dev_resume(struct device *dev) |
748 | { |
749 | struct sdw_slave *slave = dev_to_sdw_dev(dev); |
750 | struct rt1316_sdw_priv *rt1316 = dev_get_drvdata(dev); |
751 | unsigned long time; |
752 | |
753 | if (!rt1316->first_hw_init) |
754 | return 0; |
755 | |
756 | if (!slave->unattach_request) |
757 | goto regmap_sync; |
758 | |
759 | time = wait_for_completion_timeout(x: &slave->initialization_complete, |
760 | timeout: msecs_to_jiffies(RT1316_PROBE_TIMEOUT)); |
761 | if (!time) { |
762 | dev_err(&slave->dev, "%s: Initialization not complete, timed out\n" , __func__); |
763 | sdw_show_ping_status(bus: slave->bus, sync_delay: true); |
764 | |
765 | return -ETIMEDOUT; |
766 | } |
767 | |
768 | regmap_sync: |
769 | slave->unattach_request = 0; |
770 | regcache_cache_only(map: rt1316->regmap, enable: false); |
771 | regcache_sync(map: rt1316->regmap); |
772 | |
773 | return 0; |
774 | } |
775 | |
776 | static const struct dev_pm_ops rt1316_pm = { |
777 | SET_SYSTEM_SLEEP_PM_OPS(rt1316_dev_suspend, rt1316_dev_resume) |
778 | SET_RUNTIME_PM_OPS(rt1316_dev_suspend, rt1316_dev_resume, NULL) |
779 | }; |
780 | |
781 | static struct sdw_driver rt1316_sdw_driver = { |
782 | .driver = { |
783 | .name = "rt1316-sdca" , |
784 | .owner = THIS_MODULE, |
785 | .pm = &rt1316_pm, |
786 | }, |
787 | .probe = rt1316_sdw_probe, |
788 | .remove = rt1316_sdw_remove, |
789 | .ops = &rt1316_slave_ops, |
790 | .id_table = rt1316_id, |
791 | }; |
792 | module_sdw_driver(rt1316_sdw_driver); |
793 | |
794 | MODULE_DESCRIPTION("ASoC RT1316 driver SDCA SDW" ); |
795 | MODULE_AUTHOR("Shuming Fan <shumingf@realtek.com>" ); |
796 | MODULE_LICENSE("GPL" ); |
797 | |