| 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
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| 2 | #ifndef __RTCODEC5631_H__ |
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| 3 | #define __RTCODEC5631_H__ |
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| 4 | |
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| 5 | |
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| 6 | #define RT5631_RESET 0x00 |
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| 7 | #define RT5631_SPK_OUT_VOL 0x02 |
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| 8 | #define RT5631_HP_OUT_VOL 0x04 |
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| 9 | #define RT5631_MONO_AXO_1_2_VOL 0x06 |
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| 10 | #define RT5631_AUX_IN_VOL 0x0A |
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| 11 | #define RT5631_STEREO_DAC_VOL_1 0x0C |
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| 12 | #define RT5631_MIC_CTRL_1 0x0E |
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| 13 | #define RT5631_STEREO_DAC_VOL_2 0x10 |
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| 14 | #define RT5631_ADC_CTRL_1 0x12 |
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| 15 | #define RT5631_ADC_REC_MIXER 0x14 |
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| 16 | #define RT5631_ADC_CTRL_2 0x16 |
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| 17 | #define RT5631_VDAC_DIG_VOL 0x18 |
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| 18 | #define RT5631_OUTMIXER_L_CTRL 0x1A |
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| 19 | #define RT5631_OUTMIXER_R_CTRL 0x1C |
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| 20 | #define RT5631_AXO1MIXER_CTRL 0x1E |
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| 21 | #define RT5631_AXO2MIXER_CTRL 0x20 |
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| 22 | #define RT5631_MIC_CTRL_2 0x22 |
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| 23 | #define RT5631_DIG_MIC_CTRL 0x24 |
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| 24 | #define RT5631_MONO_INPUT_VOL 0x26 |
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| 25 | #define RT5631_SPK_MIXER_CTRL 0x28 |
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| 26 | #define RT5631_SPK_MONO_OUT_CTRL 0x2A |
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| 27 | #define RT5631_SPK_MONO_HP_OUT_CTRL 0x2C |
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| 28 | #define RT5631_SDP_CTRL 0x34 |
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| 29 | #define RT5631_MONO_SDP_CTRL 0x36 |
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| 30 | #define RT5631_STEREO_AD_DA_CLK_CTRL 0x38 |
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| 31 | #define RT5631_PWR_MANAG_ADD1 0x3A |
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| 32 | #define RT5631_PWR_MANAG_ADD2 0x3B |
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| 33 | #define RT5631_PWR_MANAG_ADD3 0x3C |
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| 34 | #define RT5631_PWR_MANAG_ADD4 0x3E |
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| 35 | #define RT5631_GEN_PUR_CTRL_REG 0x40 |
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| 36 | #define RT5631_GLOBAL_CLK_CTRL 0x42 |
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| 37 | #define RT5631_PLL_CTRL 0x44 |
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| 38 | #define RT5631_INT_ST_IRQ_CTRL_1 0x48 |
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| 39 | #define RT5631_INT_ST_IRQ_CTRL_2 0x4A |
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| 40 | #define RT5631_GPIO_CTRL 0x4C |
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| 41 | #define RT5631_MISC_CTRL 0x52 |
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| 42 | #define RT5631_DEPOP_FUN_CTRL_1 0x54 |
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| 43 | #define RT5631_DEPOP_FUN_CTRL_2 0x56 |
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| 44 | #define RT5631_JACK_DET_CTRL 0x5A |
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| 45 | #define RT5631_SOFT_VOL_CTRL 0x5C |
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| 46 | #define RT5631_ALC_CTRL_1 0x64 |
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| 47 | #define RT5631_ALC_CTRL_2 0x65 |
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| 48 | #define RT5631_ALC_CTRL_3 0x66 |
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| 49 | #define RT5631_PSEUDO_SPATL_CTRL 0x68 |
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| 50 | #define RT5631_INDEX_ADD 0x6A |
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| 51 | #define RT5631_INDEX_DATA 0x6C |
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| 52 | #define RT5631_EQ_CTRL 0x6E |
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| 53 | #define RT5631_VENDOR_ID 0x7A |
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| 54 | #define RT5631_VENDOR_ID1 0x7C |
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| 55 | #define RT5631_VENDOR_ID2 0x7E |
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| 56 | |
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| 57 | /* Index of Codec Private Register definition */ |
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| 58 | #define RT5631_EQ_BW_LOP 0x00 |
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| 59 | #define RT5631_EQ_GAIN_LOP 0x01 |
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| 60 | #define RT5631_EQ_FC_BP1 0x02 |
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| 61 | #define RT5631_EQ_BW_BP1 0x03 |
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| 62 | #define RT5631_EQ_GAIN_BP1 0x04 |
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| 63 | #define RT5631_EQ_FC_BP2 0x05 |
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| 64 | #define RT5631_EQ_BW_BP2 0x06 |
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| 65 | #define RT5631_EQ_GAIN_BP2 0x07 |
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| 66 | #define RT5631_EQ_FC_BP3 0x08 |
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| 67 | #define RT5631_EQ_BW_BP3 0x09 |
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| 68 | #define RT5631_EQ_GAIN_BP3 0x0a |
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| 69 | #define RT5631_EQ_BW_HIP 0x0b |
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| 70 | #define RT5631_EQ_GAIN_HIP 0x0c |
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| 71 | #define RT5631_EQ_HPF_A1 0x0d |
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| 72 | #define RT5631_EQ_HPF_A2 0x0e |
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| 73 | #define RT5631_EQ_HPF_GAIN 0x0f |
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| 74 | #define RT5631_EQ_PRE_VOL_CTRL 0x11 |
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| 75 | #define RT5631_EQ_POST_VOL_CTRL 0x12 |
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| 76 | #define RT5631_TEST_MODE_CTRL 0x39 |
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| 77 | #define RT5631_CP_INTL_REG2 0x45 |
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| 78 | #define RT5631_ADDA_MIXER_INTL_REG3 0x52 |
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| 79 | #define RT5631_SPK_INTL_CTRL 0x56 |
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| 80 | |
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| 81 | |
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| 82 | /* global definition */ |
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| 83 | #define RT5631_L_MUTE (0x1 << 15) |
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| 84 | #define RT5631_L_MUTE_SHIFT 15 |
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| 85 | #define RT5631_L_EN (0x1 << 14) |
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| 86 | #define RT5631_L_EN_SHIFT 14 |
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| 87 | #define RT5631_R_MUTE (0x1 << 7) |
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| 88 | #define RT5631_R_MUTE_SHIFT 7 |
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| 89 | #define RT5631_R_EN (0x1 << 6) |
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| 90 | #define RT5631_R_EN_SHIFT 6 |
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| 91 | #define RT5631_VOL_MASK 0x1f |
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| 92 | #define RT5631_L_VOL_SHIFT 8 |
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| 93 | #define RT5631_R_VOL_SHIFT 0 |
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| 94 | |
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| 95 | /* Speaker Output Control(0x02) */ |
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| 96 | #define RT5631_SPK_L_VOL_SEL_MASK (0x1 << 14) |
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| 97 | #define RT5631_SPK_L_VOL_SEL_VMID (0x0 << 14) |
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| 98 | #define RT5631_SPK_L_VOL_SEL_SPKMIX_L (0x1 << 14) |
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| 99 | #define RT5631_SPK_R_VOL_SEL_MASK (0x1 << 6) |
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| 100 | #define RT5631_SPK_R_VOL_SEL_VMID (0x0 << 6) |
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| 101 | #define RT5631_SPK_R_VOL_SEL_SPKMIX_R (0x1 << 6) |
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| 102 | |
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| 103 | /* Headphone Output Control(0x04) */ |
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| 104 | #define RT5631_HP_L_VOL_SEL_MASK (0x1 << 14) |
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| 105 | #define RT5631_HP_L_VOL_SEL_VMID (0x0 << 14) |
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| 106 | #define RT5631_HP_L_VOL_SEL_OUTMIX_L (0x1 << 14) |
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| 107 | #define RT5631_HP_R_VOL_SEL_MASK (0x1 << 6) |
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| 108 | #define RT5631_HP_R_VOL_SEL_VMID (0x0 << 6) |
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| 109 | #define RT5631_HP_R_VOL_SEL_OUTMIX_R (0x1 << 6) |
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| 110 | |
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| 111 | /* Output Control for AUXOUT/MONO(0x06) */ |
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| 112 | #define RT5631_AUXOUT_1_VOL_SEL_MASK (0x1 << 14) |
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| 113 | #define RT5631_AUXOUT_1_VOL_SEL_VMID (0x0 << 14) |
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| 114 | #define RT5631_AUXOUT_1_VOL_SEL_OUTMIX_L (0x1 << 14) |
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| 115 | #define RT5631_MUTE_MONO (0x1 << 13) |
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| 116 | #define RT5631_MUTE_MONO_SHIFT 13 |
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| 117 | #define RT5631_AUXOUT_2_VOL_SEL_MASK (0x1 << 6) |
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| 118 | #define RT5631_AUXOUT_2_VOL_SEL_VMID (0x0 << 6) |
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| 119 | #define RT5631_AUXOUT_2_VOL_SEL_OUTMIX_R (0x1 << 6) |
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| 120 | |
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| 121 | /* Microphone Input Control 1(0x0E) */ |
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| 122 | #define RT5631_MIC1_DIFF_INPUT_CTRL (0x1 << 15) |
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| 123 | #define RT5631_MIC1_DIFF_INPUT_SHIFT 15 |
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| 124 | #define RT5631_MIC2_DIFF_INPUT_CTRL (0x1 << 7) |
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| 125 | #define RT5631_MIC2_DIFF_INPUT_SHIFT 7 |
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| 126 | |
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| 127 | /* Stereo DAC Digital Volume2(0x10) */ |
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| 128 | #define RT5631_DAC_VOL_MASK 0xff |
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| 129 | |
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| 130 | /* ADC Recording Mixer Control(0x14) */ |
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| 131 | #define RT5631_M_OUTMIXER_L_TO_RECMIXER_L (0x1 << 15) |
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| 132 | #define RT5631_M_OUTMIXL_RECMIXL_BIT 15 |
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| 133 | #define RT5631_M_MIC1_TO_RECMIXER_L (0x1 << 14) |
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| 134 | #define RT5631_M_MIC1_RECMIXL_BIT 14 |
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| 135 | #define RT5631_M_AXIL_TO_RECMIXER_L (0x1 << 13) |
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| 136 | #define RT5631_M_AXIL_RECMIXL_BIT 13 |
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| 137 | #define RT5631_M_MONO_IN_TO_RECMIXER_L (0x1 << 12) |
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| 138 | #define RT5631_M_MONO_IN_RECMIXL_BIT 12 |
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| 139 | #define RT5631_M_OUTMIXER_R_TO_RECMIXER_R (0x1 << 7) |
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| 140 | #define RT5631_M_OUTMIXR_RECMIXR_BIT 7 |
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| 141 | #define RT5631_M_MIC2_TO_RECMIXER_R (0x1 << 6) |
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| 142 | #define RT5631_M_MIC2_RECMIXR_BIT 6 |
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| 143 | #define RT5631_M_AXIR_TO_RECMIXER_R (0x1 << 5) |
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| 144 | #define RT5631_M_AXIR_RECMIXR_BIT 5 |
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| 145 | #define RT5631_M_MONO_IN_TO_RECMIXER_R (0x1 << 4) |
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| 146 | #define RT5631_M_MONO_IN_RECMIXR_BIT 4 |
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| 147 | |
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| 148 | /* Left Output Mixer Control(0x1A) */ |
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| 149 | #define RT5631_M_RECMIXER_L_TO_OUTMIXER_L (0x1 << 15) |
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| 150 | #define RT5631_M_RECMIXL_OUTMIXL_BIT 15 |
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| 151 | #define RT5631_M_RECMIXER_R_TO_OUTMIXER_L (0x1 << 14) |
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| 152 | #define RT5631_M_RECMIXR_OUTMIXL_BIT 14 |
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| 153 | #define RT5631_M_DAC_L_TO_OUTMIXER_L (0x1 << 13) |
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| 154 | #define RT5631_M_DACL_OUTMIXL_BIT 13 |
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| 155 | #define RT5631_M_MIC1_TO_OUTMIXER_L (0x1 << 12) |
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| 156 | #define RT5631_M_MIC1_OUTMIXL_BIT 12 |
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| 157 | #define RT5631_M_MIC2_TO_OUTMIXER_L (0x1 << 11) |
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| 158 | #define RT5631_M_MIC2_OUTMIXL_BIT 11 |
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| 159 | #define RT5631_M_MONO_IN_P_TO_OUTMIXER_L (0x1 << 10) |
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| 160 | #define RT5631_M_MONO_INP_OUTMIXL_BIT 10 |
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| 161 | #define RT5631_M_AXIL_TO_OUTMIXER_L (0x1 << 9) |
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| 162 | #define RT5631_M_AXIL_OUTMIXL_BIT 9 |
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| 163 | #define RT5631_M_AXIR_TO_OUTMIXER_L (0x1 << 8) |
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| 164 | #define RT5631_M_AXIR_OUTMIXL_BIT 8 |
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| 165 | #define RT5631_M_VDAC_TO_OUTMIXER_L (0x1 << 7) |
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| 166 | #define RT5631_M_VDAC_OUTMIXL_BIT 7 |
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| 167 | |
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| 168 | /* Right Output Mixer Control(0x1C) */ |
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| 169 | #define RT5631_M_RECMIXER_L_TO_OUTMIXER_R (0x1 << 15) |
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| 170 | #define RT5631_M_RECMIXL_OUTMIXR_BIT 15 |
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| 171 | #define RT5631_M_RECMIXER_R_TO_OUTMIXER_R (0x1 << 14) |
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| 172 | #define RT5631_M_RECMIXR_OUTMIXR_BIT 14 |
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| 173 | #define RT5631_M_DAC_R_TO_OUTMIXER_R (0x1 << 13) |
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| 174 | #define RT5631_M_DACR_OUTMIXR_BIT 13 |
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| 175 | #define RT5631_M_MIC1_TO_OUTMIXER_R (0x1 << 12) |
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| 176 | #define RT5631_M_MIC1_OUTMIXR_BIT 12 |
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| 177 | #define RT5631_M_MIC2_TO_OUTMIXER_R (0x1 << 11) |
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| 178 | #define RT5631_M_MIC2_OUTMIXR_BIT 11 |
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| 179 | #define RT5631_M_MONO_IN_N_TO_OUTMIXER_R (0x1 << 10) |
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| 180 | #define RT5631_M_MONO_INN_OUTMIXR_BIT 10 |
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| 181 | #define RT5631_M_AXIL_TO_OUTMIXER_R (0x1 << 9) |
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| 182 | #define RT5631_M_AXIL_OUTMIXR_BIT 9 |
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| 183 | #define RT5631_M_AXIR_TO_OUTMIXER_R (0x1 << 8) |
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| 184 | #define RT5631_M_AXIR_OUTMIXR_BIT 8 |
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| 185 | #define RT5631_M_VDAC_TO_OUTMIXER_R (0x1 << 7) |
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| 186 | #define RT5631_M_VDAC_OUTMIXR_BIT 7 |
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| 187 | |
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| 188 | /* Lout Mixer Control(0x1E) */ |
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| 189 | #define RT5631_M_MIC1_TO_AXO1MIXER (0x1 << 15) |
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| 190 | #define RT5631_M_MIC1_AXO1MIX_BIT 15 |
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| 191 | #define RT5631_M_MIC2_TO_AXO1MIXER (0x1 << 11) |
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| 192 | #define RT5631_M_MIC2_AXO1MIX_BIT 11 |
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| 193 | #define RT5631_M_OUTMIXER_L_TO_AXO1MIXER (0x1 << 7) |
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| 194 | #define RT5631_M_OUTMIXL_AXO1MIX_BIT 7 |
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| 195 | #define RT5631_M_OUTMIXER_R_TO_AXO1MIXER (0x1 << 6) |
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| 196 | #define RT5631_M_OUTMIXR_AXO1MIX_BIT 6 |
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| 197 | |
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| 198 | /* Rout Mixer Control(0x20) */ |
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| 199 | #define RT5631_M_MIC1_TO_AXO2MIXER (0x1 << 15) |
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| 200 | #define RT5631_M_MIC1_AXO2MIX_BIT 15 |
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| 201 | #define RT5631_M_MIC2_TO_AXO2MIXER (0x1 << 11) |
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| 202 | #define RT5631_M_MIC2_AXO2MIX_BIT 11 |
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| 203 | #define RT5631_M_OUTMIXER_L_TO_AXO2MIXER (0x1 << 7) |
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| 204 | #define RT5631_M_OUTMIXL_AXO2MIX_BIT 7 |
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| 205 | #define RT5631_M_OUTMIXER_R_TO_AXO2MIXER (0x1 << 6) |
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| 206 | #define RT5631_M_OUTMIXR_AXO2MIX_BIT 6 |
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| 207 | |
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| 208 | /* Micphone Input Control 2(0x22) */ |
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| 209 | #define RT5631_MIC_BIAS_90_PRECNET_AVDD 1 |
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| 210 | #define RT5631_MIC_BIAS_75_PRECNET_AVDD 2 |
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| 211 | |
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| 212 | #define RT5631_MIC1_BOOST_CTRL_MASK (0xf << 12) |
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| 213 | #define RT5631_MIC1_BOOST_CTRL_BYPASS (0x0 << 12) |
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| 214 | #define RT5631_MIC1_BOOST_CTRL_20DB (0x1 << 12) |
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| 215 | #define RT5631_MIC1_BOOST_CTRL_24DB (0x2 << 12) |
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| 216 | #define RT5631_MIC1_BOOST_CTRL_30DB (0x3 << 12) |
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| 217 | #define RT5631_MIC1_BOOST_CTRL_35DB (0x4 << 12) |
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| 218 | #define RT5631_MIC1_BOOST_CTRL_40DB (0x5 << 12) |
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| 219 | #define RT5631_MIC1_BOOST_CTRL_34DB (0x6 << 12) |
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| 220 | #define RT5631_MIC1_BOOST_CTRL_50DB (0x7 << 12) |
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| 221 | #define RT5631_MIC1_BOOST_CTRL_52DB (0x8 << 12) |
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| 222 | #define RT5631_MIC1_BOOST_SHIFT 12 |
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| 223 | |
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| 224 | #define RT5631_MIC2_BOOST_CTRL_MASK (0xf << 8) |
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| 225 | #define RT5631_MIC2_BOOST_CTRL_BYPASS (0x0 << 8) |
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| 226 | #define RT5631_MIC2_BOOST_CTRL_20DB (0x1 << 8) |
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| 227 | #define RT5631_MIC2_BOOST_CTRL_24DB (0x2 << 8) |
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| 228 | #define RT5631_MIC2_BOOST_CTRL_30DB (0x3 << 8) |
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| 229 | #define RT5631_MIC2_BOOST_CTRL_35DB (0x4 << 8) |
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| 230 | #define RT5631_MIC2_BOOST_CTRL_40DB (0x5 << 8) |
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| 231 | #define RT5631_MIC2_BOOST_CTRL_34DB (0x6 << 8) |
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| 232 | #define RT5631_MIC2_BOOST_CTRL_50DB (0x7 << 8) |
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| 233 | #define RT5631_MIC2_BOOST_CTRL_52DB (0x8 << 8) |
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| 234 | #define RT5631_MIC2_BOOST_SHIFT 8 |
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| 235 | |
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| 236 | #define RT5631_MICBIAS1_VOLT_CTRL_MASK (0x1 << 7) |
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| 237 | #define RT5631_MICBIAS1_VOLT_CTRL_90P (0x0 << 7) |
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| 238 | #define RT5631_MICBIAS1_VOLT_CTRL_75P (0x1 << 7) |
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| 239 | |
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| 240 | #define RT5631_MICBIAS1_S_C_DET_MASK (0x1 << 6) |
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| 241 | #define RT5631_MICBIAS1_S_C_DET_DIS (0x0 << 6) |
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| 242 | #define RT5631_MICBIAS1_S_C_DET_ENA (0x1 << 6) |
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| 243 | |
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| 244 | #define RT5631_MICBIAS1_SHORT_CURR_DET_MASK (0x3 << 4) |
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| 245 | #define RT5631_MICBIAS1_SHORT_CURR_DET_600UA (0x0 << 4) |
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| 246 | #define RT5631_MICBIAS1_SHORT_CURR_DET_1500UA (0x1 << 4) |
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| 247 | #define RT5631_MICBIAS1_SHORT_CURR_DET_2000UA (0x2 << 4) |
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| 248 | |
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| 249 | #define RT5631_MICBIAS2_VOLT_CTRL_MASK (0x1 << 3) |
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| 250 | #define RT5631_MICBIAS2_VOLT_CTRL_90P (0x0 << 3) |
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| 251 | #define RT5631_MICBIAS2_VOLT_CTRL_75P (0x1 << 3) |
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| 252 | |
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| 253 | #define RT5631_MICBIAS2_S_C_DET_MASK (0x1 << 2) |
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| 254 | #define RT5631_MICBIAS2_S_C_DET_DIS (0x0 << 2) |
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| 255 | #define RT5631_MICBIAS2_S_C_DET_ENA (0x1 << 2) |
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| 256 | |
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| 257 | #define RT5631_MICBIAS2_SHORT_CURR_DET_MASK (0x3) |
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| 258 | #define RT5631_MICBIAS2_SHORT_CURR_DET_600UA (0x0) |
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| 259 | #define RT5631_MICBIAS2_SHORT_CURR_DET_1500UA (0x1) |
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| 260 | #define RT5631_MICBIAS2_SHORT_CURR_DET_2000UA (0x2) |
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| 261 | |
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| 262 | |
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| 263 | /* Digital Microphone Control(0x24) */ |
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| 264 | #define RT5631_DMIC_ENA_MASK (0x1 << 15) |
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| 265 | #define RT5631_DMIC_ENA_SHIFT 15 |
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| 266 | /* DMIC_ENA: DMIC to ADC Digital filter */ |
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| 267 | #define RT5631_DMIC_ENA (0x1 << 15) |
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| 268 | /* DMIC_DIS: ADC mixer to ADC Digital filter */ |
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| 269 | #define RT5631_DMIC_DIS (0x0 << 15) |
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| 270 | #define RT5631_DMIC_L_CH_MUTE (0x1 << 13) |
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| 271 | #define RT5631_DMIC_L_CH_MUTE_SHIFT 13 |
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| 272 | #define RT5631_DMIC_R_CH_MUTE (0x1 << 12) |
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| 273 | #define RT5631_DMIC_R_CH_MUTE_SHIFT 12 |
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| 274 | #define RT5631_DMIC_L_CH_LATCH_MASK (0x1 << 9) |
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| 275 | #define RT5631_DMIC_L_CH_LATCH_RISING (0x1 << 9) |
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| 276 | #define RT5631_DMIC_L_CH_LATCH_FALLING (0x0 << 9) |
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| 277 | #define RT5631_DMIC_R_CH_LATCH_MASK (0x1 << 8) |
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| 278 | #define RT5631_DMIC_R_CH_LATCH_RISING (0x1 << 8) |
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| 279 | #define RT5631_DMIC_R_CH_LATCH_FALLING (0x0 << 8) |
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| 280 | #define RT5631_DMIC_CLK_CTRL_MASK (0x3 << 4) |
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| 281 | #define RT5631_DMIC_CLK_CTRL_TO_128FS (0x0 << 4) |
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| 282 | #define RT5631_DMIC_CLK_CTRL_TO_64FS (0x1 << 4) |
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| 283 | #define RT5631_DMIC_CLK_CTRL_TO_32FS (0x2 << 4) |
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| 284 | |
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| 285 | /* Microphone Input Volume(0x26) */ |
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| 286 | #define RT5631_MONO_DIFF_INPUT_SHIFT 15 |
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| 287 | |
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| 288 | /* Speaker Mixer Control(0x28) */ |
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| 289 | #define RT5631_M_RECMIXER_L_TO_SPKMIXER_L (0x1 << 15) |
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| 290 | #define RT5631_M_RECMIXL_SPKMIXL_BIT 15 |
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| 291 | #define RT5631_M_MIC1_P_TO_SPKMIXER_L (0x1 << 14) |
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| 292 | #define RT5631_M_MIC1P_SPKMIXL_BIT 14 |
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| 293 | #define RT5631_M_DAC_L_TO_SPKMIXER_L (0x1 << 13) |
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| 294 | #define RT5631_M_DACL_SPKMIXL_BIT 13 |
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| 295 | #define RT5631_M_OUTMIXER_L_TO_SPKMIXER_L (0x1 << 12) |
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| 296 | #define RT5631_M_OUTMIXL_SPKMIXL_BIT 12 |
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| 297 | |
|---|
| 298 | #define RT5631_M_RECMIXER_R_TO_SPKMIXER_R (0x1 << 7) |
|---|
| 299 | #define RT5631_M_RECMIXR_SPKMIXR_BIT 7 |
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| 300 | #define RT5631_M_MIC2_P_TO_SPKMIXER_R (0x1 << 6) |
|---|
| 301 | #define RT5631_M_MIC2P_SPKMIXR_BIT 6 |
|---|
| 302 | #define RT5631_M_DAC_R_TO_SPKMIXER_R (0x1 << 5) |
|---|
| 303 | #define RT5631_M_DACR_SPKMIXR_BIT 5 |
|---|
| 304 | #define RT5631_M_OUTMIXER_R_TO_SPKMIXER_R (0x1 << 4) |
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| 305 | #define RT5631_M_OUTMIXR_SPKMIXR_BIT 4 |
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| 306 | |
|---|
| 307 | /* Speaker/Mono Output Control(0x2A) */ |
|---|
| 308 | #define RT5631_M_SPKVOL_L_TO_SPOL_MIXER (0x1 << 15) |
|---|
| 309 | #define RT5631_M_SPKVOLL_SPOLMIX_BIT 15 |
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| 310 | #define RT5631_M_SPKVOL_R_TO_SPOL_MIXER (0x1 << 14) |
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| 311 | #define RT5631_M_SPKVOLR_SPOLMIX_BIT 14 |
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| 312 | #define RT5631_M_SPKVOL_L_TO_SPOR_MIXER (0x1 << 13) |
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| 313 | #define RT5631_M_SPKVOLL_SPORMIX_BIT 13 |
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| 314 | #define RT5631_M_SPKVOL_R_TO_SPOR_MIXER (0x1 << 12) |
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| 315 | #define RT5631_M_SPKVOLR_SPORMIX_BIT 12 |
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| 316 | #define RT5631_M_OUTVOL_L_TO_MONOMIXER (0x1 << 11) |
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| 317 | #define RT5631_M_OUTVOLL_MONOMIX_BIT 11 |
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| 318 | #define RT5631_M_OUTVOL_R_TO_MONOMIXER (0x1 << 10) |
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| 319 | #define RT5631_M_OUTVOLR_MONOMIX_BIT 10 |
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| 320 | |
|---|
| 321 | /* Speaker/Mono/HP Output Control(0x2C) */ |
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| 322 | #define RT5631_SPK_L_MUX_SEL_MASK (0x3 << 14) |
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| 323 | #define RT5631_SPK_L_MUX_SEL_SPKMIXER_L (0x0 << 14) |
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| 324 | #define RT5631_SPK_L_MUX_SEL_MONO_IN (0x1 << 14) |
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| 325 | #define RT5631_SPK_L_MUX_SEL_DAC_L (0x3 << 14) |
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| 326 | #define RT5631_SPK_L_MUX_SEL_SHIFT 14 |
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| 327 | |
|---|
| 328 | #define RT5631_SPK_R_MUX_SEL_MASK (0x3 << 10) |
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| 329 | #define RT5631_SPK_R_MUX_SEL_SPKMIXER_R (0x0 << 10) |
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| 330 | #define RT5631_SPK_R_MUX_SEL_MONO_IN (0x1 << 10) |
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| 331 | #define RT5631_SPK_R_MUX_SEL_DAC_R (0x3 << 10) |
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| 332 | #define RT5631_SPK_R_MUX_SEL_SHIFT 10 |
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| 333 | |
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| 334 | #define RT5631_MONO_MUX_SEL_MASK (0x3 << 6) |
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| 335 | #define RT5631_MONO_MUX_SEL_MONOMIXER (0x0 << 6) |
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| 336 | #define RT5631_MONO_MUX_SEL_MONO_IN (0x1 << 6) |
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| 337 | #define RT5631_MONO_MUX_SEL_SHIFT 6 |
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| 338 | |
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| 339 | #define RT5631_HP_L_MUX_SEL_MASK (0x1 << 3) |
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| 340 | #define RT5631_HP_L_MUX_SEL_HPVOL_L (0x0 << 3) |
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| 341 | #define RT5631_HP_L_MUX_SEL_DAC_L (0x1 << 3) |
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| 342 | #define RT5631_HP_L_MUX_SEL_SHIFT 3 |
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| 343 | |
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| 344 | #define RT5631_HP_R_MUX_SEL_MASK (0x1 << 2) |
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| 345 | #define RT5631_HP_R_MUX_SEL_HPVOL_R (0x0 << 2) |
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| 346 | #define RT5631_HP_R_MUX_SEL_DAC_R (0x1 << 2) |
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| 347 | #define RT5631_HP_R_MUX_SEL_SHIFT 2 |
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| 348 | |
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| 349 | /* Stereo I2S Serial Data Port Control(0x34) */ |
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| 350 | #define RT5631_SDP_MODE_SEL_MASK (0x1 << 15) |
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| 351 | #define RT5631_SDP_MODE_SEL_MASTER (0x0 << 15) |
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| 352 | #define RT5631_SDP_MODE_SEL_SLAVE (0x1 << 15) |
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| 353 | |
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| 354 | #define RT5631_SDP_ADC_CPS_SEL_MASK (0x3 << 10) |
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| 355 | #define RT5631_SDP_ADC_CPS_SEL_OFF (0x0 << 10) |
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| 356 | #define RT5631_SDP_ADC_CPS_SEL_U_LAW (0x1 << 10) |
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| 357 | #define RT5631_SDP_ADC_CPS_SEL_A_LAW (0x2 << 10) |
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| 358 | |
|---|
| 359 | #define RT5631_SDP_DAC_CPS_SEL_MASK (0x3 << 8) |
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| 360 | #define RT5631_SDP_DAC_CPS_SEL_OFF (0x0 << 8) |
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| 361 | #define RT5631_SDP_DAC_CPS_SEL_U_LAW (0x1 << 8) |
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| 362 | #define RT5631_SDP_DAC_CPS_SEL_A_LAW (0x2 << 8) |
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| 363 | /* 0:Normal 1:Invert */ |
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| 364 | #define RT5631_SDP_I2S_BCLK_POL_CTRL (0x1 << 7) |
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| 365 | /* 0:Normal 1:Invert */ |
|---|
| 366 | #define RT5631_SDP_DAC_R_INV (0x1 << 6) |
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| 367 | /* 0:ADC data appear at left phase of LRCK |
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| 368 | * 1:ADC data appear at right phase of LRCK |
|---|
| 369 | */ |
|---|
| 370 | #define RT5631_SDP_ADC_DATA_L_R_SWAP (0x1 << 5) |
|---|
| 371 | /* 0:DAC data appear at left phase of LRCK |
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| 372 | * 1:DAC data appear at right phase of LRCK |
|---|
| 373 | */ |
|---|
| 374 | #define RT5631_SDP_DAC_DATA_L_R_SWAP (0x1 << 4) |
|---|
| 375 | |
|---|
| 376 | /* Data Length Slection */ |
|---|
| 377 | #define RT5631_SDP_I2S_DL_MASK (0x3 << 2) |
|---|
| 378 | #define RT5631_SDP_I2S_DL_16 (0x0 << 2) |
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| 379 | #define RT5631_SDP_I2S_DL_20 (0x1 << 2) |
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| 380 | #define RT5631_SDP_I2S_DL_24 (0x2 << 2) |
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| 381 | #define RT5631_SDP_I2S_DL_8 (0x3 << 2) |
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| 382 | |
|---|
| 383 | /* PCM Data Format Selection */ |
|---|
| 384 | #define RT5631_SDP_I2S_DF_MASK (0x3) |
|---|
| 385 | #define RT5631_SDP_I2S_DF_I2S (0x0) |
|---|
| 386 | #define RT5631_SDP_I2S_DF_LEFT (0x1) |
|---|
| 387 | #define RT5631_SDP_I2S_DF_PCM_A (0x2) |
|---|
| 388 | #define RT5631_SDP_I2S_DF_PCM_B (0x3) |
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| 389 | |
|---|
| 390 | /* Stereo AD/DA Clock Control(0x38h) */ |
|---|
| 391 | #define RT5631_I2S_PRE_DIV_MASK (0x7 << 13) |
|---|
| 392 | #define RT5631_I2S_PRE_DIV_1 (0x0 << 13) |
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| 393 | #define RT5631_I2S_PRE_DIV_2 (0x1 << 13) |
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| 394 | #define RT5631_I2S_PRE_DIV_4 (0x2 << 13) |
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| 395 | #define RT5631_I2S_PRE_DIV_8 (0x3 << 13) |
|---|
| 396 | #define RT5631_I2S_PRE_DIV_16 (0x4 << 13) |
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| 397 | #define RT5631_I2S_PRE_DIV_32 (0x5 << 13) |
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| 398 | /* CLOCK RELATIVE OF BCLK AND LCRK */ |
|---|
| 399 | #define RT5631_I2S_LRCK_SEL_N_BCLK_MASK (0x1 << 12) |
|---|
| 400 | #define RT5631_I2S_LRCK_SEL_64_BCLK (0x0 << 12) /* 64FS */ |
|---|
| 401 | #define RT5631_I2S_LRCK_SEL_32_BCLK (0x1 << 12) /* 32FS */ |
|---|
| 402 | |
|---|
| 403 | #define RT5631_DAC_OSR_SEL_MASK (0x3 << 10) |
|---|
| 404 | #define RT5631_DAC_OSR_SEL_128FS (0x3 << 10) |
|---|
| 405 | #define RT5631_DAC_OSR_SEL_64FS (0x3 << 10) |
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| 406 | #define RT5631_DAC_OSR_SEL_32FS (0x3 << 10) |
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| 407 | #define RT5631_DAC_OSR_SEL_16FS (0x3 << 10) |
|---|
| 408 | |
|---|
| 409 | #define RT5631_ADC_OSR_SEL_MASK (0x3 << 8) |
|---|
| 410 | #define RT5631_ADC_OSR_SEL_128FS (0x3 << 8) |
|---|
| 411 | #define RT5631_ADC_OSR_SEL_64FS (0x3 << 8) |
|---|
| 412 | #define RT5631_ADC_OSR_SEL_32FS (0x3 << 8) |
|---|
| 413 | #define RT5631_ADC_OSR_SEL_16FS (0x3 << 8) |
|---|
| 414 | |
|---|
| 415 | #define RT5631_ADDA_FILTER_CLK_SEL_256FS (0 << 7) /* 256FS */ |
|---|
| 416 | #define RT5631_ADDA_FILTER_CLK_SEL_384FS (1 << 7) /* 384FS */ |
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| 417 | |
|---|
| 418 | /* Power managment addition 1 (0x3A) */ |
|---|
| 419 | #define RT5631_PWR_MAIN_I2S_EN (0x1 << 15) |
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| 420 | #define RT5631_PWR_MAIN_I2S_BIT 15 |
|---|
| 421 | #define RT5631_PWR_CLASS_D (0x1 << 12) |
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| 422 | #define RT5631_PWR_CLASS_D_BIT 12 |
|---|
| 423 | #define RT5631_PWR_ADC_L_CLK (0x1 << 11) |
|---|
| 424 | #define RT5631_PWR_ADC_L_CLK_BIT 11 |
|---|
| 425 | #define RT5631_PWR_ADC_R_CLK (0x1 << 10) |
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| 426 | #define RT5631_PWR_ADC_R_CLK_BIT 10 |
|---|
| 427 | #define RT5631_PWR_DAC_L_CLK (0x1 << 9) |
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| 428 | #define RT5631_PWR_DAC_L_CLK_BIT 9 |
|---|
| 429 | #define RT5631_PWR_DAC_R_CLK (0x1 << 8) |
|---|
| 430 | #define RT5631_PWR_DAC_R_CLK_BIT 8 |
|---|
| 431 | #define RT5631_PWR_DAC_REF (0x1 << 7) |
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| 432 | #define RT5631_PWR_DAC_REF_BIT 7 |
|---|
| 433 | #define RT5631_PWR_DAC_L_TO_MIXER (0x1 << 6) |
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| 434 | #define RT5631_PWR_DAC_L_TO_MIXER_BIT 6 |
|---|
| 435 | #define RT5631_PWR_DAC_R_TO_MIXER (0x1 << 5) |
|---|
| 436 | #define RT5631_PWR_DAC_R_TO_MIXER_BIT 5 |
|---|
| 437 | |
|---|
| 438 | /* Power managment addition 2 (0x3B) */ |
|---|
| 439 | #define RT5631_PWR_OUTMIXER_L (0x1 << 15) |
|---|
| 440 | #define RT5631_PWR_OUTMIXER_L_BIT 15 |
|---|
| 441 | #define RT5631_PWR_OUTMIXER_R (0x1 << 14) |
|---|
| 442 | #define RT5631_PWR_OUTMIXER_R_BIT 14 |
|---|
| 443 | #define RT5631_PWR_SPKMIXER_L (0x1 << 13) |
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| 444 | #define RT5631_PWR_SPKMIXER_L_BIT 13 |
|---|
| 445 | #define RT5631_PWR_SPKMIXER_R (0x1 << 12) |
|---|
| 446 | #define RT5631_PWR_SPKMIXER_R_BIT 12 |
|---|
| 447 | #define RT5631_PWR_RECMIXER_L (0x1 << 11) |
|---|
| 448 | #define RT5631_PWR_RECMIXER_L_BIT 11 |
|---|
| 449 | #define RT5631_PWR_RECMIXER_R (0x1 << 10) |
|---|
| 450 | #define RT5631_PWR_RECMIXER_R_BIT 10 |
|---|
| 451 | #define RT5631_PWR_MIC1_BOOT_GAIN (0x1 << 5) |
|---|
| 452 | #define RT5631_PWR_MIC1_BOOT_GAIN_BIT 5 |
|---|
| 453 | #define RT5631_PWR_MIC2_BOOT_GAIN (0x1 << 4) |
|---|
| 454 | #define RT5631_PWR_MIC2_BOOT_GAIN_BIT 4 |
|---|
| 455 | #define RT5631_PWR_MICBIAS1_VOL (0x1 << 3) |
|---|
| 456 | #define RT5631_PWR_MICBIAS1_VOL_BIT 3 |
|---|
| 457 | #define RT5631_PWR_MICBIAS2_VOL (0x1 << 2) |
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| 458 | #define RT5631_PWR_MICBIAS2_VOL_BIT 2 |
|---|
| 459 | #define RT5631_PWR_PLL1 (0x1 << 1) |
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| 460 | #define RT5631_PWR_PLL1_BIT 1 |
|---|
| 461 | #define RT5631_PWR_PLL2 (0x1 << 0) |
|---|
| 462 | #define RT5631_PWR_PLL2_BIT 0 |
|---|
| 463 | |
|---|
| 464 | /* Power managment addition 3(0x3C) */ |
|---|
| 465 | #define RT5631_PWR_VREF (0x1 << 15) |
|---|
| 466 | #define RT5631_PWR_VREF_BIT 15 |
|---|
| 467 | #define RT5631_PWR_FAST_VREF_CTRL (0x1 << 14) |
|---|
| 468 | #define RT5631_PWR_FAST_VREF_CTRL_BIT 14 |
|---|
| 469 | #define RT5631_PWR_MAIN_BIAS (0x1 << 13) |
|---|
| 470 | #define RT5631_PWR_MAIN_BIAS_BIT 13 |
|---|
| 471 | #define RT5631_PWR_AXO1MIXER (0x1 << 11) |
|---|
| 472 | #define RT5631_PWR_AXO1MIXER_BIT 11 |
|---|
| 473 | #define RT5631_PWR_AXO2MIXER (0x1 << 10) |
|---|
| 474 | #define RT5631_PWR_AXO2MIXER_BIT 10 |
|---|
| 475 | #define RT5631_PWR_MONOMIXER (0x1 << 9) |
|---|
| 476 | #define RT5631_PWR_MONOMIXER_BIT 9 |
|---|
| 477 | #define RT5631_PWR_MONO_DEPOP_DIS (0x1 << 8) |
|---|
| 478 | #define RT5631_PWR_MONO_DEPOP_DIS_BIT 8 |
|---|
| 479 | #define RT5631_PWR_MONO_AMP_EN (0x1 << 7) |
|---|
| 480 | #define RT5631_PWR_MONO_AMP_EN_BIT 7 |
|---|
| 481 | #define RT5631_PWR_CHARGE_PUMP (0x1 << 4) |
|---|
| 482 | #define RT5631_PWR_CHARGE_PUMP_BIT 4 |
|---|
| 483 | #define RT5631_PWR_HP_L_AMP (0x1 << 3) |
|---|
| 484 | #define RT5631_PWR_HP_L_AMP_BIT 3 |
|---|
| 485 | #define RT5631_PWR_HP_R_AMP (0x1 << 2) |
|---|
| 486 | #define RT5631_PWR_HP_R_AMP_BIT 2 |
|---|
| 487 | #define RT5631_PWR_HP_DEPOP_DIS (0x1 << 1) |
|---|
| 488 | #define RT5631_PWR_HP_DEPOP_DIS_BIT 1 |
|---|
| 489 | #define RT5631_PWR_HP_AMP_DRIVING (0x1 << 0) |
|---|
| 490 | #define RT5631_PWR_HP_AMP_DRIVING_BIT 0 |
|---|
| 491 | |
|---|
| 492 | /* Power managment addition 4(0x3E) */ |
|---|
| 493 | #define RT5631_PWR_SPK_L_VOL (0x1 << 15) |
|---|
| 494 | #define RT5631_PWR_SPK_L_VOL_BIT 15 |
|---|
| 495 | #define RT5631_PWR_SPK_R_VOL (0x1 << 14) |
|---|
| 496 | #define RT5631_PWR_SPK_R_VOL_BIT 14 |
|---|
| 497 | #define RT5631_PWR_LOUT_VOL (0x1 << 13) |
|---|
| 498 | #define RT5631_PWR_LOUT_VOL_BIT 13 |
|---|
| 499 | #define RT5631_PWR_ROUT_VOL (0x1 << 12) |
|---|
| 500 | #define RT5631_PWR_ROUT_VOL_BIT 12 |
|---|
| 501 | #define RT5631_PWR_HP_L_OUT_VOL (0x1 << 11) |
|---|
| 502 | #define RT5631_PWR_HP_L_OUT_VOL_BIT 11 |
|---|
| 503 | #define RT5631_PWR_HP_R_OUT_VOL (0x1 << 10) |
|---|
| 504 | #define RT5631_PWR_HP_R_OUT_VOL_BIT 10 |
|---|
| 505 | #define RT5631_PWR_AXIL_IN_VOL (0x1 << 9) |
|---|
| 506 | #define RT5631_PWR_AXIL_IN_VOL_BIT 9 |
|---|
| 507 | #define RT5631_PWR_AXIR_IN_VOL (0x1 << 8) |
|---|
| 508 | #define RT5631_PWR_AXIR_IN_VOL_BIT 8 |
|---|
| 509 | #define RT5631_PWR_MONO_IN_P_VOL (0x1 << 7) |
|---|
| 510 | #define RT5631_PWR_MONO_IN_P_VOL_BIT 7 |
|---|
| 511 | #define RT5631_PWR_MONO_IN_N_VOL (0x1 << 6) |
|---|
| 512 | #define RT5631_PWR_MONO_IN_N_VOL_BIT 6 |
|---|
| 513 | |
|---|
| 514 | /* General Purpose Control Register(0x40) */ |
|---|
| 515 | #define RT5631_SPK_AMP_AUTO_RATIO_EN (0x1 << 15) |
|---|
| 516 | |
|---|
| 517 | #define RT5631_SPK_AMP_RATIO_CTRL_MASK (0x7 << 12) |
|---|
| 518 | #define RT5631_SPK_AMP_RATIO_CTRL_2_34 (0x0 << 12) /* 7.40DB */ |
|---|
| 519 | #define RT5631_SPK_AMP_RATIO_CTRL_1_99 (0x1 << 12) /* 5.99DB */ |
|---|
| 520 | #define RT5631_SPK_AMP_RATIO_CTRL_1_68 (0x2 << 12) /* 4.50DB */ |
|---|
| 521 | #define RT5631_SPK_AMP_RATIO_CTRL_1_56 (0x3 << 12) /* 3.86DB */ |
|---|
| 522 | #define RT5631_SPK_AMP_RATIO_CTRL_1_44 (0x4 << 12) /* 3.16DB */ |
|---|
| 523 | #define RT5631_SPK_AMP_RATIO_CTRL_1_27 (0x5 << 12) /* 2.10DB */ |
|---|
| 524 | #define RT5631_SPK_AMP_RATIO_CTRL_1_09 (0x6 << 12) /* 0.80DB */ |
|---|
| 525 | #define RT5631_SPK_AMP_RATIO_CTRL_1_00 (0x7 << 12) /* 0.00DB */ |
|---|
| 526 | #define RT5631_SPK_AMP_RATIO_CTRL_SHIFT 12 |
|---|
| 527 | |
|---|
| 528 | #define RT5631_STEREO_DAC_HI_PASS_FILT_EN (0x1 << 11) |
|---|
| 529 | #define RT5631_STEREO_ADC_HI_PASS_FILT_EN (0x1 << 10) |
|---|
| 530 | /* Select ADC Wind Filter Clock type */ |
|---|
| 531 | #define RT5631_ADC_WIND_FILT_MASK (0x3 << 4) |
|---|
| 532 | #define RT5631_ADC_WIND_FILT_8_16_32K (0x0 << 4) /*8/16/32k*/ |
|---|
| 533 | #define RT5631_ADC_WIND_FILT_11_22_44K (0x1 << 4) /*11/22/44k*/ |
|---|
| 534 | #define RT5631_ADC_WIND_FILT_12_24_48K (0x2 << 4) /*12/24/48k*/ |
|---|
| 535 | #define RT5631_ADC_WIND_FILT_EN (0x1 << 3) |
|---|
| 536 | /* SelectADC Wind Filter Corner Frequency */ |
|---|
| 537 | #define RT5631_ADC_WIND_CNR_FREQ_MASK (0x7 << 0) |
|---|
| 538 | #define RT5631_ADC_WIND_CNR_FREQ_82_113_122 (0x0 << 0) /* 82/113/122 Hz */ |
|---|
| 539 | #define RT5631_ADC_WIND_CNR_FREQ_102_141_153 (0x1 << 0) /* 102/141/153 Hz */ |
|---|
| 540 | #define RT5631_ADC_WIND_CNR_FREQ_131_180_156 (0x2 << 0) /* 131/180/156 Hz */ |
|---|
| 541 | #define RT5631_ADC_WIND_CNR_FREQ_163_225_245 (0x3 << 0) /* 163/225/245 Hz */ |
|---|
| 542 | #define RT5631_ADC_WIND_CNR_FREQ_204_281_306 (0x4 << 0) /* 204/281/306 Hz */ |
|---|
| 543 | #define RT5631_ADC_WIND_CNR_FREQ_261_360_392 (0x5 << 0) /* 261/360/392 Hz */ |
|---|
| 544 | #define RT5631_ADC_WIND_CNR_FREQ_327_450_490 (0x6 << 0) /* 327/450/490 Hz */ |
|---|
| 545 | #define RT5631_ADC_WIND_CNR_FREQ_408_563_612 (0x7 << 0) /* 408/563/612 Hz */ |
|---|
| 546 | |
|---|
| 547 | /* Global Clock Control Register(0x42) */ |
|---|
| 548 | #define RT5631_SYSCLK_SOUR_SEL_MASK (0x3 << 14) |
|---|
| 549 | #define RT5631_SYSCLK_SOUR_SEL_MCLK (0x0 << 14) |
|---|
| 550 | #define RT5631_SYSCLK_SOUR_SEL_PLL (0x1 << 14) |
|---|
| 551 | #define RT5631_SYSCLK_SOUR_SEL_PLL_TCK (0x2 << 14) |
|---|
| 552 | |
|---|
| 553 | #define RT5631_PLLCLK_SOUR_SEL_MASK (0x3 << 12) |
|---|
| 554 | #define RT5631_PLLCLK_SOUR_SEL_MCLK (0x0 << 12) |
|---|
| 555 | #define RT5631_PLLCLK_SOUR_SEL_BCLK (0x1 << 12) |
|---|
| 556 | #define RT5631_PLLCLK_SOUR_SEL_VBCLK (0x2 << 12) |
|---|
| 557 | |
|---|
| 558 | #define RT5631_PLLCLK_PRE_DIV1 (0x0 << 11) |
|---|
| 559 | #define RT5631_PLLCLK_PRE_DIV2 (0x1 << 11) |
|---|
| 560 | |
|---|
| 561 | /* PLL Control(0x44) */ |
|---|
| 562 | #define RT5631_PLL_CTRL_M_VAL(m) ((m)&0xf) |
|---|
| 563 | #define RT5631_PLL_CTRL_K_VAL(k) (((k)&0x7) << 4) |
|---|
| 564 | #define RT5631_PLL_CTRL_N_VAL(n) (((n)&0xff) << 8) |
|---|
| 565 | |
|---|
| 566 | /* Internal Status and IRQ Control2(0x4A) */ |
|---|
| 567 | #define RT5631_ADC_DATA_SEL_MASK (0x3 << 14) |
|---|
| 568 | #define RT5631_ADC_DATA_SEL_Disable (0x0 << 14) |
|---|
| 569 | #define RT5631_ADC_DATA_SEL_MIC1 (0x1 << 14) |
|---|
| 570 | #define RT5631_ADC_DATA_SEL_MIC1_SHIFT 14 |
|---|
| 571 | #define RT5631_ADC_DATA_SEL_MIC2 (0x2 << 14) |
|---|
| 572 | #define RT5631_ADC_DATA_SEL_MIC2_SHIFT 15 |
|---|
| 573 | #define RT5631_ADC_DATA_SEL_STO (0x3 << 14) |
|---|
| 574 | #define RT5631_ADC_DATA_SEL_SHIFT 14 |
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| 575 | |
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| 576 | /* GPIO Pin Configuration(0x4C) */ |
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| 577 | #define RT5631_GPIO_PIN_FUN_SEL_MASK (0x1 << 15) |
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| 578 | #define RT5631_GPIO_PIN_FUN_SEL_IRQ (0x1 << 15) |
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| 579 | #define RT5631_GPIO_PIN_FUN_SEL_GPIO_DIMC (0x0 << 15) |
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| 580 | |
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| 581 | #define RT5631_GPIO_DMIC_FUN_SEL_MASK (0x1 << 3) |
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| 582 | #define RT5631_GPIO_DMIC_FUN_SEL_DIMC (0x1 << 3) |
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| 583 | #define RT5631_GPIO_DMIC_FUN_SEL_GPIO (0x0 << 3) |
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| 584 | |
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| 585 | #define RT5631_GPIO_PIN_CON_MASK (0x1 << 2) |
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| 586 | #define RT5631_GPIO_PIN_SET_INPUT (0x0 << 2) |
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| 587 | #define RT5631_GPIO_PIN_SET_OUTPUT (0x1 << 2) |
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| 588 | |
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| 589 | /* De-POP function Control 1(0x54) */ |
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| 590 | #define RT5631_POW_ON_SOFT_GEN (0x1 << 15) |
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| 591 | #define RT5631_EN_MUTE_UNMUTE_DEPOP (0x1 << 14) |
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| 592 | #define RT5631_EN_DEPOP2_FOR_HP (0x1 << 7) |
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| 593 | /* Power Down HPAMP_L Starts Up Signal */ |
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| 594 | #define RT5631_PD_HPAMP_L_ST_UP (0x1 << 5) |
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| 595 | /* Power Down HPAMP_R Starts Up Signal */ |
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| 596 | #define RT5631_PD_HPAMP_R_ST_UP (0x1 << 4) |
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| 597 | /* Enable left HP mute/unmute depop */ |
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| 598 | #define RT5631_EN_HP_L_M_UN_MUTE_DEPOP (0x1 << 1) |
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| 599 | /* Enable right HP mute/unmute depop */ |
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| 600 | #define RT5631_EN_HP_R_M_UN_MUTE_DEPOP (0x1 << 0) |
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| 601 | |
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| 602 | /* De-POP Fnction Control(0x56) */ |
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| 603 | #define RT5631_EN_ONE_BIT_DEPOP (0x1 << 15) |
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| 604 | #define RT5631_EN_CAP_FREE_DEPOP (0x1 << 14) |
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| 605 | |
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| 606 | /* Jack Detect Control Register(0x5A) */ |
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| 607 | #define RT5631_JD_USE_MASK (0x3 << 14) |
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| 608 | #define RT5631_JD_USE_JD2 (0x3 << 14) |
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| 609 | #define RT5631_JD_USE_JD1 (0x2 << 14) |
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| 610 | #define RT5631_JD_USE_GPIO (0x1 << 14) |
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| 611 | #define RT5631_JD_OFF (0x0 << 14) |
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| 612 | /* JD trigger enable for HP */ |
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| 613 | #define RT5631_JD_HP_EN (0x1 << 11) |
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| 614 | #define RT5631_JD_HP_TRI_MASK (0x1 << 10) |
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| 615 | #define RT5631_JD_HP_TRI_HI (0x1 << 10) |
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| 616 | #define RT5631_JD_HP_TRI_LO (0x1 << 10) |
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| 617 | /* JD trigger enable for speaker LP/LN */ |
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| 618 | #define RT5631_JD_SPK_L_EN (0x1 << 9) |
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| 619 | #define RT5631_JD_SPK_L_TRI_MASK (0x1 << 8) |
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| 620 | #define RT5631_JD_SPK_L_TRI_HI (0x1 << 8) |
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| 621 | #define RT5631_JD_SPK_L_TRI_LO (0x0 << 8) |
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| 622 | /* JD trigger enable for speaker RP/RN */ |
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| 623 | #define RT5631_JD_SPK_R_EN (0x1 << 7) |
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| 624 | #define RT5631_JD_SPK_R_TRI_MASK (0x1 << 6) |
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| 625 | #define RT5631_JD_SPK_R_TRI_HI (0x1 << 6) |
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| 626 | #define RT5631_JD_SPK_R_TRI_LO (0x0 << 6) |
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| 627 | /* JD trigger enable for monoout */ |
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| 628 | #define RT5631_JD_MONO_EN (0x1 << 5) |
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| 629 | #define RT5631_JD_MONO_TRI_MASK (0x1 << 4) |
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| 630 | #define RT5631_JD_MONO_TRI_HI (0x1 << 4) |
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| 631 | #define RT5631_JD_MONO_TRI_LO (0x0 << 4) |
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| 632 | /* JD trigger enable for Lout */ |
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| 633 | #define RT5631_JD_AUX_1_EN (0x1 << 3) |
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| 634 | #define RT5631_JD_AUX_1_MASK (0x1 << 2) |
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| 635 | #define RT5631_JD_AUX_1_TRI_HI (0x1 << 2) |
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| 636 | #define RT5631_JD_AUX_1_TRI_LO (0x0 << 2) |
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| 637 | /* JD trigger enable for Rout */ |
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| 638 | #define RT5631_JD_AUX_2_EN (0x1 << 1) |
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| 639 | #define RT5631_JD_AUX_2_MASK (0x1 << 0) |
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| 640 | #define RT5631_JD_AUX_2_TRI_HI (0x1 << 0) |
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| 641 | #define RT5631_JD_AUX_2_TRI_LO (0x0 << 0) |
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| 642 | |
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| 643 | /* ALC CONTROL 1(0x64) */ |
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| 644 | #define RT5631_ALC_ATTACK_RATE_MASK (0x1F << 8) |
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| 645 | #define RT5631_ALC_RECOVERY_RATE_MASK (0x1F << 0) |
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| 646 | |
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| 647 | /* ALC CONTROL 2(0x65) */ |
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| 648 | /* select Compensation gain for Noise gate function */ |
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| 649 | #define RT5631_ALC_COM_NOISE_GATE_MASK (0xF << 0) |
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| 650 | |
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| 651 | /* ALC CONTROL 3(0x66) */ |
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| 652 | #define RT5631_ALC_FUN_MASK (0x3 << 14) |
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| 653 | #define RT5631_ALC_FUN_DIS (0x0 << 14) |
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| 654 | #define RT5631_ALC_ENA_DAC_PATH (0x1 << 14) |
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| 655 | #define RT5631_ALC_ENA_ADC_PATH (0x3 << 14) |
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| 656 | #define RT5631_ALC_PARA_UPDATE (0x1 << 13) |
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| 657 | #define RT5631_ALC_LIMIT_LEVEL_MASK (0x1F << 8) |
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| 658 | #define RT5631_ALC_NOISE_GATE_FUN_MASK (0x1 << 7) |
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| 659 | #define RT5631_ALC_NOISE_GATE_FUN_DIS (0x0 << 7) |
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| 660 | #define RT5631_ALC_NOISE_GATE_FUN_ENA (0x1 << 7) |
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| 661 | /* ALC noise gate hold data function */ |
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| 662 | #define RT5631_ALC_NOISE_GATE_H_D_MASK (0x1 << 6) |
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| 663 | #define RT5631_ALC_NOISE_GATE_H_D_DIS (0x0 << 6) |
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| 664 | #define RT5631_ALC_NOISE_GATE_H_D_ENA (0x1 << 6) |
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| 665 | |
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| 666 | /* Psedueo Stereo & Spatial Effect Block Control(0x68) */ |
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| 667 | #define RT5631_SPATIAL_CTRL_EN (0x1 << 15) |
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| 668 | #define RT5631_ALL_PASS_FILTER_EN (0x1 << 14) |
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| 669 | #define RT5631_PSEUDO_STEREO_EN (0x1 << 13) |
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| 670 | #define RT5631_STEREO_EXPENSION_EN (0x1 << 12) |
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| 671 | /* 3D gain parameter */ |
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| 672 | #define RT5631_GAIN_3D_PARA_MASK (0x3 << 6) |
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| 673 | #define RT5631_GAIN_3D_PARA_1_00 (0x0 << 6) /* 3D gain 1.0 */ |
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| 674 | #define RT5631_GAIN_3D_PARA_1_50 (0x1 << 6) /* 3D gain 1.5 */ |
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| 675 | #define RT5631_GAIN_3D_PARA_2_00 (0x2 << 6) /* 3D gain 2.0 */ |
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| 676 | /* 3D ratio parameter */ |
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| 677 | #define RT5631_RATIO_3D_MASK (0x3 << 4) |
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| 678 | #define RT5631_RATIO_3D_0_0 (0x0 << 4) /* 3D ratio 0.0 */ |
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| 679 | #define RT5631_RATIO_3D_0_66 (0x1 << 4) /* 3D ratio 0.66 */ |
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| 680 | #define RT5631_RATIO_3D_1_0 (0x2 << 4) /* 3D ratio 1.0 */ |
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| 681 | /* select samplerate for all pass filter */ |
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| 682 | #define RT5631_APF_FUN_SLE_MASK (0x3 << 0) |
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| 683 | #define RT5631_APF_FUN_SEL_48K (0x3 << 0) |
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| 684 | #define RT5631_APF_FUN_SEL_44_1K (0x2 << 0) |
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| 685 | #define RT5631_APF_FUN_SEL_32K (0x1 << 0) |
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| 686 | #define RT5631_APF_FUN_DIS (0x0 << 0) |
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| 687 | |
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| 688 | /* EQ CONTROL 1(0x6E) */ |
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| 689 | #define RT5631_HW_EQ_PATH_SEL_MASK (0x1 << 15) |
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| 690 | #define RT5631_HW_EQ_PATH_SEL_DAC (0x0 << 15) |
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| 691 | #define RT5631_HW_EQ_PATH_SEL_ADC (0x1 << 15) |
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| 692 | #define RT5631_HW_EQ_UPDATE_CTRL (0x1 << 14) |
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| 693 | |
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| 694 | #define RT5631_EN_HW_EQ_HPF2 (0x1 << 5) |
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| 695 | #define RT5631_EN_HW_EQ_HPF1 (0x1 << 4) |
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| 696 | #define RT5631_EN_HW_EQ_BP3 (0x1 << 3) |
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| 697 | #define RT5631_EN_HW_EQ_BP2 (0x1 << 2) |
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| 698 | #define RT5631_EN_HW_EQ_BP1 (0x1 << 1) |
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| 699 | #define RT5631_EN_HW_EQ_LPF (0x1 << 0) |
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| 700 | |
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| 701 | |
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| 702 | #endif /* __RTCODEC5631_H__ */ |
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| 703 | |
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