| 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
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| 2 | /* |
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| 3 | * rt5682.h -- RT5682/RT5658 ALSA SoC audio driver |
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| 4 | * |
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| 5 | * Copyright 2018 Realtek Microelectronics |
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| 6 | * Author: Bard Liao <bardliao@realtek.com> |
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| 7 | */ |
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| 8 | |
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| 9 | #ifndef __RT5682_H__ |
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| 10 | #define __RT5682_H__ |
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| 11 | |
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| 12 | #include <sound/rt5682.h> |
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| 13 | #include <linux/regulator/consumer.h> |
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| 14 | #include <linux/gpio/consumer.h> |
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| 15 | #include <linux/clk.h> |
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| 16 | #include <linux/clkdev.h> |
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| 17 | #include <linux/clk-provider.h> |
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| 18 | #include <linux/soundwire/sdw.h> |
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| 19 | #include <linux/soundwire/sdw_type.h> |
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| 20 | |
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| 21 | #define DEVICE_ID 0x6530 |
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| 22 | |
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| 23 | /* Info */ |
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| 24 | #define RT5682_RESET 0x0000 |
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| 25 | #define RT5682_VERSION_ID 0x00fd |
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| 26 | #define RT5682_VENDOR_ID 0x00fe |
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| 27 | #define RT5682_DEVICE_ID 0x00ff |
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| 28 | /* I/O - Output */ |
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| 29 | #define RT5682_HP_CTRL_1 0x0002 |
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| 30 | #define RT5682_HP_CTRL_2 0x0003 |
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| 31 | #define RT5682_HPL_GAIN 0x0005 |
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| 32 | #define RT5682_HPR_GAIN 0x0006 |
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| 33 | |
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| 34 | #define RT5682_I2C_CTRL 0x0008 |
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| 35 | |
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| 36 | /* I/O - Input */ |
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| 37 | #define RT5682_CBJ_BST_CTRL 0x000b |
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| 38 | #define RT5682_CBJ_CTRL_1 0x0010 |
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| 39 | #define RT5682_CBJ_CTRL_2 0x0011 |
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| 40 | #define RT5682_CBJ_CTRL_3 0x0012 |
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| 41 | #define RT5682_CBJ_CTRL_4 0x0013 |
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| 42 | #define RT5682_CBJ_CTRL_5 0x0014 |
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| 43 | #define RT5682_CBJ_CTRL_6 0x0015 |
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| 44 | #define RT5682_CBJ_CTRL_7 0x0016 |
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| 45 | /* I/O - ADC/DAC/DMIC */ |
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| 46 | #define RT5682_DAC1_DIG_VOL 0x0019 |
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| 47 | #define RT5682_STO1_ADC_DIG_VOL 0x001c |
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| 48 | #define RT5682_STO1_ADC_BOOST 0x001f |
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| 49 | #define RT5682_HP_IMP_GAIN_1 0x0022 |
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| 50 | #define RT5682_HP_IMP_GAIN_2 0x0023 |
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| 51 | /* Mixer - D-D */ |
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| 52 | #define RT5682_SIDETONE_CTRL 0x0024 |
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| 53 | #define RT5682_STO1_ADC_MIXER 0x0026 |
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| 54 | #define RT5682_AD_DA_MIXER 0x0029 |
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| 55 | #define RT5682_STO1_DAC_MIXER 0x002a |
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| 56 | #define RT5682_A_DAC1_MUX 0x002b |
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| 57 | #define RT5682_DIG_INF2_DATA 0x0030 |
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| 58 | /* Mixer - ADC */ |
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| 59 | #define RT5682_REC_MIXER 0x003c |
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| 60 | #define RT5682_CAL_REC 0x0044 |
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| 61 | #define RT5682_ALC_BACK_GAIN 0x0049 |
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| 62 | /* Power */ |
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| 63 | #define RT5682_PWR_DIG_1 0x0061 |
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| 64 | #define RT5682_PWR_DIG_2 0x0062 |
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| 65 | #define RT5682_PWR_ANLG_1 0x0063 |
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| 66 | #define RT5682_PWR_ANLG_2 0x0064 |
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| 67 | #define RT5682_PWR_ANLG_3 0x0065 |
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| 68 | #define RT5682_PWR_MIXER 0x0066 |
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| 69 | #define RT5682_PWR_VOL 0x0067 |
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| 70 | /* Clock Detect */ |
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| 71 | #define RT5682_CLK_DET 0x006b |
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| 72 | /* Filter Auto Reset */ |
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| 73 | #define RT5682_RESET_LPF_CTRL 0x006c |
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| 74 | #define RT5682_RESET_HPF_CTRL 0x006d |
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| 75 | /* DMIC */ |
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| 76 | #define RT5682_DMIC_CTRL_1 0x006e |
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| 77 | /* Format - ADC/DAC */ |
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| 78 | #define RT5682_I2S1_SDP 0x0070 |
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| 79 | #define RT5682_I2S2_SDP 0x0071 |
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| 80 | #define RT5682_ADDA_CLK_1 0x0073 |
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| 81 | #define RT5682_ADDA_CLK_2 0x0074 |
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| 82 | #define RT5682_I2S1_F_DIV_CTRL_1 0x0075 |
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| 83 | #define RT5682_I2S1_F_DIV_CTRL_2 0x0076 |
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| 84 | /* Format - TDM Control */ |
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| 85 | #define RT5682_TDM_CTRL 0x0079 |
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| 86 | #define RT5682_TDM_ADDA_CTRL_1 0x007a |
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| 87 | #define RT5682_TDM_ADDA_CTRL_2 0x007b |
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| 88 | #define RT5682_DATA_SEL_CTRL_1 0x007c |
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| 89 | #define RT5682_TDM_TCON_CTRL 0x007e |
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| 90 | /* Function - Analog */ |
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| 91 | #define RT5682_GLB_CLK 0x0080 |
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| 92 | #define RT5682_PLL_CTRL_1 0x0081 |
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| 93 | #define RT5682_PLL_CTRL_2 0x0082 |
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| 94 | #define RT5682_PLL_TRACK_1 0x0083 |
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| 95 | #define RT5682_PLL_TRACK_2 0x0084 |
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| 96 | #define RT5682_PLL_TRACK_3 0x0085 |
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| 97 | #define RT5682_PLL_TRACK_4 0x0086 |
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| 98 | #define RT5682_PLL_TRACK_5 0x0087 |
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| 99 | #define RT5682_PLL_TRACK_6 0x0088 |
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| 100 | #define RT5682_PLL_TRACK_11 0x008c |
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| 101 | #define RT5682_SDW_REF_CLK 0x008d |
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| 102 | #define RT5682_DEPOP_1 0x008e |
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| 103 | #define RT5682_DEPOP_2 0x008f |
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| 104 | #define RT5682_HP_CHARGE_PUMP_1 0x0091 |
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| 105 | #define RT5682_HP_CHARGE_PUMP_2 0x0092 |
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| 106 | #define RT5682_MICBIAS_1 0x0093 |
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| 107 | #define RT5682_MICBIAS_2 0x0094 |
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| 108 | #define RT5682_PLL_TRACK_12 0x0098 |
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| 109 | #define RT5682_PLL_TRACK_14 0x009a |
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| 110 | #define RT5682_PLL2_CTRL_1 0x009b |
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| 111 | #define RT5682_PLL2_CTRL_2 0x009c |
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| 112 | #define RT5682_PLL2_CTRL_3 0x009d |
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| 113 | #define RT5682_PLL2_CTRL_4 0x009e |
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| 114 | #define RT5682_RC_CLK_CTRL 0x009f |
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| 115 | #define RT5682_I2S_M_CLK_CTRL_1 0x00a0 |
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| 116 | #define RT5682_I2S2_F_DIV_CTRL_1 0x00a3 |
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| 117 | #define RT5682_I2S2_F_DIV_CTRL_2 0x00a4 |
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| 118 | /* Function - Digital */ |
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| 119 | #define RT5682_EQ_CTRL_1 0x00ae |
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| 120 | #define RT5682_EQ_CTRL_2 0x00af |
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| 121 | #define RT5682_IRQ_CTRL_1 0x00b6 |
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| 122 | #define RT5682_IRQ_CTRL_2 0x00b7 |
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| 123 | #define RT5682_IRQ_CTRL_3 0x00b8 |
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| 124 | #define RT5682_IRQ_CTRL_4 0x00b9 |
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| 125 | #define RT5682_INT_ST_1 0x00be |
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| 126 | #define RT5682_GPIO_CTRL_1 0x00c0 |
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| 127 | #define RT5682_GPIO_CTRL_2 0x00c1 |
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| 128 | #define RT5682_GPIO_CTRL_3 0x00c2 |
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| 129 | #define RT5682_HP_AMP_DET_CTRL_1 0x00d0 |
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| 130 | #define RT5682_HP_AMP_DET_CTRL_2 0x00d1 |
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| 131 | #define RT5682_MID_HP_AMP_DET 0x00d2 |
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| 132 | #define RT5682_LOW_HP_AMP_DET 0x00d3 |
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| 133 | #define RT5682_DELAY_BUF_CTRL 0x00d4 |
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| 134 | #define RT5682_SV_ZCD_1 0x00d9 |
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| 135 | #define RT5682_SV_ZCD_2 0x00da |
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| 136 | #define RT5682_IL_CMD_1 0x00db |
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| 137 | #define RT5682_IL_CMD_2 0x00dc |
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| 138 | #define RT5682_IL_CMD_3 0x00dd |
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| 139 | #define RT5682_IL_CMD_4 0x00de |
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| 140 | #define RT5682_IL_CMD_5 0x00df |
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| 141 | #define RT5682_IL_CMD_6 0x00e0 |
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| 142 | #define RT5682_4BTN_IL_CMD_1 0x00e2 |
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| 143 | #define RT5682_4BTN_IL_CMD_2 0x00e3 |
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| 144 | #define RT5682_4BTN_IL_CMD_3 0x00e4 |
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| 145 | #define RT5682_4BTN_IL_CMD_4 0x00e5 |
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| 146 | #define RT5682_4BTN_IL_CMD_5 0x00e6 |
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| 147 | #define RT5682_4BTN_IL_CMD_6 0x00e7 |
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| 148 | #define RT5682_4BTN_IL_CMD_7 0x00e8 |
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| 149 | |
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| 150 | #define RT5682_ADC_STO1_HP_CTRL_1 0x00ea |
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| 151 | #define RT5682_ADC_STO1_HP_CTRL_2 0x00eb |
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| 152 | #define RT5682_AJD1_CTRL 0x00f0 |
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| 153 | #define RT5682_JD1_THD 0x00f1 |
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| 154 | #define RT5682_JD2_THD 0x00f2 |
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| 155 | #define RT5682_JD_CTRL_1 0x00f6 |
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| 156 | /* General Control */ |
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| 157 | #define RT5682_DUMMY_1 0x00fa |
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| 158 | #define RT5682_DUMMY_2 0x00fb |
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| 159 | #define RT5682_DUMMY_3 0x00fc |
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| 160 | |
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| 161 | #define RT5682_DAC_ADC_DIG_VOL1 0x0100 |
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| 162 | #define RT5682_BIAS_CUR_CTRL_2 0x010b |
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| 163 | #define RT5682_BIAS_CUR_CTRL_3 0x010c |
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| 164 | #define RT5682_BIAS_CUR_CTRL_4 0x010d |
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| 165 | #define RT5682_BIAS_CUR_CTRL_5 0x010e |
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| 166 | #define RT5682_BIAS_CUR_CTRL_6 0x010f |
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| 167 | #define RT5682_BIAS_CUR_CTRL_7 0x0110 |
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| 168 | #define RT5682_BIAS_CUR_CTRL_8 0x0111 |
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| 169 | #define RT5682_BIAS_CUR_CTRL_9 0x0112 |
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| 170 | #define RT5682_BIAS_CUR_CTRL_10 0x0113 |
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| 171 | #define RT5682_VREF_REC_OP_FB_CAP_CTRL 0x0117 |
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| 172 | #define RT5682_CHARGE_PUMP_1 0x0125 |
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| 173 | #define RT5682_DIG_IN_CTRL_1 0x0132 |
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| 174 | #define RT5682_PAD_DRIVING_CTRL 0x0136 |
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| 175 | #define RT5682_SOFT_RAMP_DEPOP 0x0138 |
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| 176 | #define RT5682_CHOP_DAC 0x013a |
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| 177 | #define RT5682_CHOP_ADC 0x013b |
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| 178 | #define RT5682_CALIB_ADC_CTRL 0x013c |
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| 179 | #define RT5682_VOL_TEST 0x013f |
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| 180 | #define RT5682_SPKVDD_DET_STA 0x0142 |
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| 181 | #define RT5682_TEST_MODE_CTRL_1 0x0145 |
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| 182 | #define RT5682_TEST_MODE_CTRL_2 0x0146 |
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| 183 | #define RT5682_TEST_MODE_CTRL_3 0x0147 |
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| 184 | #define RT5682_TEST_MODE_CTRL_4 0x0148 |
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| 185 | #define RT5682_TEST_MODE_CTRL_5 0x0149 |
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| 186 | #define RT5682_PLL1_INTERNAL 0x0150 |
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| 187 | #define RT5682_PLL2_INTERNAL 0x0156 |
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| 188 | #define RT5682_STO_NG2_CTRL_1 0x0160 |
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| 189 | #define RT5682_STO_NG2_CTRL_2 0x0161 |
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| 190 | #define RT5682_STO_NG2_CTRL_3 0x0162 |
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| 191 | #define RT5682_STO_NG2_CTRL_4 0x0163 |
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| 192 | #define RT5682_STO_NG2_CTRL_5 0x0164 |
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| 193 | #define RT5682_STO_NG2_CTRL_6 0x0165 |
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| 194 | #define RT5682_STO_NG2_CTRL_7 0x0166 |
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| 195 | #define RT5682_STO_NG2_CTRL_8 0x0167 |
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| 196 | #define RT5682_STO_NG2_CTRL_9 0x0168 |
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| 197 | #define RT5682_STO_NG2_CTRL_10 0x0169 |
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| 198 | #define RT5682_STO1_DAC_SIL_DET 0x0190 |
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| 199 | #define RT5682_SIL_PSV_CTRL1 0x0194 |
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| 200 | #define RT5682_SIL_PSV_CTRL2 0x0195 |
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| 201 | #define RT5682_SIL_PSV_CTRL3 0x0197 |
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| 202 | #define RT5682_SIL_PSV_CTRL4 0x0198 |
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| 203 | #define RT5682_SIL_PSV_CTRL5 0x0199 |
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| 204 | #define RT5682_HP_IMP_SENS_CTRL_01 0x01af |
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| 205 | #define RT5682_HP_IMP_SENS_CTRL_02 0x01b0 |
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| 206 | #define RT5682_HP_IMP_SENS_CTRL_03 0x01b1 |
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| 207 | #define RT5682_HP_IMP_SENS_CTRL_04 0x01b2 |
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| 208 | #define RT5682_HP_IMP_SENS_CTRL_05 0x01b3 |
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| 209 | #define RT5682_HP_IMP_SENS_CTRL_06 0x01b4 |
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| 210 | #define RT5682_HP_IMP_SENS_CTRL_07 0x01b5 |
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| 211 | #define RT5682_HP_IMP_SENS_CTRL_08 0x01b6 |
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| 212 | #define RT5682_HP_IMP_SENS_CTRL_09 0x01b7 |
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| 213 | #define RT5682_HP_IMP_SENS_CTRL_10 0x01b8 |
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| 214 | #define RT5682_HP_IMP_SENS_CTRL_11 0x01b9 |
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| 215 | #define RT5682_HP_IMP_SENS_CTRL_12 0x01ba |
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| 216 | #define RT5682_HP_IMP_SENS_CTRL_13 0x01bb |
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| 217 | #define RT5682_HP_IMP_SENS_CTRL_14 0x01bc |
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| 218 | #define RT5682_HP_IMP_SENS_CTRL_15 0x01bd |
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| 219 | #define RT5682_HP_IMP_SENS_CTRL_16 0x01be |
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| 220 | #define RT5682_HP_IMP_SENS_CTRL_17 0x01bf |
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| 221 | #define RT5682_HP_IMP_SENS_CTRL_18 0x01c0 |
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| 222 | #define RT5682_HP_IMP_SENS_CTRL_19 0x01c1 |
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| 223 | #define RT5682_HP_IMP_SENS_CTRL_20 0x01c2 |
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| 224 | #define RT5682_HP_IMP_SENS_CTRL_21 0x01c3 |
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| 225 | #define RT5682_HP_IMP_SENS_CTRL_22 0x01c4 |
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| 226 | #define RT5682_HP_IMP_SENS_CTRL_23 0x01c5 |
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| 227 | #define RT5682_HP_IMP_SENS_CTRL_24 0x01c6 |
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| 228 | #define RT5682_HP_IMP_SENS_CTRL_25 0x01c7 |
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| 229 | #define RT5682_HP_IMP_SENS_CTRL_26 0x01c8 |
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| 230 | #define RT5682_HP_IMP_SENS_CTRL_27 0x01c9 |
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| 231 | #define RT5682_HP_IMP_SENS_CTRL_28 0x01ca |
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| 232 | #define RT5682_HP_IMP_SENS_CTRL_29 0x01cb |
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| 233 | #define RT5682_HP_IMP_SENS_CTRL_30 0x01cc |
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| 234 | #define RT5682_HP_IMP_SENS_CTRL_31 0x01cd |
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| 235 | #define RT5682_HP_IMP_SENS_CTRL_32 0x01ce |
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| 236 | #define RT5682_HP_IMP_SENS_CTRL_33 0x01cf |
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| 237 | #define RT5682_HP_IMP_SENS_CTRL_34 0x01d0 |
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| 238 | #define RT5682_HP_IMP_SENS_CTRL_35 0x01d1 |
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| 239 | #define RT5682_HP_IMP_SENS_CTRL_36 0x01d2 |
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| 240 | #define RT5682_HP_IMP_SENS_CTRL_37 0x01d3 |
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| 241 | #define RT5682_HP_IMP_SENS_CTRL_38 0x01d4 |
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| 242 | #define RT5682_HP_IMP_SENS_CTRL_39 0x01d5 |
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| 243 | #define RT5682_HP_IMP_SENS_CTRL_40 0x01d6 |
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| 244 | #define RT5682_HP_IMP_SENS_CTRL_41 0x01d7 |
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| 245 | #define RT5682_HP_IMP_SENS_CTRL_42 0x01d8 |
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| 246 | #define RT5682_HP_IMP_SENS_CTRL_43 0x01d9 |
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| 247 | #define RT5682_HP_LOGIC_CTRL_1 0x01da |
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| 248 | #define RT5682_HP_LOGIC_CTRL_2 0x01db |
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| 249 | #define RT5682_HP_LOGIC_CTRL_3 0x01dc |
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| 250 | #define RT5682_HP_CALIB_CTRL_1 0x01de |
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| 251 | #define RT5682_HP_CALIB_CTRL_2 0x01df |
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| 252 | #define RT5682_HP_CALIB_CTRL_3 0x01e0 |
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| 253 | #define RT5682_HP_CALIB_CTRL_4 0x01e1 |
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| 254 | #define RT5682_HP_CALIB_CTRL_5 0x01e2 |
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| 255 | #define RT5682_HP_CALIB_CTRL_6 0x01e3 |
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| 256 | #define RT5682_HP_CALIB_CTRL_7 0x01e4 |
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| 257 | #define RT5682_HP_CALIB_CTRL_9 0x01e6 |
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| 258 | #define RT5682_HP_CALIB_CTRL_10 0x01e7 |
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| 259 | #define RT5682_HP_CALIB_CTRL_11 0x01e8 |
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| 260 | #define RT5682_HP_CALIB_STA_1 0x01ea |
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| 261 | #define RT5682_HP_CALIB_STA_2 0x01eb |
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| 262 | #define RT5682_HP_CALIB_STA_3 0x01ec |
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| 263 | #define RT5682_HP_CALIB_STA_4 0x01ed |
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| 264 | #define RT5682_HP_CALIB_STA_5 0x01ee |
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| 265 | #define RT5682_HP_CALIB_STA_6 0x01ef |
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| 266 | #define RT5682_HP_CALIB_STA_7 0x01f0 |
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| 267 | #define RT5682_HP_CALIB_STA_8 0x01f1 |
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| 268 | #define RT5682_HP_CALIB_STA_9 0x01f2 |
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| 269 | #define RT5682_HP_CALIB_STA_10 0x01f3 |
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| 270 | #define RT5682_HP_CALIB_STA_11 0x01f4 |
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| 271 | #define RT5682_SAR_IL_CMD_1 0x0210 |
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| 272 | #define RT5682_SAR_IL_CMD_2 0x0211 |
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| 273 | #define RT5682_SAR_IL_CMD_3 0x0212 |
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| 274 | #define RT5682_SAR_IL_CMD_4 0x0213 |
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| 275 | #define RT5682_SAR_IL_CMD_5 0x0214 |
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| 276 | #define RT5682_SAR_IL_CMD_6 0x0215 |
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| 277 | #define RT5682_SAR_IL_CMD_7 0x0216 |
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| 278 | #define RT5682_SAR_IL_CMD_8 0x0217 |
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| 279 | #define RT5682_SAR_IL_CMD_9 0x0218 |
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| 280 | #define RT5682_SAR_IL_CMD_10 0x0219 |
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| 281 | #define RT5682_SAR_IL_CMD_11 0x021a |
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| 282 | #define RT5682_SAR_IL_CMD_12 0x021b |
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| 283 | #define RT5682_SAR_IL_CMD_13 0x021c |
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| 284 | #define RT5682_EFUSE_CTRL_1 0x0250 |
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| 285 | #define RT5682_EFUSE_CTRL_2 0x0251 |
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| 286 | #define RT5682_EFUSE_CTRL_3 0x0252 |
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| 287 | #define RT5682_EFUSE_CTRL_4 0x0253 |
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| 288 | #define RT5682_EFUSE_CTRL_5 0x0254 |
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| 289 | #define RT5682_EFUSE_CTRL_6 0x0255 |
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| 290 | #define RT5682_EFUSE_CTRL_7 0x0256 |
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| 291 | #define RT5682_EFUSE_CTRL_8 0x0257 |
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| 292 | #define RT5682_EFUSE_CTRL_9 0x0258 |
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| 293 | #define RT5682_EFUSE_CTRL_10 0x0259 |
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| 294 | #define RT5682_EFUSE_CTRL_11 0x025a |
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| 295 | #define RT5682_JD_TOP_VC_VTRL 0x0270 |
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| 296 | #define RT5682_DRC1_CTRL_0 0x02ff |
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| 297 | #define RT5682_DRC1_CTRL_1 0x0300 |
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| 298 | #define RT5682_DRC1_CTRL_2 0x0301 |
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| 299 | #define RT5682_DRC1_CTRL_3 0x0302 |
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| 300 | #define RT5682_DRC1_CTRL_4 0x0303 |
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| 301 | #define RT5682_DRC1_CTRL_5 0x0304 |
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| 302 | #define RT5682_DRC1_CTRL_6 0x0305 |
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| 303 | #define RT5682_DRC1_HARD_LMT_CTRL_1 0x0306 |
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| 304 | #define RT5682_DRC1_HARD_LMT_CTRL_2 0x0307 |
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| 305 | #define RT5682_DRC1_PRIV_1 0x0310 |
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| 306 | #define RT5682_DRC1_PRIV_2 0x0311 |
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| 307 | #define RT5682_DRC1_PRIV_3 0x0312 |
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| 308 | #define RT5682_DRC1_PRIV_4 0x0313 |
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| 309 | #define RT5682_DRC1_PRIV_5 0x0314 |
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| 310 | #define RT5682_DRC1_PRIV_6 0x0315 |
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| 311 | #define RT5682_DRC1_PRIV_7 0x0316 |
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| 312 | #define RT5682_DRC1_PRIV_8 0x0317 |
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| 313 | #define RT5682_EQ_AUTO_RCV_CTRL1 0x03c0 |
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| 314 | #define RT5682_EQ_AUTO_RCV_CTRL2 0x03c1 |
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| 315 | #define RT5682_EQ_AUTO_RCV_CTRL3 0x03c2 |
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| 316 | #define RT5682_EQ_AUTO_RCV_CTRL4 0x03c3 |
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| 317 | #define RT5682_EQ_AUTO_RCV_CTRL5 0x03c4 |
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| 318 | #define RT5682_EQ_AUTO_RCV_CTRL6 0x03c5 |
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| 319 | #define RT5682_EQ_AUTO_RCV_CTRL7 0x03c6 |
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| 320 | #define RT5682_EQ_AUTO_RCV_CTRL8 0x03c7 |
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| 321 | #define RT5682_EQ_AUTO_RCV_CTRL9 0x03c8 |
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| 322 | #define RT5682_EQ_AUTO_RCV_CTRL10 0x03c9 |
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| 323 | #define RT5682_EQ_AUTO_RCV_CTRL11 0x03ca |
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| 324 | #define RT5682_EQ_AUTO_RCV_CTRL12 0x03cb |
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| 325 | #define RT5682_EQ_AUTO_RCV_CTRL13 0x03cc |
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| 326 | #define RT5682_ADC_L_EQ_LPF1_A1 0x03d0 |
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| 327 | #define RT5682_R_EQ_LPF1_A1 0x03d1 |
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| 328 | #define RT5682_L_EQ_LPF1_H0 0x03d2 |
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| 329 | #define RT5682_R_EQ_LPF1_H0 0x03d3 |
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| 330 | #define RT5682_L_EQ_BPF1_A1 0x03d4 |
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| 331 | #define RT5682_R_EQ_BPF1_A1 0x03d5 |
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| 332 | #define RT5682_L_EQ_BPF1_A2 0x03d6 |
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| 333 | #define RT5682_R_EQ_BPF1_A2 0x03d7 |
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| 334 | #define RT5682_L_EQ_BPF1_H0 0x03d8 |
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| 335 | #define RT5682_R_EQ_BPF1_H0 0x03d9 |
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| 336 | #define RT5682_L_EQ_BPF2_A1 0x03da |
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| 337 | #define RT5682_R_EQ_BPF2_A1 0x03db |
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| 338 | #define RT5682_L_EQ_BPF2_A2 0x03dc |
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| 339 | #define RT5682_R_EQ_BPF2_A2 0x03dd |
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| 340 | #define RT5682_L_EQ_BPF2_H0 0x03de |
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| 341 | #define RT5682_R_EQ_BPF2_H0 0x03df |
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| 342 | #define RT5682_L_EQ_BPF3_A1 0x03e0 |
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| 343 | #define RT5682_R_EQ_BPF3_A1 0x03e1 |
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| 344 | #define RT5682_L_EQ_BPF3_A2 0x03e2 |
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| 345 | #define RT5682_R_EQ_BPF3_A2 0x03e3 |
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| 346 | #define RT5682_L_EQ_BPF3_H0 0x03e4 |
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| 347 | #define RT5682_R_EQ_BPF3_H0 0x03e5 |
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| 348 | #define RT5682_L_EQ_BPF4_A1 0x03e6 |
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| 349 | #define RT5682_R_EQ_BPF4_A1 0x03e7 |
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| 350 | #define RT5682_L_EQ_BPF4_A2 0x03e8 |
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| 351 | #define RT5682_R_EQ_BPF4_A2 0x03e9 |
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| 352 | #define RT5682_L_EQ_BPF4_H0 0x03ea |
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| 353 | #define RT5682_R_EQ_BPF4_H0 0x03eb |
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| 354 | #define RT5682_L_EQ_HPF1_A1 0x03ec |
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| 355 | #define RT5682_R_EQ_HPF1_A1 0x03ed |
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| 356 | #define RT5682_L_EQ_HPF1_H0 0x03ee |
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| 357 | #define RT5682_R_EQ_HPF1_H0 0x03ef |
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| 358 | #define RT5682_L_EQ_PRE_VOL 0x03f0 |
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| 359 | #define RT5682_R_EQ_PRE_VOL 0x03f1 |
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| 360 | #define RT5682_L_EQ_POST_VOL 0x03f2 |
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| 361 | #define RT5682_R_EQ_POST_VOL 0x03f3 |
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| 362 | #define RT5682_I2C_MODE 0xffff |
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| 363 | |
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| 364 | |
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| 365 | /* global definition */ |
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| 366 | #define RT5682_L_MUTE (0x1 << 15) |
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| 367 | #define RT5682_L_MUTE_SFT 15 |
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| 368 | #define RT5682_VOL_L_MUTE (0x1 << 14) |
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| 369 | #define RT5682_VOL_L_SFT 14 |
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| 370 | #define RT5682_R_MUTE (0x1 << 7) |
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| 371 | #define RT5682_R_MUTE_SFT 7 |
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| 372 | #define RT5682_VOL_R_MUTE (0x1 << 6) |
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| 373 | #define RT5682_VOL_R_SFT 6 |
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| 374 | #define RT5682_L_VOL_MASK (0x3f << 8) |
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| 375 | #define RT5682_L_VOL_SFT 8 |
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| 376 | #define RT5682_R_VOL_MASK (0x3f) |
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| 377 | #define RT5682_R_VOL_SFT 0 |
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| 378 | |
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| 379 | /* Headphone Amp Control 2 (0x0003) */ |
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| 380 | #define RT5682_HP_C2_DAC_AMP_MUTE_SFT 15 |
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| 381 | #define RT5682_HP_C2_DAC_AMP_MUTE (0x1 << 15) |
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| 382 | #define RT5682_HP_C2_DAC_L_EN_SFT 14 |
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| 383 | #define RT5682_HP_C2_DAC_L_EN (0x1 << 14) |
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| 384 | #define RT5682_HP_C2_DAC_R_EN_SFT 13 |
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| 385 | #define RT5682_HP_C2_DAC_R_EN (0x1 << 13) |
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| 386 | |
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| 387 | /*Headphone Amp L/R Analog Gain and Digital NG2 Gain Control (0x0005 0x0006)*/ |
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| 388 | #define RT5682_G_HP (0xf << 8) |
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| 389 | #define RT5682_G_HP_SFT 8 |
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| 390 | #define RT5682_G_STO_DA_DMIX (0xf) |
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| 391 | #define RT5682_G_STO_DA_SFT 0 |
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| 392 | |
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| 393 | /* CBJ Control (0x000b) */ |
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| 394 | #define RT5682_BST_CBJ_MASK (0xf << 8) |
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| 395 | #define RT5682_BST_CBJ_SFT 8 |
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| 396 | |
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| 397 | /* Embeeded Jack and Type Detection Control 1 (0x0010) */ |
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| 398 | #define RT5682_EMB_JD_EN (0x1 << 15) |
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| 399 | #define RT5682_EMB_JD_EN_SFT 15 |
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| 400 | #define RT5682_EMB_JD_RST (0x1 << 14) |
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| 401 | #define RT5682_JD_MODE (0x1 << 13) |
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| 402 | #define RT5682_JD_MODE_SFT 13 |
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| 403 | #define RT5682_DET_TYPE (0x1 << 12) |
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| 404 | #define RT5682_DET_TYPE_SFT 12 |
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| 405 | #define RT5682_POLA_EXT_JD_MASK (0x1 << 11) |
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| 406 | #define RT5682_POLA_EXT_JD_LOW (0x1 << 11) |
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| 407 | #define RT5682_POLA_EXT_JD_HIGH (0x0 << 11) |
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| 408 | #define RT5682_EXT_JD_DIG (0x1 << 9) |
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| 409 | #define RT5682_POL_FAST_OFF_MASK (0x1 << 8) |
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| 410 | #define RT5682_POL_FAST_OFF_HIGH (0x1 << 8) |
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| 411 | #define RT5682_POL_FAST_OFF_LOW (0x0 << 8) |
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| 412 | #define RT5682_FAST_OFF_MASK (0x1 << 7) |
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| 413 | #define RT5682_FAST_OFF_EN (0x1 << 7) |
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| 414 | #define RT5682_FAST_OFF_DIS (0x0 << 7) |
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| 415 | #define RT5682_VREF_POW_MASK (0x1 << 6) |
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| 416 | #define RT5682_VREF_POW_FSM (0x0 << 6) |
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| 417 | #define RT5682_VREF_POW_REG (0x1 << 6) |
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| 418 | #define RT5682_MB1_PATH_MASK (0x1 << 5) |
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| 419 | #define RT5682_CTRL_MB1_REG (0x1 << 5) |
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| 420 | #define RT5682_CTRL_MB1_FSM (0x0 << 5) |
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| 421 | #define RT5682_MB2_PATH_MASK (0x1 << 4) |
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| 422 | #define RT5682_CTRL_MB2_REG (0x1 << 4) |
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| 423 | #define RT5682_CTRL_MB2_FSM (0x0 << 4) |
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| 424 | #define RT5682_TRIG_JD_MASK (0x1 << 3) |
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| 425 | #define RT5682_TRIG_JD_HIGH (0x1 << 3) |
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| 426 | #define RT5682_TRIG_JD_LOW (0x0 << 3) |
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| 427 | #define RT5682_MIC_CAP_MASK (0x1 << 1) |
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| 428 | #define RT5682_MIC_CAP_HS (0x1 << 1) |
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| 429 | #define RT5682_MIC_CAP_HP (0x0 << 1) |
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| 430 | #define RT5682_MIC_CAP_SRC_MASK (0x1) |
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| 431 | #define RT5682_MIC_CAP_SRC_REG (0x1) |
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| 432 | #define RT5682_MIC_CAP_SRC_ANA (0x0) |
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| 433 | |
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| 434 | /* Embeeded Jack and Type Detection Control 2 (0x0011) */ |
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| 435 | #define RT5682_EXT_JD_SRC (0x7 << 4) |
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| 436 | #define RT5682_EXT_JD_SRC_SFT 4 |
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| 437 | #define RT5682_EXT_JD_SRC_GPIO_JD1 (0x0 << 4) |
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| 438 | #define RT5682_EXT_JD_SRC_GPIO_JD2 (0x1 << 4) |
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| 439 | #define RT5682_EXT_JD_SRC_JDH (0x2 << 4) |
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| 440 | #define RT5682_EXT_JD_SRC_JDL (0x3 << 4) |
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| 441 | #define RT5682_EXT_JD_SRC_MANUAL (0x4 << 4) |
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| 442 | #define RT5682_JACK_TYPE_MASK (0x3) |
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| 443 | |
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| 444 | /* Combo Jack and Type Detection Control 3 (0x0012) */ |
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| 445 | #define RT5682_CBJ_IN_BUF_EN (0x1 << 7) |
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| 446 | |
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| 447 | /* Combo Jack and Type Detection Control 4 (0x0013) */ |
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| 448 | #define RT5682_SEL_SHT_MID_TON_MASK (0x3 << 12) |
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| 449 | #define RT5682_SEL_SHT_MID_TON_2 (0x0 << 12) |
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| 450 | #define RT5682_SEL_SHT_MID_TON_3 (0x1 << 12) |
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| 451 | #define RT5682_CBJ_JD_TEST_MASK (0x1 << 6) |
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| 452 | #define RT5682_CBJ_JD_TEST_NORM (0x0 << 6) |
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| 453 | #define RT5682_CBJ_JD_TEST_MODE (0x1 << 6) |
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| 454 | |
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| 455 | /* DAC1 Digital Volume (0x0019) */ |
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| 456 | #define RT5682_DAC_L1_VOL_MASK (0xff << 8) |
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| 457 | #define RT5682_DAC_L1_VOL_SFT 8 |
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| 458 | #define RT5682_DAC_R1_VOL_MASK (0xff) |
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| 459 | #define RT5682_DAC_R1_VOL_SFT 0 |
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| 460 | |
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| 461 | /* ADC Digital Volume Control (0x001c) */ |
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| 462 | #define RT5682_ADC_L_VOL_MASK (0x7f << 8) |
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| 463 | #define RT5682_ADC_L_VOL_SFT 8 |
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| 464 | #define RT5682_ADC_R_VOL_MASK (0x7f) |
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| 465 | #define RT5682_ADC_R_VOL_SFT 0 |
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| 466 | |
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| 467 | /* Stereo1 ADC Boost Gain Control (0x001f) */ |
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| 468 | #define RT5682_STO1_ADC_L_BST_MASK (0x3 << 14) |
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| 469 | #define RT5682_STO1_ADC_L_BST_SFT 14 |
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| 470 | #define RT5682_STO1_ADC_R_BST_MASK (0x3 << 12) |
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| 471 | #define RT5682_STO1_ADC_R_BST_SFT 12 |
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| 472 | |
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| 473 | /* Sidetone Control (0x0024) */ |
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| 474 | #define RT5682_ST_SRC_SEL (0x1 << 8) |
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| 475 | #define RT5682_ST_SRC_SFT 8 |
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| 476 | #define RT5682_ST_EN_MASK (0x1 << 6) |
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| 477 | #define RT5682_ST_DIS (0x0 << 6) |
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| 478 | #define RT5682_ST_EN (0x1 << 6) |
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| 479 | #define RT5682_ST_EN_SFT 6 |
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| 480 | |
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| 481 | /* Stereo1 ADC Mixer Control (0x0026) */ |
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| 482 | #define RT5682_M_STO1_ADC_L1 (0x1 << 15) |
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| 483 | #define RT5682_M_STO1_ADC_L1_SFT 15 |
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| 484 | #define RT5682_M_STO1_ADC_L2 (0x1 << 14) |
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| 485 | #define RT5682_M_STO1_ADC_L2_SFT 14 |
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| 486 | #define RT5682_STO1_ADC1L_SRC_MASK (0x1 << 13) |
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| 487 | #define RT5682_STO1_ADC1L_SRC_SFT 13 |
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| 488 | #define RT5682_STO1_ADC1_SRC_ADC (0x1 << 13) |
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| 489 | #define RT5682_STO1_ADC1_SRC_DACMIX (0x0 << 13) |
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| 490 | #define RT5682_STO1_ADC2L_SRC_MASK (0x1 << 12) |
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| 491 | #define RT5682_STO1_ADC2L_SRC_SFT 12 |
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| 492 | #define RT5682_STO1_ADCL_SRC_MASK (0x3 << 10) |
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| 493 | #define RT5682_STO1_ADCL_SRC_SFT 10 |
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| 494 | #define RT5682_STO1_DD_L_SRC_MASK (0x1 << 9) |
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| 495 | #define RT5682_STO1_DD_L_SRC_SFT 9 |
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| 496 | #define RT5682_STO1_DMIC_SRC_MASK (0x1 << 8) |
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| 497 | #define RT5682_STO1_DMIC_SRC_SFT 8 |
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| 498 | #define RT5682_STO1_DMIC_SRC_DMIC2 (0x1 << 8) |
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| 499 | #define RT5682_STO1_DMIC_SRC_DMIC1 (0x0 << 8) |
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| 500 | #define RT5682_M_STO1_ADC_R1 (0x1 << 7) |
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| 501 | #define RT5682_M_STO1_ADC_R1_SFT 7 |
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| 502 | #define RT5682_M_STO1_ADC_R2 (0x1 << 6) |
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| 503 | #define RT5682_M_STO1_ADC_R2_SFT 6 |
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| 504 | #define RT5682_STO1_ADC1R_SRC_MASK (0x1 << 5) |
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| 505 | #define RT5682_STO1_ADC1R_SRC_SFT 5 |
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| 506 | #define RT5682_STO1_ADC2R_SRC_MASK (0x1 << 4) |
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| 507 | #define RT5682_STO1_ADC2R_SRC_SFT 4 |
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| 508 | #define RT5682_STO1_ADCR_SRC_MASK (0x3 << 2) |
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| 509 | #define RT5682_STO1_ADCR_SRC_SFT 2 |
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| 510 | |
|---|
| 511 | /* ADC Mixer to DAC Mixer Control (0x0029) */ |
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| 512 | #define RT5682_M_ADCMIX_L (0x1 << 15) |
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| 513 | #define RT5682_M_ADCMIX_L_SFT 15 |
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| 514 | #define RT5682_M_DAC1_L (0x1 << 14) |
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| 515 | #define RT5682_M_DAC1_L_SFT 14 |
|---|
| 516 | #define RT5682_DAC1_R_SEL_MASK (0x1 << 10) |
|---|
| 517 | #define RT5682_DAC1_R_SEL_SFT 10 |
|---|
| 518 | #define RT5682_DAC1_L_SEL_MASK (0x1 << 8) |
|---|
| 519 | #define RT5682_DAC1_L_SEL_SFT 8 |
|---|
| 520 | #define RT5682_M_ADCMIX_R (0x1 << 7) |
|---|
| 521 | #define RT5682_M_ADCMIX_R_SFT 7 |
|---|
| 522 | #define RT5682_M_DAC1_R (0x1 << 6) |
|---|
| 523 | #define RT5682_M_DAC1_R_SFT 6 |
|---|
| 524 | |
|---|
| 525 | /* Stereo1 DAC Mixer Control (0x002a) */ |
|---|
| 526 | #define RT5682_M_DAC_L1_STO_L (0x1 << 15) |
|---|
| 527 | #define RT5682_M_DAC_L1_STO_L_SFT 15 |
|---|
| 528 | #define RT5682_G_DAC_L1_STO_L_MASK (0x1 << 14) |
|---|
| 529 | #define RT5682_G_DAC_L1_STO_L_SFT 14 |
|---|
| 530 | #define RT5682_M_DAC_R1_STO_L (0x1 << 13) |
|---|
| 531 | #define RT5682_M_DAC_R1_STO_L_SFT 13 |
|---|
| 532 | #define RT5682_G_DAC_R1_STO_L_MASK (0x1 << 12) |
|---|
| 533 | #define RT5682_G_DAC_R1_STO_L_SFT 12 |
|---|
| 534 | #define RT5682_M_DAC_L1_STO_R (0x1 << 7) |
|---|
| 535 | #define RT5682_M_DAC_L1_STO_R_SFT 7 |
|---|
| 536 | #define RT5682_G_DAC_L1_STO_R_MASK (0x1 << 6) |
|---|
| 537 | #define RT5682_G_DAC_L1_STO_R_SFT 6 |
|---|
| 538 | #define RT5682_M_DAC_R1_STO_R (0x1 << 5) |
|---|
| 539 | #define RT5682_M_DAC_R1_STO_R_SFT 5 |
|---|
| 540 | #define RT5682_G_DAC_R1_STO_R_MASK (0x1 << 4) |
|---|
| 541 | #define RT5682_G_DAC_R1_STO_R_SFT 4 |
|---|
| 542 | |
|---|
| 543 | /* Analog DAC1 Input Source Control (0x002b) */ |
|---|
| 544 | #define RT5682_M_ST_STO_L (0x1 << 9) |
|---|
| 545 | #define RT5682_M_ST_STO_L_SFT 9 |
|---|
| 546 | #define RT5682_M_ST_STO_R (0x1 << 8) |
|---|
| 547 | #define RT5682_M_ST_STO_R_SFT 8 |
|---|
| 548 | #define RT5682_DAC_L1_SRC_MASK (0x3 << 4) |
|---|
| 549 | #define RT5682_A_DACL1_SFT 4 |
|---|
| 550 | #define RT5682_DAC_R1_SRC_MASK (0x3) |
|---|
| 551 | #define RT5682_A_DACR1_SFT 0 |
|---|
| 552 | |
|---|
| 553 | /* Digital Interface Data Control (0x0030) */ |
|---|
| 554 | #define RT5682_IF2_ADC_SEL_MASK (0x3 << 0) |
|---|
| 555 | #define RT5682_IF2_ADC_SEL_SFT 0 |
|---|
| 556 | |
|---|
| 557 | /* REC Left Mixer Control 2 (0x003c) */ |
|---|
| 558 | #define RT5682_G_CBJ_RM1_L (0x7 << 10) |
|---|
| 559 | #define RT5682_G_CBJ_RM1_L_SFT 10 |
|---|
| 560 | #define RT5682_M_CBJ_RM1_L (0x1 << 7) |
|---|
| 561 | #define RT5682_M_CBJ_RM1_L_SFT 7 |
|---|
| 562 | |
|---|
| 563 | /* Power Management for Digital 1 (0x0061) */ |
|---|
| 564 | #define RT5682_PWR_I2S1 (0x1 << 15) |
|---|
| 565 | #define RT5682_PWR_I2S1_BIT 15 |
|---|
| 566 | #define RT5682_PWR_I2S2 (0x1 << 14) |
|---|
| 567 | #define RT5682_PWR_I2S2_BIT 14 |
|---|
| 568 | #define RT5682_PWR_DAC_L1 (0x1 << 11) |
|---|
| 569 | #define RT5682_PWR_DAC_L1_BIT 11 |
|---|
| 570 | #define RT5682_PWR_DAC_R1 (0x1 << 10) |
|---|
| 571 | #define RT5682_PWR_DAC_R1_BIT 10 |
|---|
| 572 | #define RT5682_PWR_LDO (0x1 << 8) |
|---|
| 573 | #define RT5682_PWR_LDO_BIT 8 |
|---|
| 574 | #define RT5682_PWR_ADC_L1 (0x1 << 4) |
|---|
| 575 | #define RT5682_PWR_ADC_L1_BIT 4 |
|---|
| 576 | #define RT5682_PWR_ADC_R1 (0x1 << 3) |
|---|
| 577 | #define RT5682_PWR_ADC_R1_BIT 3 |
|---|
| 578 | #define RT5682_DIG_GATE_CTRL (0x1 << 0) |
|---|
| 579 | #define RT5682_DIG_GATE_CTRL_SFT 0 |
|---|
| 580 | |
|---|
| 581 | |
|---|
| 582 | /* Power Management for Digital 2 (0x0062) */ |
|---|
| 583 | #define RT5682_PWR_ADC_S1F (0x1 << 15) |
|---|
| 584 | #define RT5682_PWR_ADC_S1F_BIT 15 |
|---|
| 585 | #define RT5682_PWR_DAC_S1F (0x1 << 10) |
|---|
| 586 | #define RT5682_PWR_DAC_S1F_BIT 10 |
|---|
| 587 | |
|---|
| 588 | /* Power Management for Analog 1 (0x0063) */ |
|---|
| 589 | #define RT5682_PWR_VREF1 (0x1 << 15) |
|---|
| 590 | #define RT5682_PWR_VREF1_BIT 15 |
|---|
| 591 | #define RT5682_PWR_FV1 (0x1 << 14) |
|---|
| 592 | #define RT5682_PWR_FV1_BIT 14 |
|---|
| 593 | #define RT5682_PWR_VREF2 (0x1 << 13) |
|---|
| 594 | #define RT5682_PWR_VREF2_BIT 13 |
|---|
| 595 | #define RT5682_PWR_FV2 (0x1 << 12) |
|---|
| 596 | #define RT5682_PWR_FV2_BIT 12 |
|---|
| 597 | #define RT5682_LDO1_DBG_MASK (0x3 << 10) |
|---|
| 598 | #define RT5682_PWR_MB (0x1 << 9) |
|---|
| 599 | #define RT5682_PWR_MB_BIT 9 |
|---|
| 600 | #define RT5682_PWR_BG (0x1 << 7) |
|---|
| 601 | #define RT5682_PWR_BG_BIT 7 |
|---|
| 602 | #define RT5682_LDO1_BYPASS_MASK (0x1 << 6) |
|---|
| 603 | #define RT5682_LDO1_BYPASS (0x1 << 6) |
|---|
| 604 | #define RT5682_LDO1_NOT_BYPASS (0x0 << 6) |
|---|
| 605 | #define RT5682_PWR_MA_BIT 6 |
|---|
| 606 | #define RT5682_LDO1_DVO_MASK (0x3 << 4) |
|---|
| 607 | #define RT5682_LDO1_DVO_09 (0x0 << 4) |
|---|
| 608 | #define RT5682_LDO1_DVO_10 (0x1 << 4) |
|---|
| 609 | #define RT5682_LDO1_DVO_12 (0x2 << 4) |
|---|
| 610 | #define RT5682_LDO1_DVO_14 (0x3 << 4) |
|---|
| 611 | #define RT5682_HP_DRIVER_MASK (0x3 << 2) |
|---|
| 612 | #define RT5682_HP_DRIVER_1X (0x0 << 2) |
|---|
| 613 | #define RT5682_HP_DRIVER_3X (0x1 << 2) |
|---|
| 614 | #define RT5682_HP_DRIVER_5X (0x3 << 2) |
|---|
| 615 | #define RT5682_PWR_HA_L (0x1 << 1) |
|---|
| 616 | #define RT5682_PWR_HA_L_BIT 1 |
|---|
| 617 | #define RT5682_PWR_HA_R (0x1 << 0) |
|---|
| 618 | #define RT5682_PWR_HA_R_BIT 0 |
|---|
| 619 | |
|---|
| 620 | /* Power Management for Analog 2 (0x0064) */ |
|---|
| 621 | #define RT5682_PWR_MB1 (0x1 << 11) |
|---|
| 622 | #define RT5682_PWR_MB1_PWR_DOWN (0x0 << 11) |
|---|
| 623 | #define RT5682_PWR_MB1_BIT 11 |
|---|
| 624 | #define RT5682_PWR_MB2 (0x1 << 10) |
|---|
| 625 | #define RT5682_PWR_MB2_PWR_DOWN (0x0 << 10) |
|---|
| 626 | #define RT5682_PWR_MB2_BIT 10 |
|---|
| 627 | #define RT5682_PWR_JDH (0x1 << 3) |
|---|
| 628 | #define RT5682_PWR_JDH_BIT 3 |
|---|
| 629 | #define RT5682_PWR_JDL (0x1 << 2) |
|---|
| 630 | #define RT5682_PWR_JDL_BIT 2 |
|---|
| 631 | #define RT5682_PWR_RM1_L (0x1 << 1) |
|---|
| 632 | #define RT5682_PWR_RM1_L_BIT 1 |
|---|
| 633 | |
|---|
| 634 | /* Power Management for Analog 3 (0x0065) */ |
|---|
| 635 | #define RT5682_PWR_CBJ (0x1 << 9) |
|---|
| 636 | #define RT5682_PWR_CBJ_BIT 9 |
|---|
| 637 | #define RT5682_PWR_PLL (0x1 << 6) |
|---|
| 638 | #define RT5682_PWR_PLL_BIT 6 |
|---|
| 639 | #define RT5682_PWR_PLL2B (0x1 << 5) |
|---|
| 640 | #define RT5682_PWR_PLL2B_BIT 5 |
|---|
| 641 | #define RT5682_PWR_PLL2F (0x1 << 4) |
|---|
| 642 | #define RT5682_PWR_PLL2F_BIT 4 |
|---|
| 643 | #define RT5682_PWR_LDO2 (0x1 << 2) |
|---|
| 644 | #define RT5682_PWR_LDO2_BIT 2 |
|---|
| 645 | #define RT5682_PWR_DET_SPKVDD (0x1 << 1) |
|---|
| 646 | #define RT5682_PWR_DET_SPKVDD_BIT 1 |
|---|
| 647 | |
|---|
| 648 | /* Power Management for Mixer (0x0066) */ |
|---|
| 649 | #define RT5682_PWR_STO1_DAC_L (0x1 << 5) |
|---|
| 650 | #define RT5682_PWR_STO1_DAC_L_BIT 5 |
|---|
| 651 | #define RT5682_PWR_STO1_DAC_R (0x1 << 4) |
|---|
| 652 | #define RT5682_PWR_STO1_DAC_R_BIT 4 |
|---|
| 653 | |
|---|
| 654 | /* MCLK and System Clock Detection Control (0x006b) */ |
|---|
| 655 | #define RT5682_SYS_CLK_DET (0x1 << 15) |
|---|
| 656 | #define RT5682_SYS_CLK_DET_SFT 15 |
|---|
| 657 | #define RT5682_PLL1_CLK_DET (0x1 << 14) |
|---|
| 658 | #define RT5682_PLL1_CLK_DET_SFT 14 |
|---|
| 659 | #define RT5682_PLL2_CLK_DET (0x1 << 13) |
|---|
| 660 | #define RT5682_PLL2_CLK_DET_SFT 13 |
|---|
| 661 | #define RT5682_POW_CLK_DET2_SFT 8 |
|---|
| 662 | #define RT5682_POW_CLK_DET_SFT 0 |
|---|
| 663 | |
|---|
| 664 | /* Digital Microphone Control 1 (0x006e) */ |
|---|
| 665 | #define RT5682_DMIC_1_EN_MASK (0x1 << 15) |
|---|
| 666 | #define RT5682_DMIC_1_EN_SFT 15 |
|---|
| 667 | #define RT5682_DMIC_1_DIS (0x0 << 15) |
|---|
| 668 | #define RT5682_DMIC_1_EN (0x1 << 15) |
|---|
| 669 | #define RT5682_FIFO_CLK_DIV_MASK (0x7 << 12) |
|---|
| 670 | #define RT5682_FIFO_CLK_DIV_2 (0x1 << 12) |
|---|
| 671 | #define RT5682_DMIC_1_DP_MASK (0x3 << 4) |
|---|
| 672 | #define RT5682_DMIC_1_DP_SFT 4 |
|---|
| 673 | #define RT5682_DMIC_1_DP_GPIO2 (0x0 << 4) |
|---|
| 674 | #define RT5682_DMIC_1_DP_GPIO5 (0x1 << 4) |
|---|
| 675 | #define RT5682_DMIC_CLK_MASK (0xf << 0) |
|---|
| 676 | #define RT5682_DMIC_CLK_SFT 0 |
|---|
| 677 | |
|---|
| 678 | /* I2S1 Audio Serial Data Port Control (0x0070) */ |
|---|
| 679 | #define RT5682_SEL_ADCDAT_MASK (0x1 << 15) |
|---|
| 680 | #define RT5682_SEL_ADCDAT_OUT (0x0 << 15) |
|---|
| 681 | #define RT5682_SEL_ADCDAT_IN (0x1 << 15) |
|---|
| 682 | #define RT5682_SEL_ADCDAT_SFT 15 |
|---|
| 683 | #define RT5682_I2S1_TX_CHL_MASK (0x7 << 12) |
|---|
| 684 | #define RT5682_I2S1_TX_CHL_SFT 12 |
|---|
| 685 | #define RT5682_I2S1_TX_CHL_16 (0x0 << 12) |
|---|
| 686 | #define RT5682_I2S1_TX_CHL_20 (0x1 << 12) |
|---|
| 687 | #define RT5682_I2S1_TX_CHL_24 (0x2 << 12) |
|---|
| 688 | #define RT5682_I2S1_TX_CHL_32 (0x3 << 12) |
|---|
| 689 | #define RT5682_I2S1_TX_CHL_8 (0x4 << 12) |
|---|
| 690 | #define RT5682_I2S1_RX_CHL_MASK (0x7 << 8) |
|---|
| 691 | #define RT5682_I2S1_RX_CHL_SFT 8 |
|---|
| 692 | #define RT5682_I2S1_RX_CHL_16 (0x0 << 8) |
|---|
| 693 | #define RT5682_I2S1_RX_CHL_20 (0x1 << 8) |
|---|
| 694 | #define RT5682_I2S1_RX_CHL_24 (0x2 << 8) |
|---|
| 695 | #define RT5682_I2S1_RX_CHL_32 (0x3 << 8) |
|---|
| 696 | #define RT5682_I2S1_RX_CHL_8 (0x4 << 8) |
|---|
| 697 | #define RT5682_I2S1_MONO_MASK (0x1 << 7) |
|---|
| 698 | #define RT5682_I2S1_MONO_EN (0x1 << 7) |
|---|
| 699 | #define RT5682_I2S1_MONO_DIS (0x0 << 7) |
|---|
| 700 | #define RT5682_I2S2_MONO_MASK (0x1 << 6) |
|---|
| 701 | #define RT5682_I2S2_MONO_EN (0x1 << 6) |
|---|
| 702 | #define RT5682_I2S2_MONO_DIS (0x0 << 6) |
|---|
| 703 | #define RT5682_I2S1_DL_MASK (0x7 << 4) |
|---|
| 704 | #define RT5682_I2S1_DL_SFT 4 |
|---|
| 705 | #define RT5682_I2S1_DL_16 (0x0 << 4) |
|---|
| 706 | #define RT5682_I2S1_DL_20 (0x1 << 4) |
|---|
| 707 | #define RT5682_I2S1_DL_24 (0x2 << 4) |
|---|
| 708 | #define RT5682_I2S1_DL_32 (0x3 << 4) |
|---|
| 709 | #define RT5682_I2S1_DL_8 (0x4 << 4) |
|---|
| 710 | |
|---|
| 711 | /* I2S1/2 Audio Serial Data Port Control (0x0070)(0x0071) */ |
|---|
| 712 | #define RT5682_I2S2_MS_MASK (0x1 << 15) |
|---|
| 713 | #define RT5682_I2S2_MS_SFT 15 |
|---|
| 714 | #define RT5682_I2S2_MS_M (0x0 << 15) |
|---|
| 715 | #define RT5682_I2S2_MS_S (0x1 << 15) |
|---|
| 716 | #define RT5682_I2S2_PIN_CFG_MASK (0x1 << 14) |
|---|
| 717 | #define RT5682_I2S2_PIN_CFG_SFT 14 |
|---|
| 718 | #define RT5682_I2S2_CLK_SEL_MASK (0x1 << 11) |
|---|
| 719 | #define RT5682_I2S2_CLK_SEL_SFT 11 |
|---|
| 720 | #define RT5682_I2S2_OUT_MASK (0x1 << 9) |
|---|
| 721 | #define RT5682_I2S2_OUT_SFT 9 |
|---|
| 722 | #define RT5682_I2S2_OUT_UM (0x0 << 9) |
|---|
| 723 | #define RT5682_I2S2_OUT_M (0x1 << 9) |
|---|
| 724 | #define RT5682_I2S_BP_MASK (0x1 << 8) |
|---|
| 725 | #define RT5682_I2S_BP_SFT 8 |
|---|
| 726 | #define RT5682_I2S_BP_NOR (0x0 << 8) |
|---|
| 727 | #define RT5682_I2S_BP_INV (0x1 << 8) |
|---|
| 728 | #define RT5682_I2S2_MONO_EN (0x1 << 6) |
|---|
| 729 | #define RT5682_I2S2_MONO_DIS (0x0 << 6) |
|---|
| 730 | #define RT5682_I2S2_DL_MASK (0x3 << 4) |
|---|
| 731 | #define RT5682_I2S2_DL_SFT 4 |
|---|
| 732 | #define RT5682_I2S2_DL_16 (0x0 << 4) |
|---|
| 733 | #define RT5682_I2S2_DL_20 (0x1 << 4) |
|---|
| 734 | #define RT5682_I2S2_DL_24 (0x2 << 4) |
|---|
| 735 | #define RT5682_I2S2_DL_8 (0x3 << 4) |
|---|
| 736 | #define RT5682_I2S_DF_MASK (0x7) |
|---|
| 737 | #define RT5682_I2S_DF_SFT 0 |
|---|
| 738 | #define RT5682_I2S_DF_I2S (0x0) |
|---|
| 739 | #define RT5682_I2S_DF_LEFT (0x1) |
|---|
| 740 | #define RT5682_I2S_DF_PCM_A (0x2) |
|---|
| 741 | #define RT5682_I2S_DF_PCM_B (0x3) |
|---|
| 742 | #define RT5682_I2S_DF_PCM_A_N (0x6) |
|---|
| 743 | #define RT5682_I2S_DF_PCM_B_N (0x7) |
|---|
| 744 | |
|---|
| 745 | /* ADC/DAC Clock Control 1 (0x0073) */ |
|---|
| 746 | #define RT5682_ADC_OSR_MASK (0xf << 12) |
|---|
| 747 | #define RT5682_ADC_OSR_SFT 12 |
|---|
| 748 | #define RT5682_ADC_OSR_D_1 (0x0 << 12) |
|---|
| 749 | #define RT5682_ADC_OSR_D_2 (0x1 << 12) |
|---|
| 750 | #define RT5682_ADC_OSR_D_4 (0x2 << 12) |
|---|
| 751 | #define RT5682_ADC_OSR_D_6 (0x3 << 12) |
|---|
| 752 | #define RT5682_ADC_OSR_D_8 (0x4 << 12) |
|---|
| 753 | #define RT5682_ADC_OSR_D_12 (0x5 << 12) |
|---|
| 754 | #define RT5682_ADC_OSR_D_16 (0x6 << 12) |
|---|
| 755 | #define RT5682_ADC_OSR_D_24 (0x7 << 12) |
|---|
| 756 | #define RT5682_ADC_OSR_D_32 (0x8 << 12) |
|---|
| 757 | #define RT5682_ADC_OSR_D_48 (0x9 << 12) |
|---|
| 758 | #define RT5682_I2S_M_DIV_MASK (0xf << 8) |
|---|
| 759 | #define RT5682_I2S_M_DIV_SFT 8 |
|---|
| 760 | #define RT5682_I2S_M_D_1 (0x0 << 8) |
|---|
| 761 | #define RT5682_I2S_M_D_2 (0x1 << 8) |
|---|
| 762 | #define RT5682_I2S_M_D_3 (0x2 << 8) |
|---|
| 763 | #define RT5682_I2S_M_D_4 (0x3 << 8) |
|---|
| 764 | #define RT5682_I2S_M_D_6 (0x4 << 8) |
|---|
| 765 | #define RT5682_I2S_M_D_8 (0x5 << 8) |
|---|
| 766 | #define RT5682_I2S_M_D_12 (0x6 << 8) |
|---|
| 767 | #define RT5682_I2S_M_D_16 (0x7 << 8) |
|---|
| 768 | #define RT5682_I2S_M_D_24 (0x8 << 8) |
|---|
| 769 | #define RT5682_I2S_M_D_32 (0x9 << 8) |
|---|
| 770 | #define RT5682_I2S_M_D_48 (0x10 << 8) |
|---|
| 771 | #define RT5682_I2S_CLK_SRC_MASK (0x7 << 4) |
|---|
| 772 | #define RT5682_I2S_CLK_SRC_SFT 4 |
|---|
| 773 | #define RT5682_I2S_CLK_SRC_MCLK (0x0 << 4) |
|---|
| 774 | #define RT5682_I2S_CLK_SRC_PLL1 (0x1 << 4) |
|---|
| 775 | #define RT5682_I2S_CLK_SRC_PLL2 (0x2 << 4) |
|---|
| 776 | #define RT5682_I2S_CLK_SRC_SDW (0x3 << 4) |
|---|
| 777 | #define RT5682_I2S_CLK_SRC_RCCLK (0x4 << 4) /* 25M */ |
|---|
| 778 | #define RT5682_DAC_OSR_MASK (0xf << 0) |
|---|
| 779 | #define RT5682_DAC_OSR_SFT 0 |
|---|
| 780 | #define RT5682_DAC_OSR_D_1 (0x0 << 0) |
|---|
| 781 | #define RT5682_DAC_OSR_D_2 (0x1 << 0) |
|---|
| 782 | #define RT5682_DAC_OSR_D_4 (0x2 << 0) |
|---|
| 783 | #define RT5682_DAC_OSR_D_6 (0x3 << 0) |
|---|
| 784 | #define RT5682_DAC_OSR_D_8 (0x4 << 0) |
|---|
| 785 | #define RT5682_DAC_OSR_D_12 (0x5 << 0) |
|---|
| 786 | #define RT5682_DAC_OSR_D_16 (0x6 << 0) |
|---|
| 787 | #define RT5682_DAC_OSR_D_24 (0x7 << 0) |
|---|
| 788 | #define RT5682_DAC_OSR_D_32 (0x8 << 0) |
|---|
| 789 | #define RT5682_DAC_OSR_D_48 (0x9 << 0) |
|---|
| 790 | |
|---|
| 791 | /* ADC/DAC Clock Control 2 (0x0074) */ |
|---|
| 792 | #define RT5682_I2S2_BCLK_MS2_MASK (0x1 << 11) |
|---|
| 793 | #define RT5682_I2S2_BCLK_MS2_SFT 11 |
|---|
| 794 | #define RT5682_I2S2_BCLK_MS2_32 (0x0 << 11) |
|---|
| 795 | #define RT5682_I2S2_BCLK_MS2_64 (0x1 << 11) |
|---|
| 796 | |
|---|
| 797 | |
|---|
| 798 | /* TDM control 1 (0x0079) */ |
|---|
| 799 | #define RT5682_TDM_TX_CH_MASK (0x3 << 12) |
|---|
| 800 | #define RT5682_TDM_TX_CH_2 (0x0 << 12) |
|---|
| 801 | #define RT5682_TDM_TX_CH_4 (0x1 << 12) |
|---|
| 802 | #define RT5682_TDM_TX_CH_6 (0x2 << 12) |
|---|
| 803 | #define RT5682_TDM_TX_CH_8 (0x3 << 12) |
|---|
| 804 | #define RT5682_TDM_RX_CH_MASK (0x3 << 8) |
|---|
| 805 | #define RT5682_TDM_RX_CH_2 (0x0 << 8) |
|---|
| 806 | #define RT5682_TDM_RX_CH_4 (0x1 << 8) |
|---|
| 807 | #define RT5682_TDM_RX_CH_6 (0x2 << 8) |
|---|
| 808 | #define RT5682_TDM_RX_CH_8 (0x3 << 8) |
|---|
| 809 | #define RT5682_TDM_ADC_LCA_MASK (0xf << 4) |
|---|
| 810 | #define RT5682_TDM_ADC_LCA_SFT 4 |
|---|
| 811 | #define RT5682_TDM_ADC_DL_SFT 0 |
|---|
| 812 | |
|---|
| 813 | /* TDM control 2 (0x007a) */ |
|---|
| 814 | #define RT5682_IF1_ADC1_SEL_SFT 14 |
|---|
| 815 | #define RT5682_IF1_ADC2_SEL_SFT 12 |
|---|
| 816 | #define RT5682_IF1_ADC3_SEL_SFT 10 |
|---|
| 817 | #define RT5682_IF1_ADC4_SEL_SFT 8 |
|---|
| 818 | #define RT5682_TDM_ADC_SEL_SFT 4 |
|---|
| 819 | |
|---|
| 820 | /* TDM control 3 (0x007b) */ |
|---|
| 821 | #define RT5682_TDM_EN (0x1 << 7) |
|---|
| 822 | |
|---|
| 823 | /* TDM/I2S control (0x007e) */ |
|---|
| 824 | #define RT5682_TDM_S_BP_MASK (0x1 << 15) |
|---|
| 825 | #define RT5682_TDM_S_BP_SFT 15 |
|---|
| 826 | #define RT5682_TDM_S_BP_NOR (0x0 << 15) |
|---|
| 827 | #define RT5682_TDM_S_BP_INV (0x1 << 15) |
|---|
| 828 | #define RT5682_TDM_S_LP_MASK (0x1 << 14) |
|---|
| 829 | #define RT5682_TDM_S_LP_SFT 14 |
|---|
| 830 | #define RT5682_TDM_S_LP_NOR (0x0 << 14) |
|---|
| 831 | #define RT5682_TDM_S_LP_INV (0x1 << 14) |
|---|
| 832 | #define RT5682_TDM_DF_MASK (0x7 << 11) |
|---|
| 833 | #define RT5682_TDM_DF_SFT 11 |
|---|
| 834 | #define RT5682_TDM_DF_I2S (0x0 << 11) |
|---|
| 835 | #define RT5682_TDM_DF_LEFT (0x1 << 11) |
|---|
| 836 | #define RT5682_TDM_DF_PCM_A (0x2 << 11) |
|---|
| 837 | #define RT5682_TDM_DF_PCM_B (0x3 << 11) |
|---|
| 838 | #define RT5682_TDM_DF_PCM_A_N (0x6 << 11) |
|---|
| 839 | #define RT5682_TDM_DF_PCM_B_N (0x7 << 11) |
|---|
| 840 | #define RT5682_TDM_BCLK_MS1_MASK (0x3 << 9) |
|---|
| 841 | #define RT5682_TDM_BCLK_MS1_SFT 9 |
|---|
| 842 | #define RT5682_TDM_BCLK_MS1_32 (0x0 << 9) |
|---|
| 843 | #define RT5682_TDM_BCLK_MS1_64 (0x1 << 9) |
|---|
| 844 | #define RT5682_TDM_BCLK_MS1_128 (0x2 << 9) |
|---|
| 845 | #define RT5682_TDM_BCLK_MS1_256 (0x3 << 9) |
|---|
| 846 | #define RT5682_TDM_CL_MASK (0x3 << 4) |
|---|
| 847 | #define RT5682_TDM_CL_16 (0x0 << 4) |
|---|
| 848 | #define RT5682_TDM_CL_20 (0x1 << 4) |
|---|
| 849 | #define RT5682_TDM_CL_24 (0x2 << 4) |
|---|
| 850 | #define RT5682_TDM_CL_32 (0x3 << 4) |
|---|
| 851 | #define RT5682_TDM_M_BP_MASK (0x1 << 2) |
|---|
| 852 | #define RT5682_TDM_M_BP_SFT 2 |
|---|
| 853 | #define RT5682_TDM_M_BP_NOR (0x0 << 2) |
|---|
| 854 | #define RT5682_TDM_M_BP_INV (0x1 << 2) |
|---|
| 855 | #define RT5682_TDM_M_LP_MASK (0x1 << 1) |
|---|
| 856 | #define RT5682_TDM_M_LP_SFT 1 |
|---|
| 857 | #define RT5682_TDM_M_LP_NOR (0x0 << 1) |
|---|
| 858 | #define RT5682_TDM_M_LP_INV (0x1 << 1) |
|---|
| 859 | #define RT5682_TDM_MS_MASK (0x1 << 0) |
|---|
| 860 | #define RT5682_TDM_MS_SFT 0 |
|---|
| 861 | #define RT5682_TDM_MS_S (0x0 << 0) |
|---|
| 862 | #define RT5682_TDM_MS_M (0x1 << 0) |
|---|
| 863 | |
|---|
| 864 | /* Global Clock Control (0x0080) */ |
|---|
| 865 | #define RT5682_SCLK_SRC_MASK (0x7 << 13) |
|---|
| 866 | #define RT5682_SCLK_SRC_SFT 13 |
|---|
| 867 | #define RT5682_SCLK_SRC_MCLK (0x0 << 13) |
|---|
| 868 | #define RT5682_SCLK_SRC_PLL1 (0x1 << 13) |
|---|
| 869 | #define RT5682_SCLK_SRC_PLL2 (0x2 << 13) |
|---|
| 870 | #define RT5682_SCLK_SRC_SDW (0x3 << 13) |
|---|
| 871 | #define RT5682_SCLK_SRC_RCCLK (0x4 << 13) |
|---|
| 872 | #define RT5682_PLL2_SRC_MASK (0x3 << 10) |
|---|
| 873 | #define RT5682_PLL2_SRC_SFT 10 |
|---|
| 874 | #define RT5682_PLL2_SRC_MCLK (0x0 << 10) |
|---|
| 875 | #define RT5682_PLL2_SRC_BCLK1 (0x1 << 10) |
|---|
| 876 | #define RT5682_PLL2_SRC_SDW (0x2 << 10) |
|---|
| 877 | #define RT5682_PLL2_SRC_RC (0x3 << 10) |
|---|
| 878 | #define RT5682_PLL1_SRC_MASK (0x3 << 8) |
|---|
| 879 | #define RT5682_PLL1_SRC_SFT 8 |
|---|
| 880 | #define RT5682_PLL1_SRC_MCLK (0x0 << 8) |
|---|
| 881 | #define RT5682_PLL1_SRC_BCLK1 (0x1 << 8) |
|---|
| 882 | #define RT5682_PLL1_SRC_SDW (0x2 << 8) |
|---|
| 883 | #define RT5682_PLL1_SRC_RC (0x3 << 8) |
|---|
| 884 | |
|---|
| 885 | |
|---|
| 886 | |
|---|
| 887 | #define RT5682_PLL_INP_MAX 40000000 |
|---|
| 888 | #define RT5682_PLL_INP_MIN 256000 |
|---|
| 889 | /* PLL M/N/K Code Control 1 (0x0081) */ |
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| 890 | #define RT5682_PLL_N_MAX 0x001ff |
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| 891 | #define RT5682_PLL_N_MASK (RT5682_PLL_N_MAX << 7) |
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| 892 | #define RT5682_PLL_N_SFT 7 |
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| 893 | #define RT5682_PLL_K_MAX 0x001f |
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| 894 | #define RT5682_PLL_K_MASK (RT5682_PLL_K_MAX) |
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| 895 | #define RT5682_PLL_K_SFT 0 |
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| 896 | |
|---|
| 897 | /* PLL M/N/K Code Control 2 (0x0082) */ |
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| 898 | #define RT5682_PLL_M_MAX 0x00f |
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| 899 | #define RT5682_PLL_M_MASK (RT5682_PLL_M_MAX << 12) |
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| 900 | #define RT5682_PLL_M_SFT 12 |
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| 901 | #define RT5682_PLL_M_BP (0x1 << 11) |
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| 902 | #define RT5682_PLL_M_BP_SFT 11 |
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| 903 | #define RT5682_PLL_K_BP (0x1 << 10) |
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| 904 | #define RT5682_PLL_K_BP_SFT 10 |
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| 905 | #define RT5682_PLL_RST (0x1 << 1) |
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| 906 | |
|---|
| 907 | /* PLL tracking mode 1 (0x0083) */ |
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| 908 | #define RT5682_DA_ASRC_MASK (0x1 << 13) |
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| 909 | #define RT5682_DA_ASRC_SFT 13 |
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| 910 | #define RT5682_DAC_STO1_ASRC_MASK (0x1 << 12) |
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| 911 | #define RT5682_DAC_STO1_ASRC_SFT 12 |
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| 912 | #define RT5682_AD_ASRC_MASK (0x1 << 8) |
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| 913 | #define RT5682_AD_ASRC_SFT 8 |
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| 914 | #define RT5682_AD_ASRC_SEL_MASK (0x1 << 4) |
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| 915 | #define RT5682_AD_ASRC_SEL_SFT 4 |
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| 916 | #define RT5682_DMIC_ASRC_MASK (0x1 << 3) |
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| 917 | #define RT5682_DMIC_ASRC_SFT 3 |
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| 918 | #define RT5682_ADC_STO1_ASRC_MASK (0x1 << 2) |
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| 919 | #define RT5682_ADC_STO1_ASRC_SFT 2 |
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| 920 | #define RT5682_DA_ASRC_SEL_MASK (0x1 << 0) |
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| 921 | #define RT5682_DA_ASRC_SEL_SFT 0 |
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| 922 | |
|---|
| 923 | /* PLL tracking mode 2 3 (0x0084)(0x0085)*/ |
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| 924 | #define RT5682_FILTER_CLK_SEL_MASK (0x7 << 12) |
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| 925 | #define RT5682_FILTER_CLK_SEL_SFT 12 |
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| 926 | #define RT5682_FILTER_CLK_DIV_MASK (0xf << 8) |
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| 927 | #define RT5682_FILTER_CLK_DIV_SFT 8 |
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| 928 | |
|---|
| 929 | /* ASRC Control 4 (0x0086) */ |
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| 930 | #define RT5682_ASRCIN_FTK_N1_MASK (0x3 << 14) |
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| 931 | #define RT5682_ASRCIN_FTK_N1_SFT 14 |
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| 932 | #define RT5682_ASRCIN_FTK_N2_MASK (0x3 << 12) |
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| 933 | #define RT5682_ASRCIN_FTK_N2_SFT 12 |
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| 934 | #define RT5682_ASRCIN_FTK_M1_MASK (0x7 << 8) |
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| 935 | #define RT5682_ASRCIN_FTK_M1_SFT 8 |
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| 936 | #define RT5682_ASRCIN_FTK_M2_MASK (0x7 << 4) |
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| 937 | #define RT5682_ASRCIN_FTK_M2_SFT 4 |
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| 938 | |
|---|
| 939 | /* SoundWire reference clk (0x008d) */ |
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| 940 | #define RT5682_PLL2_OUT_MASK (0x1 << 8) |
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| 941 | #define RT5682_PLL2_OUT_98M (0x0 << 8) |
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| 942 | #define RT5682_PLL2_OUT_49M (0x1 << 8) |
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| 943 | #define RT5682_SDW_REF_2_MASK (0xf << 4) |
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| 944 | #define RT5682_SDW_REF_2_SFT 4 |
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| 945 | #define RT5682_SDW_REF_2_48K (0x0 << 4) |
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| 946 | #define RT5682_SDW_REF_2_96K (0x1 << 4) |
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| 947 | #define RT5682_SDW_REF_2_192K (0x2 << 4) |
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| 948 | #define RT5682_SDW_REF_2_32K (0x3 << 4) |
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| 949 | #define RT5682_SDW_REF_2_24K (0x4 << 4) |
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| 950 | #define RT5682_SDW_REF_2_16K (0x5 << 4) |
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| 951 | #define RT5682_SDW_REF_2_12K (0x6 << 4) |
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| 952 | #define RT5682_SDW_REF_2_8K (0x7 << 4) |
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| 953 | #define RT5682_SDW_REF_2_44K (0x8 << 4) |
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| 954 | #define RT5682_SDW_REF_2_88K (0x9 << 4) |
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| 955 | #define RT5682_SDW_REF_2_176K (0xa << 4) |
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| 956 | #define RT5682_SDW_REF_2_353K (0xb << 4) |
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| 957 | #define RT5682_SDW_REF_2_22K (0xc << 4) |
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| 958 | #define RT5682_SDW_REF_2_384K (0xd << 4) |
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| 959 | #define RT5682_SDW_REF_2_11K (0xe << 4) |
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| 960 | #define RT5682_SDW_REF_1_MASK (0xf << 0) |
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| 961 | #define RT5682_SDW_REF_1_SFT 0 |
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| 962 | #define RT5682_SDW_REF_1_48K (0x0 << 0) |
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| 963 | #define RT5682_SDW_REF_1_96K (0x1 << 0) |
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| 964 | #define RT5682_SDW_REF_1_192K (0x2 << 0) |
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| 965 | #define RT5682_SDW_REF_1_32K (0x3 << 0) |
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| 966 | #define RT5682_SDW_REF_1_24K (0x4 << 0) |
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| 967 | #define RT5682_SDW_REF_1_16K (0x5 << 0) |
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| 968 | #define RT5682_SDW_REF_1_12K (0x6 << 0) |
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| 969 | #define RT5682_SDW_REF_1_8K (0x7 << 0) |
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| 970 | #define RT5682_SDW_REF_1_44K (0x8 << 0) |
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| 971 | #define RT5682_SDW_REF_1_88K (0x9 << 0) |
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| 972 | #define RT5682_SDW_REF_1_176K (0xa << 0) |
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| 973 | #define RT5682_SDW_REF_1_353K (0xb << 0) |
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| 974 | #define RT5682_SDW_REF_1_22K (0xc << 0) |
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| 975 | #define RT5682_SDW_REF_1_384K (0xd << 0) |
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| 976 | #define RT5682_SDW_REF_1_11K (0xe << 0) |
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| 977 | |
|---|
| 978 | /* Depop Mode Control 1 (0x008e) */ |
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| 979 | #define RT5682_PUMP_EN (0x1 << 3) |
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| 980 | #define RT5682_PUMP_EN_SFT 3 |
|---|
| 981 | #define RT5682_CAPLESS_EN (0x1 << 0) |
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| 982 | #define RT5682_CAPLESS_EN_SFT 0 |
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| 983 | |
|---|
| 984 | /* Depop Mode Control 2 (0x8f) */ |
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| 985 | #define RT5682_RAMP_MASK (0x1 << 12) |
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| 986 | #define RT5682_RAMP_SFT 12 |
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| 987 | #define RT5682_RAMP_DIS (0x0 << 12) |
|---|
| 988 | #define RT5682_RAMP_EN (0x1 << 12) |
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| 989 | #define RT5682_BPS_MASK (0x1 << 11) |
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| 990 | #define RT5682_BPS_SFT 11 |
|---|
| 991 | #define RT5682_BPS_DIS (0x0 << 11) |
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| 992 | #define RT5682_BPS_EN (0x1 << 11) |
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| 993 | #define RT5682_FAST_UPDN_MASK (0x1 << 10) |
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| 994 | #define RT5682_FAST_UPDN_SFT 10 |
|---|
| 995 | #define RT5682_FAST_UPDN_DIS (0x0 << 10) |
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| 996 | #define RT5682_FAST_UPDN_EN (0x1 << 10) |
|---|
| 997 | #define RT5682_VLO_MASK (0x1 << 7) |
|---|
| 998 | #define RT5682_VLO_SFT 7 |
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| 999 | #define RT5682_VLO_3V (0x0 << 7) |
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| 1000 | #define RT5682_VLO_33V (0x1 << 7) |
|---|
| 1001 | |
|---|
| 1002 | /* HPOUT charge pump 1 (0x0091) */ |
|---|
| 1003 | #define RT5682_OSW_L_MASK (0x1 << 11) |
|---|
| 1004 | #define RT5682_OSW_L_SFT 11 |
|---|
| 1005 | #define RT5682_OSW_L_DIS (0x0 << 11) |
|---|
| 1006 | #define RT5682_OSW_L_EN (0x1 << 11) |
|---|
| 1007 | #define RT5682_OSW_R_MASK (0x1 << 10) |
|---|
| 1008 | #define RT5682_OSW_R_SFT 10 |
|---|
| 1009 | #define RT5682_OSW_R_DIS (0x0 << 10) |
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| 1010 | #define RT5682_OSW_R_EN (0x1 << 10) |
|---|
| 1011 | #define RT5682_PM_HP_MASK (0x3 << 8) |
|---|
| 1012 | #define RT5682_PM_HP_SFT 8 |
|---|
| 1013 | #define RT5682_PM_HP_LV (0x0 << 8) |
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| 1014 | #define RT5682_PM_HP_MV (0x1 << 8) |
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| 1015 | #define RT5682_PM_HP_HV (0x2 << 8) |
|---|
| 1016 | #define RT5682_IB_HP_MASK (0x3 << 6) |
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| 1017 | #define RT5682_IB_HP_SFT 6 |
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| 1018 | #define RT5682_IB_HP_125IL (0x0 << 6) |
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| 1019 | #define RT5682_IB_HP_25IL (0x1 << 6) |
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| 1020 | #define RT5682_IB_HP_5IL (0x2 << 6) |
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| 1021 | #define RT5682_IB_HP_1IL (0x3 << 6) |
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| 1022 | |
|---|
| 1023 | /* Micbias Control1 (0x93) */ |
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| 1024 | #define RT5682_MIC1_OV_MASK (0x3 << 14) |
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| 1025 | #define RT5682_MIC1_OV_SFT 14 |
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| 1026 | #define RT5682_MIC1_OV_2V7 (0x0 << 14) |
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| 1027 | #define RT5682_MIC1_OV_2V4 (0x1 << 14) |
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| 1028 | #define RT5682_MIC1_OV_2V25 (0x3 << 14) |
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| 1029 | #define RT5682_MIC1_OV_1V8 (0x4 << 14) |
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| 1030 | #define RT5682_MIC1_CLK_MASK (0x1 << 13) |
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| 1031 | #define RT5682_MIC1_CLK_SFT 13 |
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| 1032 | #define RT5682_MIC1_CLK_DIS (0x0 << 13) |
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| 1033 | #define RT5682_MIC1_CLK_EN (0x1 << 13) |
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| 1034 | #define RT5682_MIC1_OVCD_MASK (0x1 << 12) |
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| 1035 | #define RT5682_MIC1_OVCD_SFT 12 |
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| 1036 | #define RT5682_MIC1_OVCD_DIS (0x0 << 12) |
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| 1037 | #define RT5682_MIC1_OVCD_EN (0x1 << 12) |
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| 1038 | #define RT5682_MIC1_OVTH_MASK (0x3 << 10) |
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| 1039 | #define RT5682_MIC1_OVTH_SFT 10 |
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| 1040 | #define RT5682_MIC1_OVTH_768UA (0x0 << 10) |
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| 1041 | #define RT5682_MIC1_OVTH_960UA (0x1 << 10) |
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| 1042 | #define RT5682_MIC1_OVTH_1152UA (0x2 << 10) |
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| 1043 | #define RT5682_MIC1_OVTH_1960UA (0x3 << 10) |
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| 1044 | #define RT5682_MIC2_OV_MASK (0x3 << 8) |
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| 1045 | #define RT5682_MIC2_OV_SFT 8 |
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| 1046 | #define RT5682_MIC2_OV_2V7 (0x0 << 8) |
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| 1047 | #define RT5682_MIC2_OV_2V4 (0x1 << 8) |
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| 1048 | #define RT5682_MIC2_OV_2V25 (0x3 << 8) |
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| 1049 | #define RT5682_MIC2_OV_1V8 (0x4 << 8) |
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| 1050 | #define RT5682_MIC2_CLK_MASK (0x1 << 7) |
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| 1051 | #define RT5682_MIC2_CLK_SFT 7 |
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| 1052 | #define RT5682_MIC2_CLK_DIS (0x0 << 7) |
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| 1053 | #define RT5682_MIC2_CLK_EN (0x1 << 7) |
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| 1054 | #define RT5682_MIC2_OVTH_MASK (0x3 << 4) |
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| 1055 | #define RT5682_MIC2_OVTH_SFT 4 |
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| 1056 | #define RT5682_MIC2_OVTH_768UA (0x0 << 4) |
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| 1057 | #define RT5682_MIC2_OVTH_960UA (0x1 << 4) |
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| 1058 | #define RT5682_MIC2_OVTH_1152UA (0x2 << 4) |
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| 1059 | #define RT5682_MIC2_OVTH_1960UA (0x3 << 4) |
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| 1060 | #define RT5682_PWR_MB_MASK (0x1 << 3) |
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| 1061 | #define RT5682_PWR_MB_SFT 3 |
|---|
| 1062 | #define RT5682_PWR_MB_PD (0x0 << 3) |
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| 1063 | #define RT5682_PWR_MB_PU (0x1 << 3) |
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| 1064 | |
|---|
| 1065 | /* Micbias Control2 (0x0094) */ |
|---|
| 1066 | #define RT5682_PWR_CLK25M_MASK (0x1 << 9) |
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| 1067 | #define RT5682_PWR_CLK25M_SFT 9 |
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| 1068 | #define RT5682_PWR_CLK25M_PD (0x0 << 9) |
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| 1069 | #define RT5682_PWR_CLK25M_PU (0x1 << 9) |
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| 1070 | #define RT5682_PWR_CLK1M_MASK (0x1 << 8) |
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| 1071 | #define RT5682_PWR_CLK1M_SFT 8 |
|---|
| 1072 | #define RT5682_PWR_CLK1M_PD (0x0 << 8) |
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| 1073 | #define RT5682_PWR_CLK1M_PU (0x1 << 8) |
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| 1074 | |
|---|
| 1075 | /* PLL2 M/N/K Code Control 1 (0x009b) */ |
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| 1076 | #define RT5682_PLL2F_K_MASK (0x1f << 8) |
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| 1077 | #define RT5682_PLL2F_K_SFT 8 |
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| 1078 | #define RT5682_PLL2B_K_MASK (0xf << 4) |
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| 1079 | #define RT5682_PLL2B_K_SFT 4 |
|---|
| 1080 | #define RT5682_PLL2B_M_MASK (0xf << 0) |
|---|
| 1081 | |
|---|
| 1082 | /* PLL2 M/N/K Code Control 2 (0x009c) */ |
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| 1083 | #define RT5682_PLL2F_M_MASK (0x3f << 8) |
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| 1084 | #define RT5682_PLL2F_M_SFT 8 |
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| 1085 | #define RT5682_PLL2B_N_MASK (0x3f << 0) |
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| 1086 | |
|---|
| 1087 | /* PLL2 M/N/K Code Control 2 (0x009d) */ |
|---|
| 1088 | #define RT5682_PLL2F_N_MASK (0x7f << 8) |
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| 1089 | #define RT5682_PLL2F_N_SFT 8 |
|---|
| 1090 | |
|---|
| 1091 | /* PLL2 M/N/K Code Control 2 (0x009e) */ |
|---|
| 1092 | #define RT5682_PLL2B_SEL_PS_MASK (0x1 << 13) |
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| 1093 | #define RT5682_PLL2B_SEL_PS_SFT 13 |
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| 1094 | #define RT5682_PLL2B_PS_BYP_MASK (0x1 << 12) |
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| 1095 | #define RT5682_PLL2B_PS_BYP_SFT 12 |
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| 1096 | #define RT5682_PLL2B_M_BP_MASK (0x1 << 11) |
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| 1097 | #define RT5682_PLL2B_M_BP_SFT 11 |
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| 1098 | #define RT5682_PLL2F_M_BP_MASK (0x1 << 7) |
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| 1099 | #define RT5682_PLL2F_M_BP_SFT 7 |
|---|
| 1100 | |
|---|
| 1101 | /* RC Clock Control (0x009f) */ |
|---|
| 1102 | #define RT5682_POW_IRQ (0x1 << 15) |
|---|
| 1103 | #define RT5682_POW_JDH (0x1 << 14) |
|---|
| 1104 | #define RT5682_POW_JDL (0x1 << 13) |
|---|
| 1105 | #define RT5682_POW_ANA (0x1 << 12) |
|---|
| 1106 | |
|---|
| 1107 | /* I2S Master Mode Clock Control 1 (0x00a0) */ |
|---|
| 1108 | #define RT5682_CLK_SRC_MCLK (0x0) |
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| 1109 | #define RT5682_CLK_SRC_PLL1 (0x1) |
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| 1110 | #define RT5682_CLK_SRC_PLL2 (0x2) |
|---|
| 1111 | #define RT5682_CLK_SRC_SDW (0x3) |
|---|
| 1112 | #define RT5682_CLK_SRC_RCCLK (0x4) |
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| 1113 | #define RT5682_I2S_PD_1 (0x0) |
|---|
| 1114 | #define RT5682_I2S_PD_2 (0x1) |
|---|
| 1115 | #define RT5682_I2S_PD_3 (0x2) |
|---|
| 1116 | #define RT5682_I2S_PD_4 (0x3) |
|---|
| 1117 | #define RT5682_I2S_PD_6 (0x4) |
|---|
| 1118 | #define RT5682_I2S_PD_8 (0x5) |
|---|
| 1119 | #define RT5682_I2S_PD_12 (0x6) |
|---|
| 1120 | #define RT5682_I2S_PD_16 (0x7) |
|---|
| 1121 | #define RT5682_I2S_PD_24 (0x8) |
|---|
| 1122 | #define RT5682_I2S_PD_32 (0x9) |
|---|
| 1123 | #define RT5682_I2S_PD_48 (0xa) |
|---|
| 1124 | #define RT5682_I2S2_SRC_MASK (0x3 << 4) |
|---|
| 1125 | #define RT5682_I2S2_SRC_SFT 4 |
|---|
| 1126 | #define RT5682_I2S2_M_PD_MASK (0xf << 0) |
|---|
| 1127 | #define RT5682_I2S2_M_PD_SFT 0 |
|---|
| 1128 | |
|---|
| 1129 | /* IRQ Control 1 (0x00b6) */ |
|---|
| 1130 | #define RT5682_JD1_PULSE_EN_MASK (0x1 << 10) |
|---|
| 1131 | #define RT5682_JD1_PULSE_EN_SFT 10 |
|---|
| 1132 | #define RT5682_JD1_PULSE_DIS (0x0 << 10) |
|---|
| 1133 | #define RT5682_JD1_PULSE_EN (0x1 << 10) |
|---|
| 1134 | |
|---|
| 1135 | /* IRQ Control 2 (0x00b7) */ |
|---|
| 1136 | #define RT5682_JD1_EN_MASK (0x1 << 15) |
|---|
| 1137 | #define RT5682_JD1_EN_SFT 15 |
|---|
| 1138 | #define RT5682_JD1_DIS (0x0 << 15) |
|---|
| 1139 | #define RT5682_JD1_EN (0x1 << 15) |
|---|
| 1140 | #define RT5682_JD1_POL_MASK (0x1 << 13) |
|---|
| 1141 | #define RT5682_JD1_POL_NOR (0x0 << 13) |
|---|
| 1142 | #define RT5682_JD1_POL_INV (0x1 << 13) |
|---|
| 1143 | #define RT5682_JD1_IRQ_MASK (0x1 << 10) |
|---|
| 1144 | #define RT5682_JD1_IRQ_LEV (0x0 << 10) |
|---|
| 1145 | #define RT5682_JD1_IRQ_PUL (0x1 << 10) |
|---|
| 1146 | |
|---|
| 1147 | /* IRQ Control 3 (0x00b8) */ |
|---|
| 1148 | #define RT5682_IL_IRQ_MASK (0x1 << 7) |
|---|
| 1149 | #define RT5682_IL_IRQ_DIS (0x0 << 7) |
|---|
| 1150 | #define RT5682_IL_IRQ_EN (0x1 << 7) |
|---|
| 1151 | #define RT5682_IL_IRQ_TYPE_MASK (0x1 << 4) |
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| 1152 | #define RT5682_IL_IRQ_LEV (0x0 << 4) |
|---|
| 1153 | #define RT5682_IL_IRQ_PUL (0x1 << 4) |
|---|
| 1154 | |
|---|
| 1155 | /* GPIO Control 1 (0x00c0) */ |
|---|
| 1156 | #define RT5682_GP1_PIN_MASK (0x3 << 14) |
|---|
| 1157 | #define RT5682_GP1_PIN_SFT 14 |
|---|
| 1158 | #define RT5682_GP1_PIN_GPIO1 (0x0 << 14) |
|---|
| 1159 | #define RT5682_GP1_PIN_IRQ (0x1 << 14) |
|---|
| 1160 | #define RT5682_GP1_PIN_DMIC_CLK (0x2 << 14) |
|---|
| 1161 | #define RT5682_GP2_PIN_MASK (0x3 << 12) |
|---|
| 1162 | #define RT5682_GP2_PIN_SFT 12 |
|---|
| 1163 | #define RT5682_GP2_PIN_GPIO2 (0x0 << 12) |
|---|
| 1164 | #define RT5682_GP2_PIN_LRCK2 (0x1 << 12) |
|---|
| 1165 | #define RT5682_GP2_PIN_DMIC_SDA (0x2 << 12) |
|---|
| 1166 | #define RT5682_GP3_PIN_MASK (0x3 << 10) |
|---|
| 1167 | #define RT5682_GP3_PIN_SFT 10 |
|---|
| 1168 | #define RT5682_GP3_PIN_GPIO3 (0x0 << 10) |
|---|
| 1169 | #define RT5682_GP3_PIN_BCLK2 (0x1 << 10) |
|---|
| 1170 | #define RT5682_GP3_PIN_DMIC_CLK (0x2 << 10) |
|---|
| 1171 | #define RT5682_GP4_PIN_MASK (0x3 << 8) |
|---|
| 1172 | #define RT5682_GP4_PIN_SFT 8 |
|---|
| 1173 | #define RT5682_GP4_PIN_GPIO4 (0x0 << 8) |
|---|
| 1174 | #define RT5682_GP4_PIN_ADCDAT1 (0x1 << 8) |
|---|
| 1175 | #define RT5682_GP4_PIN_DMIC_CLK (0x2 << 8) |
|---|
| 1176 | #define RT5682_GP4_PIN_ADCDAT2 (0x3 << 8) |
|---|
| 1177 | #define RT5682_GP5_PIN_MASK (0x3 << 6) |
|---|
| 1178 | #define RT5682_GP5_PIN_SFT 6 |
|---|
| 1179 | #define RT5682_GP5_PIN_GPIO5 (0x0 << 6) |
|---|
| 1180 | #define RT5682_GP5_PIN_DACDAT1 (0x1 << 6) |
|---|
| 1181 | #define RT5682_GP5_PIN_DMIC_SDA (0x2 << 6) |
|---|
| 1182 | #define RT5682_GP6_PIN_MASK (0x1 << 5) |
|---|
| 1183 | #define RT5682_GP6_PIN_SFT 5 |
|---|
| 1184 | #define RT5682_GP6_PIN_GPIO6 (0x0 << 5) |
|---|
| 1185 | #define RT5682_GP6_PIN_LRCK1 (0x1 << 5) |
|---|
| 1186 | |
|---|
| 1187 | /* GPIO Control 2 (0x00c1)*/ |
|---|
| 1188 | #define RT5682_GP1_PF_MASK (0x1 << 15) |
|---|
| 1189 | #define RT5682_GP1_PF_IN (0x0 << 15) |
|---|
| 1190 | #define RT5682_GP1_PF_OUT (0x1 << 15) |
|---|
| 1191 | #define RT5682_GP1_OUT_MASK (0x1 << 14) |
|---|
| 1192 | #define RT5682_GP1_OUT_L (0x0 << 14) |
|---|
| 1193 | #define RT5682_GP1_OUT_H (0x1 << 14) |
|---|
| 1194 | #define RT5682_GP2_PF_MASK (0x1 << 13) |
|---|
| 1195 | #define RT5682_GP2_PF_IN (0x0 << 13) |
|---|
| 1196 | #define RT5682_GP2_PF_OUT (0x1 << 13) |
|---|
| 1197 | #define RT5682_GP2_OUT_MASK (0x1 << 12) |
|---|
| 1198 | #define RT5682_GP2_OUT_L (0x0 << 12) |
|---|
| 1199 | #define RT5682_GP2_OUT_H (0x1 << 12) |
|---|
| 1200 | #define RT5682_GP3_PF_MASK (0x1 << 11) |
|---|
| 1201 | #define RT5682_GP3_PF_IN (0x0 << 11) |
|---|
| 1202 | #define RT5682_GP3_PF_OUT (0x1 << 11) |
|---|
| 1203 | #define RT5682_GP3_OUT_MASK (0x1 << 10) |
|---|
| 1204 | #define RT5682_GP3_OUT_L (0x0 << 10) |
|---|
| 1205 | #define RT5682_GP3_OUT_H (0x1 << 10) |
|---|
| 1206 | #define RT5682_GP4_PF_MASK (0x1 << 9) |
|---|
| 1207 | #define RT5682_GP4_PF_IN (0x0 << 9) |
|---|
| 1208 | #define RT5682_GP4_PF_OUT (0x1 << 9) |
|---|
| 1209 | #define RT5682_GP4_OUT_MASK (0x1 << 8) |
|---|
| 1210 | #define RT5682_GP4_OUT_L (0x0 << 8) |
|---|
| 1211 | #define RT5682_GP4_OUT_H (0x1 << 8) |
|---|
| 1212 | #define RT5682_GP5_PF_MASK (0x1 << 7) |
|---|
| 1213 | #define RT5682_GP5_PF_IN (0x0 << 7) |
|---|
| 1214 | #define RT5682_GP5_PF_OUT (0x1 << 7) |
|---|
| 1215 | #define RT5682_GP5_OUT_MASK (0x1 << 6) |
|---|
| 1216 | #define RT5682_GP5_OUT_L (0x0 << 6) |
|---|
| 1217 | #define RT5682_GP5_OUT_H (0x1 << 6) |
|---|
| 1218 | #define RT5682_GP6_PF_MASK (0x1 << 5) |
|---|
| 1219 | #define RT5682_GP6_PF_IN (0x0 << 5) |
|---|
| 1220 | #define RT5682_GP6_PF_OUT (0x1 << 5) |
|---|
| 1221 | #define RT5682_GP6_OUT_MASK (0x1 << 4) |
|---|
| 1222 | #define RT5682_GP6_OUT_L (0x0 << 4) |
|---|
| 1223 | #define RT5682_GP6_OUT_H (0x1 << 4) |
|---|
| 1224 | |
|---|
| 1225 | |
|---|
| 1226 | /* GPIO Status (0x00c2) */ |
|---|
| 1227 | #define RT5682_GP6_STA (0x1 << 6) |
|---|
| 1228 | #define RT5682_GP5_STA (0x1 << 5) |
|---|
| 1229 | #define RT5682_GP4_STA (0x1 << 4) |
|---|
| 1230 | #define RT5682_GP3_STA (0x1 << 3) |
|---|
| 1231 | #define RT5682_GP2_STA (0x1 << 2) |
|---|
| 1232 | #define RT5682_GP1_STA (0x1 << 1) |
|---|
| 1233 | |
|---|
| 1234 | /* Soft volume and zero cross control 1 (0x00d9) */ |
|---|
| 1235 | #define RT5682_SV_MASK (0x1 << 15) |
|---|
| 1236 | #define RT5682_SV_SFT 15 |
|---|
| 1237 | #define RT5682_SV_DIS (0x0 << 15) |
|---|
| 1238 | #define RT5682_SV_EN (0x1 << 15) |
|---|
| 1239 | #define RT5682_ZCD_MASK (0x1 << 10) |
|---|
| 1240 | #define RT5682_ZCD_SFT 10 |
|---|
| 1241 | #define RT5682_ZCD_PD (0x0 << 10) |
|---|
| 1242 | #define RT5682_ZCD_PU (0x1 << 10) |
|---|
| 1243 | #define RT5682_SV_DLY_MASK (0xf) |
|---|
| 1244 | #define RT5682_SV_DLY_SFT 0 |
|---|
| 1245 | |
|---|
| 1246 | /* Soft volume and zero cross control 2 (0x00da) */ |
|---|
| 1247 | #define RT5682_ZCD_BST1_CBJ_MASK (0x1 << 7) |
|---|
| 1248 | #define RT5682_ZCD_BST1_CBJ_SFT 7 |
|---|
| 1249 | #define RT5682_ZCD_BST1_CBJ_DIS (0x0 << 7) |
|---|
| 1250 | #define RT5682_ZCD_BST1_CBJ_EN (0x1 << 7) |
|---|
| 1251 | #define RT5682_ZCD_RECMIX_MASK (0x1) |
|---|
| 1252 | #define RT5682_ZCD_RECMIX_SFT 0 |
|---|
| 1253 | #define RT5682_ZCD_RECMIX_DIS (0x0) |
|---|
| 1254 | #define RT5682_ZCD_RECMIX_EN (0x1) |
|---|
| 1255 | |
|---|
| 1256 | /* 4 Button Inline Command Control 2 (0x00e3) */ |
|---|
| 1257 | #define RT5682_4BTN_IL_MASK (0x1 << 15) |
|---|
| 1258 | #define RT5682_4BTN_IL_EN (0x1 << 15) |
|---|
| 1259 | #define RT5682_4BTN_IL_DIS (0x0 << 15) |
|---|
| 1260 | #define RT5682_4BTN_IL_RST_MASK (0x1 << 14) |
|---|
| 1261 | #define RT5682_4BTN_IL_NOR (0x1 << 14) |
|---|
| 1262 | #define RT5682_4BTN_IL_RST (0x0 << 14) |
|---|
| 1263 | |
|---|
| 1264 | /* Analog JD Control (0x00f0) */ |
|---|
| 1265 | #define RT5682_JDH_RS_MASK (0x1 << 4) |
|---|
| 1266 | #define RT5682_JDH_NO_PLUG (0x1 << 4) |
|---|
| 1267 | #define RT5682_JDH_PLUG (0x0 << 4) |
|---|
| 1268 | |
|---|
| 1269 | /* Bias current control 8 (0x0111) */ |
|---|
| 1270 | #define RT5682_HPA_CP_BIAS_CTRL_MASK (0x3 << 2) |
|---|
| 1271 | #define RT5682_HPA_CP_BIAS_2UA (0x0 << 2) |
|---|
| 1272 | #define RT5682_HPA_CP_BIAS_3UA (0x1 << 2) |
|---|
| 1273 | #define RT5682_HPA_CP_BIAS_4UA (0x2 << 2) |
|---|
| 1274 | #define RT5682_HPA_CP_BIAS_6UA (0x3 << 2) |
|---|
| 1275 | |
|---|
| 1276 | /* Charge Pump Internal Register1 (0x0125) */ |
|---|
| 1277 | #define RT5682_CP_SW_SIZE_MASK (0x7 << 8) |
|---|
| 1278 | #define RT5682_CP_SW_SIZE_L (0x4 << 8) |
|---|
| 1279 | #define RT5682_CP_SW_SIZE_M (0x2 << 8) |
|---|
| 1280 | #define RT5682_CP_SW_SIZE_S (0x1 << 8) |
|---|
| 1281 | #define RT5682_CP_CLK_HP_MASK (0x3 << 4) |
|---|
| 1282 | #define RT5682_CP_CLK_HP_100KHZ (0x0 << 4) |
|---|
| 1283 | #define RT5682_CP_CLK_HP_200KHZ (0x1 << 4) |
|---|
| 1284 | #define RT5682_CP_CLK_HP_300KHZ (0x2 << 4) |
|---|
| 1285 | #define RT5682_CP_CLK_HP_600KHZ (0x3 << 4) |
|---|
| 1286 | |
|---|
| 1287 | /* Pad Driving Control (0x0136) */ |
|---|
| 1288 | #define RT5682_PAD_DRV_GP1_MASK (0x3 << 14) |
|---|
| 1289 | #define RT5682_PAD_DRV_GP1_SFT 14 |
|---|
| 1290 | #define RT5682_PAD_DRV_GP2_MASK (0x3 << 12) |
|---|
| 1291 | #define RT5682_PAD_DRV_GP2_SFT 12 |
|---|
| 1292 | #define RT5682_PAD_DRV_GP3_MASK (0x3 << 10) |
|---|
| 1293 | #define RT5682_PAD_DRV_GP3_SFT 10 |
|---|
| 1294 | #define RT5682_PAD_DRV_GP4_MASK (0x3 << 8) |
|---|
| 1295 | #define RT5682_PAD_DRV_GP4_SFT 8 |
|---|
| 1296 | #define RT5682_PAD_DRV_GP5_MASK (0x3 << 6) |
|---|
| 1297 | #define RT5682_PAD_DRV_GP5_SFT 6 |
|---|
| 1298 | #define RT5682_PAD_DRV_GP6_MASK (0x3 << 4) |
|---|
| 1299 | #define RT5682_PAD_DRV_GP6_SFT 4 |
|---|
| 1300 | |
|---|
| 1301 | /* Chopper and Clock control for DAC (0x013a)*/ |
|---|
| 1302 | #define RT5682_CKXEN_DAC1_MASK (0x1 << 13) |
|---|
| 1303 | #define RT5682_CKXEN_DAC1_SFT 13 |
|---|
| 1304 | #define RT5682_CKGEN_DAC1_MASK (0x1 << 12) |
|---|
| 1305 | #define RT5682_CKGEN_DAC1_SFT 12 |
|---|
| 1306 | |
|---|
| 1307 | /* Chopper and Clock control for ADC (0x013b)*/ |
|---|
| 1308 | #define RT5682_CKXEN_ADC1_MASK (0x1 << 13) |
|---|
| 1309 | #define RT5682_CKXEN_ADC1_SFT 13 |
|---|
| 1310 | #define RT5682_CKGEN_ADC1_MASK (0x1 << 12) |
|---|
| 1311 | #define RT5682_CKGEN_ADC1_SFT 12 |
|---|
| 1312 | |
|---|
| 1313 | /* Volume test (0x013f)*/ |
|---|
| 1314 | #define RT5682_SEL_CLK_VOL_MASK (0x1 << 15) |
|---|
| 1315 | #define RT5682_SEL_CLK_VOL_EN (0x1 << 15) |
|---|
| 1316 | #define RT5682_SEL_CLK_VOL_DIS (0x0 << 15) |
|---|
| 1317 | |
|---|
| 1318 | /* Test Mode Control 1 (0x0145) */ |
|---|
| 1319 | #define RT5682_AD2DA_LB_MASK (0x1 << 10) |
|---|
| 1320 | #define RT5682_AD2DA_LB_SFT 10 |
|---|
| 1321 | |
|---|
| 1322 | /* Stereo Noise Gate Control 1 (0x0160) */ |
|---|
| 1323 | #define RT5682_NG2_EN_MASK (0x1 << 15) |
|---|
| 1324 | #define RT5682_NG2_EN (0x1 << 15) |
|---|
| 1325 | #define RT5682_NG2_DIS (0x0 << 15) |
|---|
| 1326 | |
|---|
| 1327 | /* Stereo1 DAC Silence Detection Control (0x0190) */ |
|---|
| 1328 | #define RT5682_DEB_STO_DAC_MASK (0x7 << 4) |
|---|
| 1329 | #define RT5682_DEB_80_MS (0x0 << 4) |
|---|
| 1330 | |
|---|
| 1331 | /* HP Behavior Logic Control 2 (0x01db) */ |
|---|
| 1332 | #define RT5682_HP_LC2_SIG_SOUR2_MASK (0x1 << 4) |
|---|
| 1333 | #define RT5682_HP_LC2_SIG_SOUR2_REG (0x1 << 4) |
|---|
| 1334 | #define RT5682_HP_LC2_SIG_SOUR2_DC_CAL (0x0 << 4) |
|---|
| 1335 | #define RT5682_HP_LC2_SIG_SOUR1_MASK (0x7) |
|---|
| 1336 | #define RT5682_HP_LC2_SIG_SOUR1_1BIT (0x7) |
|---|
| 1337 | #define RT5682_HP_LC2_SIG_SOUR1_LEGA (0x2) |
|---|
| 1338 | |
|---|
| 1339 | /* SAR ADC Inline Command Control 1 (0x0210) */ |
|---|
| 1340 | #define RT5682_SAR_BUTT_DET_MASK (0x1 << 15) |
|---|
| 1341 | #define RT5682_SAR_BUTT_DET_EN (0x1 << 15) |
|---|
| 1342 | #define RT5682_SAR_BUTT_DET_DIS (0x0 << 15) |
|---|
| 1343 | #define RT5682_SAR_BUTDET_MODE_MASK (0x1 << 14) |
|---|
| 1344 | #define RT5682_SAR_BUTDET_POW_SAV (0x1 << 14) |
|---|
| 1345 | #define RT5682_SAR_BUTDET_POW_NORM (0x0 << 14) |
|---|
| 1346 | #define RT5682_SAR_BUTDET_RST_MASK (0x1 << 13) |
|---|
| 1347 | #define RT5682_SAR_BUTDET_RST_NORMAL (0x1 << 13) |
|---|
| 1348 | #define RT5682_SAR_BUTDET_RST (0x0 << 13) |
|---|
| 1349 | #define RT5682_SAR_POW_MASK (0x1 << 12) |
|---|
| 1350 | #define RT5682_SAR_POW_EN (0x1 << 12) |
|---|
| 1351 | #define RT5682_SAR_POW_DIS (0x0 << 12) |
|---|
| 1352 | #define RT5682_SAR_RST_MASK (0x1 << 11) |
|---|
| 1353 | #define RT5682_SAR_RST_NORMAL (0x1 << 11) |
|---|
| 1354 | #define RT5682_SAR_RST (0x0 << 11) |
|---|
| 1355 | #define RT5682_SAR_BYPASS_MASK (0x1 << 10) |
|---|
| 1356 | #define RT5682_SAR_BYPASS_EN (0x1 << 10) |
|---|
| 1357 | #define RT5682_SAR_BYPASS_DIS (0x0 << 10) |
|---|
| 1358 | #define RT5682_SAR_SEL_MB1_MASK (0x1 << 9) |
|---|
| 1359 | #define RT5682_SAR_SEL_MB1_SEL (0x1 << 9) |
|---|
| 1360 | #define RT5682_SAR_SEL_MB1_NOSEL (0x0 << 9) |
|---|
| 1361 | #define RT5682_SAR_SEL_MB2_MASK (0x1 << 8) |
|---|
| 1362 | #define RT5682_SAR_SEL_MB2_SEL (0x1 << 8) |
|---|
| 1363 | #define RT5682_SAR_SEL_MB2_NOSEL (0x0 << 8) |
|---|
| 1364 | #define RT5682_SAR_SEL_MODE_MASK (0x1 << 7) |
|---|
| 1365 | #define RT5682_SAR_SEL_MODE_CMP (0x1 << 7) |
|---|
| 1366 | #define RT5682_SAR_SEL_MODE_ADC (0x0 << 7) |
|---|
| 1367 | #define RT5682_SAR_SEL_MB1_MB2_MASK (0x1 << 5) |
|---|
| 1368 | #define RT5682_SAR_SEL_MB1_MB2_AUTO (0x1 << 5) |
|---|
| 1369 | #define RT5682_SAR_SEL_MB1_MB2_MANU (0x0 << 5) |
|---|
| 1370 | #define RT5682_SAR_SEL_SIGNAL_MASK (0x1 << 4) |
|---|
| 1371 | #define RT5682_SAR_SEL_SIGNAL_AUTO (0x1 << 4) |
|---|
| 1372 | #define RT5682_SAR_SEL_SIGNAL_MANU (0x0 << 4) |
|---|
| 1373 | |
|---|
| 1374 | /* SAR ADC Inline Command Control 13 (0x021c) */ |
|---|
| 1375 | #define RT5682_SAR_SOUR_MASK (0x3f) |
|---|
| 1376 | #define RT5682_SAR_SOUR_BTN (0x3f) |
|---|
| 1377 | #define RT5682_SAR_SOUR_TYPE (0x0) |
|---|
| 1378 | |
|---|
| 1379 | /* soundwire timeout */ |
|---|
| 1380 | #define RT5682_PROBE_TIMEOUT 5000 |
|---|
| 1381 | |
|---|
| 1382 | |
|---|
| 1383 | #define RT5682_STEREO_RATES SNDRV_PCM_RATE_8000_192000 |
|---|
| 1384 | #define RT5682_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \ |
|---|
| 1385 | SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S8) |
|---|
| 1386 | |
|---|
| 1387 | /* System Clock Source */ |
|---|
| 1388 | enum { |
|---|
| 1389 | RT5682_SCLK_S_MCLK, |
|---|
| 1390 | RT5682_SCLK_S_PLL1, |
|---|
| 1391 | RT5682_SCLK_S_PLL2, |
|---|
| 1392 | RT5682_SCLK_S_RCCLK, |
|---|
| 1393 | }; |
|---|
| 1394 | |
|---|
| 1395 | /* PLL Source */ |
|---|
| 1396 | enum { |
|---|
| 1397 | RT5682_PLL1_S_MCLK, |
|---|
| 1398 | RT5682_PLL1_S_BCLK1, |
|---|
| 1399 | RT5682_PLL1_S_RCCLK, |
|---|
| 1400 | RT5682_PLL2_S_MCLK, |
|---|
| 1401 | }; |
|---|
| 1402 | |
|---|
| 1403 | enum { |
|---|
| 1404 | RT5682_PLL1, |
|---|
| 1405 | RT5682_PLL2, |
|---|
| 1406 | RT5682_PLLS, |
|---|
| 1407 | }; |
|---|
| 1408 | |
|---|
| 1409 | enum { |
|---|
| 1410 | RT5682_AIF1, |
|---|
| 1411 | RT5682_AIF2, |
|---|
| 1412 | RT5682_SDW, |
|---|
| 1413 | RT5682_AIFS |
|---|
| 1414 | }; |
|---|
| 1415 | |
|---|
| 1416 | /* filter mask */ |
|---|
| 1417 | enum { |
|---|
| 1418 | RT5682_DA_STEREO1_FILTER = 0x1, |
|---|
| 1419 | RT5682_AD_STEREO1_FILTER = (0x1 << 1), |
|---|
| 1420 | }; |
|---|
| 1421 | |
|---|
| 1422 | enum { |
|---|
| 1423 | RT5682_CLK_SEL_SYS, |
|---|
| 1424 | RT5682_CLK_SEL_I2S1_ASRC, |
|---|
| 1425 | RT5682_CLK_SEL_I2S2_ASRC, |
|---|
| 1426 | }; |
|---|
| 1427 | |
|---|
| 1428 | #define RT5682_NUM_SUPPLIES 5 |
|---|
| 1429 | |
|---|
| 1430 | struct rt5682_priv { |
|---|
| 1431 | struct snd_soc_component *component; |
|---|
| 1432 | struct device *i2c_dev; |
|---|
| 1433 | struct rt5682_platform_data pdata; |
|---|
| 1434 | struct gpio_desc *ldo1_en; |
|---|
| 1435 | struct regmap *regmap; |
|---|
| 1436 | struct regmap *sdw_regmap; |
|---|
| 1437 | struct snd_soc_jack *hs_jack; |
|---|
| 1438 | struct regulator_bulk_data supplies[RT5682_NUM_SUPPLIES]; |
|---|
| 1439 | struct delayed_work jack_detect_work; |
|---|
| 1440 | struct delayed_work jd_check_work; |
|---|
| 1441 | struct mutex disable_irq_lock; /* imp-def irq lock protection */ |
|---|
| 1442 | bool disable_irq; |
|---|
| 1443 | struct mutex calibrate_mutex; |
|---|
| 1444 | struct sdw_slave *slave; |
|---|
| 1445 | struct sdw_bus_params params; |
|---|
| 1446 | bool hw_init; |
|---|
| 1447 | bool first_hw_init; |
|---|
| 1448 | bool is_sdw; |
|---|
| 1449 | |
|---|
| 1450 | #ifdef CONFIG_COMMON_CLK |
|---|
| 1451 | struct clk_hw dai_clks_hw[RT5682_DAI_NUM_CLKS]; |
|---|
| 1452 | struct clk *mclk; |
|---|
| 1453 | #endif |
|---|
| 1454 | |
|---|
| 1455 | int sysclk; |
|---|
| 1456 | int sysclk_src; |
|---|
| 1457 | int lrck[RT5682_AIFS]; |
|---|
| 1458 | int bclk[RT5682_AIFS]; |
|---|
| 1459 | int master[RT5682_AIFS]; |
|---|
| 1460 | |
|---|
| 1461 | int pll_src[RT5682_PLLS]; |
|---|
| 1462 | int pll_in[RT5682_PLLS]; |
|---|
| 1463 | int pll_out[RT5682_PLLS]; |
|---|
| 1464 | |
|---|
| 1465 | int jack_type; |
|---|
| 1466 | int irq; |
|---|
| 1467 | int irq_work_delay_time; |
|---|
| 1468 | }; |
|---|
| 1469 | |
|---|
| 1470 | extern const char *rt5682_supply_names[RT5682_NUM_SUPPLIES]; |
|---|
| 1471 | |
|---|
| 1472 | int rt5682_sel_asrc_clk_src(struct snd_soc_component *component, |
|---|
| 1473 | unsigned int filter_mask, unsigned int clk_src); |
|---|
| 1474 | |
|---|
| 1475 | void rt5682_apply_patch_list(struct rt5682_priv *rt5682, struct device *dev); |
|---|
| 1476 | |
|---|
| 1477 | void rt5682_jack_detect_handler(struct work_struct *work); |
|---|
| 1478 | |
|---|
| 1479 | bool rt5682_volatile_register(struct device *dev, unsigned int reg); |
|---|
| 1480 | bool rt5682_readable_register(struct device *dev, unsigned int reg); |
|---|
| 1481 | |
|---|
| 1482 | int rt5682_register_component(struct device *dev); |
|---|
| 1483 | void rt5682_calibrate(struct rt5682_priv *rt5682); |
|---|
| 1484 | void rt5682_reset(struct rt5682_priv *rt5682); |
|---|
| 1485 | int rt5682_parse_dt(struct rt5682_priv *rt5682, struct device *dev); |
|---|
| 1486 | int rt5682_get_ldo1(struct rt5682_priv *rt5682, struct device *dev); |
|---|
| 1487 | |
|---|
| 1488 | int rt5682_register_dai_clks(struct rt5682_priv *rt5682); |
|---|
| 1489 | |
|---|
| 1490 | #define RT5682_REG_NUM 318 |
|---|
| 1491 | extern const struct reg_default rt5682_reg[RT5682_REG_NUM]; |
|---|
| 1492 | |
|---|
| 1493 | extern const struct snd_soc_dai_ops rt5682_aif1_dai_ops; |
|---|
| 1494 | extern const struct snd_soc_dai_ops rt5682_aif2_dai_ops; |
|---|
| 1495 | extern const struct snd_soc_component_driver rt5682_soc_component_dev; |
|---|
| 1496 | |
|---|
| 1497 | #endif /* __RT5682_H__ */ |
|---|
| 1498 | |
|---|
