1 | // SPDX-License-Identifier: GPL-2.0-only |
2 | // |
3 | // Based on sound/soc/codecs/tlv320aic3x.c by Vladimir Barinov |
4 | // |
5 | // Copyright (C) 2010 Mistral Solutions Pvt Ltd. |
6 | // Author: Shahina Shaik <shahina.s@mistralsolutions.com> |
7 | // |
8 | // Copyright (C) 2014-2018, Ambarella, Inc. |
9 | // Author: Dongge wu <dgwu@ambarella.com> |
10 | // |
11 | // Copyright (C) 2021 Axis Communications AB |
12 | // Author: Ricard Wanderlof <ricardw@axis.com> |
13 | // |
14 | |
15 | #include <dt-bindings/sound/tlv320adc3xxx.h> |
16 | #include <linux/clk.h> |
17 | #include <linux/gpio/consumer.h> |
18 | #include <linux/module.h> |
19 | #include <linux/moduleparam.h> |
20 | #include <linux/io.h> |
21 | #include <linux/init.h> |
22 | #include <linux/delay.h> |
23 | #include <linux/gpio/driver.h> |
24 | #include <linux/pm.h> |
25 | #include <linux/i2c.h> |
26 | #include <linux/platform_device.h> |
27 | #include <linux/cdev.h> |
28 | #include <linux/of_gpio.h> |
29 | #include <linux/slab.h> |
30 | #include <sound/core.h> |
31 | #include <sound/pcm.h> |
32 | #include <sound/pcm_params.h> |
33 | #include <sound/soc.h> |
34 | #include <sound/soc-dapm.h> |
35 | #include <sound/tlv.h> |
36 | #include <sound/initval.h> |
37 | |
38 | /* |
39 | * General definitions defining exported functionality. |
40 | */ |
41 | |
42 | #define ADC3XXX_MICBIAS_PINS 2 |
43 | |
44 | /* Number of GPIO pins exposed via the gpiolib interface */ |
45 | #define ADC3XXX_GPIOS_MAX 2 |
46 | |
47 | #define ADC3XXX_RATES SNDRV_PCM_RATE_8000_96000 |
48 | #define ADC3XXX_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | \ |
49 | SNDRV_PCM_FMTBIT_S20_3LE | \ |
50 | SNDRV_PCM_FMTBIT_S24_3LE | \ |
51 | SNDRV_PCM_FMTBIT_S32_LE) |
52 | |
53 | /* |
54 | * PLL modes, to be used for clk_id for set_sysclk callback. |
55 | * |
56 | * The default behavior (AUTO) is to take the first matching entry in the clock |
57 | * table, which is intended to be the PLL based one if there is more than one. |
58 | * |
59 | * Setting the clock source using simple-card (clocks or |
60 | * system-clock-frequency property) sets clk_id = 0 = ADC3XXX_PLL_AUTO. |
61 | */ |
62 | #define ADC3XXX_PLL_AUTO 0 /* Use first available mode */ |
63 | #define ADC3XXX_PLL_ENABLE 1 /* Use PLL for clock generation */ |
64 | #define ADC3XXX_PLL_BYPASS 2 /* Don't use PLL for clock generation */ |
65 | |
66 | /* Register definitions. */ |
67 | |
68 | #define ADC3XXX_PAGE_SIZE 128 |
69 | #define ADC3XXX_REG(page, reg) ((page * ADC3XXX_PAGE_SIZE) + reg) |
70 | |
71 | /* |
72 | * Page 0 registers. |
73 | */ |
74 | |
75 | #define ADC3XXX_PAGE_SELECT ADC3XXX_REG(0, 0) |
76 | #define ADC3XXX_RESET ADC3XXX_REG(0, 1) |
77 | |
78 | /* 2-3 Reserved */ |
79 | |
80 | #define ADC3XXX_CLKGEN_MUX ADC3XXX_REG(0, 4) |
81 | #define ADC3XXX_PLL_PROG_PR ADC3XXX_REG(0, 5) |
82 | #define ADC3XXX_PLL_PROG_J ADC3XXX_REG(0, 6) |
83 | #define ADC3XXX_PLL_PROG_D_MSB ADC3XXX_REG(0, 7) |
84 | #define ADC3XXX_PLL_PROG_D_LSB ADC3XXX_REG(0, 8) |
85 | |
86 | /* 9-17 Reserved */ |
87 | |
88 | #define ADC3XXX_ADC_NADC ADC3XXX_REG(0, 18) |
89 | #define ADC3XXX_ADC_MADC ADC3XXX_REG(0, 19) |
90 | #define ADC3XXX_ADC_AOSR ADC3XXX_REG(0, 20) |
91 | #define ADC3XXX_ADC_IADC ADC3XXX_REG(0, 21) |
92 | |
93 | /* 23-24 Reserved */ |
94 | |
95 | #define ADC3XXX_CLKOUT_MUX ADC3XXX_REG(0, 25) |
96 | #define ADC3XXX_CLKOUT_M_DIV ADC3XXX_REG(0, 26) |
97 | #define ADC3XXX_INTERFACE_CTRL_1 ADC3XXX_REG(0, 27) |
98 | #define ADC3XXX_CH_OFFSET_1 ADC3XXX_REG(0, 28) |
99 | #define ADC3XXX_INTERFACE_CTRL_2 ADC3XXX_REG(0, 29) |
100 | #define ADC3XXX_BCLK_N_DIV ADC3XXX_REG(0, 30) |
101 | #define ADC3XXX_INTERFACE_CTRL_3 ADC3XXX_REG(0, 31) |
102 | #define ADC3XXX_INTERFACE_CTRL_4 ADC3XXX_REG(0, 32) |
103 | #define ADC3XXX_INTERFACE_CTRL_5 ADC3XXX_REG(0, 33) |
104 | #define ADC3XXX_I2S_SYNC ADC3XXX_REG(0, 34) |
105 | /* 35 Reserved */ |
106 | #define ADC3XXX_ADC_FLAG ADC3XXX_REG(0, 36) |
107 | #define ADC3XXX_CH_OFFSET_2 ADC3XXX_REG(0, 37) |
108 | #define ADC3XXX_I2S_TDM_CTRL ADC3XXX_REG(0, 38) |
109 | /* 39-41 Reserved */ |
110 | #define ADC3XXX_INTR_FLAG_1 ADC3XXX_REG(0, 42) |
111 | #define ADC3XXX_INTR_FLAG_2 ADC3XXX_REG(0, 43) |
112 | /* 44 Reserved */ |
113 | #define ADC3XXX_INTR_FLAG_ADC1 ADC3XXX_REG(0, 45) |
114 | /* 46 Reserved */ |
115 | #define ADC3XXX_INTR_FLAG_ADC2 ADC3XXX_REG(0, 47) |
116 | #define ADC3XXX_INT1_CTRL ADC3XXX_REG(0, 48) |
117 | #define ADC3XXX_INT2_CTRL ADC3XXX_REG(0, 49) |
118 | /* 50 Reserved */ |
119 | #define ADC3XXX_GPIO2_CTRL ADC3XXX_REG(0, 51) |
120 | #define ADC3XXX_GPIO1_CTRL ADC3XXX_REG(0, 52) |
121 | #define ADC3XXX_DOUT_CTRL ADC3XXX_REG(0, 53) |
122 | /* 54-56 Reserved */ |
123 | #define ADC3XXX_SYNC_CTRL_1 ADC3XXX_REG(0, 57) |
124 | #define ADC3XXX_SYNC_CTRL_2 ADC3XXX_REG(0, 58) |
125 | #define ADC3XXX_CIC_GAIN_CTRL ADC3XXX_REG(0, 59) |
126 | /* 60 Reserved */ |
127 | #define ADC3XXX_PRB_SELECT ADC3XXX_REG(0, 61) |
128 | #define ADC3XXX_INST_MODE_CTRL ADC3XXX_REG(0, 62) |
129 | /* 63-79 Reserved */ |
130 | #define ADC3XXX_MIC_POLARITY_CTRL ADC3XXX_REG(0, 80) |
131 | #define ADC3XXX_ADC_DIGITAL ADC3XXX_REG(0, 81) |
132 | #define ADC3XXX_ADC_FGA ADC3XXX_REG(0, 82) |
133 | #define ADC3XXX_LADC_VOL ADC3XXX_REG(0, 83) |
134 | #define ADC3XXX_RADC_VOL ADC3XXX_REG(0, 84) |
135 | #define ADC3XXX_ADC_PHASE_COMP ADC3XXX_REG(0, 85) |
136 | #define ADC3XXX_LEFT_CHN_AGC_1 ADC3XXX_REG(0, 86) |
137 | #define ADC3XXX_LEFT_CHN_AGC_2 ADC3XXX_REG(0, 87) |
138 | #define ADC3XXX_LEFT_CHN_AGC_3 ADC3XXX_REG(0, 88) |
139 | #define ADC3XXX_LEFT_CHN_AGC_4 ADC3XXX_REG(0, 89) |
140 | #define ADC3XXX_LEFT_CHN_AGC_5 ADC3XXX_REG(0, 90) |
141 | #define ADC3XXX_LEFT_CHN_AGC_6 ADC3XXX_REG(0, 91) |
142 | #define ADC3XXX_LEFT_CHN_AGC_7 ADC3XXX_REG(0, 92) |
143 | #define ADC3XXX_LEFT_AGC_GAIN ADC3XXX_REG(0, 93) |
144 | #define ADC3XXX_RIGHT_CHN_AGC_1 ADC3XXX_REG(0, 94) |
145 | #define ADC3XXX_RIGHT_CHN_AGC_2 ADC3XXX_REG(0, 95) |
146 | #define ADC3XXX_RIGHT_CHN_AGC_3 ADC3XXX_REG(0, 96) |
147 | #define ADC3XXX_RIGHT_CHN_AGC_4 ADC3XXX_REG(0, 97) |
148 | #define ADC3XXX_RIGHT_CHN_AGC_5 ADC3XXX_REG(0, 98) |
149 | #define ADC3XXX_RIGHT_CHN_AGC_6 ADC3XXX_REG(0, 99) |
150 | #define ADC3XXX_RIGHT_CHN_AGC_7 ADC3XXX_REG(0, 100) |
151 | #define ADC3XXX_RIGHT_AGC_GAIN ADC3XXX_REG(0, 101) |
152 | /* 102-127 Reserved */ |
153 | |
154 | /* |
155 | * Page 1 registers. |
156 | */ |
157 | |
158 | /* 1-25 Reserved */ |
159 | #define ADC3XXX_DITHER_CTRL ADC3XXX_REG(1, 26) |
160 | /* 27-50 Reserved */ |
161 | #define ADC3XXX_MICBIAS_CTRL ADC3XXX_REG(1, 51) |
162 | #define ADC3XXX_LEFT_PGA_SEL_1 ADC3XXX_REG(1, 52) |
163 | /* 53 Reserved */ |
164 | #define ADC3XXX_LEFT_PGA_SEL_2 ADC3XXX_REG(1, 54) |
165 | #define ADC3XXX_RIGHT_PGA_SEL_1 ADC3XXX_REG(1, 55) |
166 | #define ADC3XXX_RIGHT_PGA_SEL_2 ADC3XXX_REG(1, 57) |
167 | #define ADC3XXX_LEFT_APGA_CTRL ADC3XXX_REG(1, 59) |
168 | #define ADC3XXX_RIGHT_APGA_CTRL ADC3XXX_REG(1, 60) |
169 | #define ADC3XXX_LOW_CURRENT_MODES ADC3XXX_REG(1, 61) |
170 | #define ADC3XXX_ANALOG_PGA_FLAGS ADC3XXX_REG(1, 62) |
171 | /* 63-127 Reserved */ |
172 | |
173 | /* |
174 | * Page 4 registers. First page of coefficient memory for the miniDSP. |
175 | */ |
176 | #define ADC3XXX_LEFT_ADC_IIR_COEFF_N0_MSB ADC3XXX_REG(4, 8) |
177 | #define ADC3XXX_LEFT_ADC_IIR_COEFF_N0_LSB ADC3XXX_REG(4, 9) |
178 | #define ADC3XXX_LEFT_ADC_IIR_COEFF_N1_MSB ADC3XXX_REG(4, 10) |
179 | #define ADC3XXX_LEFT_ADC_IIR_COEFF_N1_LSB ADC3XXX_REG(4, 11) |
180 | #define ADC3XXX_LEFT_ADC_IIR_COEFF_D1_MSB ADC3XXX_REG(4, 12) |
181 | #define ADC3XXX_LEFT_ADC_IIR_COEFF_D1_LSB ADC3XXX_REG(4, 13) |
182 | |
183 | #define ADC3XXX_RIGHT_ADC_IIR_COEFF_N0_MSB ADC3XXX_REG(4, 72) |
184 | #define ADC3XXX_RIGHT_ADC_IIR_COEFF_N0_LSB ADC3XXX_REG(4, 73) |
185 | #define ADC3XXX_RIGHT_ADC_IIR_COEFF_N1_MSB ADC3XXX_REG(4, 74) |
186 | #define ADC3XXX_RIGHT_ADC_IIR_COEFF_N1_LSB ADC3XXX_REG(4, 75) |
187 | #define ADC3XXX_RIGHT_ADC_IIR_COEFF_D1_MSB ADC3XXX_REG(4, 76) |
188 | #define ADC3XXX_RIGHT_ADC_IIR_COEFF_D1_LSB ADC3XXX_REG(4, 77) |
189 | |
190 | /* |
191 | * Register bits. |
192 | */ |
193 | |
194 | /* PLL Enable bits */ |
195 | #define ADC3XXX_ENABLE_PLL_SHIFT 7 |
196 | #define ADC3XXX_ENABLE_PLL (1 << ADC3XXX_ENABLE_PLL_SHIFT) |
197 | #define ADC3XXX_ENABLE_NADC_SHIFT 7 |
198 | #define ADC3XXX_ENABLE_NADC (1 << ADC3XXX_ENABLE_NADC_SHIFT) |
199 | #define ADC3XXX_ENABLE_MADC_SHIFT 7 |
200 | #define ADC3XXX_ENABLE_MADC (1 << ADC3XXX_ENABLE_MADC_SHIFT) |
201 | #define ADC3XXX_ENABLE_BCLK_SHIFT 7 |
202 | #define ADC3XXX_ENABLE_BCLK (1 << ADC3XXX_ENABLE_BCLK_SHIFT) |
203 | |
204 | /* Power bits */ |
205 | #define ADC3XXX_LADC_PWR_ON 0x80 |
206 | #define ADC3XXX_RADC_PWR_ON 0x40 |
207 | |
208 | #define ADC3XXX_SOFT_RESET 0x01 |
209 | #define ADC3XXX_BCLK_MASTER 0x08 |
210 | #define ADC3XXX_WCLK_MASTER 0x04 |
211 | |
212 | /* Interface register masks */ |
213 | #define ADC3XXX_FORMAT_MASK 0xc0 |
214 | #define ADC3XXX_FORMAT_SHIFT 6 |
215 | #define ADC3XXX_WLENGTH_MASK 0x30 |
216 | #define ADC3XXX_WLENGTH_SHIFT 4 |
217 | #define ADC3XXX_CLKDIR_MASK 0x0c |
218 | #define ADC3XXX_CLKDIR_SHIFT 2 |
219 | |
220 | /* Interface register bit patterns */ |
221 | #define ADC3XXX_FORMAT_I2S (0 << ADC3XXX_FORMAT_SHIFT) |
222 | #define ADC3XXX_FORMAT_DSP (1 << ADC3XXX_FORMAT_SHIFT) |
223 | #define ADC3XXX_FORMAT_RJF (2 << ADC3XXX_FORMAT_SHIFT) |
224 | #define ADC3XXX_FORMAT_LJF (3 << ADC3XXX_FORMAT_SHIFT) |
225 | |
226 | #define ADC3XXX_IFACE_16BITS (0 << ADC3XXX_WLENGTH_SHIFT) |
227 | #define ADC3XXX_IFACE_20BITS (1 << ADC3XXX_WLENGTH_SHIFT) |
228 | #define ADC3XXX_IFACE_24BITS (2 << ADC3XXX_WLENGTH_SHIFT) |
229 | #define ADC3XXX_IFACE_32BITS (3 << ADC3XXX_WLENGTH_SHIFT) |
230 | |
231 | /* PLL P/R bit offsets */ |
232 | #define ADC3XXX_PLLP_SHIFT 4 |
233 | #define ADC3XXX_PLLR_SHIFT 0 |
234 | #define ADC3XXX_PLL_PR_MASK 0x7f |
235 | #define ADC3XXX_PLLJ_MASK 0x3f |
236 | #define ADC3XXX_PLLD_MSB_MASK 0x3f |
237 | #define ADC3XXX_PLLD_LSB_MASK 0xff |
238 | #define ADC3XXX_NADC_MASK 0x7f |
239 | #define ADC3XXX_MADC_MASK 0x7f |
240 | #define ADC3XXX_AOSR_MASK 0xff |
241 | #define ADC3XXX_IADC_MASK 0xff |
242 | #define ADC3XXX_BDIV_MASK 0x7f |
243 | |
244 | /* PLL_CLKIN bits */ |
245 | #define ADC3XXX_PLL_CLKIN_SHIFT 2 |
246 | #define ADC3XXX_PLL_CLKIN_MCLK 0x0 |
247 | #define ADC3XXX_PLL_CLKIN_BCLK 0x1 |
248 | #define ADC3XXX_PLL_CLKIN_ZERO 0x3 |
249 | |
250 | /* CODEC_CLKIN bits */ |
251 | #define ADC3XXX_CODEC_CLKIN_SHIFT 0 |
252 | #define ADC3XXX_CODEC_CLKIN_MCLK 0x0 |
253 | #define ADC3XXX_CODEC_CLKIN_BCLK 0x1 |
254 | #define ADC3XXX_CODEC_CLKIN_PLL_CLK 0x3 |
255 | |
256 | #define ADC3XXX_USE_PLL ((ADC3XXX_PLL_CLKIN_MCLK << ADC3XXX_PLL_CLKIN_SHIFT) | \ |
257 | (ADC3XXX_CODEC_CLKIN_PLL_CLK << ADC3XXX_CODEC_CLKIN_SHIFT)) |
258 | #define ADC3XXX_NO_PLL ((ADC3XXX_PLL_CLKIN_ZERO << ADC3XXX_PLL_CLKIN_SHIFT) | \ |
259 | (ADC3XXX_CODEC_CLKIN_MCLK << ADC3XXX_CODEC_CLKIN_SHIFT)) |
260 | |
261 | /* Analog PGA control bits */ |
262 | #define ADC3XXX_LPGA_MUTE 0x80 |
263 | #define ADC3XXX_RPGA_MUTE 0x80 |
264 | |
265 | #define ADC3XXX_LPGA_GAIN_MASK 0x7f |
266 | #define ADC3XXX_RPGA_GAIN_MASK 0x7f |
267 | |
268 | /* ADC current modes */ |
269 | #define ADC3XXX_ADC_LOW_CURR_MODE 0x01 |
270 | |
271 | /* Left ADC Input selection bits */ |
272 | #define ADC3XXX_LCH_SEL1_SHIFT 0 |
273 | #define ADC3XXX_LCH_SEL2_SHIFT 2 |
274 | #define ADC3XXX_LCH_SEL3_SHIFT 4 |
275 | #define ADC3XXX_LCH_SEL4_SHIFT 6 |
276 | |
277 | #define ADC3XXX_LCH_SEL1X_SHIFT 0 |
278 | #define ADC3XXX_LCH_SEL2X_SHIFT 2 |
279 | #define ADC3XXX_LCH_SEL3X_SHIFT 4 |
280 | #define ADC3XXX_LCH_COMMON_MODE 0x40 |
281 | #define ADC3XXX_BYPASS_LPGA 0x80 |
282 | |
283 | /* Right ADC Input selection bits */ |
284 | #define ADC3XXX_RCH_SEL1_SHIFT 0 |
285 | #define ADC3XXX_RCH_SEL2_SHIFT 2 |
286 | #define ADC3XXX_RCH_SEL3_SHIFT 4 |
287 | #define ADC3XXX_RCH_SEL4_SHIFT 6 |
288 | |
289 | #define ADC3XXX_RCH_SEL1X_SHIFT 0 |
290 | #define ADC3XXX_RCH_SEL2X_SHIFT 2 |
291 | #define ADC3XXX_RCH_SEL3X_SHIFT 4 |
292 | #define ADC3XXX_RCH_COMMON_MODE 0x40 |
293 | #define ADC3XXX_BYPASS_RPGA 0x80 |
294 | |
295 | /* MICBIAS control bits */ |
296 | #define ADC3XXX_MICBIAS_MASK 0x3 |
297 | #define ADC3XXX_MICBIAS1_SHIFT 5 |
298 | #define ADC3XXX_MICBIAS2_SHIFT 3 |
299 | |
300 | #define ADC3XXX_ADC_MAX_VOLUME 64 |
301 | #define ADC3XXX_ADC_POS_VOL 24 |
302 | |
303 | /* GPIO control bits (GPIO1_CTRL and GPIO2_CTRL) */ |
304 | #define ADC3XXX_GPIO_CTRL_CFG_MASK 0x3c |
305 | #define ADC3XXX_GPIO_CTRL_CFG_SHIFT 2 |
306 | #define ADC3XXX_GPIO_CTRL_OUTPUT_CTRL_MASK 0x01 |
307 | #define ADC3XXX_GPIO_CTRL_OUTPUT_CTRL_SHIFT 0 |
308 | #define ADC3XXX_GPIO_CTRL_INPUT_VALUE_MASK 0x02 |
309 | #define ADC3XXX_GPIO_CTRL_INPUT_VALUE_SHIFT 1 |
310 | |
311 | enum adc3xxx_type { |
312 | ADC3001 = 0, |
313 | ADC3101 |
314 | }; |
315 | |
316 | struct adc3xxx { |
317 | struct device *dev; |
318 | enum adc3xxx_type type; |
319 | struct clk *mclk; |
320 | struct regmap *regmap; |
321 | struct gpio_desc *rst_pin; |
322 | unsigned int pll_mode; |
323 | unsigned int sysclk; |
324 | unsigned int gpio_cfg[ADC3XXX_GPIOS_MAX]; /* value+1 (0 => not set) */ |
325 | unsigned int micbias_vg[ADC3XXX_MICBIAS_PINS]; |
326 | int master; |
327 | u8 page_no; |
328 | int use_pll; |
329 | struct gpio_chip gpio_chip; |
330 | }; |
331 | |
332 | static const unsigned int adc3xxx_gpio_ctrl_reg[ADC3XXX_GPIOS_MAX] = { |
333 | ADC3XXX_GPIO1_CTRL, |
334 | ADC3XXX_GPIO2_CTRL |
335 | }; |
336 | |
337 | static const unsigned int adc3xxx_micbias_shift[ADC3XXX_MICBIAS_PINS] = { |
338 | ADC3XXX_MICBIAS1_SHIFT, |
339 | ADC3XXX_MICBIAS2_SHIFT |
340 | }; |
341 | |
342 | static const struct reg_default adc3xxx_defaults[] = { |
343 | /* Page 0 */ |
344 | { 0, 0x00 }, { 1, 0x00 }, { 2, 0x00 }, { 3, 0x00 }, |
345 | { 4, 0x00 }, { 5, 0x11 }, { 6, 0x04 }, { 7, 0x00 }, |
346 | { 8, 0x00 }, { 9, 0x00 }, { 10, 0x00 }, { 11, 0x00 }, |
347 | { 12, 0x00 }, { 13, 0x00 }, { 14, 0x00 }, { 15, 0x00 }, |
348 | { 16, 0x00 }, { 17, 0x00 }, { 18, 0x01 }, { 19, 0x01 }, |
349 | { 20, 0x80 }, { 21, 0x80 }, { 22, 0x04 }, { 23, 0x00 }, |
350 | { 24, 0x00 }, { 25, 0x00 }, { 26, 0x01 }, { 27, 0x00 }, |
351 | { 28, 0x00 }, { 29, 0x02 }, { 30, 0x01 }, { 31, 0x00 }, |
352 | { 32, 0x00 }, { 33, 0x10 }, { 34, 0x00 }, { 35, 0x00 }, |
353 | { 36, 0x00 }, { 37, 0x00 }, { 38, 0x02 }, { 39, 0x00 }, |
354 | { 40, 0x00 }, { 41, 0x00 }, { 42, 0x00 }, { 43, 0x00 }, |
355 | { 44, 0x00 }, { 45, 0x00 }, { 46, 0x00 }, { 47, 0x00 }, |
356 | { 48, 0x00 }, { 49, 0x00 }, { 50, 0x00 }, { 51, 0x00 }, |
357 | { 52, 0x00 }, { 53, 0x12 }, { 54, 0x00 }, { 55, 0x00 }, |
358 | { 56, 0x00 }, { 57, 0x00 }, { 58, 0x00 }, { 59, 0x44 }, |
359 | { 60, 0x00 }, { 61, 0x01 }, { 62, 0x00 }, { 63, 0x00 }, |
360 | { 64, 0x00 }, { 65, 0x00 }, { 66, 0x00 }, { 67, 0x00 }, |
361 | { 68, 0x00 }, { 69, 0x00 }, { 70, 0x00 }, { 71, 0x00 }, |
362 | { 72, 0x00 }, { 73, 0x00 }, { 74, 0x00 }, { 75, 0x00 }, |
363 | { 76, 0x00 }, { 77, 0x00 }, { 78, 0x00 }, { 79, 0x00 }, |
364 | { 80, 0x00 }, { 81, 0x00 }, { 82, 0x88 }, { 83, 0x00 }, |
365 | { 84, 0x00 }, { 85, 0x00 }, { 86, 0x00 }, { 87, 0x00 }, |
366 | { 88, 0x7f }, { 89, 0x00 }, { 90, 0x00 }, { 91, 0x00 }, |
367 | { 92, 0x00 }, { 93, 0x00 }, { 94, 0x00 }, { 95, 0x00 }, |
368 | { 96, 0x7f }, { 97, 0x00 }, { 98, 0x00 }, { 99, 0x00 }, |
369 | { 100, 0x00 }, { 101, 0x00 }, { 102, 0x00 }, { 103, 0x00 }, |
370 | { 104, 0x00 }, { 105, 0x00 }, { 106, 0x00 }, { 107, 0x00 }, |
371 | { 108, 0x00 }, { 109, 0x00 }, { 110, 0x00 }, { 111, 0x00 }, |
372 | { 112, 0x00 }, { 113, 0x00 }, { 114, 0x00 }, { 115, 0x00 }, |
373 | { 116, 0x00 }, { 117, 0x00 }, { 118, 0x00 }, { 119, 0x00 }, |
374 | { 120, 0x00 }, { 121, 0x00 }, { 122, 0x00 }, { 123, 0x00 }, |
375 | { 124, 0x00 }, { 125, 0x00 }, { 126, 0x00 }, { 127, 0x00 }, |
376 | |
377 | /* Page 1 */ |
378 | { 128, 0x00 }, { 129, 0x00 }, { 130, 0x00 }, { 131, 0x00 }, |
379 | { 132, 0x00 }, { 133, 0x00 }, { 134, 0x00 }, { 135, 0x00 }, |
380 | { 136, 0x00 }, { 137, 0x00 }, { 138, 0x00 }, { 139, 0x00 }, |
381 | { 140, 0x00 }, { 141, 0x00 }, { 142, 0x00 }, { 143, 0x00 }, |
382 | { 144, 0x00 }, { 145, 0x00 }, { 146, 0x00 }, { 147, 0x00 }, |
383 | { 148, 0x00 }, { 149, 0x00 }, { 150, 0x00 }, { 151, 0x00 }, |
384 | { 152, 0x00 }, { 153, 0x00 }, { 154, 0x00 }, { 155, 0x00 }, |
385 | { 156, 0x00 }, { 157, 0x00 }, { 158, 0x00 }, { 159, 0x00 }, |
386 | { 160, 0x00 }, { 161, 0x00 }, { 162, 0x00 }, { 163, 0x00 }, |
387 | { 164, 0x00 }, { 165, 0x00 }, { 166, 0x00 }, { 167, 0x00 }, |
388 | { 168, 0x00 }, { 169, 0x00 }, { 170, 0x00 }, { 171, 0x00 }, |
389 | { 172, 0x00 }, { 173, 0x00 }, { 174, 0x00 }, { 175, 0x00 }, |
390 | { 176, 0x00 }, { 177, 0x00 }, { 178, 0x00 }, { 179, 0x00 }, |
391 | { 180, 0xff }, { 181, 0x00 }, { 182, 0x3f }, { 183, 0xff }, |
392 | { 184, 0x00 }, { 185, 0x3f }, { 186, 0x00 }, { 187, 0x80 }, |
393 | { 188, 0x80 }, { 189, 0x00 }, { 190, 0x00 }, { 191, 0x00 }, |
394 | |
395 | /* Page 4 */ |
396 | { 1024, 0x00 }, { 1026, 0x01 }, { 1027, 0x17 }, |
397 | { 1028, 0x01 }, { 1029, 0x17 }, { 1030, 0x7d }, { 1031, 0xd3 }, |
398 | { 1032, 0x7f }, { 1033, 0xff }, { 1034, 0x00 }, { 1035, 0x00 }, |
399 | { 1036, 0x00 }, { 1037, 0x00 }, { 1038, 0x7f }, { 1039, 0xff }, |
400 | { 1040, 0x00 }, { 1041, 0x00 }, { 1042, 0x00 }, { 1043, 0x00 }, |
401 | { 1044, 0x00 }, { 1045, 0x00 }, { 1046, 0x00 }, { 1047, 0x00 }, |
402 | { 1048, 0x7f }, { 1049, 0xff }, { 1050, 0x00 }, { 1051, 0x00 }, |
403 | { 1052, 0x00 }, { 1053, 0x00 }, { 1054, 0x00 }, { 1055, 0x00 }, |
404 | { 1056, 0x00 }, { 1057, 0x00 }, { 1058, 0x7f }, { 1059, 0xff }, |
405 | { 1060, 0x00 }, { 1061, 0x00 }, { 1062, 0x00 }, { 1063, 0x00 }, |
406 | { 1064, 0x00 }, { 1065, 0x00 }, { 1066, 0x00 }, { 1067, 0x00 }, |
407 | { 1068, 0x7f }, { 1069, 0xff }, { 1070, 0x00 }, { 1071, 0x00 }, |
408 | { 1072, 0x00 }, { 1073, 0x00 }, { 1074, 0x00 }, { 1075, 0x00 }, |
409 | { 1076, 0x00 }, { 1077, 0x00 }, { 1078, 0x7f }, { 1079, 0xff }, |
410 | { 1080, 0x00 }, { 1081, 0x00 }, { 1082, 0x00 }, { 1083, 0x00 }, |
411 | { 1084, 0x00 }, { 1085, 0x00 }, { 1086, 0x00 }, { 1087, 0x00 }, |
412 | { 1088, 0x00 }, { 1089, 0x00 }, { 1090, 0x00 }, { 1091, 0x00 }, |
413 | { 1092, 0x00 }, { 1093, 0x00 }, { 1094, 0x00 }, { 1095, 0x00 }, |
414 | { 1096, 0x00 }, { 1097, 0x00 }, { 1098, 0x00 }, { 1099, 0x00 }, |
415 | { 1100, 0x00 }, { 1101, 0x00 }, { 1102, 0x00 }, { 1103, 0x00 }, |
416 | { 1104, 0x00 }, { 1105, 0x00 }, { 1106, 0x00 }, { 1107, 0x00 }, |
417 | { 1108, 0x00 }, { 1109, 0x00 }, { 1110, 0x00 }, { 1111, 0x00 }, |
418 | { 1112, 0x00 }, { 1113, 0x00 }, { 1114, 0x00 }, { 1115, 0x00 }, |
419 | { 1116, 0x00 }, { 1117, 0x00 }, { 1118, 0x00 }, { 1119, 0x00 }, |
420 | { 1120, 0x00 }, { 1121, 0x00 }, { 1122, 0x00 }, { 1123, 0x00 }, |
421 | { 1124, 0x00 }, { 1125, 0x00 }, { 1126, 0x00 }, { 1127, 0x00 }, |
422 | { 1128, 0x00 }, { 1129, 0x00 }, { 1130, 0x00 }, { 1131, 0x00 }, |
423 | { 1132, 0x00 }, { 1133, 0x00 }, { 1134, 0x00 }, { 1135, 0x00 }, |
424 | { 1136, 0x00 }, { 1137, 0x00 }, { 1138, 0x00 }, { 1139, 0x00 }, |
425 | { 1140, 0x00 }, { 1141, 0x00 }, { 1142, 0x00 }, { 1143, 0x00 }, |
426 | { 1144, 0x00 }, { 1145, 0x00 }, { 1146, 0x00 }, { 1147, 0x00 }, |
427 | { 1148, 0x00 }, { 1149, 0x00 }, { 1150, 0x00 }, { 1151, 0x00 }, |
428 | }; |
429 | |
430 | static bool adc3xxx_volatile_reg(struct device *dev, unsigned int reg) |
431 | { |
432 | switch (reg) { |
433 | case ADC3XXX_RESET: |
434 | return true; |
435 | default: |
436 | return false; |
437 | } |
438 | } |
439 | |
440 | static const struct regmap_range_cfg adc3xxx_ranges[] = { |
441 | { |
442 | .range_min = 0, |
443 | .range_max = 5 * ADC3XXX_PAGE_SIZE, |
444 | .selector_reg = ADC3XXX_PAGE_SELECT, |
445 | .selector_mask = 0xff, |
446 | .selector_shift = 0, |
447 | .window_start = 0, |
448 | .window_len = ADC3XXX_PAGE_SIZE, |
449 | } |
450 | }; |
451 | |
452 | static const struct regmap_config adc3xxx_regmap = { |
453 | .reg_bits = 8, |
454 | .val_bits = 8, |
455 | |
456 | .reg_defaults = adc3xxx_defaults, |
457 | .num_reg_defaults = ARRAY_SIZE(adc3xxx_defaults), |
458 | |
459 | .volatile_reg = adc3xxx_volatile_reg, |
460 | |
461 | .cache_type = REGCACHE_RBTREE, |
462 | |
463 | .ranges = adc3xxx_ranges, |
464 | .num_ranges = ARRAY_SIZE(adc3xxx_ranges), |
465 | .max_register = 5 * ADC3XXX_PAGE_SIZE, |
466 | }; |
467 | |
468 | struct adc3xxx_rate_divs { |
469 | u32 mclk; |
470 | u32 rate; |
471 | u8 pll_p; |
472 | u8 pll_r; |
473 | u8 pll_j; |
474 | u16 pll_d; |
475 | u8 nadc; |
476 | u8 madc; |
477 | u8 aosr; |
478 | }; |
479 | |
480 | /* |
481 | * PLL and Clock settings. |
482 | * If p member is 0, PLL is not used. |
483 | * The order of the entries in this table have the PLL entries before |
484 | * the non-PLL entries, so that the PLL modes are preferred unless |
485 | * the PLL mode setting says otherwise. |
486 | */ |
487 | static const struct adc3xxx_rate_divs adc3xxx_divs[] = { |
488 | /* mclk, rate, p, r, j, d, nadc, madc, aosr */ |
489 | /* 8k rate */ |
490 | { 12000000, 8000, 1, 1, 7, 1680, 42, 2, 128 }, |
491 | { 12288000, 8000, 1, 1, 7, 0000, 42, 2, 128 }, |
492 | /* 11.025k rate */ |
493 | { 12000000, 11025, 1, 1, 6, 8208, 29, 2, 128 }, |
494 | /* 16k rate */ |
495 | { 12000000, 16000, 1, 1, 7, 1680, 21, 2, 128 }, |
496 | { 12288000, 16000, 1, 1, 7, 0000, 21, 2, 128 }, |
497 | /* 22.05k rate */ |
498 | { 12000000, 22050, 1, 1, 7, 560, 15, 2, 128 }, |
499 | /* 32k rate */ |
500 | { 12000000, 32000, 1, 1, 8, 1920, 12, 2, 128 }, |
501 | { 12288000, 32000, 1, 1, 8, 0000, 12, 2, 128 }, |
502 | /* 44.1k rate */ |
503 | { 12000000, 44100, 1, 1, 7, 5264, 8, 2, 128 }, |
504 | /* 48k rate */ |
505 | { 12000000, 48000, 1, 1, 7, 1680, 7, 2, 128 }, |
506 | { 12288000, 48000, 1, 1, 7, 0000, 7, 2, 128 }, |
507 | { 24576000, 48000, 1, 1, 3, 5000, 7, 2, 128 }, /* With PLL */ |
508 | { 24576000, 48000, 0, 0, 0, 0000, 2, 2, 128 }, /* Without PLL */ |
509 | /* 88.2k rate */ |
510 | { 12000000, 88200, 1, 1, 7, 5264, 4, 4, 64 }, |
511 | /* 96k rate */ |
512 | { 12000000, 96000, 1, 1, 8, 1920, 4, 4, 64 }, |
513 | }; |
514 | |
515 | static int adc3xxx_get_divs(struct device *dev, int mclk, int rate, int pll_mode) |
516 | { |
517 | int i; |
518 | |
519 | dev_dbg(dev, "mclk = %d, rate = %d, clock mode %u\n" , |
520 | mclk, rate, pll_mode); |
521 | for (i = 0; i < ARRAY_SIZE(adc3xxx_divs); i++) { |
522 | const struct adc3xxx_rate_divs *mode = &adc3xxx_divs[i]; |
523 | |
524 | /* Skip this entry if it doesn't fulfill the intended clock |
525 | * mode requirement. We consider anything besides the two |
526 | * modes below to be the same as ADC3XXX_PLL_AUTO. |
527 | */ |
528 | if ((pll_mode == ADC3XXX_PLL_BYPASS && mode->pll_p) || |
529 | (pll_mode == ADC3XXX_PLL_ENABLE && !mode->pll_p)) |
530 | continue; |
531 | |
532 | if (mode->rate == rate && mode->mclk == mclk) |
533 | return i; |
534 | } |
535 | |
536 | dev_info(dev, "Master clock rate %d and sample rate %d is not supported\n" , |
537 | mclk, rate); |
538 | return -EINVAL; |
539 | } |
540 | |
541 | static int adc3xxx_pll_delay(struct snd_soc_dapm_widget *w, |
542 | struct snd_kcontrol *kcontrol, int event) |
543 | { |
544 | /* 10msec delay needed after PLL power-up to allow |
545 | * PLL and dividers to stabilize (datasheet p13). |
546 | */ |
547 | usleep_range(min: 10000, max: 20000); |
548 | |
549 | return 0; |
550 | } |
551 | |
552 | static int adc3xxx_coefficient_info(struct snd_kcontrol *kcontrol, |
553 | struct snd_ctl_elem_info *uinfo) |
554 | { |
555 | int numcoeff = kcontrol->private_value >> 16; |
556 | |
557 | uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; |
558 | uinfo->count = numcoeff; |
559 | uinfo->value.integer.min = 0; |
560 | uinfo->value.integer.max = 0xffff; /* all coefficients are 16 bit */ |
561 | return 0; |
562 | } |
563 | |
564 | static int adc3xxx_coefficient_get(struct snd_kcontrol *kcontrol, |
565 | struct snd_ctl_elem_value *ucontrol) |
566 | { |
567 | struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); |
568 | int numcoeff = kcontrol->private_value >> 16; |
569 | int reg = kcontrol->private_value & 0xffff; |
570 | int index = 0; |
571 | |
572 | for (index = 0; index < numcoeff; index++) { |
573 | unsigned int value_msb, value_lsb, value; |
574 | |
575 | value_msb = snd_soc_component_read(component, reg: reg++); |
576 | if ((int)value_msb < 0) |
577 | return (int)value_msb; |
578 | |
579 | value_lsb = snd_soc_component_read(component, reg: reg++); |
580 | if ((int)value_lsb < 0) |
581 | return (int)value_lsb; |
582 | |
583 | value = (value_msb << 8) | value_lsb; |
584 | ucontrol->value.integer.value[index] = value; |
585 | } |
586 | |
587 | return 0; |
588 | } |
589 | |
590 | static int adc3xxx_coefficient_put(struct snd_kcontrol *kcontrol, |
591 | struct snd_ctl_elem_value *ucontrol) |
592 | { |
593 | struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); |
594 | int numcoeff = kcontrol->private_value >> 16; |
595 | int reg = kcontrol->private_value & 0xffff; |
596 | int index = 0; |
597 | int ret; |
598 | |
599 | for (index = 0; index < numcoeff; index++) { |
600 | unsigned int value = ucontrol->value.integer.value[index]; |
601 | unsigned int value_msb = (value >> 8) & 0xff; |
602 | unsigned int value_lsb = value & 0xff; |
603 | |
604 | ret = snd_soc_component_write(component, reg: reg++, val: value_msb); |
605 | if (ret) |
606 | return ret; |
607 | |
608 | ret = snd_soc_component_write(component, reg: reg++, val: value_lsb); |
609 | if (ret) |
610 | return ret; |
611 | } |
612 | |
613 | return 0; |
614 | } |
615 | |
616 | /* All on-chip filters have coefficients which are expressed in terms of |
617 | * 16 bit values, so represent them as strings of 16-bit integers. |
618 | */ |
619 | #define TI_COEFFICIENTS(xname, reg, numcoeffs) { \ |
620 | .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ |
621 | .name = xname, \ |
622 | .info = adc3xxx_coefficient_info, \ |
623 | .get = adc3xxx_coefficient_get,\ |
624 | .put = adc3xxx_coefficient_put, \ |
625 | .access = SNDRV_CTL_ELEM_ACCESS_READWRITE, \ |
626 | .private_value = reg | (numcoeffs << 16) \ |
627 | } |
628 | |
629 | static const char * const adc_softstepping_text[] = { "1 step" , "2 step" , "off" }; |
630 | static SOC_ENUM_SINGLE_DECL(adc_softstepping_enum, ADC3XXX_ADC_DIGITAL, 0, |
631 | adc_softstepping_text); |
632 | |
633 | static const char * const multiplier_text[] = { "1" , "2" , "4" , "8" , "16" , "32" , "64" , "128" }; |
634 | static SOC_ENUM_SINGLE_DECL(left_agc_attack_mult_enum, |
635 | ADC3XXX_LEFT_CHN_AGC_4, 0, multiplier_text); |
636 | static SOC_ENUM_SINGLE_DECL(right_agc_attack_mult_enum, |
637 | ADC3XXX_RIGHT_CHN_AGC_4, 0, multiplier_text); |
638 | static SOC_ENUM_SINGLE_DECL(left_agc_decay_mult_enum, |
639 | ADC3XXX_LEFT_CHN_AGC_5, 0, multiplier_text); |
640 | static SOC_ENUM_SINGLE_DECL(right_agc_decay_mult_enum, |
641 | ADC3XXX_RIGHT_CHN_AGC_5, 0, multiplier_text); |
642 | |
643 | static const char * const dither_dc_offset_text[] = { |
644 | "0mV" , "15mV" , "30mV" , "45mV" , "60mV" , "75mV" , "90mV" , "105mV" , |
645 | "-15mV" , "-30mV" , "-45mV" , "-60mV" , "-75mV" , "-90mV" , "-105mV" |
646 | }; |
647 | static const unsigned int dither_dc_offset_values[] = { |
648 | 0, 1, 2, 3, 4, 5, 6, 7, 9, 10, 11, 12, 13, 14, 15 |
649 | }; |
650 | static SOC_VALUE_ENUM_DOUBLE_DECL(dither_dc_offset_enum, |
651 | ADC3XXX_DITHER_CTRL, |
652 | 4, 0, 0xf, dither_dc_offset_text, |
653 | dither_dc_offset_values); |
654 | |
655 | static const DECLARE_TLV_DB_SCALE(pga_tlv, 0, 50, 0); |
656 | static const DECLARE_TLV_DB_SCALE(adc_tlv, -1200, 50, 0); |
657 | static const DECLARE_TLV_DB_SCALE(adc_fine_tlv, -40, 10, 0); |
658 | /* AGC target: 8 values: -5.5, -8, -10, -12, -14, -17, -20, -24 dB */ |
659 | /* It would be nice to declare these in the order above, but empirically |
660 | * TLV_DB_SCALE_ITEM doesn't take lightly to the increment (second) parameter |
661 | * being negative, despite there being examples to the contrary in other |
662 | * drivers. So declare these in the order from lowest to highest, and |
663 | * set the invert flag in the SOC_DOUBLE_R_TLV declaration instead. |
664 | */ |
665 | static const DECLARE_TLV_DB_RANGE(agc_target_tlv, |
666 | 0, 0, TLV_DB_SCALE_ITEM(-2400, 0, 0), |
667 | 1, 3, TLV_DB_SCALE_ITEM(-2000, 300, 0), |
668 | 4, 6, TLV_DB_SCALE_ITEM(-1200, 200, 0), |
669 | 7, 7, TLV_DB_SCALE_ITEM(-550, 0, 0)); |
670 | /* Since the 'disabled' value (mute) is at the highest value in the dB |
671 | * range (i.e. just before -32 dB) rather than the lowest, we need to resort |
672 | * to using a TLV_DB_RANGE in order to get the mute value in the right place. |
673 | */ |
674 | static const DECLARE_TLV_DB_RANGE(agc_thresh_tlv, |
675 | 0, 30, TLV_DB_SCALE_ITEM(-9000, 200, 0), |
676 | 31, 31, TLV_DB_SCALE_ITEM(0, 0, 1)); /* disabled = mute */ |
677 | /* AGC hysteresis: 4 values: 1, 2, 4 dB, disabled (= mute) */ |
678 | static const DECLARE_TLV_DB_RANGE(agc_hysteresis_tlv, |
679 | 0, 1, TLV_DB_SCALE_ITEM(100, 100, 0), |
680 | 2, 2, TLV_DB_SCALE_ITEM(400, 0, 0), |
681 | 3, 3, TLV_DB_SCALE_ITEM(0, 0, 1)); /* disabled = mute */ |
682 | static const DECLARE_TLV_DB_SCALE(agc_max_tlv, 0, 50, 0); |
683 | /* Input attenuation: -6 dB or 0 dB */ |
684 | static const DECLARE_TLV_DB_SCALE(input_attenuation_tlv, -600, 600, 0); |
685 | |
686 | static const struct snd_kcontrol_new adc3xxx_snd_controls[] = { |
687 | SOC_DOUBLE_R_TLV("PGA Capture Volume" , ADC3XXX_LEFT_APGA_CTRL, |
688 | ADC3XXX_RIGHT_APGA_CTRL, 0, 80, 0, pga_tlv), |
689 | SOC_DOUBLE("PGA Capture Switch" , ADC3XXX_ADC_FGA, 7, 3, 1, 1), |
690 | SOC_DOUBLE_R("AGC Capture Switch" , ADC3XXX_LEFT_CHN_AGC_1, |
691 | ADC3XXX_RIGHT_CHN_AGC_1, 7, 1, 0), |
692 | SOC_DOUBLE_R_TLV("AGC Target Level Capture Volume" , ADC3XXX_LEFT_CHN_AGC_1, |
693 | ADC3XXX_RIGHT_CHN_AGC_2, 4, 0x07, 1, agc_target_tlv), |
694 | SOC_DOUBLE_R_TLV("AGC Noise Threshold Capture Volume" , ADC3XXX_LEFT_CHN_AGC_2, |
695 | ADC3XXX_RIGHT_CHN_AGC_2, 1, 0x1f, 1, agc_thresh_tlv), |
696 | SOC_DOUBLE_R_TLV("AGC Hysteresis Capture Volume" , ADC3XXX_LEFT_CHN_AGC_2, |
697 | ADC3XXX_RIGHT_CHN_AGC_2, 6, 3, 0, agc_hysteresis_tlv), |
698 | SOC_DOUBLE_R("AGC Clip Stepping Capture Switch" , ADC3XXX_LEFT_CHN_AGC_2, |
699 | ADC3XXX_RIGHT_CHN_AGC_2, 0, 1, 0), |
700 | /* |
701 | * Oddly enough, the data sheet says the default value |
702 | * for the left/right AGC maximum gain register field |
703 | * (ADC3XXX_LEFT/RIGHT_CHN_AGC_3 bits 0..6) is 0x7f = 127 |
704 | * (verified empirically) even though this value (indeed, above |
705 | * 0x50) is specified as 'Reserved. Do not use.' in the accompanying |
706 | * table in the data sheet. |
707 | */ |
708 | SOC_DOUBLE_R_TLV("AGC Maximum Capture Volume" , ADC3XXX_LEFT_CHN_AGC_3, |
709 | ADC3XXX_RIGHT_CHN_AGC_3, 0, 0x50, 0, agc_max_tlv), |
710 | SOC_DOUBLE_R("AGC Attack Time" , ADC3XXX_LEFT_CHN_AGC_4, |
711 | ADC3XXX_RIGHT_CHN_AGC_4, 3, 0x1f, 0), |
712 | /* Would like to have the multipliers as LR pairs, but there is |
713 | * no SOC_ENUM_foo which accepts two values in separate registers. |
714 | */ |
715 | SOC_ENUM("AGC Left Attack Time Multiplier" , left_agc_attack_mult_enum), |
716 | SOC_ENUM("AGC Right Attack Time Multiplier" , right_agc_attack_mult_enum), |
717 | SOC_DOUBLE_R("AGC Decay Time" , ADC3XXX_LEFT_CHN_AGC_5, |
718 | ADC3XXX_RIGHT_CHN_AGC_5, 3, 0x1f, 0), |
719 | SOC_ENUM("AGC Left Decay Time Multiplier" , left_agc_decay_mult_enum), |
720 | SOC_ENUM("AGC Right Decay Time Multiplier" , right_agc_decay_mult_enum), |
721 | SOC_DOUBLE_R("AGC Noise Debounce" , ADC3XXX_LEFT_CHN_AGC_6, |
722 | ADC3XXX_RIGHT_CHN_AGC_6, 0, 0x1f, 0), |
723 | SOC_DOUBLE_R("AGC Signal Debounce" , ADC3XXX_LEFT_CHN_AGC_7, |
724 | ADC3XXX_RIGHT_CHN_AGC_7, 0, 0x0f, 0), |
725 | /* Read only register */ |
726 | SOC_DOUBLE_R_S_TLV("AGC Applied Capture Volume" , ADC3XXX_LEFT_AGC_GAIN, |
727 | ADC3XXX_RIGHT_AGC_GAIN, 0, -24, 40, 6, 0, adc_tlv), |
728 | /* ADC soft stepping */ |
729 | SOC_ENUM("ADC Soft Stepping" , adc_softstepping_enum), |
730 | /* Left/Right Input attenuation */ |
731 | SOC_SINGLE_TLV("Left Input IN_1L Capture Volume" , |
732 | ADC3XXX_LEFT_PGA_SEL_1, 0, 1, 1, input_attenuation_tlv), |
733 | SOC_SINGLE_TLV("Left Input IN_2L Capture Volume" , |
734 | ADC3XXX_LEFT_PGA_SEL_1, 2, 1, 1, input_attenuation_tlv), |
735 | SOC_SINGLE_TLV("Left Input IN_3L Capture Volume" , |
736 | ADC3XXX_LEFT_PGA_SEL_1, 4, 1, 1, input_attenuation_tlv), |
737 | SOC_SINGLE_TLV("Left Input IN_1R Capture Volume" , |
738 | ADC3XXX_LEFT_PGA_SEL_2, 0, 1, 1, input_attenuation_tlv), |
739 | SOC_SINGLE_TLV("Left Input DIF_2L_3L Capture Volume" , |
740 | ADC3XXX_LEFT_PGA_SEL_1, 6, 1, 1, input_attenuation_tlv), |
741 | SOC_SINGLE_TLV("Left Input DIF_1L_1R Capture Volume" , |
742 | ADC3XXX_LEFT_PGA_SEL_2, 4, 1, 1, input_attenuation_tlv), |
743 | SOC_SINGLE_TLV("Left Input DIF_2R_3R Capture Volume" , |
744 | ADC3XXX_LEFT_PGA_SEL_2, 2, 1, 1, input_attenuation_tlv), |
745 | SOC_SINGLE_TLV("Right Input IN_1R Capture Volume" , |
746 | ADC3XXX_RIGHT_PGA_SEL_1, 0, 1, 1, input_attenuation_tlv), |
747 | SOC_SINGLE_TLV("Right Input IN_2R Capture Volume" , |
748 | ADC3XXX_RIGHT_PGA_SEL_1, 2, 1, 1, input_attenuation_tlv), |
749 | SOC_SINGLE_TLV("Right Input IN_3R Capture Volume" , |
750 | ADC3XXX_RIGHT_PGA_SEL_1, 4, 1, 1, input_attenuation_tlv), |
751 | SOC_SINGLE_TLV("Right Input IN_1L Capture Volume" , |
752 | ADC3XXX_RIGHT_PGA_SEL_2, 0, 1, 1, input_attenuation_tlv), |
753 | SOC_SINGLE_TLV("Right Input DIF_2R_3R Capture Volume" , |
754 | ADC3XXX_RIGHT_PGA_SEL_1, 6, 1, 1, input_attenuation_tlv), |
755 | SOC_SINGLE_TLV("Right Input DIF_1L_1R Capture Volume" , |
756 | ADC3XXX_RIGHT_PGA_SEL_2, 4, 1, 1, input_attenuation_tlv), |
757 | SOC_SINGLE_TLV("Right Input DIF_2L_3L Capture Volume" , |
758 | ADC3XXX_RIGHT_PGA_SEL_2, 2, 1, 1, input_attenuation_tlv), |
759 | SOC_DOUBLE_R_S_TLV("ADC Volume Control Capture Volume" , ADC3XXX_LADC_VOL, |
760 | ADC3XXX_RADC_VOL, 0, -24, 40, 6, 0, adc_tlv), |
761 | /* Empirically, the following doesn't work the way it's supposed |
762 | * to. Values 0, -0.1, -0.2 and -0.3 dB result in the same level, and |
763 | * -0.4 dB drops about 0.12 dB on a specific chip. |
764 | */ |
765 | SOC_DOUBLE_TLV("ADC Fine Volume Control Capture Volume" , ADC3XXX_ADC_FGA, |
766 | 4, 0, 4, 1, adc_fine_tlv), |
767 | SOC_SINGLE("Left ADC Unselected CM Bias Capture Switch" , |
768 | ADC3XXX_LEFT_PGA_SEL_2, 6, 1, 0), |
769 | SOC_SINGLE("Right ADC Unselected CM Bias Capture Switch" , |
770 | ADC3XXX_RIGHT_PGA_SEL_2, 6, 1, 0), |
771 | SOC_ENUM("Dither Control DC Offset" , dither_dc_offset_enum), |
772 | |
773 | /* Coefficient memory for miniDSP. */ |
774 | /* For the default PRB_R1 processing block, the only available |
775 | * filter is the first order IIR. |
776 | */ |
777 | |
778 | TI_COEFFICIENTS("Left ADC IIR Coefficients N0 N1 D1" , |
779 | ADC3XXX_LEFT_ADC_IIR_COEFF_N0_MSB, 3), |
780 | |
781 | TI_COEFFICIENTS("Right ADC IIR Coefficients N0 N1 D1" , |
782 | ADC3XXX_RIGHT_ADC_IIR_COEFF_N0_MSB, 3), |
783 | }; |
784 | |
785 | /* Left input selection, Single Ended inputs and Differential inputs */ |
786 | static const struct snd_kcontrol_new left_input_mixer_controls[] = { |
787 | SOC_DAPM_SINGLE("IN_1L Capture Switch" , |
788 | ADC3XXX_LEFT_PGA_SEL_1, 1, 0x1, 1), |
789 | SOC_DAPM_SINGLE("IN_2L Capture Switch" , |
790 | ADC3XXX_LEFT_PGA_SEL_1, 3, 0x1, 1), |
791 | SOC_DAPM_SINGLE("IN_3L Capture Switch" , |
792 | ADC3XXX_LEFT_PGA_SEL_1, 5, 0x1, 1), |
793 | SOC_DAPM_SINGLE("DIF_2L_3L Capture Switch" , |
794 | ADC3XXX_LEFT_PGA_SEL_1, 7, 0x1, 1), |
795 | SOC_DAPM_SINGLE("DIF_1L_1R Capture Switch" , |
796 | ADC3XXX_LEFT_PGA_SEL_2, 5, 0x1, 1), |
797 | SOC_DAPM_SINGLE("DIF_2R_3R Capture Switch" , |
798 | ADC3XXX_LEFT_PGA_SEL_2, 3, 0x1, 1), |
799 | SOC_DAPM_SINGLE("IN_1R Capture Switch" , |
800 | ADC3XXX_LEFT_PGA_SEL_2, 1, 0x1, 1), |
801 | }; |
802 | |
803 | /* Right input selection, Single Ended inputs and Differential inputs */ |
804 | static const struct snd_kcontrol_new right_input_mixer_controls[] = { |
805 | SOC_DAPM_SINGLE("IN_1R Capture Switch" , |
806 | ADC3XXX_RIGHT_PGA_SEL_1, 1, 0x1, 1), |
807 | SOC_DAPM_SINGLE("IN_2R Capture Switch" , |
808 | ADC3XXX_RIGHT_PGA_SEL_1, 3, 0x1, 1), |
809 | SOC_DAPM_SINGLE("IN_3R Capture Switch" , |
810 | ADC3XXX_RIGHT_PGA_SEL_1, 5, 0x1, 1), |
811 | SOC_DAPM_SINGLE("DIF_2R_3R Capture Switch" , |
812 | ADC3XXX_RIGHT_PGA_SEL_1, 7, 0x1, 1), |
813 | SOC_DAPM_SINGLE("DIF_1L_1R Capture Switch" , |
814 | ADC3XXX_RIGHT_PGA_SEL_2, 5, 0x1, 1), |
815 | SOC_DAPM_SINGLE("DIF_2L_3L Capture Switch" , |
816 | ADC3XXX_RIGHT_PGA_SEL_2, 3, 0x1, 1), |
817 | SOC_DAPM_SINGLE("IN_1L Capture Switch" , |
818 | ADC3XXX_RIGHT_PGA_SEL_2, 1, 0x1, 1), |
819 | }; |
820 | |
821 | /* Left Digital Mic input for left ADC */ |
822 | static const struct snd_kcontrol_new left_input_dmic_controls[] = { |
823 | SOC_DAPM_SINGLE("Left ADC Capture Switch" , |
824 | ADC3XXX_ADC_DIGITAL, 3, 0x1, 0), |
825 | }; |
826 | |
827 | /* Right Digital Mic input for Right ADC */ |
828 | static const struct snd_kcontrol_new right_input_dmic_controls[] = { |
829 | SOC_DAPM_SINGLE("Right ADC Capture Switch" , |
830 | ADC3XXX_ADC_DIGITAL, 2, 0x1, 0), |
831 | }; |
832 | |
833 | /* DAPM widgets */ |
834 | static const struct snd_soc_dapm_widget adc3xxx_dapm_widgets[] = { |
835 | |
836 | /* Left Input Selection */ |
837 | SND_SOC_DAPM_MIXER("Left Input" , SND_SOC_NOPM, 0, 0, |
838 | &left_input_mixer_controls[0], |
839 | ARRAY_SIZE(left_input_mixer_controls)), |
840 | /* Right Input Selection */ |
841 | SND_SOC_DAPM_MIXER("Right Input" , SND_SOC_NOPM, 0, 0, |
842 | &right_input_mixer_controls[0], |
843 | ARRAY_SIZE(right_input_mixer_controls)), |
844 | /* PGA selection */ |
845 | SND_SOC_DAPM_PGA("Left PGA" , ADC3XXX_LEFT_APGA_CTRL, 7, 1, NULL, 0), |
846 | SND_SOC_DAPM_PGA("Right PGA" , ADC3XXX_RIGHT_APGA_CTRL, 7, 1, NULL, 0), |
847 | |
848 | /* Digital Microphone Input Control for Left/Right ADC */ |
849 | SND_SOC_DAPM_MIXER("Left DMic Input" , SND_SOC_NOPM, 0, 0, |
850 | &left_input_dmic_controls[0], |
851 | ARRAY_SIZE(left_input_dmic_controls)), |
852 | SND_SOC_DAPM_MIXER("Right DMic Input" , SND_SOC_NOPM, 0, 0, |
853 | &right_input_dmic_controls[0], |
854 | ARRAY_SIZE(right_input_dmic_controls)), |
855 | |
856 | /* Left/Right ADC */ |
857 | SND_SOC_DAPM_ADC("Left ADC" , "Left Capture" , ADC3XXX_ADC_DIGITAL, 7, 0), |
858 | SND_SOC_DAPM_ADC("Right ADC" , "Right Capture" , ADC3XXX_ADC_DIGITAL, 6, 0), |
859 | |
860 | /* Inputs */ |
861 | SND_SOC_DAPM_INPUT("IN_1L" ), |
862 | SND_SOC_DAPM_INPUT("IN_1R" ), |
863 | SND_SOC_DAPM_INPUT("IN_2L" ), |
864 | SND_SOC_DAPM_INPUT("IN_2R" ), |
865 | SND_SOC_DAPM_INPUT("IN_3L" ), |
866 | SND_SOC_DAPM_INPUT("IN_3R" ), |
867 | SND_SOC_DAPM_INPUT("DIFL_1L_1R" ), |
868 | SND_SOC_DAPM_INPUT("DIFL_2L_3L" ), |
869 | SND_SOC_DAPM_INPUT("DIFL_2R_3R" ), |
870 | SND_SOC_DAPM_INPUT("DIFR_1L_1R" ), |
871 | SND_SOC_DAPM_INPUT("DIFR_2L_3L" ), |
872 | SND_SOC_DAPM_INPUT("DIFR_2R_3R" ), |
873 | SND_SOC_DAPM_INPUT("DMic_L" ), |
874 | SND_SOC_DAPM_INPUT("DMic_R" ), |
875 | |
876 | /* Digital audio interface output */ |
877 | SND_SOC_DAPM_AIF_OUT("AIF_OUT" , "Capture" , 0, SND_SOC_NOPM, 0, 0), |
878 | |
879 | /* Clocks */ |
880 | SND_SOC_DAPM_SUPPLY("PLL_CLK" , ADC3XXX_PLL_PROG_PR, ADC3XXX_ENABLE_PLL_SHIFT, |
881 | 0, adc3xxx_pll_delay, SND_SOC_DAPM_POST_PMU), |
882 | |
883 | SND_SOC_DAPM_SUPPLY("ADC_CLK" , ADC3XXX_ADC_NADC, ADC3XXX_ENABLE_NADC_SHIFT, |
884 | 0, NULL, 0), |
885 | SND_SOC_DAPM_SUPPLY("ADC_MOD_CLK" , ADC3XXX_ADC_MADC, ADC3XXX_ENABLE_MADC_SHIFT, |
886 | 0, NULL, 0), |
887 | |
888 | /* This refers to the generated BCLK in master mode. */ |
889 | SND_SOC_DAPM_SUPPLY("BCLK" , ADC3XXX_BCLK_N_DIV, ADC3XXX_ENABLE_BCLK_SHIFT, |
890 | 0, NULL, 0), |
891 | }; |
892 | |
893 | static const struct snd_soc_dapm_route adc3xxx_intercon[] = { |
894 | /* Left input selection from switches */ |
895 | { "Left Input" , "IN_1L Capture Switch" , "IN_1L" }, |
896 | { "Left Input" , "IN_2L Capture Switch" , "IN_2L" }, |
897 | { "Left Input" , "IN_3L Capture Switch" , "IN_3L" }, |
898 | { "Left Input" , "DIF_2L_3L Capture Switch" , "DIFL_2L_3L" }, |
899 | { "Left Input" , "DIF_1L_1R Capture Switch" , "DIFL_1L_1R" }, |
900 | { "Left Input" , "DIF_2R_3R Capture Switch" , "DIFL_2R_3R" }, |
901 | { "Left Input" , "IN_1R Capture Switch" , "IN_1R" }, |
902 | |
903 | /* Left input selection to left PGA */ |
904 | { "Left PGA" , NULL, "Left Input" }, |
905 | |
906 | /* Left PGA to left ADC */ |
907 | { "Left ADC" , NULL, "Left PGA" }, |
908 | |
909 | /* Right input selection from switches */ |
910 | { "Right Input" , "IN_1R Capture Switch" , "IN_1R" }, |
911 | { "Right Input" , "IN_2R Capture Switch" , "IN_2R" }, |
912 | { "Right Input" , "IN_3R Capture Switch" , "IN_3R" }, |
913 | { "Right Input" , "DIF_2R_3R Capture Switch" , "DIFR_2R_3R" }, |
914 | { "Right Input" , "DIF_1L_1R Capture Switch" , "DIFR_1L_1R" }, |
915 | { "Right Input" , "DIF_2L_3L Capture Switch" , "DIFR_2L_3L" }, |
916 | { "Right Input" , "IN_1L Capture Switch" , "IN_1L" }, |
917 | |
918 | /* Right input selection to right PGA */ |
919 | { "Right PGA" , NULL, "Right Input" }, |
920 | |
921 | /* Right PGA to right ADC */ |
922 | { "Right ADC" , NULL, "Right PGA" }, |
923 | |
924 | /* Left DMic Input selection from switch */ |
925 | { "Left DMic Input" , "Left ADC Capture Switch" , "DMic_L" }, |
926 | |
927 | /* Left DMic to left ADC */ |
928 | { "Left ADC" , NULL, "Left DMic Input" }, |
929 | |
930 | /* Right DMic Input selection from switch */ |
931 | { "Right DMic Input" , "Right ADC Capture Switch" , "DMic_R" }, |
932 | |
933 | /* Right DMic to right ADC */ |
934 | { "Right ADC" , NULL, "Right DMic Input" }, |
935 | |
936 | /* ADC to AIF output */ |
937 | { "AIF_OUT" , NULL, "Left ADC" }, |
938 | { "AIF_OUT" , NULL, "Right ADC" }, |
939 | |
940 | /* Clocking */ |
941 | { "ADC_MOD_CLK" , NULL, "ADC_CLK" }, |
942 | { "Left ADC" , NULL, "ADC_MOD_CLK" }, |
943 | { "Right ADC" , NULL, "ADC_MOD_CLK" }, |
944 | |
945 | { "BCLK" , NULL, "ADC_CLK" }, |
946 | }; |
947 | |
948 | static const struct snd_soc_dapm_route adc3xxx_pll_intercon[] = { |
949 | { "ADC_CLK" , NULL, "PLL_CLK" }, |
950 | }; |
951 | |
952 | static const struct snd_soc_dapm_route adc3xxx_bclk_out_intercon[] = { |
953 | { "AIF_OUT" , NULL, "BCLK" } |
954 | }; |
955 | |
956 | static int adc3xxx_gpio_request(struct gpio_chip *chip, unsigned int offset) |
957 | { |
958 | struct adc3xxx *adc3xxx = gpiochip_get_data(gc: chip); |
959 | |
960 | if (offset >= ADC3XXX_GPIOS_MAX) |
961 | return -EINVAL; |
962 | |
963 | /* GPIO1 is offset 0, GPIO2 is offset 1 */ |
964 | /* We check here that the GPIO pins are either not configured in the |
965 | * DT, or that they purposely are set as outputs. |
966 | * (Input mode not yet implemented). |
967 | */ |
968 | if (adc3xxx->gpio_cfg[offset] != 0 && |
969 | adc3xxx->gpio_cfg[offset] != ADC3XXX_GPIO_GPO + 1) |
970 | return -EINVAL; |
971 | |
972 | return 0; |
973 | } |
974 | |
975 | static int adc3xxx_gpio_direction_out(struct gpio_chip *chip, |
976 | unsigned int offset, int value) |
977 | { |
978 | struct adc3xxx *adc3xxx = gpiochip_get_data(gc: chip); |
979 | |
980 | /* Set GPIO output function. */ |
981 | return regmap_update_bits(map: adc3xxx->regmap, |
982 | reg: adc3xxx_gpio_ctrl_reg[offset], |
983 | ADC3XXX_GPIO_CTRL_CFG_MASK | |
984 | ADC3XXX_GPIO_CTRL_OUTPUT_CTRL_MASK, |
985 | ADC3XXX_GPIO_GPO << ADC3XXX_GPIO_CTRL_CFG_SHIFT | |
986 | !!value << ADC3XXX_GPIO_CTRL_OUTPUT_CTRL_SHIFT); |
987 | } |
988 | |
989 | /* With only GPIO outputs configured, we never get the .direction_out call, |
990 | * so we set the output mode and output value in the same call. Hence |
991 | * .set in practice does the same thing as .direction_out . |
992 | */ |
993 | static void adc3xxx_gpio_set(struct gpio_chip *chip, unsigned int offset, |
994 | int value) |
995 | { |
996 | (void) adc3xxx_gpio_direction_out(chip, offset, value); |
997 | } |
998 | |
999 | /* Even though we only support GPIO output for now, some GPIO clients |
1000 | * want to read the current pin state using the .get callback. |
1001 | */ |
1002 | static int adc3xxx_gpio_get(struct gpio_chip *chip, unsigned int offset) |
1003 | { |
1004 | struct adc3xxx *adc3xxx = gpiochip_get_data(gc: chip); |
1005 | unsigned int regval; |
1006 | int ret; |
1007 | |
1008 | /* We only allow output pins, so just read the value set in the output |
1009 | * pin register field. |
1010 | */ |
1011 | ret = regmap_read(map: adc3xxx->regmap, reg: adc3xxx_gpio_ctrl_reg[offset], val: ®val); |
1012 | if (ret) |
1013 | return ret; |
1014 | return !!(regval & ADC3XXX_GPIO_CTRL_OUTPUT_CTRL_MASK); |
1015 | } |
1016 | |
1017 | static const struct gpio_chip adc3xxx_gpio_chip = { |
1018 | .label = "adc3xxx" , |
1019 | .owner = THIS_MODULE, |
1020 | .request = adc3xxx_gpio_request, |
1021 | .direction_output = adc3xxx_gpio_direction_out, |
1022 | .set = adc3xxx_gpio_set, |
1023 | .get = adc3xxx_gpio_get, |
1024 | .can_sleep = 1, |
1025 | }; |
1026 | |
1027 | static void adc3xxx_free_gpio(struct adc3xxx *adc3xxx) |
1028 | { |
1029 | #ifdef CONFIG_GPIOLIB |
1030 | gpiochip_remove(gc: &adc3xxx->gpio_chip); |
1031 | #endif |
1032 | } |
1033 | |
1034 | static void adc3xxx_init_gpio(struct adc3xxx *adc3xxx) |
1035 | { |
1036 | int gpio, micbias; |
1037 | int ret; |
1038 | |
1039 | adc3xxx->gpio_chip = adc3xxx_gpio_chip; |
1040 | adc3xxx->gpio_chip.ngpio = ADC3XXX_GPIOS_MAX; |
1041 | adc3xxx->gpio_chip.parent = adc3xxx->dev; |
1042 | adc3xxx->gpio_chip.base = -1; |
1043 | |
1044 | ret = gpiochip_add_data(&adc3xxx->gpio_chip, adc3xxx); |
1045 | if (ret) |
1046 | dev_err(adc3xxx->dev, "Failed to add gpios: %d\n" , ret); |
1047 | |
1048 | /* Set up potential GPIO configuration from the devicetree. |
1049 | * This allows us to set up things which are not software |
1050 | * controllable GPIOs, such as PDM microphone I/O, |
1051 | */ |
1052 | for (gpio = 0; gpio < ADC3XXX_GPIOS_MAX; gpio++) { |
1053 | unsigned int cfg = adc3xxx->gpio_cfg[gpio]; |
1054 | |
1055 | if (cfg) { |
1056 | cfg--; /* actual value to use is stored +1 */ |
1057 | regmap_update_bits(map: adc3xxx->regmap, |
1058 | reg: adc3xxx_gpio_ctrl_reg[gpio], |
1059 | ADC3XXX_GPIO_CTRL_CFG_MASK, |
1060 | val: cfg << ADC3XXX_GPIO_CTRL_CFG_SHIFT); |
1061 | } |
1062 | } |
1063 | |
1064 | /* Set up micbias voltage */ |
1065 | for (micbias = 0; micbias < ADC3XXX_MICBIAS_PINS; micbias++) { |
1066 | unsigned int vg = adc3xxx->micbias_vg[micbias]; |
1067 | |
1068 | regmap_update_bits(map: adc3xxx->regmap, |
1069 | ADC3XXX_MICBIAS_CTRL, |
1070 | ADC3XXX_MICBIAS_MASK << adc3xxx_micbias_shift[micbias], |
1071 | val: vg << adc3xxx_micbias_shift[micbias]); |
1072 | } |
1073 | } |
1074 | |
1075 | static int adc3xxx_parse_dt_gpio(struct adc3xxx *adc3xxx, |
1076 | const char *propname, unsigned int *cfg) |
1077 | { |
1078 | struct device *dev = adc3xxx->dev; |
1079 | struct device_node *np = dev->of_node; |
1080 | unsigned int val; |
1081 | |
1082 | if (!of_property_read_u32(np, propname, out_value: &val)) { |
1083 | if (val & ~15 || val == 7 || val >= 11) { |
1084 | dev_err(dev, "Invalid property value for '%s'\n" , propname); |
1085 | return -EINVAL; |
1086 | } |
1087 | if (val == ADC3XXX_GPIO_GPI) |
1088 | dev_warn(dev, "GPIO Input read not yet implemented\n" ); |
1089 | *cfg = val + 1; /* 0 => not set up, all others shifted +1 */ |
1090 | } |
1091 | return 0; |
1092 | } |
1093 | |
1094 | static int adc3xxx_parse_dt_micbias(struct adc3xxx *adc3xxx, |
1095 | const char *propname, unsigned int *vg) |
1096 | { |
1097 | struct device *dev = adc3xxx->dev; |
1098 | struct device_node *np = dev->of_node; |
1099 | unsigned int val; |
1100 | |
1101 | if (!of_property_read_u32(np, propname, out_value: &val)) { |
1102 | if (val > ADC3XXX_MICBIAS_AVDD) { |
1103 | dev_err(dev, "Invalid property value for '%s'\n" , propname); |
1104 | return -EINVAL; |
1105 | } |
1106 | *vg = val; |
1107 | } |
1108 | return 0; |
1109 | } |
1110 | |
1111 | static int adc3xxx_parse_pll_mode(uint32_t val, unsigned int *pll_mode) |
1112 | { |
1113 | if (val != ADC3XXX_PLL_ENABLE && val != ADC3XXX_PLL_BYPASS && |
1114 | val != ADC3XXX_PLL_AUTO) |
1115 | return -EINVAL; |
1116 | |
1117 | *pll_mode = val; |
1118 | |
1119 | return 0; |
1120 | } |
1121 | |
1122 | static void adc3xxx_setup_pll(struct snd_soc_component *component, |
1123 | int div_entry) |
1124 | { |
1125 | int i = div_entry; |
1126 | |
1127 | /* P & R values */ |
1128 | snd_soc_component_write(component, ADC3XXX_PLL_PROG_PR, |
1129 | val: (adc3xxx_divs[i].pll_p << ADC3XXX_PLLP_SHIFT) | |
1130 | (adc3xxx_divs[i].pll_r << ADC3XXX_PLLR_SHIFT)); |
1131 | /* J value */ |
1132 | snd_soc_component_write(component, ADC3XXX_PLL_PROG_J, |
1133 | val: adc3xxx_divs[i].pll_j & ADC3XXX_PLLJ_MASK); |
1134 | /* D value */ |
1135 | snd_soc_component_write(component, ADC3XXX_PLL_PROG_D_LSB, |
1136 | val: adc3xxx_divs[i].pll_d & ADC3XXX_PLLD_LSB_MASK); |
1137 | snd_soc_component_write(component, ADC3XXX_PLL_PROG_D_MSB, |
1138 | val: (adc3xxx_divs[i].pll_d >> 8) & ADC3XXX_PLLD_MSB_MASK); |
1139 | } |
1140 | |
1141 | static int adc3xxx_hw_params(struct snd_pcm_substream *substream, |
1142 | struct snd_pcm_hw_params *params, |
1143 | struct snd_soc_dai *dai) |
1144 | { |
1145 | struct snd_soc_component *component = dai->component; |
1146 | struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component: dai->component); |
1147 | struct adc3xxx *adc3xxx = snd_soc_component_get_drvdata(c: component); |
1148 | int i, width = 16; |
1149 | u8 iface_len, bdiv; |
1150 | |
1151 | i = adc3xxx_get_divs(dev: component->dev, mclk: adc3xxx->sysclk, |
1152 | rate: params_rate(p: params), pll_mode: adc3xxx->pll_mode); |
1153 | |
1154 | if (i < 0) |
1155 | return i; |
1156 | |
1157 | /* select data word length */ |
1158 | switch (params_width(p: params)) { |
1159 | case 16: |
1160 | iface_len = ADC3XXX_IFACE_16BITS; |
1161 | width = 16; |
1162 | break; |
1163 | case 20: |
1164 | iface_len = ADC3XXX_IFACE_20BITS; |
1165 | width = 20; |
1166 | break; |
1167 | case 24: |
1168 | iface_len = ADC3XXX_IFACE_24BITS; |
1169 | width = 24; |
1170 | break; |
1171 | case 32: |
1172 | iface_len = ADC3XXX_IFACE_32BITS; |
1173 | width = 32; |
1174 | break; |
1175 | default: |
1176 | dev_err(component->dev, "Unsupported serial data format\n" ); |
1177 | return -EINVAL; |
1178 | } |
1179 | snd_soc_component_update_bits(component, ADC3XXX_INTERFACE_CTRL_1, |
1180 | ADC3XXX_WLENGTH_MASK, val: iface_len); |
1181 | if (adc3xxx_divs[i].pll_p) { /* If PLL used for this mode */ |
1182 | adc3xxx_setup_pll(component, div_entry: i); |
1183 | snd_soc_component_write(component, ADC3XXX_CLKGEN_MUX, ADC3XXX_USE_PLL); |
1184 | if (!adc3xxx->use_pll) { |
1185 | snd_soc_dapm_add_routes(dapm, route: adc3xxx_pll_intercon, |
1186 | ARRAY_SIZE(adc3xxx_pll_intercon)); |
1187 | adc3xxx->use_pll = 1; |
1188 | } |
1189 | } else { |
1190 | snd_soc_component_write(component, ADC3XXX_CLKGEN_MUX, ADC3XXX_NO_PLL); |
1191 | if (adc3xxx->use_pll) { |
1192 | snd_soc_dapm_del_routes(dapm, route: adc3xxx_pll_intercon, |
1193 | ARRAY_SIZE(adc3xxx_pll_intercon)); |
1194 | adc3xxx->use_pll = 0; |
1195 | } |
1196 | } |
1197 | |
1198 | /* NADC */ |
1199 | snd_soc_component_update_bits(component, ADC3XXX_ADC_NADC, |
1200 | ADC3XXX_NADC_MASK, val: adc3xxx_divs[i].nadc); |
1201 | /* MADC */ |
1202 | snd_soc_component_update_bits(component, ADC3XXX_ADC_MADC, |
1203 | ADC3XXX_MADC_MASK, val: adc3xxx_divs[i].madc); |
1204 | /* AOSR */ |
1205 | snd_soc_component_update_bits(component, ADC3XXX_ADC_AOSR, |
1206 | ADC3XXX_AOSR_MASK, val: adc3xxx_divs[i].aosr); |
1207 | /* BDIV N Value */ |
1208 | /* BCLK is (by default) set up to be derived from ADC_CLK */ |
1209 | bdiv = (adc3xxx_divs[i].aosr * adc3xxx_divs[i].madc) / (2 * width); |
1210 | snd_soc_component_update_bits(component, ADC3XXX_BCLK_N_DIV, |
1211 | ADC3XXX_BDIV_MASK, val: bdiv); |
1212 | |
1213 | return 0; |
1214 | } |
1215 | |
1216 | static const char *adc3xxx_pll_mode_text(int pll_mode) |
1217 | { |
1218 | switch (pll_mode) { |
1219 | case ADC3XXX_PLL_AUTO: |
1220 | return "PLL auto" ; |
1221 | case ADC3XXX_PLL_ENABLE: |
1222 | return "PLL enable" ; |
1223 | case ADC3XXX_PLL_BYPASS: |
1224 | return "PLL bypass" ; |
1225 | default: |
1226 | break; |
1227 | } |
1228 | |
1229 | return "PLL unknown" ; |
1230 | } |
1231 | |
1232 | static int adc3xxx_set_dai_sysclk(struct snd_soc_dai *codec_dai, |
1233 | int clk_id, unsigned int freq, int dir) |
1234 | { |
1235 | struct snd_soc_component *component = codec_dai->component; |
1236 | struct adc3xxx *adc3xxx = snd_soc_component_get_drvdata(c: component); |
1237 | int ret; |
1238 | |
1239 | ret = adc3xxx_parse_pll_mode(val: clk_id, pll_mode: &adc3xxx->pll_mode); |
1240 | if (ret < 0) |
1241 | return ret; |
1242 | |
1243 | adc3xxx->sysclk = freq; |
1244 | dev_dbg(component->dev, "Set sysclk to %u Hz, %s\n" , |
1245 | freq, adc3xxx_pll_mode_text(adc3xxx->pll_mode)); |
1246 | return 0; |
1247 | } |
1248 | |
1249 | static int adc3xxx_set_dai_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt) |
1250 | { |
1251 | struct snd_soc_component *component = codec_dai->component; |
1252 | struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component); |
1253 | struct adc3xxx *adc3xxx = snd_soc_component_get_drvdata(c: component); |
1254 | u8 clkdir = 0, format = 0; |
1255 | int master = 0; |
1256 | int ret; |
1257 | |
1258 | switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) { |
1259 | case SND_SOC_DAIFMT_CBP_CFP: |
1260 | master = 1; |
1261 | clkdir = ADC3XXX_BCLK_MASTER | ADC3XXX_WCLK_MASTER; |
1262 | break; |
1263 | case SND_SOC_DAIFMT_CBC_CFC: |
1264 | master = 0; |
1265 | break; |
1266 | default: |
1267 | dev_err(component->dev, "Invalid DAI clock setup\n" ); |
1268 | return -EINVAL; |
1269 | } |
1270 | |
1271 | /* |
1272 | * match both interface format and signal polarities since they |
1273 | * are fixed |
1274 | */ |
1275 | switch (fmt & (SND_SOC_DAIFMT_FORMAT_MASK | SND_SOC_DAIFMT_INV_MASK)) { |
1276 | case SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF: |
1277 | format = ADC3XXX_FORMAT_I2S; |
1278 | break; |
1279 | case SND_SOC_DAIFMT_DSP_A | SND_SOC_DAIFMT_IB_NF: |
1280 | format = ADC3XXX_FORMAT_DSP; |
1281 | break; |
1282 | case SND_SOC_DAIFMT_DSP_B | SND_SOC_DAIFMT_IB_NF: |
1283 | format = ADC3XXX_FORMAT_DSP; |
1284 | break; |
1285 | case SND_SOC_DAIFMT_RIGHT_J | SND_SOC_DAIFMT_NB_NF: |
1286 | format = ADC3XXX_FORMAT_RJF; |
1287 | break; |
1288 | case SND_SOC_DAIFMT_LEFT_J | SND_SOC_DAIFMT_NB_NF: |
1289 | format = ADC3XXX_FORMAT_LJF; |
1290 | break; |
1291 | default: |
1292 | dev_err(component->dev, "Invalid DAI format\n" ); |
1293 | return -EINVAL; |
1294 | } |
1295 | |
1296 | /* Add/del route enabling BCLK output as applicable */ |
1297 | if (master && !adc3xxx->master) |
1298 | snd_soc_dapm_add_routes(dapm, route: adc3xxx_bclk_out_intercon, |
1299 | ARRAY_SIZE(adc3xxx_bclk_out_intercon)); |
1300 | else if (!master && adc3xxx->master) |
1301 | snd_soc_dapm_del_routes(dapm, route: adc3xxx_bclk_out_intercon, |
1302 | ARRAY_SIZE(adc3xxx_bclk_out_intercon)); |
1303 | adc3xxx->master = master; |
1304 | |
1305 | /* set clock direction and format */ |
1306 | ret = snd_soc_component_update_bits(component, |
1307 | ADC3XXX_INTERFACE_CTRL_1, |
1308 | ADC3XXX_CLKDIR_MASK | ADC3XXX_FORMAT_MASK, |
1309 | val: clkdir | format); |
1310 | if (ret < 0) |
1311 | return ret; |
1312 | return 0; |
1313 | } |
1314 | |
1315 | static const struct snd_soc_dai_ops adc3xxx_dai_ops = { |
1316 | .hw_params = adc3xxx_hw_params, |
1317 | .set_sysclk = adc3xxx_set_dai_sysclk, |
1318 | .set_fmt = adc3xxx_set_dai_fmt, |
1319 | }; |
1320 | |
1321 | static struct snd_soc_dai_driver adc3xxx_dai = { |
1322 | .name = "tlv320adc3xxx-hifi" , |
1323 | .capture = { |
1324 | .stream_name = "Capture" , |
1325 | .channels_min = 1, |
1326 | .channels_max = 2, |
1327 | .rates = ADC3XXX_RATES, |
1328 | .formats = ADC3XXX_FORMATS, |
1329 | }, |
1330 | .ops = &adc3xxx_dai_ops, |
1331 | }; |
1332 | |
1333 | static const struct snd_soc_component_driver soc_component_dev_adc3xxx = { |
1334 | .controls = adc3xxx_snd_controls, |
1335 | .num_controls = ARRAY_SIZE(adc3xxx_snd_controls), |
1336 | .dapm_widgets = adc3xxx_dapm_widgets, |
1337 | .num_dapm_widgets = ARRAY_SIZE(adc3xxx_dapm_widgets), |
1338 | .dapm_routes = adc3xxx_intercon, |
1339 | .num_dapm_routes = ARRAY_SIZE(adc3xxx_intercon), |
1340 | .endianness = 1, |
1341 | }; |
1342 | |
1343 | static const struct i2c_device_id adc3xxx_i2c_id[] = { |
1344 | { "tlv320adc3001" , ADC3001 }, |
1345 | { "tlv320adc3101" , ADC3101 }, |
1346 | {} |
1347 | }; |
1348 | MODULE_DEVICE_TABLE(i2c, adc3xxx_i2c_id); |
1349 | |
1350 | static int adc3xxx_i2c_probe(struct i2c_client *i2c) |
1351 | { |
1352 | struct device *dev = &i2c->dev; |
1353 | struct adc3xxx *adc3xxx = NULL; |
1354 | const struct i2c_device_id *id; |
1355 | int ret; |
1356 | |
1357 | adc3xxx = devm_kzalloc(dev, size: sizeof(struct adc3xxx), GFP_KERNEL); |
1358 | if (!adc3xxx) |
1359 | return -ENOMEM; |
1360 | adc3xxx->dev = dev; |
1361 | |
1362 | adc3xxx->rst_pin = devm_gpiod_get(dev, con_id: "reset" , flags: GPIOD_OUT_LOW); |
1363 | if (IS_ERR(ptr: adc3xxx->rst_pin)) { |
1364 | return dev_err_probe(dev, err: PTR_ERR(ptr: adc3xxx->rst_pin), |
1365 | fmt: "Failed to request rst_pin\n" ); |
1366 | } |
1367 | |
1368 | adc3xxx->mclk = devm_clk_get(dev, NULL); |
1369 | if (IS_ERR(ptr: adc3xxx->mclk)) { |
1370 | /* |
1371 | * The chip itself supports running off the BCLK either |
1372 | * directly or via the PLL, but the driver does not (yet), so |
1373 | * having a specified mclk is required. Otherwise, we could |
1374 | * use the lack of a clocks property to indicate when BCLK is |
1375 | * intended as the clock source. |
1376 | */ |
1377 | return dev_err_probe(dev, err: PTR_ERR(ptr: adc3xxx->mclk), |
1378 | fmt: "Failed to acquire MCLK\n" ); |
1379 | } else if (adc3xxx->mclk) { |
1380 | ret = clk_prepare_enable(clk: adc3xxx->mclk); |
1381 | if (ret < 0) |
1382 | return ret; |
1383 | dev_dbg(dev, "Enabled MCLK, freq %lu Hz\n" , clk_get_rate(adc3xxx->mclk)); |
1384 | } |
1385 | |
1386 | ret = adc3xxx_parse_dt_gpio(adc3xxx, propname: "ti,dmdin-gpio1" , cfg: &adc3xxx->gpio_cfg[0]); |
1387 | if (ret < 0) |
1388 | goto err_unprepare_mclk; |
1389 | ret = adc3xxx_parse_dt_gpio(adc3xxx, propname: "ti,dmclk-gpio2" , cfg: &adc3xxx->gpio_cfg[1]); |
1390 | if (ret < 0) |
1391 | goto err_unprepare_mclk; |
1392 | ret = adc3xxx_parse_dt_micbias(adc3xxx, propname: "ti,micbias1-vg" , vg: &adc3xxx->micbias_vg[0]); |
1393 | if (ret < 0) |
1394 | goto err_unprepare_mclk; |
1395 | ret = adc3xxx_parse_dt_micbias(adc3xxx, propname: "ti,micbias2-vg" , vg: &adc3xxx->micbias_vg[1]); |
1396 | if (ret < 0) |
1397 | goto err_unprepare_mclk; |
1398 | |
1399 | adc3xxx->regmap = devm_regmap_init_i2c(i2c, &adc3xxx_regmap); |
1400 | if (IS_ERR(ptr: adc3xxx->regmap)) { |
1401 | ret = PTR_ERR(ptr: adc3xxx->regmap); |
1402 | goto err_unprepare_mclk; |
1403 | } |
1404 | |
1405 | i2c_set_clientdata(client: i2c, data: adc3xxx); |
1406 | |
1407 | id = i2c_match_id(id: adc3xxx_i2c_id, client: i2c); |
1408 | adc3xxx->type = id->driver_data; |
1409 | |
1410 | /* Reset codec chip */ |
1411 | gpiod_set_value_cansleep(desc: adc3xxx->rst_pin, value: 1); |
1412 | usleep_range(min: 2000, max: 100000); /* Requirement: > 10 ns (datasheet p13) */ |
1413 | gpiod_set_value_cansleep(desc: adc3xxx->rst_pin, value: 0); |
1414 | |
1415 | /* Potentially set up pins used as GPIOs */ |
1416 | adc3xxx_init_gpio(adc3xxx); |
1417 | |
1418 | ret = snd_soc_register_component(dev, |
1419 | component_driver: &soc_component_dev_adc3xxx, dai_drv: &adc3xxx_dai, num_dai: 1); |
1420 | if (ret < 0) { |
1421 | dev_err(dev, "Failed to register codec: %d\n" , ret); |
1422 | goto err_unprepare_mclk; |
1423 | } |
1424 | |
1425 | return 0; |
1426 | |
1427 | err_unprepare_mclk: |
1428 | clk_disable_unprepare(clk: adc3xxx->mclk); |
1429 | return ret; |
1430 | } |
1431 | |
1432 | static void adc3xxx_i2c_remove(struct i2c_client *client) |
1433 | { |
1434 | struct adc3xxx *adc3xxx = i2c_get_clientdata(client); |
1435 | |
1436 | if (adc3xxx->mclk) |
1437 | clk_disable_unprepare(clk: adc3xxx->mclk); |
1438 | adc3xxx_free_gpio(adc3xxx); |
1439 | snd_soc_unregister_component(dev: &client->dev); |
1440 | } |
1441 | |
1442 | static const struct of_device_id tlv320adc3xxx_of_match[] = { |
1443 | { .compatible = "ti,tlv320adc3001" , }, |
1444 | { .compatible = "ti,tlv320adc3101" , }, |
1445 | {}, |
1446 | }; |
1447 | MODULE_DEVICE_TABLE(of, tlv320adc3xxx_of_match); |
1448 | |
1449 | static struct i2c_driver adc3xxx_i2c_driver = { |
1450 | .driver = { |
1451 | .name = "tlv320adc3xxx-codec" , |
1452 | .of_match_table = tlv320adc3xxx_of_match, |
1453 | }, |
1454 | .probe = adc3xxx_i2c_probe, |
1455 | .remove = adc3xxx_i2c_remove, |
1456 | .id_table = adc3xxx_i2c_id, |
1457 | }; |
1458 | |
1459 | module_i2c_driver(adc3xxx_i2c_driver); |
1460 | |
1461 | MODULE_DESCRIPTION("ASoC TLV320ADC3xxx codec driver" ); |
1462 | MODULE_AUTHOR("shahina.s@mistralsolutions.com" ); |
1463 | MODULE_LICENSE("GPL v2" ); |
1464 | |