1 | // SPDX-License-Identifier: GPL-2.0-only |
2 | /* |
3 | * ALSA SoC Texas Instruments TLV320DAC33 codec driver |
4 | * |
5 | * Author: Peter Ujfalusi <peter.ujfalusi@ti.com> |
6 | * |
7 | * Copyright: (C) 2009 Nokia Corporation |
8 | */ |
9 | |
10 | #include <linux/module.h> |
11 | #include <linux/moduleparam.h> |
12 | #include <linux/init.h> |
13 | #include <linux/delay.h> |
14 | #include <linux/pm.h> |
15 | #include <linux/i2c.h> |
16 | #include <linux/interrupt.h> |
17 | #include <linux/gpio.h> |
18 | #include <linux/regulator/consumer.h> |
19 | #include <linux/slab.h> |
20 | #include <sound/core.h> |
21 | #include <sound/pcm.h> |
22 | #include <sound/pcm_params.h> |
23 | #include <sound/soc.h> |
24 | #include <sound/initval.h> |
25 | #include <sound/tlv.h> |
26 | |
27 | #include <sound/tlv320dac33-plat.h> |
28 | #include "tlv320dac33.h" |
29 | |
30 | /* |
31 | * The internal FIFO is 24576 bytes long |
32 | * It can be configured to hold 16bit or 24bit samples |
33 | * In 16bit configuration the FIFO can hold 6144 stereo samples |
34 | * In 24bit configuration the FIFO can hold 4096 stereo samples |
35 | */ |
36 | #define DAC33_FIFO_SIZE_16BIT 6144 |
37 | #define DAC33_FIFO_SIZE_24BIT 4096 |
38 | #define DAC33_MODE7_MARGIN 10 /* Safety margin for FIFO in Mode7 */ |
39 | |
40 | #define BURST_BASEFREQ_HZ 49152000 |
41 | |
42 | #define SAMPLES_TO_US(rate, samples) \ |
43 | (1000000000 / (((rate) * 1000) / (samples))) |
44 | |
45 | #define US_TO_SAMPLES(rate, us) \ |
46 | ((rate) / (1000000 / ((us) < 1000000 ? (us) : 1000000))) |
47 | |
48 | #define UTHR_FROM_PERIOD_SIZE(samples, playrate, burstrate) \ |
49 | (((samples)*5000) / (((burstrate)*5000) / ((burstrate) - (playrate)))) |
50 | |
51 | static void dac33_calculate_times(struct snd_pcm_substream *substream, |
52 | struct snd_soc_component *component); |
53 | static int dac33_prepare_chip(struct snd_pcm_substream *substream, |
54 | struct snd_soc_component *component); |
55 | |
56 | enum dac33_state { |
57 | DAC33_IDLE = 0, |
58 | DAC33_PREFILL, |
59 | DAC33_PLAYBACK, |
60 | DAC33_FLUSH, |
61 | }; |
62 | |
63 | enum dac33_fifo_modes { |
64 | DAC33_FIFO_BYPASS = 0, |
65 | DAC33_FIFO_MODE1, |
66 | DAC33_FIFO_MODE7, |
67 | DAC33_FIFO_LAST_MODE, |
68 | }; |
69 | |
70 | #define DAC33_NUM_SUPPLIES 3 |
71 | static const char *dac33_supply_names[DAC33_NUM_SUPPLIES] = { |
72 | "AVDD" , |
73 | "DVDD" , |
74 | "IOVDD" , |
75 | }; |
76 | |
77 | struct tlv320dac33_priv { |
78 | struct mutex mutex; |
79 | struct work_struct work; |
80 | struct snd_soc_component *component; |
81 | struct regulator_bulk_data supplies[DAC33_NUM_SUPPLIES]; |
82 | struct snd_pcm_substream *substream; |
83 | int power_gpio; |
84 | int chip_power; |
85 | int irq; |
86 | unsigned int refclk; |
87 | |
88 | unsigned int alarm_threshold; /* set to be half of LATENCY_TIME_MS */ |
89 | enum dac33_fifo_modes fifo_mode;/* FIFO mode selection */ |
90 | unsigned int fifo_size; /* Size of the FIFO in samples */ |
91 | unsigned int nsample; /* burst read amount from host */ |
92 | int mode1_latency; /* latency caused by the i2c writes in |
93 | * us */ |
94 | u8 burst_bclkdiv; /* BCLK divider value in burst mode */ |
95 | u8 *reg_cache; |
96 | unsigned int burst_rate; /* Interface speed in Burst modes */ |
97 | |
98 | int keep_bclk; /* Keep the BCLK continuously running |
99 | * in FIFO modes */ |
100 | spinlock_t lock; |
101 | unsigned long long t_stamp1; /* Time stamp for FIFO modes to */ |
102 | unsigned long long t_stamp2; /* calculate the FIFO caused delay */ |
103 | |
104 | unsigned int mode1_us_burst; /* Time to burst read n number of |
105 | * samples */ |
106 | unsigned int mode7_us_to_lthr; /* Time to reach lthr from uthr */ |
107 | |
108 | unsigned int uthr; |
109 | |
110 | enum dac33_state state; |
111 | struct i2c_client *i2c; |
112 | }; |
113 | |
114 | static const u8 dac33_reg[DAC33_CACHEREGNUM] = { |
115 | 0x00, 0x00, 0x00, 0x00, /* 0x00 - 0x03 */ |
116 | 0x00, 0x00, 0x00, 0x00, /* 0x04 - 0x07 */ |
117 | 0x00, 0x00, 0x00, 0x00, /* 0x08 - 0x0b */ |
118 | 0x00, 0x00, 0x00, 0x00, /* 0x0c - 0x0f */ |
119 | 0x00, 0x00, 0x00, 0x00, /* 0x10 - 0x13 */ |
120 | 0x00, 0x00, 0x00, 0x00, /* 0x14 - 0x17 */ |
121 | 0x00, 0x00, 0x00, 0x00, /* 0x18 - 0x1b */ |
122 | 0x00, 0x00, 0x00, 0x00, /* 0x1c - 0x1f */ |
123 | 0x00, 0x00, 0x00, 0x00, /* 0x20 - 0x23 */ |
124 | 0x00, 0x00, 0x00, 0x00, /* 0x24 - 0x27 */ |
125 | 0x00, 0x00, 0x00, 0x00, /* 0x28 - 0x2b */ |
126 | 0x00, 0x00, 0x00, 0x80, /* 0x2c - 0x2f */ |
127 | 0x80, 0x00, 0x00, 0x00, /* 0x30 - 0x33 */ |
128 | 0x00, 0x00, 0x00, 0x00, /* 0x34 - 0x37 */ |
129 | 0x00, 0x00, /* 0x38 - 0x39 */ |
130 | /* Registers 0x3a - 0x3f are reserved */ |
131 | 0x00, 0x00, /* 0x3a - 0x3b */ |
132 | 0x00, 0x00, 0x00, 0x00, /* 0x3c - 0x3f */ |
133 | |
134 | 0x00, 0x00, 0x00, 0x00, /* 0x40 - 0x43 */ |
135 | 0x00, 0x80, /* 0x44 - 0x45 */ |
136 | /* Registers 0x46 - 0x47 are reserved */ |
137 | 0x80, 0x80, /* 0x46 - 0x47 */ |
138 | |
139 | 0x80, 0x00, 0x00, /* 0x48 - 0x4a */ |
140 | /* Registers 0x4b - 0x7c are reserved */ |
141 | 0x00, /* 0x4b */ |
142 | 0x00, 0x00, 0x00, 0x00, /* 0x4c - 0x4f */ |
143 | 0x00, 0x00, 0x00, 0x00, /* 0x50 - 0x53 */ |
144 | 0x00, 0x00, 0x00, 0x00, /* 0x54 - 0x57 */ |
145 | 0x00, 0x00, 0x00, 0x00, /* 0x58 - 0x5b */ |
146 | 0x00, 0x00, 0x00, 0x00, /* 0x5c - 0x5f */ |
147 | 0x00, 0x00, 0x00, 0x00, /* 0x60 - 0x63 */ |
148 | 0x00, 0x00, 0x00, 0x00, /* 0x64 - 0x67 */ |
149 | 0x00, 0x00, 0x00, 0x00, /* 0x68 - 0x6b */ |
150 | 0x00, 0x00, 0x00, 0x00, /* 0x6c - 0x6f */ |
151 | 0x00, 0x00, 0x00, 0x00, /* 0x70 - 0x73 */ |
152 | 0x00, 0x00, 0x00, 0x00, /* 0x74 - 0x77 */ |
153 | 0x00, 0x00, 0x00, 0x00, /* 0x78 - 0x7b */ |
154 | 0x00, /* 0x7c */ |
155 | |
156 | 0xda, 0x33, 0x03, /* 0x7d - 0x7f */ |
157 | }; |
158 | |
159 | /* Register read and write */ |
160 | static inline unsigned int dac33_read_reg_cache(struct snd_soc_component *component, |
161 | unsigned reg) |
162 | { |
163 | struct tlv320dac33_priv *dac33 = snd_soc_component_get_drvdata(c: component); |
164 | u8 *cache = dac33->reg_cache; |
165 | if (reg >= DAC33_CACHEREGNUM) |
166 | return 0; |
167 | |
168 | return cache[reg]; |
169 | } |
170 | |
171 | static inline void dac33_write_reg_cache(struct snd_soc_component *component, |
172 | u8 reg, u8 value) |
173 | { |
174 | struct tlv320dac33_priv *dac33 = snd_soc_component_get_drvdata(c: component); |
175 | u8 *cache = dac33->reg_cache; |
176 | if (reg >= DAC33_CACHEREGNUM) |
177 | return; |
178 | |
179 | cache[reg] = value; |
180 | } |
181 | |
182 | static int dac33_read(struct snd_soc_component *component, unsigned int reg, |
183 | u8 *value) |
184 | { |
185 | struct tlv320dac33_priv *dac33 = snd_soc_component_get_drvdata(c: component); |
186 | int val, ret = 0; |
187 | |
188 | *value = reg & 0xff; |
189 | |
190 | /* If powered off, return the cached value */ |
191 | if (dac33->chip_power) { |
192 | val = i2c_smbus_read_byte_data(client: dac33->i2c, command: value[0]); |
193 | if (val < 0) { |
194 | dev_err(component->dev, "Read failed (%d)\n" , val); |
195 | value[0] = dac33_read_reg_cache(component, reg); |
196 | ret = val; |
197 | } else { |
198 | value[0] = val; |
199 | dac33_write_reg_cache(component, reg, value: val); |
200 | } |
201 | } else { |
202 | value[0] = dac33_read_reg_cache(component, reg); |
203 | } |
204 | |
205 | return ret; |
206 | } |
207 | |
208 | static int dac33_write(struct snd_soc_component *component, unsigned int reg, |
209 | unsigned int value) |
210 | { |
211 | struct tlv320dac33_priv *dac33 = snd_soc_component_get_drvdata(c: component); |
212 | u8 data[2]; |
213 | int ret = 0; |
214 | |
215 | /* |
216 | * data is |
217 | * D15..D8 dac33 register offset |
218 | * D7...D0 register data |
219 | */ |
220 | data[0] = reg & 0xff; |
221 | data[1] = value & 0xff; |
222 | |
223 | dac33_write_reg_cache(component, reg: data[0], value: data[1]); |
224 | if (dac33->chip_power) { |
225 | ret = i2c_master_send(client: dac33->i2c, buf: data, count: 2); |
226 | if (ret != 2) |
227 | dev_err(component->dev, "Write failed (%d)\n" , ret); |
228 | else |
229 | ret = 0; |
230 | } |
231 | |
232 | return ret; |
233 | } |
234 | |
235 | static int dac33_write_locked(struct snd_soc_component *component, unsigned int reg, |
236 | unsigned int value) |
237 | { |
238 | struct tlv320dac33_priv *dac33 = snd_soc_component_get_drvdata(c: component); |
239 | int ret; |
240 | |
241 | mutex_lock(&dac33->mutex); |
242 | ret = dac33_write(component, reg, value); |
243 | mutex_unlock(lock: &dac33->mutex); |
244 | |
245 | return ret; |
246 | } |
247 | |
248 | #define DAC33_I2C_ADDR_AUTOINC 0x80 |
249 | static int dac33_write16(struct snd_soc_component *component, unsigned int reg, |
250 | unsigned int value) |
251 | { |
252 | struct tlv320dac33_priv *dac33 = snd_soc_component_get_drvdata(c: component); |
253 | u8 data[3]; |
254 | int ret = 0; |
255 | |
256 | /* |
257 | * data is |
258 | * D23..D16 dac33 register offset |
259 | * D15..D8 register data MSB |
260 | * D7...D0 register data LSB |
261 | */ |
262 | data[0] = reg & 0xff; |
263 | data[1] = (value >> 8) & 0xff; |
264 | data[2] = value & 0xff; |
265 | |
266 | dac33_write_reg_cache(component, reg: data[0], value: data[1]); |
267 | dac33_write_reg_cache(component, reg: data[0] + 1, value: data[2]); |
268 | |
269 | if (dac33->chip_power) { |
270 | /* We need to set autoincrement mode for 16 bit writes */ |
271 | data[0] |= DAC33_I2C_ADDR_AUTOINC; |
272 | ret = i2c_master_send(client: dac33->i2c, buf: data, count: 3); |
273 | if (ret != 3) |
274 | dev_err(component->dev, "Write failed (%d)\n" , ret); |
275 | else |
276 | ret = 0; |
277 | } |
278 | |
279 | return ret; |
280 | } |
281 | |
282 | static void dac33_init_chip(struct snd_soc_component *component) |
283 | { |
284 | struct tlv320dac33_priv *dac33 = snd_soc_component_get_drvdata(c: component); |
285 | |
286 | if (unlikely(!dac33->chip_power)) |
287 | return; |
288 | |
289 | /* A : DAC sample rate Fsref/1.5 */ |
290 | dac33_write(component, DAC33_DAC_CTRL_A, DAC33_DACRATE(0)); |
291 | /* B : DAC src=normal, not muted */ |
292 | dac33_write(component, DAC33_DAC_CTRL_B, DAC33_DACSRCR_RIGHT | |
293 | DAC33_DACSRCL_LEFT); |
294 | /* C : (defaults) */ |
295 | dac33_write(component, DAC33_DAC_CTRL_C, value: 0x00); |
296 | |
297 | /* 73 : volume soft stepping control, |
298 | clock source = internal osc (?) */ |
299 | dac33_write(component, DAC33_ANA_VOL_SOFT_STEP_CTRL, DAC33_VOLCLKEN); |
300 | |
301 | /* Restore only selected registers (gains mostly) */ |
302 | dac33_write(component, DAC33_LDAC_DIG_VOL_CTRL, |
303 | value: dac33_read_reg_cache(component, DAC33_LDAC_DIG_VOL_CTRL)); |
304 | dac33_write(component, DAC33_RDAC_DIG_VOL_CTRL, |
305 | value: dac33_read_reg_cache(component, DAC33_RDAC_DIG_VOL_CTRL)); |
306 | |
307 | dac33_write(component, DAC33_LINEL_TO_LLO_VOL, |
308 | value: dac33_read_reg_cache(component, DAC33_LINEL_TO_LLO_VOL)); |
309 | dac33_write(component, DAC33_LINER_TO_RLO_VOL, |
310 | value: dac33_read_reg_cache(component, DAC33_LINER_TO_RLO_VOL)); |
311 | |
312 | dac33_write(component, DAC33_OUT_AMP_CTRL, |
313 | value: dac33_read_reg_cache(component, DAC33_OUT_AMP_CTRL)); |
314 | |
315 | dac33_write(component, DAC33_LDAC_PWR_CTRL, |
316 | value: dac33_read_reg_cache(component, DAC33_LDAC_PWR_CTRL)); |
317 | dac33_write(component, DAC33_RDAC_PWR_CTRL, |
318 | value: dac33_read_reg_cache(component, DAC33_RDAC_PWR_CTRL)); |
319 | } |
320 | |
321 | static inline int dac33_read_id(struct snd_soc_component *component) |
322 | { |
323 | int i, ret = 0; |
324 | u8 reg; |
325 | |
326 | for (i = 0; i < 3; i++) { |
327 | ret = dac33_read(component, DAC33_DEVICE_ID_MSB + i, value: ®); |
328 | if (ret < 0) |
329 | break; |
330 | } |
331 | |
332 | return ret; |
333 | } |
334 | |
335 | static inline void dac33_soft_power(struct snd_soc_component *component, int power) |
336 | { |
337 | u8 reg; |
338 | |
339 | reg = dac33_read_reg_cache(component, DAC33_PWR_CTRL); |
340 | if (power) |
341 | reg |= DAC33_PDNALLB; |
342 | else |
343 | reg &= ~(DAC33_PDNALLB | DAC33_OSCPDNB | |
344 | DAC33_DACRPDNB | DAC33_DACLPDNB); |
345 | dac33_write(component, DAC33_PWR_CTRL, value: reg); |
346 | } |
347 | |
348 | static inline void dac33_disable_digital(struct snd_soc_component *component) |
349 | { |
350 | u8 reg; |
351 | |
352 | /* Stop the DAI clock */ |
353 | reg = dac33_read_reg_cache(component, DAC33_SER_AUDIOIF_CTRL_B); |
354 | reg &= ~DAC33_BCLKON; |
355 | dac33_write(component, DAC33_SER_AUDIOIF_CTRL_B, value: reg); |
356 | |
357 | /* Power down the Oscillator, and DACs */ |
358 | reg = dac33_read_reg_cache(component, DAC33_PWR_CTRL); |
359 | reg &= ~(DAC33_OSCPDNB | DAC33_DACRPDNB | DAC33_DACLPDNB); |
360 | dac33_write(component, DAC33_PWR_CTRL, value: reg); |
361 | } |
362 | |
363 | static int dac33_hard_power(struct snd_soc_component *component, int power) |
364 | { |
365 | struct tlv320dac33_priv *dac33 = snd_soc_component_get_drvdata(c: component); |
366 | int ret = 0; |
367 | |
368 | mutex_lock(&dac33->mutex); |
369 | |
370 | /* Safety check */ |
371 | if (unlikely(power == dac33->chip_power)) { |
372 | dev_dbg(component->dev, "Trying to set the same power state: %s\n" , |
373 | power ? "ON" : "OFF" ); |
374 | goto exit; |
375 | } |
376 | |
377 | if (power) { |
378 | ret = regulator_bulk_enable(ARRAY_SIZE(dac33->supplies), |
379 | consumers: dac33->supplies); |
380 | if (ret != 0) { |
381 | dev_err(component->dev, |
382 | "Failed to enable supplies: %d\n" , ret); |
383 | goto exit; |
384 | } |
385 | |
386 | if (dac33->power_gpio >= 0) |
387 | gpio_set_value(gpio: dac33->power_gpio, value: 1); |
388 | |
389 | dac33->chip_power = 1; |
390 | } else { |
391 | dac33_soft_power(component, power: 0); |
392 | if (dac33->power_gpio >= 0) |
393 | gpio_set_value(gpio: dac33->power_gpio, value: 0); |
394 | |
395 | ret = regulator_bulk_disable(ARRAY_SIZE(dac33->supplies), |
396 | consumers: dac33->supplies); |
397 | if (ret != 0) { |
398 | dev_err(component->dev, |
399 | "Failed to disable supplies: %d\n" , ret); |
400 | goto exit; |
401 | } |
402 | |
403 | dac33->chip_power = 0; |
404 | } |
405 | |
406 | exit: |
407 | mutex_unlock(lock: &dac33->mutex); |
408 | return ret; |
409 | } |
410 | |
411 | static int dac33_playback_event(struct snd_soc_dapm_widget *w, |
412 | struct snd_kcontrol *kcontrol, int event) |
413 | { |
414 | struct snd_soc_component *component = snd_soc_dapm_to_component(dapm: w->dapm); |
415 | struct tlv320dac33_priv *dac33 = snd_soc_component_get_drvdata(c: component); |
416 | |
417 | switch (event) { |
418 | case SND_SOC_DAPM_PRE_PMU: |
419 | if (likely(dac33->substream)) { |
420 | dac33_calculate_times(substream: dac33->substream, component); |
421 | dac33_prepare_chip(substream: dac33->substream, component); |
422 | } |
423 | break; |
424 | case SND_SOC_DAPM_POST_PMD: |
425 | dac33_disable_digital(component); |
426 | break; |
427 | } |
428 | return 0; |
429 | } |
430 | |
431 | static int dac33_get_fifo_mode(struct snd_kcontrol *kcontrol, |
432 | struct snd_ctl_elem_value *ucontrol) |
433 | { |
434 | struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); |
435 | struct tlv320dac33_priv *dac33 = snd_soc_component_get_drvdata(c: component); |
436 | |
437 | ucontrol->value.enumerated.item[0] = dac33->fifo_mode; |
438 | |
439 | return 0; |
440 | } |
441 | |
442 | static int dac33_set_fifo_mode(struct snd_kcontrol *kcontrol, |
443 | struct snd_ctl_elem_value *ucontrol) |
444 | { |
445 | struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); |
446 | struct tlv320dac33_priv *dac33 = snd_soc_component_get_drvdata(c: component); |
447 | int ret = 0; |
448 | |
449 | if (dac33->fifo_mode == ucontrol->value.enumerated.item[0]) |
450 | return 0; |
451 | /* Do not allow changes while stream is running*/ |
452 | if (snd_soc_component_active(component)) |
453 | return -EPERM; |
454 | |
455 | if (ucontrol->value.enumerated.item[0] >= DAC33_FIFO_LAST_MODE) |
456 | ret = -EINVAL; |
457 | else |
458 | dac33->fifo_mode = ucontrol->value.enumerated.item[0]; |
459 | |
460 | return ret; |
461 | } |
462 | |
463 | /* Codec operation modes */ |
464 | static const char *dac33_fifo_mode_texts[] = { |
465 | "Bypass" , "Mode 1" , "Mode 7" |
466 | }; |
467 | |
468 | static SOC_ENUM_SINGLE_EXT_DECL(dac33_fifo_mode_enum, dac33_fifo_mode_texts); |
469 | |
470 | /* L/R Line Output Gain */ |
471 | static const char *lr_lineout_gain_texts[] = { |
472 | "Line -12dB DAC 0dB" , "Line -6dB DAC 6dB" , |
473 | "Line 0dB DAC 12dB" , "Line 6dB DAC 18dB" , |
474 | }; |
475 | |
476 | static SOC_ENUM_SINGLE_DECL(l_lineout_gain_enum, |
477 | DAC33_LDAC_PWR_CTRL, 0, |
478 | lr_lineout_gain_texts); |
479 | |
480 | static SOC_ENUM_SINGLE_DECL(r_lineout_gain_enum, |
481 | DAC33_RDAC_PWR_CTRL, 0, |
482 | lr_lineout_gain_texts); |
483 | |
484 | /* |
485 | * DACL/R digital volume control: |
486 | * from 0 dB to -63.5 in 0.5 dB steps |
487 | * Need to be inverted later on: |
488 | * 0x00 == 0 dB |
489 | * 0x7f == -63.5 dB |
490 | */ |
491 | static DECLARE_TLV_DB_SCALE(dac_digivol_tlv, -6350, 50, 0); |
492 | |
493 | static const struct snd_kcontrol_new dac33_snd_controls[] = { |
494 | SOC_DOUBLE_R_TLV("DAC Digital Playback Volume" , |
495 | DAC33_LDAC_DIG_VOL_CTRL, DAC33_RDAC_DIG_VOL_CTRL, |
496 | 0, 0x7f, 1, dac_digivol_tlv), |
497 | SOC_DOUBLE_R("DAC Digital Playback Switch" , |
498 | DAC33_LDAC_DIG_VOL_CTRL, DAC33_RDAC_DIG_VOL_CTRL, 7, 1, 1), |
499 | SOC_DOUBLE_R("Line to Line Out Volume" , |
500 | DAC33_LINEL_TO_LLO_VOL, DAC33_LINER_TO_RLO_VOL, 0, 127, 1), |
501 | SOC_ENUM("Left Line Output Gain" , l_lineout_gain_enum), |
502 | SOC_ENUM("Right Line Output Gain" , r_lineout_gain_enum), |
503 | }; |
504 | |
505 | static const struct snd_kcontrol_new dac33_mode_snd_controls[] = { |
506 | SOC_ENUM_EXT("FIFO Mode" , dac33_fifo_mode_enum, |
507 | dac33_get_fifo_mode, dac33_set_fifo_mode), |
508 | }; |
509 | |
510 | /* Analog bypass */ |
511 | static const struct snd_kcontrol_new dac33_dapm_abypassl_control = |
512 | SOC_DAPM_SINGLE("Switch" , DAC33_LINEL_TO_LLO_VOL, 7, 1, 1); |
513 | |
514 | static const struct snd_kcontrol_new dac33_dapm_abypassr_control = |
515 | SOC_DAPM_SINGLE("Switch" , DAC33_LINER_TO_RLO_VOL, 7, 1, 1); |
516 | |
517 | /* LOP L/R invert selection */ |
518 | static const char *dac33_lr_lom_texts[] = {"DAC" , "LOP" }; |
519 | |
520 | static SOC_ENUM_SINGLE_DECL(dac33_left_lom_enum, |
521 | DAC33_OUT_AMP_CTRL, 3, |
522 | dac33_lr_lom_texts); |
523 | |
524 | static const struct snd_kcontrol_new dac33_dapm_left_lom_control = |
525 | SOC_DAPM_ENUM("Route" , dac33_left_lom_enum); |
526 | |
527 | static SOC_ENUM_SINGLE_DECL(dac33_right_lom_enum, |
528 | DAC33_OUT_AMP_CTRL, 2, |
529 | dac33_lr_lom_texts); |
530 | |
531 | static const struct snd_kcontrol_new dac33_dapm_right_lom_control = |
532 | SOC_DAPM_ENUM("Route" , dac33_right_lom_enum); |
533 | |
534 | static const struct snd_soc_dapm_widget dac33_dapm_widgets[] = { |
535 | SND_SOC_DAPM_OUTPUT("LEFT_LO" ), |
536 | SND_SOC_DAPM_OUTPUT("RIGHT_LO" ), |
537 | |
538 | SND_SOC_DAPM_INPUT("LINEL" ), |
539 | SND_SOC_DAPM_INPUT("LINER" ), |
540 | |
541 | SND_SOC_DAPM_DAC("DACL" , "Left Playback" , SND_SOC_NOPM, 0, 0), |
542 | SND_SOC_DAPM_DAC("DACR" , "Right Playback" , SND_SOC_NOPM, 0, 0), |
543 | |
544 | /* Analog bypass */ |
545 | SND_SOC_DAPM_SWITCH("Analog Left Bypass" , SND_SOC_NOPM, 0, 0, |
546 | &dac33_dapm_abypassl_control), |
547 | SND_SOC_DAPM_SWITCH("Analog Right Bypass" , SND_SOC_NOPM, 0, 0, |
548 | &dac33_dapm_abypassr_control), |
549 | |
550 | SND_SOC_DAPM_MUX("Left LOM Inverted From" , SND_SOC_NOPM, 0, 0, |
551 | &dac33_dapm_left_lom_control), |
552 | SND_SOC_DAPM_MUX("Right LOM Inverted From" , SND_SOC_NOPM, 0, 0, |
553 | &dac33_dapm_right_lom_control), |
554 | /* |
555 | * For DAPM path, when only the anlog bypass path is enabled, and the |
556 | * LOP inverted from the corresponding DAC side. |
557 | * This is needed, so we can attach the DAC power supply in this case. |
558 | */ |
559 | SND_SOC_DAPM_PGA("Left Bypass PGA" , SND_SOC_NOPM, 0, 0, NULL, 0), |
560 | SND_SOC_DAPM_PGA("Right Bypass PGA" , SND_SOC_NOPM, 0, 0, NULL, 0), |
561 | |
562 | SND_SOC_DAPM_REG(snd_soc_dapm_mixer, "Output Left Amplifier" , |
563 | DAC33_OUT_AMP_PWR_CTRL, 6, 3, 3, 0), |
564 | SND_SOC_DAPM_REG(snd_soc_dapm_mixer, "Output Right Amplifier" , |
565 | DAC33_OUT_AMP_PWR_CTRL, 4, 3, 3, 0), |
566 | |
567 | SND_SOC_DAPM_SUPPLY("Left DAC Power" , |
568 | DAC33_LDAC_PWR_CTRL, 2, 0, NULL, 0), |
569 | SND_SOC_DAPM_SUPPLY("Right DAC Power" , |
570 | DAC33_RDAC_PWR_CTRL, 2, 0, NULL, 0), |
571 | |
572 | SND_SOC_DAPM_SUPPLY("Codec Power" , |
573 | DAC33_PWR_CTRL, 4, 0, NULL, 0), |
574 | |
575 | SND_SOC_DAPM_PRE("Pre Playback" , dac33_playback_event), |
576 | SND_SOC_DAPM_POST("Post Playback" , dac33_playback_event), |
577 | }; |
578 | |
579 | static const struct snd_soc_dapm_route audio_map[] = { |
580 | /* Analog bypass */ |
581 | {"Analog Left Bypass" , "Switch" , "LINEL" }, |
582 | {"Analog Right Bypass" , "Switch" , "LINER" }, |
583 | |
584 | {"Output Left Amplifier" , NULL, "DACL" }, |
585 | {"Output Right Amplifier" , NULL, "DACR" }, |
586 | |
587 | {"Left Bypass PGA" , NULL, "Analog Left Bypass" }, |
588 | {"Right Bypass PGA" , NULL, "Analog Right Bypass" }, |
589 | |
590 | {"Left LOM Inverted From" , "DAC" , "Left Bypass PGA" }, |
591 | {"Right LOM Inverted From" , "DAC" , "Right Bypass PGA" }, |
592 | {"Left LOM Inverted From" , "LOP" , "Analog Left Bypass" }, |
593 | {"Right LOM Inverted From" , "LOP" , "Analog Right Bypass" }, |
594 | |
595 | {"Output Left Amplifier" , NULL, "Left LOM Inverted From" }, |
596 | {"Output Right Amplifier" , NULL, "Right LOM Inverted From" }, |
597 | |
598 | {"DACL" , NULL, "Left DAC Power" }, |
599 | {"DACR" , NULL, "Right DAC Power" }, |
600 | |
601 | {"Left Bypass PGA" , NULL, "Left DAC Power" }, |
602 | {"Right Bypass PGA" , NULL, "Right DAC Power" }, |
603 | |
604 | /* output */ |
605 | {"LEFT_LO" , NULL, "Output Left Amplifier" }, |
606 | {"RIGHT_LO" , NULL, "Output Right Amplifier" }, |
607 | |
608 | {"LEFT_LO" , NULL, "Codec Power" }, |
609 | {"RIGHT_LO" , NULL, "Codec Power" }, |
610 | }; |
611 | |
612 | static int dac33_set_bias_level(struct snd_soc_component *component, |
613 | enum snd_soc_bias_level level) |
614 | { |
615 | int ret; |
616 | |
617 | switch (level) { |
618 | case SND_SOC_BIAS_ON: |
619 | break; |
620 | case SND_SOC_BIAS_PREPARE: |
621 | break; |
622 | case SND_SOC_BIAS_STANDBY: |
623 | if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF) { |
624 | /* Coming from OFF, switch on the component */ |
625 | ret = dac33_hard_power(component, power: 1); |
626 | if (ret != 0) |
627 | return ret; |
628 | |
629 | dac33_init_chip(component); |
630 | } |
631 | break; |
632 | case SND_SOC_BIAS_OFF: |
633 | /* Do not power off, when the component is already off */ |
634 | if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF) |
635 | return 0; |
636 | ret = dac33_hard_power(component, power: 0); |
637 | if (ret != 0) |
638 | return ret; |
639 | break; |
640 | } |
641 | |
642 | return 0; |
643 | } |
644 | |
645 | static inline void dac33_prefill_handler(struct tlv320dac33_priv *dac33) |
646 | { |
647 | struct snd_soc_component *component = dac33->component; |
648 | unsigned int delay; |
649 | unsigned long flags; |
650 | |
651 | switch (dac33->fifo_mode) { |
652 | case DAC33_FIFO_MODE1: |
653 | dac33_write16(component, DAC33_NSAMPLE_MSB, |
654 | DAC33_THRREG(dac33->nsample)); |
655 | |
656 | /* Take the timestamps */ |
657 | spin_lock_irqsave(&dac33->lock, flags); |
658 | dac33->t_stamp2 = ktime_to_us(kt: ktime_get()); |
659 | dac33->t_stamp1 = dac33->t_stamp2; |
660 | spin_unlock_irqrestore(lock: &dac33->lock, flags); |
661 | |
662 | dac33_write16(component, DAC33_PREFILL_MSB, |
663 | DAC33_THRREG(dac33->alarm_threshold)); |
664 | /* Enable Alarm Threshold IRQ with a delay */ |
665 | delay = SAMPLES_TO_US(dac33->burst_rate, |
666 | dac33->alarm_threshold) + 1000; |
667 | usleep_range(min: delay, max: delay + 500); |
668 | dac33_write(component, DAC33_FIFO_IRQ_MASK, DAC33_MAT); |
669 | break; |
670 | case DAC33_FIFO_MODE7: |
671 | /* Take the timestamp */ |
672 | spin_lock_irqsave(&dac33->lock, flags); |
673 | dac33->t_stamp1 = ktime_to_us(kt: ktime_get()); |
674 | /* Move back the timestamp with drain time */ |
675 | dac33->t_stamp1 -= dac33->mode7_us_to_lthr; |
676 | spin_unlock_irqrestore(lock: &dac33->lock, flags); |
677 | |
678 | dac33_write16(component, DAC33_PREFILL_MSB, |
679 | DAC33_THRREG(DAC33_MODE7_MARGIN)); |
680 | |
681 | /* Enable Upper Threshold IRQ */ |
682 | dac33_write(component, DAC33_FIFO_IRQ_MASK, DAC33_MUT); |
683 | break; |
684 | default: |
685 | dev_warn(component->dev, "Unhandled FIFO mode: %d\n" , |
686 | dac33->fifo_mode); |
687 | break; |
688 | } |
689 | } |
690 | |
691 | static inline void dac33_playback_handler(struct tlv320dac33_priv *dac33) |
692 | { |
693 | struct snd_soc_component *component = dac33->component; |
694 | unsigned long flags; |
695 | |
696 | switch (dac33->fifo_mode) { |
697 | case DAC33_FIFO_MODE1: |
698 | /* Take the timestamp */ |
699 | spin_lock_irqsave(&dac33->lock, flags); |
700 | dac33->t_stamp2 = ktime_to_us(kt: ktime_get()); |
701 | spin_unlock_irqrestore(lock: &dac33->lock, flags); |
702 | |
703 | dac33_write16(component, DAC33_NSAMPLE_MSB, |
704 | DAC33_THRREG(dac33->nsample)); |
705 | break; |
706 | case DAC33_FIFO_MODE7: |
707 | /* At the moment we are not using interrupts in mode7 */ |
708 | break; |
709 | default: |
710 | dev_warn(component->dev, "Unhandled FIFO mode: %d\n" , |
711 | dac33->fifo_mode); |
712 | break; |
713 | } |
714 | } |
715 | |
716 | static void dac33_work(struct work_struct *work) |
717 | { |
718 | struct snd_soc_component *component; |
719 | struct tlv320dac33_priv *dac33; |
720 | u8 reg; |
721 | |
722 | dac33 = container_of(work, struct tlv320dac33_priv, work); |
723 | component = dac33->component; |
724 | |
725 | mutex_lock(&dac33->mutex); |
726 | switch (dac33->state) { |
727 | case DAC33_PREFILL: |
728 | dac33->state = DAC33_PLAYBACK; |
729 | dac33_prefill_handler(dac33); |
730 | break; |
731 | case DAC33_PLAYBACK: |
732 | dac33_playback_handler(dac33); |
733 | break; |
734 | case DAC33_IDLE: |
735 | break; |
736 | case DAC33_FLUSH: |
737 | dac33->state = DAC33_IDLE; |
738 | /* Mask all interrupts from dac33 */ |
739 | dac33_write(component, DAC33_FIFO_IRQ_MASK, value: 0); |
740 | |
741 | /* flush fifo */ |
742 | reg = dac33_read_reg_cache(component, DAC33_FIFO_CTRL_A); |
743 | reg |= DAC33_FIFOFLUSH; |
744 | dac33_write(component, DAC33_FIFO_CTRL_A, value: reg); |
745 | break; |
746 | } |
747 | mutex_unlock(lock: &dac33->mutex); |
748 | } |
749 | |
750 | static irqreturn_t dac33_interrupt_handler(int irq, void *dev) |
751 | { |
752 | struct snd_soc_component *component = dev; |
753 | struct tlv320dac33_priv *dac33 = snd_soc_component_get_drvdata(c: component); |
754 | unsigned long flags; |
755 | |
756 | spin_lock_irqsave(&dac33->lock, flags); |
757 | dac33->t_stamp1 = ktime_to_us(kt: ktime_get()); |
758 | spin_unlock_irqrestore(lock: &dac33->lock, flags); |
759 | |
760 | /* Do not schedule the workqueue in Mode7 */ |
761 | if (dac33->fifo_mode != DAC33_FIFO_MODE7) |
762 | schedule_work(work: &dac33->work); |
763 | |
764 | return IRQ_HANDLED; |
765 | } |
766 | |
767 | static void dac33_oscwait(struct snd_soc_component *component) |
768 | { |
769 | int timeout = 60; |
770 | u8 reg; |
771 | |
772 | do { |
773 | usleep_range(min: 1000, max: 2000); |
774 | dac33_read(component, DAC33_INT_OSC_STATUS, value: ®); |
775 | } while (((reg & 0x03) != DAC33_OSCSTATUS_NORMAL) && timeout--); |
776 | if ((reg & 0x03) != DAC33_OSCSTATUS_NORMAL) |
777 | dev_err(component->dev, |
778 | "internal oscillator calibration failed\n" ); |
779 | } |
780 | |
781 | static int dac33_startup(struct snd_pcm_substream *substream, |
782 | struct snd_soc_dai *dai) |
783 | { |
784 | struct snd_soc_component *component = dai->component; |
785 | struct tlv320dac33_priv *dac33 = snd_soc_component_get_drvdata(c: component); |
786 | |
787 | /* Stream started, save the substream pointer */ |
788 | dac33->substream = substream; |
789 | |
790 | return 0; |
791 | } |
792 | |
793 | static void dac33_shutdown(struct snd_pcm_substream *substream, |
794 | struct snd_soc_dai *dai) |
795 | { |
796 | struct snd_soc_component *component = dai->component; |
797 | struct tlv320dac33_priv *dac33 = snd_soc_component_get_drvdata(c: component); |
798 | |
799 | dac33->substream = NULL; |
800 | } |
801 | |
802 | #define CALC_BURST_RATE(bclkdiv, bclk_per_sample) \ |
803 | (BURST_BASEFREQ_HZ / bclkdiv / bclk_per_sample) |
804 | static int dac33_hw_params(struct snd_pcm_substream *substream, |
805 | struct snd_pcm_hw_params *params, |
806 | struct snd_soc_dai *dai) |
807 | { |
808 | struct snd_soc_component *component = dai->component; |
809 | struct tlv320dac33_priv *dac33 = snd_soc_component_get_drvdata(c: component); |
810 | |
811 | /* Check parameters for validity */ |
812 | switch (params_rate(p: params)) { |
813 | case 44100: |
814 | case 48000: |
815 | break; |
816 | default: |
817 | dev_err(component->dev, "unsupported rate %d\n" , |
818 | params_rate(params)); |
819 | return -EINVAL; |
820 | } |
821 | |
822 | switch (params_width(p: params)) { |
823 | case 16: |
824 | dac33->fifo_size = DAC33_FIFO_SIZE_16BIT; |
825 | dac33->burst_rate = CALC_BURST_RATE(dac33->burst_bclkdiv, 32); |
826 | break; |
827 | case 32: |
828 | dac33->fifo_size = DAC33_FIFO_SIZE_24BIT; |
829 | dac33->burst_rate = CALC_BURST_RATE(dac33->burst_bclkdiv, 64); |
830 | break; |
831 | default: |
832 | dev_err(component->dev, "unsupported width %d\n" , |
833 | params_width(params)); |
834 | return -EINVAL; |
835 | } |
836 | |
837 | return 0; |
838 | } |
839 | |
840 | #define CALC_OSCSET(rate, refclk) ( \ |
841 | ((((rate * 10000) / refclk) * 4096) + 7000) / 10000) |
842 | #define CALC_RATIOSET(rate, refclk) ( \ |
843 | ((((refclk * 100000) / rate) * 16384) + 50000) / 100000) |
844 | |
845 | /* |
846 | * tlv320dac33 is strict on the sequence of the register writes, if the register |
847 | * writes happens in different order, than dac33 might end up in unknown state. |
848 | * Use the known, working sequence of register writes to initialize the dac33. |
849 | */ |
850 | static int dac33_prepare_chip(struct snd_pcm_substream *substream, |
851 | struct snd_soc_component *component) |
852 | { |
853 | struct tlv320dac33_priv *dac33 = snd_soc_component_get_drvdata(c: component); |
854 | unsigned int oscset, ratioset, pwr_ctrl, reg_tmp; |
855 | u8 aictrl_a, aictrl_b, fifoctrl_a; |
856 | |
857 | switch (substream->runtime->rate) { |
858 | case 44100: |
859 | case 48000: |
860 | oscset = CALC_OSCSET(substream->runtime->rate, dac33->refclk); |
861 | ratioset = CALC_RATIOSET(substream->runtime->rate, |
862 | dac33->refclk); |
863 | break; |
864 | default: |
865 | dev_err(component->dev, "unsupported rate %d\n" , |
866 | substream->runtime->rate); |
867 | return -EINVAL; |
868 | } |
869 | |
870 | |
871 | aictrl_a = dac33_read_reg_cache(component, DAC33_SER_AUDIOIF_CTRL_A); |
872 | aictrl_a &= ~(DAC33_NCYCL_MASK | DAC33_WLEN_MASK); |
873 | /* Read FIFO control A, and clear FIFO flush bit */ |
874 | fifoctrl_a = dac33_read_reg_cache(component, DAC33_FIFO_CTRL_A); |
875 | fifoctrl_a &= ~DAC33_FIFOFLUSH; |
876 | |
877 | fifoctrl_a &= ~DAC33_WIDTH; |
878 | switch (substream->runtime->format) { |
879 | case SNDRV_PCM_FORMAT_S16_LE: |
880 | aictrl_a |= (DAC33_NCYCL_16 | DAC33_WLEN_16); |
881 | fifoctrl_a |= DAC33_WIDTH; |
882 | break; |
883 | case SNDRV_PCM_FORMAT_S32_LE: |
884 | aictrl_a |= (DAC33_NCYCL_32 | DAC33_WLEN_24); |
885 | break; |
886 | default: |
887 | dev_err(component->dev, "unsupported format %d\n" , |
888 | substream->runtime->format); |
889 | return -EINVAL; |
890 | } |
891 | |
892 | mutex_lock(&dac33->mutex); |
893 | |
894 | if (!dac33->chip_power) { |
895 | /* |
896 | * Chip is not powered yet. |
897 | * Do the init in the dac33_set_bias_level later. |
898 | */ |
899 | mutex_unlock(lock: &dac33->mutex); |
900 | return 0; |
901 | } |
902 | |
903 | dac33_soft_power(component, power: 0); |
904 | dac33_soft_power(component, power: 1); |
905 | |
906 | reg_tmp = dac33_read_reg_cache(component, DAC33_INT_OSC_CTRL); |
907 | dac33_write(component, DAC33_INT_OSC_CTRL, value: reg_tmp); |
908 | |
909 | /* Write registers 0x08 and 0x09 (MSB, LSB) */ |
910 | dac33_write16(component, DAC33_INT_OSC_FREQ_RAT_A, value: oscset); |
911 | |
912 | /* OSC calibration time */ |
913 | dac33_write(component, DAC33_CALIB_TIME, value: 96); |
914 | |
915 | /* adjustment treshold & step */ |
916 | dac33_write(component, DAC33_INT_OSC_CTRL_B, DAC33_ADJTHRSHLD(2) | |
917 | DAC33_ADJSTEP(1)); |
918 | |
919 | /* div=4 / gain=1 / div */ |
920 | dac33_write(component, DAC33_INT_OSC_CTRL_C, DAC33_REFDIV(4)); |
921 | |
922 | pwr_ctrl = dac33_read_reg_cache(component, DAC33_PWR_CTRL); |
923 | pwr_ctrl |= DAC33_OSCPDNB | DAC33_DACRPDNB | DAC33_DACLPDNB; |
924 | dac33_write(component, DAC33_PWR_CTRL, value: pwr_ctrl); |
925 | |
926 | dac33_oscwait(component); |
927 | |
928 | if (dac33->fifo_mode) { |
929 | /* Generic for all FIFO modes */ |
930 | /* 50-51 : ASRC Control registers */ |
931 | dac33_write(component, DAC33_ASRC_CTRL_A, DAC33_SRCLKDIV(1)); |
932 | dac33_write(component, DAC33_ASRC_CTRL_B, value: 1); /* ??? */ |
933 | |
934 | /* Write registers 0x34 and 0x35 (MSB, LSB) */ |
935 | dac33_write16(component, DAC33_SRC_REF_CLK_RATIO_A, value: ratioset); |
936 | |
937 | /* Set interrupts to high active */ |
938 | dac33_write(component, DAC33_INTP_CTRL_A, DAC33_INTPM_AHIGH); |
939 | } else { |
940 | /* FIFO bypass mode */ |
941 | /* 50-51 : ASRC Control registers */ |
942 | dac33_write(component, DAC33_ASRC_CTRL_A, DAC33_SRCBYP); |
943 | dac33_write(component, DAC33_ASRC_CTRL_B, value: 0); /* ??? */ |
944 | } |
945 | |
946 | /* Interrupt behaviour configuration */ |
947 | switch (dac33->fifo_mode) { |
948 | case DAC33_FIFO_MODE1: |
949 | dac33_write(component, DAC33_FIFO_IRQ_MODE_B, |
950 | DAC33_ATM(DAC33_FIFO_IRQ_MODE_LEVEL)); |
951 | break; |
952 | case DAC33_FIFO_MODE7: |
953 | dac33_write(component, DAC33_FIFO_IRQ_MODE_A, |
954 | DAC33_UTM(DAC33_FIFO_IRQ_MODE_LEVEL)); |
955 | break; |
956 | default: |
957 | /* in FIFO bypass mode, the interrupts are not used */ |
958 | break; |
959 | } |
960 | |
961 | aictrl_b = dac33_read_reg_cache(component, DAC33_SER_AUDIOIF_CTRL_B); |
962 | |
963 | switch (dac33->fifo_mode) { |
964 | case DAC33_FIFO_MODE1: |
965 | /* |
966 | * For mode1: |
967 | * Disable the FIFO bypass (Enable the use of FIFO) |
968 | * Select nSample mode |
969 | * BCLK is only running when data is needed by DAC33 |
970 | */ |
971 | fifoctrl_a &= ~DAC33_FBYPAS; |
972 | fifoctrl_a &= ~DAC33_FAUTO; |
973 | if (dac33->keep_bclk) |
974 | aictrl_b |= DAC33_BCLKON; |
975 | else |
976 | aictrl_b &= ~DAC33_BCLKON; |
977 | break; |
978 | case DAC33_FIFO_MODE7: |
979 | /* |
980 | * For mode1: |
981 | * Disable the FIFO bypass (Enable the use of FIFO) |
982 | * Select Threshold mode |
983 | * BCLK is only running when data is needed by DAC33 |
984 | */ |
985 | fifoctrl_a &= ~DAC33_FBYPAS; |
986 | fifoctrl_a |= DAC33_FAUTO; |
987 | if (dac33->keep_bclk) |
988 | aictrl_b |= DAC33_BCLKON; |
989 | else |
990 | aictrl_b &= ~DAC33_BCLKON; |
991 | break; |
992 | default: |
993 | /* |
994 | * For FIFO bypass mode: |
995 | * Enable the FIFO bypass (Disable the FIFO use) |
996 | * Set the BCLK as continuous |
997 | */ |
998 | fifoctrl_a |= DAC33_FBYPAS; |
999 | aictrl_b |= DAC33_BCLKON; |
1000 | break; |
1001 | } |
1002 | |
1003 | dac33_write(component, DAC33_FIFO_CTRL_A, value: fifoctrl_a); |
1004 | dac33_write(component, DAC33_SER_AUDIOIF_CTRL_A, value: aictrl_a); |
1005 | dac33_write(component, DAC33_SER_AUDIOIF_CTRL_B, value: aictrl_b); |
1006 | |
1007 | /* |
1008 | * BCLK divide ratio |
1009 | * 0: 1.5 |
1010 | * 1: 1 |
1011 | * 2: 2 |
1012 | * ... |
1013 | * 254: 254 |
1014 | * 255: 255 |
1015 | */ |
1016 | if (dac33->fifo_mode) |
1017 | dac33_write(component, DAC33_SER_AUDIOIF_CTRL_C, |
1018 | value: dac33->burst_bclkdiv); |
1019 | else |
1020 | if (substream->runtime->format == SNDRV_PCM_FORMAT_S16_LE) |
1021 | dac33_write(component, DAC33_SER_AUDIOIF_CTRL_C, value: 32); |
1022 | else |
1023 | dac33_write(component, DAC33_SER_AUDIOIF_CTRL_C, value: 16); |
1024 | |
1025 | switch (dac33->fifo_mode) { |
1026 | case DAC33_FIFO_MODE1: |
1027 | dac33_write16(component, DAC33_ATHR_MSB, |
1028 | DAC33_THRREG(dac33->alarm_threshold)); |
1029 | break; |
1030 | case DAC33_FIFO_MODE7: |
1031 | /* |
1032 | * Configure the threshold levels, and leave 10 sample space |
1033 | * at the bottom, and also at the top of the FIFO |
1034 | */ |
1035 | dac33_write16(component, DAC33_UTHR_MSB, DAC33_THRREG(dac33->uthr)); |
1036 | dac33_write16(component, DAC33_LTHR_MSB, |
1037 | DAC33_THRREG(DAC33_MODE7_MARGIN)); |
1038 | break; |
1039 | default: |
1040 | break; |
1041 | } |
1042 | |
1043 | mutex_unlock(lock: &dac33->mutex); |
1044 | |
1045 | return 0; |
1046 | } |
1047 | |
1048 | static void dac33_calculate_times(struct snd_pcm_substream *substream, |
1049 | struct snd_soc_component *component) |
1050 | { |
1051 | struct tlv320dac33_priv *dac33 = snd_soc_component_get_drvdata(c: component); |
1052 | unsigned int period_size = substream->runtime->period_size; |
1053 | unsigned int rate = substream->runtime->rate; |
1054 | unsigned int nsample_limit; |
1055 | |
1056 | /* In bypass mode we don't need to calculate */ |
1057 | if (!dac33->fifo_mode) |
1058 | return; |
1059 | |
1060 | switch (dac33->fifo_mode) { |
1061 | case DAC33_FIFO_MODE1: |
1062 | /* Number of samples under i2c latency */ |
1063 | dac33->alarm_threshold = US_TO_SAMPLES(rate, |
1064 | dac33->mode1_latency); |
1065 | nsample_limit = dac33->fifo_size - dac33->alarm_threshold; |
1066 | |
1067 | if (period_size <= dac33->alarm_threshold) |
1068 | /* |
1069 | * Configure nSamaple to number of periods, |
1070 | * which covers the latency requironment. |
1071 | */ |
1072 | dac33->nsample = period_size * |
1073 | ((dac33->alarm_threshold / period_size) + |
1074 | ((dac33->alarm_threshold % period_size) ? |
1075 | 1 : 0)); |
1076 | else if (period_size > nsample_limit) |
1077 | dac33->nsample = nsample_limit; |
1078 | else |
1079 | dac33->nsample = period_size; |
1080 | |
1081 | dac33->mode1_us_burst = SAMPLES_TO_US(dac33->burst_rate, |
1082 | dac33->nsample); |
1083 | dac33->t_stamp1 = 0; |
1084 | dac33->t_stamp2 = 0; |
1085 | break; |
1086 | case DAC33_FIFO_MODE7: |
1087 | dac33->uthr = UTHR_FROM_PERIOD_SIZE(period_size, rate, |
1088 | dac33->burst_rate) + 9; |
1089 | if (dac33->uthr > (dac33->fifo_size - DAC33_MODE7_MARGIN)) |
1090 | dac33->uthr = dac33->fifo_size - DAC33_MODE7_MARGIN; |
1091 | if (dac33->uthr < (DAC33_MODE7_MARGIN + 10)) |
1092 | dac33->uthr = (DAC33_MODE7_MARGIN + 10); |
1093 | |
1094 | dac33->mode7_us_to_lthr = |
1095 | SAMPLES_TO_US(substream->runtime->rate, |
1096 | dac33->uthr - DAC33_MODE7_MARGIN + 1); |
1097 | dac33->t_stamp1 = 0; |
1098 | break; |
1099 | default: |
1100 | break; |
1101 | } |
1102 | |
1103 | } |
1104 | |
1105 | static int dac33_pcm_trigger(struct snd_pcm_substream *substream, int cmd, |
1106 | struct snd_soc_dai *dai) |
1107 | { |
1108 | struct snd_soc_component *component = dai->component; |
1109 | struct tlv320dac33_priv *dac33 = snd_soc_component_get_drvdata(c: component); |
1110 | int ret = 0; |
1111 | |
1112 | switch (cmd) { |
1113 | case SNDRV_PCM_TRIGGER_START: |
1114 | case SNDRV_PCM_TRIGGER_RESUME: |
1115 | case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: |
1116 | if (dac33->fifo_mode) { |
1117 | dac33->state = DAC33_PREFILL; |
1118 | schedule_work(work: &dac33->work); |
1119 | } |
1120 | break; |
1121 | case SNDRV_PCM_TRIGGER_STOP: |
1122 | case SNDRV_PCM_TRIGGER_SUSPEND: |
1123 | case SNDRV_PCM_TRIGGER_PAUSE_PUSH: |
1124 | if (dac33->fifo_mode) { |
1125 | dac33->state = DAC33_FLUSH; |
1126 | schedule_work(work: &dac33->work); |
1127 | } |
1128 | break; |
1129 | default: |
1130 | ret = -EINVAL; |
1131 | } |
1132 | |
1133 | return ret; |
1134 | } |
1135 | |
1136 | static snd_pcm_sframes_t dac33_dai_delay( |
1137 | struct snd_pcm_substream *substream, |
1138 | struct snd_soc_dai *dai) |
1139 | { |
1140 | struct snd_soc_component *component = dai->component; |
1141 | struct tlv320dac33_priv *dac33 = snd_soc_component_get_drvdata(c: component); |
1142 | unsigned long long t0, t1, t_now; |
1143 | unsigned int time_delta, uthr; |
1144 | int samples_out, samples_in, samples; |
1145 | snd_pcm_sframes_t delay = 0; |
1146 | unsigned long flags; |
1147 | |
1148 | switch (dac33->fifo_mode) { |
1149 | case DAC33_FIFO_BYPASS: |
1150 | break; |
1151 | case DAC33_FIFO_MODE1: |
1152 | spin_lock_irqsave(&dac33->lock, flags); |
1153 | t0 = dac33->t_stamp1; |
1154 | t1 = dac33->t_stamp2; |
1155 | spin_unlock_irqrestore(lock: &dac33->lock, flags); |
1156 | t_now = ktime_to_us(kt: ktime_get()); |
1157 | |
1158 | /* We have not started to fill the FIFO yet, delay is 0 */ |
1159 | if (!t1) |
1160 | goto out; |
1161 | |
1162 | if (t0 > t1) { |
1163 | /* |
1164 | * Phase 1: |
1165 | * After Alarm threshold, and before nSample write |
1166 | */ |
1167 | time_delta = t_now - t0; |
1168 | samples_out = time_delta ? US_TO_SAMPLES( |
1169 | substream->runtime->rate, |
1170 | time_delta) : 0; |
1171 | |
1172 | if (likely(dac33->alarm_threshold > samples_out)) |
1173 | delay = dac33->alarm_threshold - samples_out; |
1174 | else |
1175 | delay = 0; |
1176 | } else if ((t_now - t1) <= dac33->mode1_us_burst) { |
1177 | /* |
1178 | * Phase 2: |
1179 | * After nSample write (during burst operation) |
1180 | */ |
1181 | time_delta = t_now - t0; |
1182 | samples_out = time_delta ? US_TO_SAMPLES( |
1183 | substream->runtime->rate, |
1184 | time_delta) : 0; |
1185 | |
1186 | time_delta = t_now - t1; |
1187 | samples_in = time_delta ? US_TO_SAMPLES( |
1188 | dac33->burst_rate, |
1189 | time_delta) : 0; |
1190 | |
1191 | samples = dac33->alarm_threshold; |
1192 | samples += (samples_in - samples_out); |
1193 | |
1194 | if (likely(samples > 0)) |
1195 | delay = samples; |
1196 | else |
1197 | delay = 0; |
1198 | } else { |
1199 | /* |
1200 | * Phase 3: |
1201 | * After burst operation, before next alarm threshold |
1202 | */ |
1203 | time_delta = t_now - t0; |
1204 | samples_out = time_delta ? US_TO_SAMPLES( |
1205 | substream->runtime->rate, |
1206 | time_delta) : 0; |
1207 | |
1208 | samples_in = dac33->nsample; |
1209 | samples = dac33->alarm_threshold; |
1210 | samples += (samples_in - samples_out); |
1211 | |
1212 | if (likely(samples > 0)) |
1213 | delay = samples > dac33->fifo_size ? |
1214 | dac33->fifo_size : samples; |
1215 | else |
1216 | delay = 0; |
1217 | } |
1218 | break; |
1219 | case DAC33_FIFO_MODE7: |
1220 | spin_lock_irqsave(&dac33->lock, flags); |
1221 | t0 = dac33->t_stamp1; |
1222 | uthr = dac33->uthr; |
1223 | spin_unlock_irqrestore(lock: &dac33->lock, flags); |
1224 | t_now = ktime_to_us(kt: ktime_get()); |
1225 | |
1226 | /* We have not started to fill the FIFO yet, delay is 0 */ |
1227 | if (!t0) |
1228 | goto out; |
1229 | |
1230 | if (t_now <= t0) { |
1231 | /* |
1232 | * Either the timestamps are messed or equal. Report |
1233 | * maximum delay |
1234 | */ |
1235 | delay = uthr; |
1236 | goto out; |
1237 | } |
1238 | |
1239 | time_delta = t_now - t0; |
1240 | if (time_delta <= dac33->mode7_us_to_lthr) { |
1241 | /* |
1242 | * Phase 1: |
1243 | * After burst (draining phase) |
1244 | */ |
1245 | samples_out = US_TO_SAMPLES( |
1246 | substream->runtime->rate, |
1247 | time_delta); |
1248 | |
1249 | if (likely(uthr > samples_out)) |
1250 | delay = uthr - samples_out; |
1251 | else |
1252 | delay = 0; |
1253 | } else { |
1254 | /* |
1255 | * Phase 2: |
1256 | * During burst operation |
1257 | */ |
1258 | time_delta = time_delta - dac33->mode7_us_to_lthr; |
1259 | |
1260 | samples_out = US_TO_SAMPLES( |
1261 | substream->runtime->rate, |
1262 | time_delta); |
1263 | samples_in = US_TO_SAMPLES( |
1264 | dac33->burst_rate, |
1265 | time_delta); |
1266 | delay = DAC33_MODE7_MARGIN + samples_in - samples_out; |
1267 | |
1268 | if (unlikely(delay > uthr)) |
1269 | delay = uthr; |
1270 | } |
1271 | break; |
1272 | default: |
1273 | dev_warn(component->dev, "Unhandled FIFO mode: %d\n" , |
1274 | dac33->fifo_mode); |
1275 | break; |
1276 | } |
1277 | out: |
1278 | return delay; |
1279 | } |
1280 | |
1281 | static int dac33_set_dai_sysclk(struct snd_soc_dai *codec_dai, |
1282 | int clk_id, unsigned int freq, int dir) |
1283 | { |
1284 | struct snd_soc_component *component = codec_dai->component; |
1285 | struct tlv320dac33_priv *dac33 = snd_soc_component_get_drvdata(c: component); |
1286 | u8 ioc_reg, asrcb_reg; |
1287 | |
1288 | ioc_reg = dac33_read_reg_cache(component, DAC33_INT_OSC_CTRL); |
1289 | asrcb_reg = dac33_read_reg_cache(component, DAC33_ASRC_CTRL_B); |
1290 | switch (clk_id) { |
1291 | case TLV320DAC33_MCLK: |
1292 | ioc_reg |= DAC33_REFSEL; |
1293 | asrcb_reg |= DAC33_SRCREFSEL; |
1294 | break; |
1295 | case TLV320DAC33_SLEEPCLK: |
1296 | ioc_reg &= ~DAC33_REFSEL; |
1297 | asrcb_reg &= ~DAC33_SRCREFSEL; |
1298 | break; |
1299 | default: |
1300 | dev_err(component->dev, "Invalid clock ID (%d)\n" , clk_id); |
1301 | break; |
1302 | } |
1303 | dac33->refclk = freq; |
1304 | |
1305 | dac33_write_reg_cache(component, DAC33_INT_OSC_CTRL, value: ioc_reg); |
1306 | dac33_write_reg_cache(component, DAC33_ASRC_CTRL_B, value: asrcb_reg); |
1307 | |
1308 | return 0; |
1309 | } |
1310 | |
1311 | static int dac33_set_dai_fmt(struct snd_soc_dai *codec_dai, |
1312 | unsigned int fmt) |
1313 | { |
1314 | struct snd_soc_component *component = codec_dai->component; |
1315 | struct tlv320dac33_priv *dac33 = snd_soc_component_get_drvdata(c: component); |
1316 | u8 aictrl_a, aictrl_b; |
1317 | |
1318 | aictrl_a = dac33_read_reg_cache(component, DAC33_SER_AUDIOIF_CTRL_A); |
1319 | aictrl_b = dac33_read_reg_cache(component, DAC33_SER_AUDIOIF_CTRL_B); |
1320 | |
1321 | switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) { |
1322 | case SND_SOC_DAIFMT_CBP_CFP: |
1323 | aictrl_a |= (DAC33_MSBCLK | DAC33_MSWCLK); |
1324 | break; |
1325 | case SND_SOC_DAIFMT_CBC_CFC: |
1326 | if (dac33->fifo_mode) { |
1327 | dev_err(component->dev, "FIFO mode requires provider mode\n" ); |
1328 | return -EINVAL; |
1329 | } else |
1330 | aictrl_a &= ~(DAC33_MSBCLK | DAC33_MSWCLK); |
1331 | break; |
1332 | default: |
1333 | return -EINVAL; |
1334 | } |
1335 | |
1336 | aictrl_a &= ~DAC33_AFMT_MASK; |
1337 | switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { |
1338 | case SND_SOC_DAIFMT_I2S: |
1339 | aictrl_a |= DAC33_AFMT_I2S; |
1340 | break; |
1341 | case SND_SOC_DAIFMT_DSP_A: |
1342 | aictrl_a |= DAC33_AFMT_DSP; |
1343 | aictrl_b &= ~DAC33_DATA_DELAY_MASK; |
1344 | aictrl_b |= DAC33_DATA_DELAY(0); |
1345 | break; |
1346 | case SND_SOC_DAIFMT_RIGHT_J: |
1347 | aictrl_a |= DAC33_AFMT_RIGHT_J; |
1348 | break; |
1349 | case SND_SOC_DAIFMT_LEFT_J: |
1350 | aictrl_a |= DAC33_AFMT_LEFT_J; |
1351 | break; |
1352 | default: |
1353 | dev_err(component->dev, "Unsupported format (%u)\n" , |
1354 | fmt & SND_SOC_DAIFMT_FORMAT_MASK); |
1355 | return -EINVAL; |
1356 | } |
1357 | |
1358 | dac33_write_reg_cache(component, DAC33_SER_AUDIOIF_CTRL_A, value: aictrl_a); |
1359 | dac33_write_reg_cache(component, DAC33_SER_AUDIOIF_CTRL_B, value: aictrl_b); |
1360 | |
1361 | return 0; |
1362 | } |
1363 | |
1364 | static int dac33_soc_probe(struct snd_soc_component *component) |
1365 | { |
1366 | struct tlv320dac33_priv *dac33 = snd_soc_component_get_drvdata(c: component); |
1367 | int ret = 0; |
1368 | |
1369 | dac33->component = component; |
1370 | |
1371 | /* Read the tlv320dac33 ID registers */ |
1372 | ret = dac33_hard_power(component, power: 1); |
1373 | if (ret != 0) { |
1374 | dev_err(component->dev, "Failed to power up component: %d\n" , ret); |
1375 | goto err_power; |
1376 | } |
1377 | ret = dac33_read_id(component); |
1378 | dac33_hard_power(component, power: 0); |
1379 | |
1380 | if (ret < 0) { |
1381 | dev_err(component->dev, "Failed to read chip ID: %d\n" , ret); |
1382 | ret = -ENODEV; |
1383 | goto err_power; |
1384 | } |
1385 | |
1386 | /* Check if the IRQ number is valid and request it */ |
1387 | if (dac33->irq >= 0) { |
1388 | ret = request_irq(irq: dac33->irq, handler: dac33_interrupt_handler, |
1389 | IRQF_TRIGGER_RISING, |
1390 | name: component->name, dev: component); |
1391 | if (ret < 0) { |
1392 | dev_err(component->dev, "Could not request IRQ%d (%d)\n" , |
1393 | dac33->irq, ret); |
1394 | dac33->irq = -1; |
1395 | } |
1396 | if (dac33->irq != -1) { |
1397 | INIT_WORK(&dac33->work, dac33_work); |
1398 | } |
1399 | } |
1400 | |
1401 | /* Only add the FIFO controls, if we have valid IRQ number */ |
1402 | if (dac33->irq >= 0) |
1403 | snd_soc_add_component_controls(component, controls: dac33_mode_snd_controls, |
1404 | ARRAY_SIZE(dac33_mode_snd_controls)); |
1405 | |
1406 | err_power: |
1407 | return ret; |
1408 | } |
1409 | |
1410 | static void dac33_soc_remove(struct snd_soc_component *component) |
1411 | { |
1412 | struct tlv320dac33_priv *dac33 = snd_soc_component_get_drvdata(c: component); |
1413 | |
1414 | if (dac33->irq >= 0) { |
1415 | free_irq(dac33->irq, dac33->component); |
1416 | flush_work(work: &dac33->work); |
1417 | } |
1418 | } |
1419 | |
1420 | static const struct snd_soc_component_driver soc_component_dev_tlv320dac33 = { |
1421 | .read = dac33_read_reg_cache, |
1422 | .write = dac33_write_locked, |
1423 | .set_bias_level = dac33_set_bias_level, |
1424 | .probe = dac33_soc_probe, |
1425 | .remove = dac33_soc_remove, |
1426 | .controls = dac33_snd_controls, |
1427 | .num_controls = ARRAY_SIZE(dac33_snd_controls), |
1428 | .dapm_widgets = dac33_dapm_widgets, |
1429 | .num_dapm_widgets = ARRAY_SIZE(dac33_dapm_widgets), |
1430 | .dapm_routes = audio_map, |
1431 | .num_dapm_routes = ARRAY_SIZE(audio_map), |
1432 | .use_pmdown_time = 1, |
1433 | .endianness = 1, |
1434 | }; |
1435 | |
1436 | #define DAC33_RATES (SNDRV_PCM_RATE_44100 | \ |
1437 | SNDRV_PCM_RATE_48000) |
1438 | #define DAC33_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE) |
1439 | |
1440 | static const struct snd_soc_dai_ops dac33_dai_ops = { |
1441 | .startup = dac33_startup, |
1442 | .shutdown = dac33_shutdown, |
1443 | .hw_params = dac33_hw_params, |
1444 | .trigger = dac33_pcm_trigger, |
1445 | .delay = dac33_dai_delay, |
1446 | .set_sysclk = dac33_set_dai_sysclk, |
1447 | .set_fmt = dac33_set_dai_fmt, |
1448 | }; |
1449 | |
1450 | static struct snd_soc_dai_driver dac33_dai = { |
1451 | .name = "tlv320dac33-hifi" , |
1452 | .playback = { |
1453 | .stream_name = "Playback" , |
1454 | .channels_min = 2, |
1455 | .channels_max = 2, |
1456 | .rates = DAC33_RATES, |
1457 | .formats = DAC33_FORMATS, |
1458 | .sig_bits = 24, |
1459 | }, |
1460 | .ops = &dac33_dai_ops, |
1461 | }; |
1462 | |
1463 | static int dac33_i2c_probe(struct i2c_client *client) |
1464 | { |
1465 | struct tlv320dac33_platform_data *pdata; |
1466 | struct tlv320dac33_priv *dac33; |
1467 | int ret, i; |
1468 | |
1469 | if (client->dev.platform_data == NULL) { |
1470 | dev_err(&client->dev, "Platform data not set\n" ); |
1471 | return -ENODEV; |
1472 | } |
1473 | pdata = client->dev.platform_data; |
1474 | |
1475 | dac33 = devm_kzalloc(dev: &client->dev, size: sizeof(struct tlv320dac33_priv), |
1476 | GFP_KERNEL); |
1477 | if (dac33 == NULL) |
1478 | return -ENOMEM; |
1479 | |
1480 | dac33->reg_cache = devm_kmemdup(dev: &client->dev, |
1481 | src: dac33_reg, |
1482 | ARRAY_SIZE(dac33_reg) * sizeof(u8), |
1483 | GFP_KERNEL); |
1484 | if (!dac33->reg_cache) |
1485 | return -ENOMEM; |
1486 | |
1487 | dac33->i2c = client; |
1488 | mutex_init(&dac33->mutex); |
1489 | spin_lock_init(&dac33->lock); |
1490 | |
1491 | i2c_set_clientdata(client, data: dac33); |
1492 | |
1493 | dac33->power_gpio = pdata->power_gpio; |
1494 | dac33->burst_bclkdiv = pdata->burst_bclkdiv; |
1495 | dac33->keep_bclk = pdata->keep_bclk; |
1496 | dac33->mode1_latency = pdata->mode1_latency; |
1497 | if (!dac33->mode1_latency) |
1498 | dac33->mode1_latency = 10000; /* 10ms */ |
1499 | dac33->irq = client->irq; |
1500 | /* Disable FIFO use by default */ |
1501 | dac33->fifo_mode = DAC33_FIFO_BYPASS; |
1502 | |
1503 | /* Check if the reset GPIO number is valid and request it */ |
1504 | if (dac33->power_gpio >= 0) { |
1505 | ret = gpio_request(gpio: dac33->power_gpio, label: "tlv320dac33 reset" ); |
1506 | if (ret < 0) { |
1507 | dev_err(&client->dev, |
1508 | "Failed to request reset GPIO (%d)\n" , |
1509 | dac33->power_gpio); |
1510 | goto err_gpio; |
1511 | } |
1512 | gpio_direction_output(gpio: dac33->power_gpio, value: 0); |
1513 | } |
1514 | |
1515 | for (i = 0; i < ARRAY_SIZE(dac33->supplies); i++) |
1516 | dac33->supplies[i].supply = dac33_supply_names[i]; |
1517 | |
1518 | ret = devm_regulator_bulk_get(dev: &client->dev, ARRAY_SIZE(dac33->supplies), |
1519 | consumers: dac33->supplies); |
1520 | |
1521 | if (ret != 0) { |
1522 | dev_err(&client->dev, "Failed to request supplies: %d\n" , ret); |
1523 | goto err_get; |
1524 | } |
1525 | |
1526 | ret = devm_snd_soc_register_component(dev: &client->dev, |
1527 | component_driver: &soc_component_dev_tlv320dac33, dai_drv: &dac33_dai, num_dai: 1); |
1528 | if (ret < 0) |
1529 | goto err_get; |
1530 | |
1531 | return ret; |
1532 | err_get: |
1533 | if (dac33->power_gpio >= 0) |
1534 | gpio_free(gpio: dac33->power_gpio); |
1535 | err_gpio: |
1536 | return ret; |
1537 | } |
1538 | |
1539 | static void dac33_i2c_remove(struct i2c_client *client) |
1540 | { |
1541 | struct tlv320dac33_priv *dac33 = i2c_get_clientdata(client); |
1542 | |
1543 | if (unlikely(dac33->chip_power)) |
1544 | dac33_hard_power(component: dac33->component, power: 0); |
1545 | |
1546 | if (dac33->power_gpio >= 0) |
1547 | gpio_free(gpio: dac33->power_gpio); |
1548 | } |
1549 | |
1550 | static const struct i2c_device_id tlv320dac33_i2c_id[] = { |
1551 | { |
1552 | .name = "tlv320dac33" , |
1553 | .driver_data = 0, |
1554 | }, |
1555 | { }, |
1556 | }; |
1557 | MODULE_DEVICE_TABLE(i2c, tlv320dac33_i2c_id); |
1558 | |
1559 | static struct i2c_driver tlv320dac33_i2c_driver = { |
1560 | .driver = { |
1561 | .name = "tlv320dac33-codec" , |
1562 | }, |
1563 | .probe = dac33_i2c_probe, |
1564 | .remove = dac33_i2c_remove, |
1565 | .id_table = tlv320dac33_i2c_id, |
1566 | }; |
1567 | |
1568 | module_i2c_driver(tlv320dac33_i2c_driver); |
1569 | |
1570 | MODULE_DESCRIPTION("ASoC TLV320DAC33 codec driver" ); |
1571 | MODULE_AUTHOR("Peter Ujfalusi <peter.ujfalusi@ti.com>" ); |
1572 | MODULE_LICENSE("GPL" ); |
1573 | |