1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
2 | /* |
3 | * wm8962.h -- WM8962 ASoC driver |
4 | * |
5 | * Copyright 2010 Wolfson Microelectronics, plc |
6 | * |
7 | * Author: Mark Brown <broonie@opensource.wolfsonmicro.com> |
8 | */ |
9 | |
10 | #ifndef _WM8962_H |
11 | #define _WM8962_H |
12 | |
13 | #include <asm/types.h> |
14 | #include <sound/soc.h> |
15 | |
16 | #define WM8962_SYSCLK_MCLK 0 |
17 | #define WM8962_SYSCLK_FLL 1 |
18 | #define WM8962_SYSCLK_PLL3 2 |
19 | |
20 | #define WM8962_FLL 1 |
21 | |
22 | #define WM8962_FLL_MCLK 1 |
23 | #define WM8962_FLL_BCLK 2 |
24 | #define WM8962_FLL_OSC 3 |
25 | #define WM8962_FLL_INT 4 |
26 | |
27 | /* |
28 | * Register values. |
29 | */ |
30 | #define WM8962_LEFT_INPUT_VOLUME 0x00 |
31 | #define WM8962_RIGHT_INPUT_VOLUME 0x01 |
32 | #define WM8962_HPOUTL_VOLUME 0x02 |
33 | #define WM8962_HPOUTR_VOLUME 0x03 |
34 | #define WM8962_CLOCKING1 0x04 |
35 | #define WM8962_ADC_DAC_CONTROL_1 0x05 |
36 | #define WM8962_ADC_DAC_CONTROL_2 0x06 |
37 | #define WM8962_AUDIO_INTERFACE_0 0x07 |
38 | #define WM8962_CLOCKING2 0x08 |
39 | #define WM8962_AUDIO_INTERFACE_1 0x09 |
40 | #define WM8962_LEFT_DAC_VOLUME 0x0A |
41 | #define WM8962_RIGHT_DAC_VOLUME 0x0B |
42 | #define WM8962_AUDIO_INTERFACE_2 0x0E |
43 | #define WM8962_SOFTWARE_RESET 0x0F |
44 | #define WM8962_ALC1 0x11 |
45 | #define WM8962_ALC2 0x12 |
46 | #define WM8962_ALC3 0x13 |
47 | #define WM8962_NOISE_GATE 0x14 |
48 | #define WM8962_LEFT_ADC_VOLUME 0x15 |
49 | #define WM8962_RIGHT_ADC_VOLUME 0x16 |
50 | #define WM8962_ADDITIONAL_CONTROL_1 0x17 |
51 | #define WM8962_ADDITIONAL_CONTROL_2 0x18 |
52 | #define WM8962_PWR_MGMT_1 0x19 |
53 | #define WM8962_PWR_MGMT_2 0x1A |
54 | #define WM8962_ADDITIONAL_CONTROL_3 0x1B |
55 | #define WM8962_ANTI_POP 0x1C |
56 | #define WM8962_CLOCKING_3 0x1E |
57 | #define WM8962_INPUT_MIXER_CONTROL_1 0x1F |
58 | #define WM8962_LEFT_INPUT_MIXER_VOLUME 0x20 |
59 | #define WM8962_RIGHT_INPUT_MIXER_VOLUME 0x21 |
60 | #define WM8962_INPUT_MIXER_CONTROL_2 0x22 |
61 | #define WM8962_INPUT_BIAS_CONTROL 0x23 |
62 | #define WM8962_LEFT_INPUT_PGA_CONTROL 0x25 |
63 | #define WM8962_RIGHT_INPUT_PGA_CONTROL 0x26 |
64 | #define WM8962_SPKOUTL_VOLUME 0x28 |
65 | #define WM8962_SPKOUTR_VOLUME 0x29 |
66 | #define WM8962_THERMAL_SHUTDOWN_STATUS 0x2F |
67 | #define WM8962_ADDITIONAL_CONTROL_4 0x30 |
68 | #define WM8962_CLASS_D_CONTROL_1 0x31 |
69 | #define WM8962_CLASS_D_CONTROL_2 0x33 |
70 | #define WM8962_CLOCKING_4 0x38 |
71 | #define WM8962_DAC_DSP_MIXING_1 0x39 |
72 | #define WM8962_DAC_DSP_MIXING_2 0x3A |
73 | #define WM8962_DC_SERVO_0 0x3C |
74 | #define WM8962_DC_SERVO_1 0x3D |
75 | #define WM8962_DC_SERVO_4 0x40 |
76 | #define WM8962_DC_SERVO_6 0x42 |
77 | #define WM8962_ANALOGUE_PGA_BIAS 0x44 |
78 | #define WM8962_ANALOGUE_HP_0 0x45 |
79 | #define WM8962_ANALOGUE_HP_2 0x47 |
80 | #define WM8962_CHARGE_PUMP_1 0x48 |
81 | #define WM8962_CHARGE_PUMP_B 0x52 |
82 | #define WM8962_WRITE_SEQUENCER_CONTROL_1 0x57 |
83 | #define WM8962_WRITE_SEQUENCER_CONTROL_2 0x5A |
84 | #define WM8962_WRITE_SEQUENCER_CONTROL_3 0x5D |
85 | #define WM8962_CONTROL_INTERFACE 0x5E |
86 | #define WM8962_MIXER_ENABLES 0x63 |
87 | #define WM8962_HEADPHONE_MIXER_1 0x64 |
88 | #define WM8962_HEADPHONE_MIXER_2 0x65 |
89 | #define WM8962_HEADPHONE_MIXER_3 0x66 |
90 | #define WM8962_HEADPHONE_MIXER_4 0x67 |
91 | #define WM8962_SPEAKER_MIXER_1 0x69 |
92 | #define WM8962_SPEAKER_MIXER_2 0x6A |
93 | #define WM8962_SPEAKER_MIXER_3 0x6B |
94 | #define WM8962_SPEAKER_MIXER_4 0x6C |
95 | #define WM8962_SPEAKER_MIXER_5 0x6D |
96 | #define WM8962_BEEP_GENERATOR_1 0x6E |
97 | #define WM8962_OSCILLATOR_TRIM_3 0x73 |
98 | #define WM8962_OSCILLATOR_TRIM_4 0x74 |
99 | #define WM8962_OSCILLATOR_TRIM_7 0x77 |
100 | #define WM8962_ANALOGUE_CLOCKING1 0x7C |
101 | #define WM8962_ANALOGUE_CLOCKING2 0x7D |
102 | #define WM8962_ANALOGUE_CLOCKING3 0x7E |
103 | #define WM8962_PLL_SOFTWARE_RESET 0x7F |
104 | #define WM8962_PLL2 0x81 |
105 | #define WM8962_PLL_4 0x83 |
106 | #define WM8962_PLL_9 0x88 |
107 | #define WM8962_PLL_10 0x89 |
108 | #define WM8962_PLL_11 0x8A |
109 | #define WM8962_PLL_12 0x8B |
110 | #define WM8962_PLL_13 0x8C |
111 | #define WM8962_PLL_14 0x8D |
112 | #define WM8962_PLL_15 0x8E |
113 | #define WM8962_PLL_16 0x8F |
114 | #define WM8962_FLL_CONTROL_1 0x9B |
115 | #define WM8962_FLL_CONTROL_2 0x9C |
116 | #define WM8962_FLL_CONTROL_3 0x9D |
117 | #define WM8962_FLL_CONTROL_5 0x9F |
118 | #define WM8962_FLL_CONTROL_6 0xA0 |
119 | #define WM8962_FLL_CONTROL_7 0xA1 |
120 | #define WM8962_FLL_CONTROL_8 0xA2 |
121 | #define WM8962_GENERAL_TEST_1 0xFC |
122 | #define WM8962_DF1 0x100 |
123 | #define WM8962_DF2 0x101 |
124 | #define WM8962_DF3 0x102 |
125 | #define WM8962_DF4 0x103 |
126 | #define WM8962_DF5 0x104 |
127 | #define WM8962_DF6 0x105 |
128 | #define WM8962_DF7 0x106 |
129 | #define WM8962_LHPF1 0x108 |
130 | #define WM8962_LHPF2 0x109 |
131 | #define WM8962_THREED1 0x10C |
132 | #define WM8962_THREED2 0x10D |
133 | #define WM8962_THREED3 0x10E |
134 | #define WM8962_THREED4 0x10F |
135 | #define WM8962_DRC_1 0x114 |
136 | #define WM8962_DRC_2 0x115 |
137 | #define WM8962_DRC_3 0x116 |
138 | #define WM8962_DRC_4 0x117 |
139 | #define WM8962_DRC_5 0x118 |
140 | #define WM8962_TLOOPBACK 0x11D |
141 | #define WM8962_EQ1 0x14F |
142 | #define WM8962_EQ2 0x150 |
143 | #define WM8962_EQ3 0x151 |
144 | #define WM8962_EQ4 0x152 |
145 | #define WM8962_EQ5 0x153 |
146 | #define WM8962_EQ6 0x154 |
147 | #define WM8962_EQ7 0x155 |
148 | #define WM8962_EQ8 0x156 |
149 | #define WM8962_EQ9 0x157 |
150 | #define WM8962_EQ10 0x158 |
151 | #define WM8962_EQ11 0x159 |
152 | #define WM8962_EQ12 0x15A |
153 | #define WM8962_EQ13 0x15B |
154 | #define WM8962_EQ14 0x15C |
155 | #define WM8962_EQ15 0x15D |
156 | #define WM8962_EQ16 0x15E |
157 | #define WM8962_EQ17 0x15F |
158 | #define WM8962_EQ18 0x160 |
159 | #define WM8962_EQ19 0x161 |
160 | #define WM8962_EQ20 0x162 |
161 | #define WM8962_EQ21 0x163 |
162 | #define WM8962_EQ22 0x164 |
163 | #define WM8962_EQ23 0x165 |
164 | #define WM8962_EQ24 0x166 |
165 | #define WM8962_EQ25 0x167 |
166 | #define WM8962_EQ26 0x168 |
167 | #define WM8962_EQ27 0x169 |
168 | #define WM8962_EQ28 0x16A |
169 | #define WM8962_EQ29 0x16B |
170 | #define WM8962_EQ30 0x16C |
171 | #define WM8962_EQ31 0x16D |
172 | #define WM8962_EQ32 0x16E |
173 | #define WM8962_EQ33 0x16F |
174 | #define WM8962_EQ34 0x170 |
175 | #define WM8962_EQ35 0x171 |
176 | #define WM8962_EQ36 0x172 |
177 | #define WM8962_EQ37 0x173 |
178 | #define WM8962_EQ38 0x174 |
179 | #define WM8962_EQ39 0x175 |
180 | #define WM8962_EQ40 0x176 |
181 | #define WM8962_EQ41 0x177 |
182 | #define WM8962_GPIO_BASE 0x200 |
183 | #define WM8962_GPIO_2 0x201 |
184 | #define WM8962_GPIO_3 0x202 |
185 | #define WM8962_GPIO_5 0x204 |
186 | #define WM8962_GPIO_6 0x205 |
187 | #define WM8962_INTERRUPT_STATUS_1 0x230 |
188 | #define WM8962_INTERRUPT_STATUS_2 0x231 |
189 | #define WM8962_INTERRUPT_STATUS_1_MASK 0x238 |
190 | #define WM8962_INTERRUPT_STATUS_2_MASK 0x239 |
191 | #define WM8962_INTERRUPT_CONTROL 0x240 |
192 | #define WM8962_IRQ_DEBOUNCE 0x248 |
193 | #define WM8962_MICINT_SOURCE_POL 0x24A |
194 | #define WM8962_DSP2_POWER_MANAGEMENT 0x300 |
195 | #define WM8962_DSP2_EXECCONTROL 0x40D |
196 | #define WM8962_WRITE_SEQUENCER_0 0x1000 |
197 | #define WM8962_WRITE_SEQUENCER_1 0x1001 |
198 | #define WM8962_WRITE_SEQUENCER_2 0x1002 |
199 | #define WM8962_WRITE_SEQUENCER_3 0x1003 |
200 | #define WM8962_WRITE_SEQUENCER_4 0x1004 |
201 | #define WM8962_WRITE_SEQUENCER_5 0x1005 |
202 | #define WM8962_WRITE_SEQUENCER_6 0x1006 |
203 | #define WM8962_WRITE_SEQUENCER_7 0x1007 |
204 | #define WM8962_WRITE_SEQUENCER_8 0x1008 |
205 | #define WM8962_WRITE_SEQUENCER_9 0x1009 |
206 | #define WM8962_WRITE_SEQUENCER_10 0x100A |
207 | #define WM8962_WRITE_SEQUENCER_11 0x100B |
208 | #define WM8962_WRITE_SEQUENCER_12 0x100C |
209 | #define WM8962_WRITE_SEQUENCER_13 0x100D |
210 | #define WM8962_WRITE_SEQUENCER_14 0x100E |
211 | #define WM8962_WRITE_SEQUENCER_15 0x100F |
212 | #define WM8962_WRITE_SEQUENCER_16 0x1010 |
213 | #define WM8962_WRITE_SEQUENCER_17 0x1011 |
214 | #define WM8962_WRITE_SEQUENCER_18 0x1012 |
215 | #define WM8962_WRITE_SEQUENCER_19 0x1013 |
216 | #define WM8962_WRITE_SEQUENCER_20 0x1014 |
217 | #define WM8962_WRITE_SEQUENCER_21 0x1015 |
218 | #define WM8962_WRITE_SEQUENCER_22 0x1016 |
219 | #define WM8962_WRITE_SEQUENCER_23 0x1017 |
220 | #define WM8962_WRITE_SEQUENCER_24 0x1018 |
221 | #define WM8962_WRITE_SEQUENCER_25 0x1019 |
222 | #define WM8962_WRITE_SEQUENCER_26 0x101A |
223 | #define WM8962_WRITE_SEQUENCER_27 0x101B |
224 | #define WM8962_WRITE_SEQUENCER_28 0x101C |
225 | #define WM8962_WRITE_SEQUENCER_29 0x101D |
226 | #define WM8962_WRITE_SEQUENCER_30 0x101E |
227 | #define WM8962_WRITE_SEQUENCER_31 0x101F |
228 | #define WM8962_WRITE_SEQUENCER_32 0x1020 |
229 | #define WM8962_WRITE_SEQUENCER_33 0x1021 |
230 | #define WM8962_WRITE_SEQUENCER_34 0x1022 |
231 | #define WM8962_WRITE_SEQUENCER_35 0x1023 |
232 | #define WM8962_WRITE_SEQUENCER_36 0x1024 |
233 | #define WM8962_WRITE_SEQUENCER_37 0x1025 |
234 | #define WM8962_WRITE_SEQUENCER_38 0x1026 |
235 | #define WM8962_WRITE_SEQUENCER_39 0x1027 |
236 | #define WM8962_WRITE_SEQUENCER_40 0x1028 |
237 | #define WM8962_WRITE_SEQUENCER_41 0x1029 |
238 | #define WM8962_WRITE_SEQUENCER_42 0x102A |
239 | #define WM8962_WRITE_SEQUENCER_43 0x102B |
240 | #define WM8962_WRITE_SEQUENCER_44 0x102C |
241 | #define WM8962_WRITE_SEQUENCER_45 0x102D |
242 | #define WM8962_WRITE_SEQUENCER_46 0x102E |
243 | #define WM8962_WRITE_SEQUENCER_47 0x102F |
244 | #define WM8962_WRITE_SEQUENCER_48 0x1030 |
245 | #define WM8962_WRITE_SEQUENCER_49 0x1031 |
246 | #define WM8962_WRITE_SEQUENCER_50 0x1032 |
247 | #define WM8962_WRITE_SEQUENCER_51 0x1033 |
248 | #define WM8962_WRITE_SEQUENCER_52 0x1034 |
249 | #define WM8962_WRITE_SEQUENCER_53 0x1035 |
250 | #define WM8962_WRITE_SEQUENCER_54 0x1036 |
251 | #define WM8962_WRITE_SEQUENCER_55 0x1037 |
252 | #define WM8962_WRITE_SEQUENCER_56 0x1038 |
253 | #define WM8962_WRITE_SEQUENCER_57 0x1039 |
254 | #define WM8962_WRITE_SEQUENCER_58 0x103A |
255 | #define WM8962_WRITE_SEQUENCER_59 0x103B |
256 | #define WM8962_WRITE_SEQUENCER_60 0x103C |
257 | #define WM8962_WRITE_SEQUENCER_61 0x103D |
258 | #define WM8962_WRITE_SEQUENCER_62 0x103E |
259 | #define WM8962_WRITE_SEQUENCER_63 0x103F |
260 | #define WM8962_WRITE_SEQUENCER_64 0x1040 |
261 | #define WM8962_WRITE_SEQUENCER_65 0x1041 |
262 | #define WM8962_WRITE_SEQUENCER_66 0x1042 |
263 | #define WM8962_WRITE_SEQUENCER_67 0x1043 |
264 | #define WM8962_WRITE_SEQUENCER_68 0x1044 |
265 | #define WM8962_WRITE_SEQUENCER_69 0x1045 |
266 | #define WM8962_WRITE_SEQUENCER_70 0x1046 |
267 | #define WM8962_WRITE_SEQUENCER_71 0x1047 |
268 | #define WM8962_WRITE_SEQUENCER_72 0x1048 |
269 | #define WM8962_WRITE_SEQUENCER_73 0x1049 |
270 | #define WM8962_WRITE_SEQUENCER_74 0x104A |
271 | #define WM8962_WRITE_SEQUENCER_75 0x104B |
272 | #define WM8962_WRITE_SEQUENCER_76 0x104C |
273 | #define WM8962_WRITE_SEQUENCER_77 0x104D |
274 | #define WM8962_WRITE_SEQUENCER_78 0x104E |
275 | #define WM8962_WRITE_SEQUENCER_79 0x104F |
276 | #define WM8962_WRITE_SEQUENCER_80 0x1050 |
277 | #define WM8962_WRITE_SEQUENCER_81 0x1051 |
278 | #define WM8962_WRITE_SEQUENCER_82 0x1052 |
279 | #define WM8962_WRITE_SEQUENCER_83 0x1053 |
280 | #define WM8962_WRITE_SEQUENCER_84 0x1054 |
281 | #define WM8962_WRITE_SEQUENCER_85 0x1055 |
282 | #define WM8962_WRITE_SEQUENCER_86 0x1056 |
283 | #define WM8962_WRITE_SEQUENCER_87 0x1057 |
284 | #define WM8962_WRITE_SEQUENCER_88 0x1058 |
285 | #define WM8962_WRITE_SEQUENCER_89 0x1059 |
286 | #define WM8962_WRITE_SEQUENCER_90 0x105A |
287 | #define WM8962_WRITE_SEQUENCER_91 0x105B |
288 | #define WM8962_WRITE_SEQUENCER_92 0x105C |
289 | #define WM8962_WRITE_SEQUENCER_93 0x105D |
290 | #define WM8962_WRITE_SEQUENCER_94 0x105E |
291 | #define WM8962_WRITE_SEQUENCER_95 0x105F |
292 | #define WM8962_WRITE_SEQUENCER_96 0x1060 |
293 | #define WM8962_WRITE_SEQUENCER_97 0x1061 |
294 | #define WM8962_WRITE_SEQUENCER_98 0x1062 |
295 | #define WM8962_WRITE_SEQUENCER_99 0x1063 |
296 | #define WM8962_WRITE_SEQUENCER_100 0x1064 |
297 | #define WM8962_WRITE_SEQUENCER_101 0x1065 |
298 | #define WM8962_WRITE_SEQUENCER_102 0x1066 |
299 | #define WM8962_WRITE_SEQUENCER_103 0x1067 |
300 | #define WM8962_WRITE_SEQUENCER_104 0x1068 |
301 | #define WM8962_WRITE_SEQUENCER_105 0x1069 |
302 | #define WM8962_WRITE_SEQUENCER_106 0x106A |
303 | #define WM8962_WRITE_SEQUENCER_107 0x106B |
304 | #define WM8962_WRITE_SEQUENCER_108 0x106C |
305 | #define WM8962_WRITE_SEQUENCER_109 0x106D |
306 | #define WM8962_WRITE_SEQUENCER_110 0x106E |
307 | #define WM8962_WRITE_SEQUENCER_111 0x106F |
308 | #define WM8962_WRITE_SEQUENCER_112 0x1070 |
309 | #define WM8962_WRITE_SEQUENCER_113 0x1071 |
310 | #define WM8962_WRITE_SEQUENCER_114 0x1072 |
311 | #define WM8962_WRITE_SEQUENCER_115 0x1073 |
312 | #define WM8962_WRITE_SEQUENCER_116 0x1074 |
313 | #define WM8962_WRITE_SEQUENCER_117 0x1075 |
314 | #define WM8962_WRITE_SEQUENCER_118 0x1076 |
315 | #define WM8962_WRITE_SEQUENCER_119 0x1077 |
316 | #define WM8962_WRITE_SEQUENCER_120 0x1078 |
317 | #define WM8962_WRITE_SEQUENCER_121 0x1079 |
318 | #define WM8962_WRITE_SEQUENCER_122 0x107A |
319 | #define WM8962_WRITE_SEQUENCER_123 0x107B |
320 | #define WM8962_WRITE_SEQUENCER_124 0x107C |
321 | #define WM8962_WRITE_SEQUENCER_125 0x107D |
322 | #define WM8962_WRITE_SEQUENCER_126 0x107E |
323 | #define WM8962_WRITE_SEQUENCER_127 0x107F |
324 | #define WM8962_WRITE_SEQUENCER_128 0x1080 |
325 | #define WM8962_WRITE_SEQUENCER_129 0x1081 |
326 | #define WM8962_WRITE_SEQUENCER_130 0x1082 |
327 | #define WM8962_WRITE_SEQUENCER_131 0x1083 |
328 | #define WM8962_WRITE_SEQUENCER_132 0x1084 |
329 | #define WM8962_WRITE_SEQUENCER_133 0x1085 |
330 | #define WM8962_WRITE_SEQUENCER_134 0x1086 |
331 | #define WM8962_WRITE_SEQUENCER_135 0x1087 |
332 | #define WM8962_WRITE_SEQUENCER_136 0x1088 |
333 | #define WM8962_WRITE_SEQUENCER_137 0x1089 |
334 | #define WM8962_WRITE_SEQUENCER_138 0x108A |
335 | #define WM8962_WRITE_SEQUENCER_139 0x108B |
336 | #define WM8962_WRITE_SEQUENCER_140 0x108C |
337 | #define WM8962_WRITE_SEQUENCER_141 0x108D |
338 | #define WM8962_WRITE_SEQUENCER_142 0x108E |
339 | #define WM8962_WRITE_SEQUENCER_143 0x108F |
340 | #define WM8962_WRITE_SEQUENCER_144 0x1090 |
341 | #define WM8962_WRITE_SEQUENCER_145 0x1091 |
342 | #define WM8962_WRITE_SEQUENCER_146 0x1092 |
343 | #define WM8962_WRITE_SEQUENCER_147 0x1093 |
344 | #define WM8962_WRITE_SEQUENCER_148 0x1094 |
345 | #define WM8962_WRITE_SEQUENCER_149 0x1095 |
346 | #define WM8962_WRITE_SEQUENCER_150 0x1096 |
347 | #define WM8962_WRITE_SEQUENCER_151 0x1097 |
348 | #define WM8962_WRITE_SEQUENCER_152 0x1098 |
349 | #define WM8962_WRITE_SEQUENCER_153 0x1099 |
350 | #define WM8962_WRITE_SEQUENCER_154 0x109A |
351 | #define WM8962_WRITE_SEQUENCER_155 0x109B |
352 | #define WM8962_WRITE_SEQUENCER_156 0x109C |
353 | #define WM8962_WRITE_SEQUENCER_157 0x109D |
354 | #define WM8962_WRITE_SEQUENCER_158 0x109E |
355 | #define WM8962_WRITE_SEQUENCER_159 0x109F |
356 | #define WM8962_WRITE_SEQUENCER_160 0x10A0 |
357 | #define WM8962_WRITE_SEQUENCER_161 0x10A1 |
358 | #define WM8962_WRITE_SEQUENCER_162 0x10A2 |
359 | #define WM8962_WRITE_SEQUENCER_163 0x10A3 |
360 | #define WM8962_WRITE_SEQUENCER_164 0x10A4 |
361 | #define WM8962_WRITE_SEQUENCER_165 0x10A5 |
362 | #define WM8962_WRITE_SEQUENCER_166 0x10A6 |
363 | #define WM8962_WRITE_SEQUENCER_167 0x10A7 |
364 | #define WM8962_WRITE_SEQUENCER_168 0x10A8 |
365 | #define WM8962_WRITE_SEQUENCER_169 0x10A9 |
366 | #define WM8962_WRITE_SEQUENCER_170 0x10AA |
367 | #define WM8962_WRITE_SEQUENCER_171 0x10AB |
368 | #define WM8962_WRITE_SEQUENCER_172 0x10AC |
369 | #define WM8962_WRITE_SEQUENCER_173 0x10AD |
370 | #define WM8962_WRITE_SEQUENCER_174 0x10AE |
371 | #define WM8962_WRITE_SEQUENCER_175 0x10AF |
372 | #define WM8962_WRITE_SEQUENCER_176 0x10B0 |
373 | #define WM8962_WRITE_SEQUENCER_177 0x10B1 |
374 | #define WM8962_WRITE_SEQUENCER_178 0x10B2 |
375 | #define WM8962_WRITE_SEQUENCER_179 0x10B3 |
376 | #define WM8962_WRITE_SEQUENCER_180 0x10B4 |
377 | #define WM8962_WRITE_SEQUENCER_181 0x10B5 |
378 | #define WM8962_WRITE_SEQUENCER_182 0x10B6 |
379 | #define WM8962_WRITE_SEQUENCER_183 0x10B7 |
380 | #define WM8962_WRITE_SEQUENCER_184 0x10B8 |
381 | #define WM8962_WRITE_SEQUENCER_185 0x10B9 |
382 | #define WM8962_WRITE_SEQUENCER_186 0x10BA |
383 | #define WM8962_WRITE_SEQUENCER_187 0x10BB |
384 | #define WM8962_WRITE_SEQUENCER_188 0x10BC |
385 | #define WM8962_WRITE_SEQUENCER_189 0x10BD |
386 | #define WM8962_WRITE_SEQUENCER_190 0x10BE |
387 | #define WM8962_WRITE_SEQUENCER_191 0x10BF |
388 | #define WM8962_WRITE_SEQUENCER_192 0x10C0 |
389 | #define WM8962_WRITE_SEQUENCER_193 0x10C1 |
390 | #define WM8962_WRITE_SEQUENCER_194 0x10C2 |
391 | #define WM8962_WRITE_SEQUENCER_195 0x10C3 |
392 | #define WM8962_WRITE_SEQUENCER_196 0x10C4 |
393 | #define WM8962_WRITE_SEQUENCER_197 0x10C5 |
394 | #define WM8962_WRITE_SEQUENCER_198 0x10C6 |
395 | #define WM8962_WRITE_SEQUENCER_199 0x10C7 |
396 | #define WM8962_WRITE_SEQUENCER_200 0x10C8 |
397 | #define WM8962_WRITE_SEQUENCER_201 0x10C9 |
398 | #define WM8962_WRITE_SEQUENCER_202 0x10CA |
399 | #define WM8962_WRITE_SEQUENCER_203 0x10CB |
400 | #define WM8962_WRITE_SEQUENCER_204 0x10CC |
401 | #define WM8962_WRITE_SEQUENCER_205 0x10CD |
402 | #define WM8962_WRITE_SEQUENCER_206 0x10CE |
403 | #define WM8962_WRITE_SEQUENCER_207 0x10CF |
404 | #define WM8962_WRITE_SEQUENCER_208 0x10D0 |
405 | #define WM8962_WRITE_SEQUENCER_209 0x10D1 |
406 | #define WM8962_WRITE_SEQUENCER_210 0x10D2 |
407 | #define WM8962_WRITE_SEQUENCER_211 0x10D3 |
408 | #define WM8962_WRITE_SEQUENCER_212 0x10D4 |
409 | #define WM8962_WRITE_SEQUENCER_213 0x10D5 |
410 | #define WM8962_WRITE_SEQUENCER_214 0x10D6 |
411 | #define WM8962_WRITE_SEQUENCER_215 0x10D7 |
412 | #define WM8962_WRITE_SEQUENCER_216 0x10D8 |
413 | #define WM8962_WRITE_SEQUENCER_217 0x10D9 |
414 | #define WM8962_WRITE_SEQUENCER_218 0x10DA |
415 | #define WM8962_WRITE_SEQUENCER_219 0x10DB |
416 | #define WM8962_WRITE_SEQUENCER_220 0x10DC |
417 | #define WM8962_WRITE_SEQUENCER_221 0x10DD |
418 | #define WM8962_WRITE_SEQUENCER_222 0x10DE |
419 | #define WM8962_WRITE_SEQUENCER_223 0x10DF |
420 | #define WM8962_WRITE_SEQUENCER_224 0x10E0 |
421 | #define WM8962_WRITE_SEQUENCER_225 0x10E1 |
422 | #define WM8962_WRITE_SEQUENCER_226 0x10E2 |
423 | #define WM8962_WRITE_SEQUENCER_227 0x10E3 |
424 | #define WM8962_WRITE_SEQUENCER_228 0x10E4 |
425 | #define WM8962_WRITE_SEQUENCER_229 0x10E5 |
426 | #define WM8962_WRITE_SEQUENCER_230 0x10E6 |
427 | #define WM8962_WRITE_SEQUENCER_231 0x10E7 |
428 | #define WM8962_WRITE_SEQUENCER_232 0x10E8 |
429 | #define WM8962_WRITE_SEQUENCER_233 0x10E9 |
430 | #define WM8962_WRITE_SEQUENCER_234 0x10EA |
431 | #define WM8962_WRITE_SEQUENCER_235 0x10EB |
432 | #define WM8962_WRITE_SEQUENCER_236 0x10EC |
433 | #define WM8962_WRITE_SEQUENCER_237 0x10ED |
434 | #define WM8962_WRITE_SEQUENCER_238 0x10EE |
435 | #define WM8962_WRITE_SEQUENCER_239 0x10EF |
436 | #define WM8962_WRITE_SEQUENCER_240 0x10F0 |
437 | #define WM8962_WRITE_SEQUENCER_241 0x10F1 |
438 | #define WM8962_WRITE_SEQUENCER_242 0x10F2 |
439 | #define WM8962_WRITE_SEQUENCER_243 0x10F3 |
440 | #define WM8962_WRITE_SEQUENCER_244 0x10F4 |
441 | #define WM8962_WRITE_SEQUENCER_245 0x10F5 |
442 | #define WM8962_WRITE_SEQUENCER_246 0x10F6 |
443 | #define WM8962_WRITE_SEQUENCER_247 0x10F7 |
444 | #define WM8962_WRITE_SEQUENCER_248 0x10F8 |
445 | #define WM8962_WRITE_SEQUENCER_249 0x10F9 |
446 | #define WM8962_WRITE_SEQUENCER_250 0x10FA |
447 | #define WM8962_WRITE_SEQUENCER_251 0x10FB |
448 | #define WM8962_WRITE_SEQUENCER_252 0x10FC |
449 | #define WM8962_WRITE_SEQUENCER_253 0x10FD |
450 | #define WM8962_WRITE_SEQUENCER_254 0x10FE |
451 | #define WM8962_WRITE_SEQUENCER_255 0x10FF |
452 | #define WM8962_WRITE_SEQUENCER_256 0x1100 |
453 | #define WM8962_WRITE_SEQUENCER_257 0x1101 |
454 | #define WM8962_WRITE_SEQUENCER_258 0x1102 |
455 | #define WM8962_WRITE_SEQUENCER_259 0x1103 |
456 | #define WM8962_WRITE_SEQUENCER_260 0x1104 |
457 | #define WM8962_WRITE_SEQUENCER_261 0x1105 |
458 | #define WM8962_WRITE_SEQUENCER_262 0x1106 |
459 | #define WM8962_WRITE_SEQUENCER_263 0x1107 |
460 | #define WM8962_WRITE_SEQUENCER_264 0x1108 |
461 | #define WM8962_WRITE_SEQUENCER_265 0x1109 |
462 | #define WM8962_WRITE_SEQUENCER_266 0x110A |
463 | #define WM8962_WRITE_SEQUENCER_267 0x110B |
464 | #define WM8962_WRITE_SEQUENCER_268 0x110C |
465 | #define WM8962_WRITE_SEQUENCER_269 0x110D |
466 | #define WM8962_WRITE_SEQUENCER_270 0x110E |
467 | #define WM8962_WRITE_SEQUENCER_271 0x110F |
468 | #define WM8962_WRITE_SEQUENCER_272 0x1110 |
469 | #define WM8962_WRITE_SEQUENCER_273 0x1111 |
470 | #define WM8962_WRITE_SEQUENCER_274 0x1112 |
471 | #define WM8962_WRITE_SEQUENCER_275 0x1113 |
472 | #define WM8962_WRITE_SEQUENCER_276 0x1114 |
473 | #define WM8962_WRITE_SEQUENCER_277 0x1115 |
474 | #define WM8962_WRITE_SEQUENCER_278 0x1116 |
475 | #define WM8962_WRITE_SEQUENCER_279 0x1117 |
476 | #define WM8962_WRITE_SEQUENCER_280 0x1118 |
477 | #define WM8962_WRITE_SEQUENCER_281 0x1119 |
478 | #define WM8962_WRITE_SEQUENCER_282 0x111A |
479 | #define WM8962_WRITE_SEQUENCER_283 0x111B |
480 | #define WM8962_WRITE_SEQUENCER_284 0x111C |
481 | #define WM8962_WRITE_SEQUENCER_285 0x111D |
482 | #define WM8962_WRITE_SEQUENCER_286 0x111E |
483 | #define WM8962_WRITE_SEQUENCER_287 0x111F |
484 | #define WM8962_WRITE_SEQUENCER_288 0x1120 |
485 | #define WM8962_WRITE_SEQUENCER_289 0x1121 |
486 | #define WM8962_WRITE_SEQUENCER_290 0x1122 |
487 | #define WM8962_WRITE_SEQUENCER_291 0x1123 |
488 | #define WM8962_WRITE_SEQUENCER_292 0x1124 |
489 | #define WM8962_WRITE_SEQUENCER_293 0x1125 |
490 | #define WM8962_WRITE_SEQUENCER_294 0x1126 |
491 | #define WM8962_WRITE_SEQUENCER_295 0x1127 |
492 | #define WM8962_WRITE_SEQUENCER_296 0x1128 |
493 | #define WM8962_WRITE_SEQUENCER_297 0x1129 |
494 | #define WM8962_WRITE_SEQUENCER_298 0x112A |
495 | #define WM8962_WRITE_SEQUENCER_299 0x112B |
496 | #define WM8962_WRITE_SEQUENCER_300 0x112C |
497 | #define WM8962_WRITE_SEQUENCER_301 0x112D |
498 | #define WM8962_WRITE_SEQUENCER_302 0x112E |
499 | #define WM8962_WRITE_SEQUENCER_303 0x112F |
500 | #define WM8962_WRITE_SEQUENCER_304 0x1130 |
501 | #define WM8962_WRITE_SEQUENCER_305 0x1131 |
502 | #define WM8962_WRITE_SEQUENCER_306 0x1132 |
503 | #define WM8962_WRITE_SEQUENCER_307 0x1133 |
504 | #define WM8962_WRITE_SEQUENCER_308 0x1134 |
505 | #define WM8962_WRITE_SEQUENCER_309 0x1135 |
506 | #define WM8962_WRITE_SEQUENCER_310 0x1136 |
507 | #define WM8962_WRITE_SEQUENCER_311 0x1137 |
508 | #define WM8962_WRITE_SEQUENCER_312 0x1138 |
509 | #define WM8962_WRITE_SEQUENCER_313 0x1139 |
510 | #define WM8962_WRITE_SEQUENCER_314 0x113A |
511 | #define WM8962_WRITE_SEQUENCER_315 0x113B |
512 | #define WM8962_WRITE_SEQUENCER_316 0x113C |
513 | #define WM8962_WRITE_SEQUENCER_317 0x113D |
514 | #define WM8962_WRITE_SEQUENCER_318 0x113E |
515 | #define WM8962_WRITE_SEQUENCER_319 0x113F |
516 | #define WM8962_WRITE_SEQUENCER_320 0x1140 |
517 | #define WM8962_WRITE_SEQUENCER_321 0x1141 |
518 | #define WM8962_WRITE_SEQUENCER_322 0x1142 |
519 | #define WM8962_WRITE_SEQUENCER_323 0x1143 |
520 | #define WM8962_WRITE_SEQUENCER_324 0x1144 |
521 | #define WM8962_WRITE_SEQUENCER_325 0x1145 |
522 | #define WM8962_WRITE_SEQUENCER_326 0x1146 |
523 | #define WM8962_WRITE_SEQUENCER_327 0x1147 |
524 | #define WM8962_WRITE_SEQUENCER_328 0x1148 |
525 | #define WM8962_WRITE_SEQUENCER_329 0x1149 |
526 | #define WM8962_WRITE_SEQUENCER_330 0x114A |
527 | #define WM8962_WRITE_SEQUENCER_331 0x114B |
528 | #define WM8962_WRITE_SEQUENCER_332 0x114C |
529 | #define WM8962_WRITE_SEQUENCER_333 0x114D |
530 | #define WM8962_WRITE_SEQUENCER_334 0x114E |
531 | #define WM8962_WRITE_SEQUENCER_335 0x114F |
532 | #define WM8962_WRITE_SEQUENCER_336 0x1150 |
533 | #define WM8962_WRITE_SEQUENCER_337 0x1151 |
534 | #define WM8962_WRITE_SEQUENCER_338 0x1152 |
535 | #define WM8962_WRITE_SEQUENCER_339 0x1153 |
536 | #define WM8962_WRITE_SEQUENCER_340 0x1154 |
537 | #define WM8962_WRITE_SEQUENCER_341 0x1155 |
538 | #define WM8962_WRITE_SEQUENCER_342 0x1156 |
539 | #define WM8962_WRITE_SEQUENCER_343 0x1157 |
540 | #define WM8962_WRITE_SEQUENCER_344 0x1158 |
541 | #define WM8962_WRITE_SEQUENCER_345 0x1159 |
542 | #define WM8962_WRITE_SEQUENCER_346 0x115A |
543 | #define WM8962_WRITE_SEQUENCER_347 0x115B |
544 | #define WM8962_WRITE_SEQUENCER_348 0x115C |
545 | #define WM8962_WRITE_SEQUENCER_349 0x115D |
546 | #define WM8962_WRITE_SEQUENCER_350 0x115E |
547 | #define WM8962_WRITE_SEQUENCER_351 0x115F |
548 | #define WM8962_WRITE_SEQUENCER_352 0x1160 |
549 | #define WM8962_WRITE_SEQUENCER_353 0x1161 |
550 | #define WM8962_WRITE_SEQUENCER_354 0x1162 |
551 | #define WM8962_WRITE_SEQUENCER_355 0x1163 |
552 | #define WM8962_WRITE_SEQUENCER_356 0x1164 |
553 | #define WM8962_WRITE_SEQUENCER_357 0x1165 |
554 | #define WM8962_WRITE_SEQUENCER_358 0x1166 |
555 | #define WM8962_WRITE_SEQUENCER_359 0x1167 |
556 | #define WM8962_WRITE_SEQUENCER_360 0x1168 |
557 | #define WM8962_WRITE_SEQUENCER_361 0x1169 |
558 | #define WM8962_WRITE_SEQUENCER_362 0x116A |
559 | #define WM8962_WRITE_SEQUENCER_363 0x116B |
560 | #define WM8962_WRITE_SEQUENCER_364 0x116C |
561 | #define WM8962_WRITE_SEQUENCER_365 0x116D |
562 | #define WM8962_WRITE_SEQUENCER_366 0x116E |
563 | #define WM8962_WRITE_SEQUENCER_367 0x116F |
564 | #define WM8962_WRITE_SEQUENCER_368 0x1170 |
565 | #define WM8962_WRITE_SEQUENCER_369 0x1171 |
566 | #define WM8962_WRITE_SEQUENCER_370 0x1172 |
567 | #define WM8962_WRITE_SEQUENCER_371 0x1173 |
568 | #define WM8962_WRITE_SEQUENCER_372 0x1174 |
569 | #define WM8962_WRITE_SEQUENCER_373 0x1175 |
570 | #define WM8962_WRITE_SEQUENCER_374 0x1176 |
571 | #define WM8962_WRITE_SEQUENCER_375 0x1177 |
572 | #define WM8962_WRITE_SEQUENCER_376 0x1178 |
573 | #define WM8962_WRITE_SEQUENCER_377 0x1179 |
574 | #define WM8962_WRITE_SEQUENCER_378 0x117A |
575 | #define WM8962_WRITE_SEQUENCER_379 0x117B |
576 | #define WM8962_WRITE_SEQUENCER_380 0x117C |
577 | #define WM8962_WRITE_SEQUENCER_381 0x117D |
578 | #define WM8962_WRITE_SEQUENCER_382 0x117E |
579 | #define WM8962_WRITE_SEQUENCER_383 0x117F |
580 | #define WM8962_WRITE_SEQUENCER_384 0x1180 |
581 | #define WM8962_WRITE_SEQUENCER_385 0x1181 |
582 | #define WM8962_WRITE_SEQUENCER_386 0x1182 |
583 | #define WM8962_WRITE_SEQUENCER_387 0x1183 |
584 | #define WM8962_WRITE_SEQUENCER_388 0x1184 |
585 | #define WM8962_WRITE_SEQUENCER_389 0x1185 |
586 | #define WM8962_WRITE_SEQUENCER_390 0x1186 |
587 | #define WM8962_WRITE_SEQUENCER_391 0x1187 |
588 | #define WM8962_WRITE_SEQUENCER_392 0x1188 |
589 | #define WM8962_WRITE_SEQUENCER_393 0x1189 |
590 | #define WM8962_WRITE_SEQUENCER_394 0x118A |
591 | #define WM8962_WRITE_SEQUENCER_395 0x118B |
592 | #define WM8962_WRITE_SEQUENCER_396 0x118C |
593 | #define WM8962_WRITE_SEQUENCER_397 0x118D |
594 | #define WM8962_WRITE_SEQUENCER_398 0x118E |
595 | #define WM8962_WRITE_SEQUENCER_399 0x118F |
596 | #define WM8962_WRITE_SEQUENCER_400 0x1190 |
597 | #define WM8962_WRITE_SEQUENCER_401 0x1191 |
598 | #define WM8962_WRITE_SEQUENCER_402 0x1192 |
599 | #define WM8962_WRITE_SEQUENCER_403 0x1193 |
600 | #define WM8962_WRITE_SEQUENCER_404 0x1194 |
601 | #define WM8962_WRITE_SEQUENCER_405 0x1195 |
602 | #define WM8962_WRITE_SEQUENCER_406 0x1196 |
603 | #define WM8962_WRITE_SEQUENCER_407 0x1197 |
604 | #define WM8962_WRITE_SEQUENCER_408 0x1198 |
605 | #define WM8962_WRITE_SEQUENCER_409 0x1199 |
606 | #define WM8962_WRITE_SEQUENCER_410 0x119A |
607 | #define WM8962_WRITE_SEQUENCER_411 0x119B |
608 | #define WM8962_WRITE_SEQUENCER_412 0x119C |
609 | #define WM8962_WRITE_SEQUENCER_413 0x119D |
610 | #define WM8962_WRITE_SEQUENCER_414 0x119E |
611 | #define WM8962_WRITE_SEQUENCER_415 0x119F |
612 | #define WM8962_WRITE_SEQUENCER_416 0x11A0 |
613 | #define WM8962_WRITE_SEQUENCER_417 0x11A1 |
614 | #define WM8962_WRITE_SEQUENCER_418 0x11A2 |
615 | #define WM8962_WRITE_SEQUENCER_419 0x11A3 |
616 | #define WM8962_WRITE_SEQUENCER_420 0x11A4 |
617 | #define WM8962_WRITE_SEQUENCER_421 0x11A5 |
618 | #define WM8962_WRITE_SEQUENCER_422 0x11A6 |
619 | #define WM8962_WRITE_SEQUENCER_423 0x11A7 |
620 | #define WM8962_WRITE_SEQUENCER_424 0x11A8 |
621 | #define WM8962_WRITE_SEQUENCER_425 0x11A9 |
622 | #define WM8962_WRITE_SEQUENCER_426 0x11AA |
623 | #define WM8962_WRITE_SEQUENCER_427 0x11AB |
624 | #define WM8962_WRITE_SEQUENCER_428 0x11AC |
625 | #define WM8962_WRITE_SEQUENCER_429 0x11AD |
626 | #define WM8962_WRITE_SEQUENCER_430 0x11AE |
627 | #define WM8962_WRITE_SEQUENCER_431 0x11AF |
628 | #define WM8962_WRITE_SEQUENCER_432 0x11B0 |
629 | #define WM8962_WRITE_SEQUENCER_433 0x11B1 |
630 | #define WM8962_WRITE_SEQUENCER_434 0x11B2 |
631 | #define WM8962_WRITE_SEQUENCER_435 0x11B3 |
632 | #define WM8962_WRITE_SEQUENCER_436 0x11B4 |
633 | #define WM8962_WRITE_SEQUENCER_437 0x11B5 |
634 | #define WM8962_WRITE_SEQUENCER_438 0x11B6 |
635 | #define WM8962_WRITE_SEQUENCER_439 0x11B7 |
636 | #define WM8962_WRITE_SEQUENCER_440 0x11B8 |
637 | #define WM8962_WRITE_SEQUENCER_441 0x11B9 |
638 | #define WM8962_WRITE_SEQUENCER_442 0x11BA |
639 | #define WM8962_WRITE_SEQUENCER_443 0x11BB |
640 | #define WM8962_WRITE_SEQUENCER_444 0x11BC |
641 | #define WM8962_WRITE_SEQUENCER_445 0x11BD |
642 | #define WM8962_WRITE_SEQUENCER_446 0x11BE |
643 | #define WM8962_WRITE_SEQUENCER_447 0x11BF |
644 | #define WM8962_WRITE_SEQUENCER_448 0x11C0 |
645 | #define WM8962_WRITE_SEQUENCER_449 0x11C1 |
646 | #define WM8962_WRITE_SEQUENCER_450 0x11C2 |
647 | #define WM8962_WRITE_SEQUENCER_451 0x11C3 |
648 | #define WM8962_WRITE_SEQUENCER_452 0x11C4 |
649 | #define WM8962_WRITE_SEQUENCER_453 0x11C5 |
650 | #define WM8962_WRITE_SEQUENCER_454 0x11C6 |
651 | #define WM8962_WRITE_SEQUENCER_455 0x11C7 |
652 | #define WM8962_WRITE_SEQUENCER_456 0x11C8 |
653 | #define WM8962_WRITE_SEQUENCER_457 0x11C9 |
654 | #define WM8962_WRITE_SEQUENCER_458 0x11CA |
655 | #define WM8962_WRITE_SEQUENCER_459 0x11CB |
656 | #define WM8962_WRITE_SEQUENCER_460 0x11CC |
657 | #define WM8962_WRITE_SEQUENCER_461 0x11CD |
658 | #define WM8962_WRITE_SEQUENCER_462 0x11CE |
659 | #define WM8962_WRITE_SEQUENCER_463 0x11CF |
660 | #define WM8962_WRITE_SEQUENCER_464 0x11D0 |
661 | #define WM8962_WRITE_SEQUENCER_465 0x11D1 |
662 | #define WM8962_WRITE_SEQUENCER_466 0x11D2 |
663 | #define WM8962_WRITE_SEQUENCER_467 0x11D3 |
664 | #define WM8962_WRITE_SEQUENCER_468 0x11D4 |
665 | #define WM8962_WRITE_SEQUENCER_469 0x11D5 |
666 | #define WM8962_WRITE_SEQUENCER_470 0x11D6 |
667 | #define WM8962_WRITE_SEQUENCER_471 0x11D7 |
668 | #define WM8962_WRITE_SEQUENCER_472 0x11D8 |
669 | #define WM8962_WRITE_SEQUENCER_473 0x11D9 |
670 | #define WM8962_WRITE_SEQUENCER_474 0x11DA |
671 | #define WM8962_WRITE_SEQUENCER_475 0x11DB |
672 | #define WM8962_WRITE_SEQUENCER_476 0x11DC |
673 | #define WM8962_WRITE_SEQUENCER_477 0x11DD |
674 | #define WM8962_WRITE_SEQUENCER_478 0x11DE |
675 | #define WM8962_WRITE_SEQUENCER_479 0x11DF |
676 | #define WM8962_WRITE_SEQUENCER_480 0x11E0 |
677 | #define WM8962_WRITE_SEQUENCER_481 0x11E1 |
678 | #define WM8962_WRITE_SEQUENCER_482 0x11E2 |
679 | #define WM8962_WRITE_SEQUENCER_483 0x11E3 |
680 | #define WM8962_WRITE_SEQUENCER_484 0x11E4 |
681 | #define WM8962_WRITE_SEQUENCER_485 0x11E5 |
682 | #define WM8962_WRITE_SEQUENCER_486 0x11E6 |
683 | #define WM8962_WRITE_SEQUENCER_487 0x11E7 |
684 | #define WM8962_WRITE_SEQUENCER_488 0x11E8 |
685 | #define WM8962_WRITE_SEQUENCER_489 0x11E9 |
686 | #define WM8962_WRITE_SEQUENCER_490 0x11EA |
687 | #define WM8962_WRITE_SEQUENCER_491 0x11EB |
688 | #define WM8962_WRITE_SEQUENCER_492 0x11EC |
689 | #define WM8962_WRITE_SEQUENCER_493 0x11ED |
690 | #define WM8962_WRITE_SEQUENCER_494 0x11EE |
691 | #define WM8962_WRITE_SEQUENCER_495 0x11EF |
692 | #define WM8962_WRITE_SEQUENCER_496 0x11F0 |
693 | #define WM8962_WRITE_SEQUENCER_497 0x11F1 |
694 | #define WM8962_WRITE_SEQUENCER_498 0x11F2 |
695 | #define WM8962_WRITE_SEQUENCER_499 0x11F3 |
696 | #define WM8962_WRITE_SEQUENCER_500 0x11F4 |
697 | #define WM8962_WRITE_SEQUENCER_501 0x11F5 |
698 | #define WM8962_WRITE_SEQUENCER_502 0x11F6 |
699 | #define WM8962_WRITE_SEQUENCER_503 0x11F7 |
700 | #define WM8962_WRITE_SEQUENCER_504 0x11F8 |
701 | #define WM8962_WRITE_SEQUENCER_505 0x11F9 |
702 | #define WM8962_WRITE_SEQUENCER_506 0x11FA |
703 | #define WM8962_WRITE_SEQUENCER_507 0x11FB |
704 | #define WM8962_WRITE_SEQUENCER_508 0x11FC |
705 | #define WM8962_WRITE_SEQUENCER_509 0x11FD |
706 | #define WM8962_WRITE_SEQUENCER_510 0x11FE |
707 | #define WM8962_WRITE_SEQUENCER_511 0x11FF |
708 | #define WM8962_DSP2_INSTRUCTION_RAM_0 0x2000 |
709 | #define WM8962_DSP2_ADDRESS_RAM_2 0x2400 |
710 | #define WM8962_DSP2_ADDRESS_RAM_1 0x2401 |
711 | #define WM8962_DSP2_ADDRESS_RAM_0 0x2402 |
712 | #define WM8962_DSP2_DATA1_RAM_1 0x3000 |
713 | #define WM8962_DSP2_DATA1_RAM_0 0x3001 |
714 | #define WM8962_DSP2_DATA2_RAM_1 0x3400 |
715 | #define WM8962_DSP2_DATA2_RAM_0 0x3401 |
716 | #define WM8962_DSP2_DATA3_RAM_1 0x3800 |
717 | #define WM8962_DSP2_DATA3_RAM_0 0x3801 |
718 | #define WM8962_DSP2_COEFF_RAM_0 0x3C00 |
719 | #define WM8962_RETUNEADC_SHARED_COEFF_1 0x4000 |
720 | #define WM8962_RETUNEADC_SHARED_COEFF_0 0x4001 |
721 | #define WM8962_RETUNEDAC_SHARED_COEFF_1 0x4002 |
722 | #define WM8962_RETUNEDAC_SHARED_COEFF_0 0x4003 |
723 | #define WM8962_SOUNDSTAGE_ENABLES_1 0x4004 |
724 | #define WM8962_SOUNDSTAGE_ENABLES_0 0x4005 |
725 | #define WM8962_HDBASS_AI_1 0x4200 |
726 | #define WM8962_HDBASS_AI_0 0x4201 |
727 | #define WM8962_HDBASS_AR_1 0x4202 |
728 | #define WM8962_HDBASS_AR_0 0x4203 |
729 | #define WM8962_HDBASS_B_1 0x4204 |
730 | #define WM8962_HDBASS_B_0 0x4205 |
731 | #define WM8962_HDBASS_K_1 0x4206 |
732 | #define WM8962_HDBASS_K_0 0x4207 |
733 | #define WM8962_HDBASS_N1_1 0x4208 |
734 | #define WM8962_HDBASS_N1_0 0x4209 |
735 | #define WM8962_HDBASS_N2_1 0x420A |
736 | #define WM8962_HDBASS_N2_0 0x420B |
737 | #define WM8962_HDBASS_N3_1 0x420C |
738 | #define WM8962_HDBASS_N3_0 0x420D |
739 | #define WM8962_HDBASS_N4_1 0x420E |
740 | #define WM8962_HDBASS_N4_0 0x420F |
741 | #define WM8962_HDBASS_N5_1 0x4210 |
742 | #define WM8962_HDBASS_N5_0 0x4211 |
743 | #define WM8962_HDBASS_X1_1 0x4212 |
744 | #define WM8962_HDBASS_X1_0 0x4213 |
745 | #define WM8962_HDBASS_X2_1 0x4214 |
746 | #define WM8962_HDBASS_X2_0 0x4215 |
747 | #define WM8962_HDBASS_X3_1 0x4216 |
748 | #define WM8962_HDBASS_X3_0 0x4217 |
749 | #define WM8962_HDBASS_ATK_1 0x4218 |
750 | #define WM8962_HDBASS_ATK_0 0x4219 |
751 | #define WM8962_HDBASS_DCY_1 0x421A |
752 | #define WM8962_HDBASS_DCY_0 0x421B |
753 | #define WM8962_HDBASS_PG_1 0x421C |
754 | #define WM8962_HDBASS_PG_0 0x421D |
755 | #define WM8962_HPF_C_1 0x4400 |
756 | #define WM8962_HPF_C_0 0x4401 |
757 | #define WM8962_ADCL_RETUNE_C1_1 0x4600 |
758 | #define WM8962_ADCL_RETUNE_C1_0 0x4601 |
759 | #define WM8962_ADCL_RETUNE_C2_1 0x4602 |
760 | #define WM8962_ADCL_RETUNE_C2_0 0x4603 |
761 | #define WM8962_ADCL_RETUNE_C3_1 0x4604 |
762 | #define WM8962_ADCL_RETUNE_C3_0 0x4605 |
763 | #define WM8962_ADCL_RETUNE_C4_1 0x4606 |
764 | #define WM8962_ADCL_RETUNE_C4_0 0x4607 |
765 | #define WM8962_ADCL_RETUNE_C5_1 0x4608 |
766 | #define WM8962_ADCL_RETUNE_C5_0 0x4609 |
767 | #define WM8962_ADCL_RETUNE_C6_1 0x460A |
768 | #define WM8962_ADCL_RETUNE_C6_0 0x460B |
769 | #define WM8962_ADCL_RETUNE_C7_1 0x460C |
770 | #define WM8962_ADCL_RETUNE_C7_0 0x460D |
771 | #define WM8962_ADCL_RETUNE_C8_1 0x460E |
772 | #define WM8962_ADCL_RETUNE_C8_0 0x460F |
773 | #define WM8962_ADCL_RETUNE_C9_1 0x4610 |
774 | #define WM8962_ADCL_RETUNE_C9_0 0x4611 |
775 | #define WM8962_ADCL_RETUNE_C10_1 0x4612 |
776 | #define WM8962_ADCL_RETUNE_C10_0 0x4613 |
777 | #define WM8962_ADCL_RETUNE_C11_1 0x4614 |
778 | #define WM8962_ADCL_RETUNE_C11_0 0x4615 |
779 | #define WM8962_ADCL_RETUNE_C12_1 0x4616 |
780 | #define WM8962_ADCL_RETUNE_C12_0 0x4617 |
781 | #define WM8962_ADCL_RETUNE_C13_1 0x4618 |
782 | #define WM8962_ADCL_RETUNE_C13_0 0x4619 |
783 | #define WM8962_ADCL_RETUNE_C14_1 0x461A |
784 | #define WM8962_ADCL_RETUNE_C14_0 0x461B |
785 | #define WM8962_ADCL_RETUNE_C15_1 0x461C |
786 | #define WM8962_ADCL_RETUNE_C15_0 0x461D |
787 | #define WM8962_ADCL_RETUNE_C16_1 0x461E |
788 | #define WM8962_ADCL_RETUNE_C16_0 0x461F |
789 | #define WM8962_ADCL_RETUNE_C17_1 0x4620 |
790 | #define WM8962_ADCL_RETUNE_C17_0 0x4621 |
791 | #define WM8962_ADCL_RETUNE_C18_1 0x4622 |
792 | #define WM8962_ADCL_RETUNE_C18_0 0x4623 |
793 | #define WM8962_ADCL_RETUNE_C19_1 0x4624 |
794 | #define WM8962_ADCL_RETUNE_C19_0 0x4625 |
795 | #define WM8962_ADCL_RETUNE_C20_1 0x4626 |
796 | #define WM8962_ADCL_RETUNE_C20_0 0x4627 |
797 | #define WM8962_ADCL_RETUNE_C21_1 0x4628 |
798 | #define WM8962_ADCL_RETUNE_C21_0 0x4629 |
799 | #define WM8962_ADCL_RETUNE_C22_1 0x462A |
800 | #define WM8962_ADCL_RETUNE_C22_0 0x462B |
801 | #define WM8962_ADCL_RETUNE_C23_1 0x462C |
802 | #define WM8962_ADCL_RETUNE_C23_0 0x462D |
803 | #define WM8962_ADCL_RETUNE_C24_1 0x462E |
804 | #define WM8962_ADCL_RETUNE_C24_0 0x462F |
805 | #define WM8962_ADCL_RETUNE_C25_1 0x4630 |
806 | #define WM8962_ADCL_RETUNE_C25_0 0x4631 |
807 | #define WM8962_ADCL_RETUNE_C26_1 0x4632 |
808 | #define WM8962_ADCL_RETUNE_C26_0 0x4633 |
809 | #define WM8962_ADCL_RETUNE_C27_1 0x4634 |
810 | #define WM8962_ADCL_RETUNE_C27_0 0x4635 |
811 | #define WM8962_ADCL_RETUNE_C28_1 0x4636 |
812 | #define WM8962_ADCL_RETUNE_C28_0 0x4637 |
813 | #define WM8962_ADCL_RETUNE_C29_1 0x4638 |
814 | #define WM8962_ADCL_RETUNE_C29_0 0x4639 |
815 | #define WM8962_ADCL_RETUNE_C30_1 0x463A |
816 | #define WM8962_ADCL_RETUNE_C30_0 0x463B |
817 | #define WM8962_ADCL_RETUNE_C31_1 0x463C |
818 | #define WM8962_ADCL_RETUNE_C31_0 0x463D |
819 | #define WM8962_ADCL_RETUNE_C32_1 0x463E |
820 | #define WM8962_ADCL_RETUNE_C32_0 0x463F |
821 | #define WM8962_RETUNEADC_PG2_1 0x4800 |
822 | #define WM8962_RETUNEADC_PG2_0 0x4801 |
823 | #define WM8962_RETUNEADC_PG_1 0x4802 |
824 | #define WM8962_RETUNEADC_PG_0 0x4803 |
825 | #define WM8962_ADCR_RETUNE_C1_1 0x4A00 |
826 | #define WM8962_ADCR_RETUNE_C1_0 0x4A01 |
827 | #define WM8962_ADCR_RETUNE_C2_1 0x4A02 |
828 | #define WM8962_ADCR_RETUNE_C2_0 0x4A03 |
829 | #define WM8962_ADCR_RETUNE_C3_1 0x4A04 |
830 | #define WM8962_ADCR_RETUNE_C3_0 0x4A05 |
831 | #define WM8962_ADCR_RETUNE_C4_1 0x4A06 |
832 | #define WM8962_ADCR_RETUNE_C4_0 0x4A07 |
833 | #define WM8962_ADCR_RETUNE_C5_1 0x4A08 |
834 | #define WM8962_ADCR_RETUNE_C5_0 0x4A09 |
835 | #define WM8962_ADCR_RETUNE_C6_1 0x4A0A |
836 | #define WM8962_ADCR_RETUNE_C6_0 0x4A0B |
837 | #define WM8962_ADCR_RETUNE_C7_1 0x4A0C |
838 | #define WM8962_ADCR_RETUNE_C7_0 0x4A0D |
839 | #define WM8962_ADCR_RETUNE_C8_1 0x4A0E |
840 | #define WM8962_ADCR_RETUNE_C8_0 0x4A0F |
841 | #define WM8962_ADCR_RETUNE_C9_1 0x4A10 |
842 | #define WM8962_ADCR_RETUNE_C9_0 0x4A11 |
843 | #define WM8962_ADCR_RETUNE_C10_1 0x4A12 |
844 | #define WM8962_ADCR_RETUNE_C10_0 0x4A13 |
845 | #define WM8962_ADCR_RETUNE_C11_1 0x4A14 |
846 | #define WM8962_ADCR_RETUNE_C11_0 0x4A15 |
847 | #define WM8962_ADCR_RETUNE_C12_1 0x4A16 |
848 | #define WM8962_ADCR_RETUNE_C12_0 0x4A17 |
849 | #define WM8962_ADCR_RETUNE_C13_1 0x4A18 |
850 | #define WM8962_ADCR_RETUNE_C13_0 0x4A19 |
851 | #define WM8962_ADCR_RETUNE_C14_1 0x4A1A |
852 | #define WM8962_ADCR_RETUNE_C14_0 0x4A1B |
853 | #define WM8962_ADCR_RETUNE_C15_1 0x4A1C |
854 | #define WM8962_ADCR_RETUNE_C15_0 0x4A1D |
855 | #define WM8962_ADCR_RETUNE_C16_1 0x4A1E |
856 | #define WM8962_ADCR_RETUNE_C16_0 0x4A1F |
857 | #define WM8962_ADCR_RETUNE_C17_1 0x4A20 |
858 | #define WM8962_ADCR_RETUNE_C17_0 0x4A21 |
859 | #define WM8962_ADCR_RETUNE_C18_1 0x4A22 |
860 | #define WM8962_ADCR_RETUNE_C18_0 0x4A23 |
861 | #define WM8962_ADCR_RETUNE_C19_1 0x4A24 |
862 | #define WM8962_ADCR_RETUNE_C19_0 0x4A25 |
863 | #define WM8962_ADCR_RETUNE_C20_1 0x4A26 |
864 | #define WM8962_ADCR_RETUNE_C20_0 0x4A27 |
865 | #define WM8962_ADCR_RETUNE_C21_1 0x4A28 |
866 | #define WM8962_ADCR_RETUNE_C21_0 0x4A29 |
867 | #define WM8962_ADCR_RETUNE_C22_1 0x4A2A |
868 | #define WM8962_ADCR_RETUNE_C22_0 0x4A2B |
869 | #define WM8962_ADCR_RETUNE_C23_1 0x4A2C |
870 | #define WM8962_ADCR_RETUNE_C23_0 0x4A2D |
871 | #define WM8962_ADCR_RETUNE_C24_1 0x4A2E |
872 | #define WM8962_ADCR_RETUNE_C24_0 0x4A2F |
873 | #define WM8962_ADCR_RETUNE_C25_1 0x4A30 |
874 | #define WM8962_ADCR_RETUNE_C25_0 0x4A31 |
875 | #define WM8962_ADCR_RETUNE_C26_1 0x4A32 |
876 | #define WM8962_ADCR_RETUNE_C26_0 0x4A33 |
877 | #define WM8962_ADCR_RETUNE_C27_1 0x4A34 |
878 | #define WM8962_ADCR_RETUNE_C27_0 0x4A35 |
879 | #define WM8962_ADCR_RETUNE_C28_1 0x4A36 |
880 | #define WM8962_ADCR_RETUNE_C28_0 0x4A37 |
881 | #define WM8962_ADCR_RETUNE_C29_1 0x4A38 |
882 | #define WM8962_ADCR_RETUNE_C29_0 0x4A39 |
883 | #define WM8962_ADCR_RETUNE_C30_1 0x4A3A |
884 | #define WM8962_ADCR_RETUNE_C30_0 0x4A3B |
885 | #define WM8962_ADCR_RETUNE_C31_1 0x4A3C |
886 | #define WM8962_ADCR_RETUNE_C31_0 0x4A3D |
887 | #define WM8962_ADCR_RETUNE_C32_1 0x4A3E |
888 | #define WM8962_ADCR_RETUNE_C32_0 0x4A3F |
889 | #define WM8962_DACL_RETUNE_C1_1 0x4C00 |
890 | #define WM8962_DACL_RETUNE_C1_0 0x4C01 |
891 | #define WM8962_DACL_RETUNE_C2_1 0x4C02 |
892 | #define WM8962_DACL_RETUNE_C2_0 0x4C03 |
893 | #define WM8962_DACL_RETUNE_C3_1 0x4C04 |
894 | #define WM8962_DACL_RETUNE_C3_0 0x4C05 |
895 | #define WM8962_DACL_RETUNE_C4_1 0x4C06 |
896 | #define WM8962_DACL_RETUNE_C4_0 0x4C07 |
897 | #define WM8962_DACL_RETUNE_C5_1 0x4C08 |
898 | #define WM8962_DACL_RETUNE_C5_0 0x4C09 |
899 | #define WM8962_DACL_RETUNE_C6_1 0x4C0A |
900 | #define WM8962_DACL_RETUNE_C6_0 0x4C0B |
901 | #define WM8962_DACL_RETUNE_C7_1 0x4C0C |
902 | #define WM8962_DACL_RETUNE_C7_0 0x4C0D |
903 | #define WM8962_DACL_RETUNE_C8_1 0x4C0E |
904 | #define WM8962_DACL_RETUNE_C8_0 0x4C0F |
905 | #define WM8962_DACL_RETUNE_C9_1 0x4C10 |
906 | #define WM8962_DACL_RETUNE_C9_0 0x4C11 |
907 | #define WM8962_DACL_RETUNE_C10_1 0x4C12 |
908 | #define WM8962_DACL_RETUNE_C10_0 0x4C13 |
909 | #define WM8962_DACL_RETUNE_C11_1 0x4C14 |
910 | #define WM8962_DACL_RETUNE_C11_0 0x4C15 |
911 | #define WM8962_DACL_RETUNE_C12_1 0x4C16 |
912 | #define WM8962_DACL_RETUNE_C12_0 0x4C17 |
913 | #define WM8962_DACL_RETUNE_C13_1 0x4C18 |
914 | #define WM8962_DACL_RETUNE_C13_0 0x4C19 |
915 | #define WM8962_DACL_RETUNE_C14_1 0x4C1A |
916 | #define WM8962_DACL_RETUNE_C14_0 0x4C1B |
917 | #define WM8962_DACL_RETUNE_C15_1 0x4C1C |
918 | #define WM8962_DACL_RETUNE_C15_0 0x4C1D |
919 | #define WM8962_DACL_RETUNE_C16_1 0x4C1E |
920 | #define WM8962_DACL_RETUNE_C16_0 0x4C1F |
921 | #define WM8962_DACL_RETUNE_C17_1 0x4C20 |
922 | #define WM8962_DACL_RETUNE_C17_0 0x4C21 |
923 | #define WM8962_DACL_RETUNE_C18_1 0x4C22 |
924 | #define WM8962_DACL_RETUNE_C18_0 0x4C23 |
925 | #define WM8962_DACL_RETUNE_C19_1 0x4C24 |
926 | #define WM8962_DACL_RETUNE_C19_0 0x4C25 |
927 | #define WM8962_DACL_RETUNE_C20_1 0x4C26 |
928 | #define WM8962_DACL_RETUNE_C20_0 0x4C27 |
929 | #define WM8962_DACL_RETUNE_C21_1 0x4C28 |
930 | #define WM8962_DACL_RETUNE_C21_0 0x4C29 |
931 | #define WM8962_DACL_RETUNE_C22_1 0x4C2A |
932 | #define WM8962_DACL_RETUNE_C22_0 0x4C2B |
933 | #define WM8962_DACL_RETUNE_C23_1 0x4C2C |
934 | #define WM8962_DACL_RETUNE_C23_0 0x4C2D |
935 | #define WM8962_DACL_RETUNE_C24_1 0x4C2E |
936 | #define WM8962_DACL_RETUNE_C24_0 0x4C2F |
937 | #define WM8962_DACL_RETUNE_C25_1 0x4C30 |
938 | #define WM8962_DACL_RETUNE_C25_0 0x4C31 |
939 | #define WM8962_DACL_RETUNE_C26_1 0x4C32 |
940 | #define WM8962_DACL_RETUNE_C26_0 0x4C33 |
941 | #define WM8962_DACL_RETUNE_C27_1 0x4C34 |
942 | #define WM8962_DACL_RETUNE_C27_0 0x4C35 |
943 | #define WM8962_DACL_RETUNE_C28_1 0x4C36 |
944 | #define WM8962_DACL_RETUNE_C28_0 0x4C37 |
945 | #define WM8962_DACL_RETUNE_C29_1 0x4C38 |
946 | #define WM8962_DACL_RETUNE_C29_0 0x4C39 |
947 | #define WM8962_DACL_RETUNE_C30_1 0x4C3A |
948 | #define WM8962_DACL_RETUNE_C30_0 0x4C3B |
949 | #define WM8962_DACL_RETUNE_C31_1 0x4C3C |
950 | #define WM8962_DACL_RETUNE_C31_0 0x4C3D |
951 | #define WM8962_DACL_RETUNE_C32_1 0x4C3E |
952 | #define WM8962_DACL_RETUNE_C32_0 0x4C3F |
953 | #define WM8962_RETUNEDAC_PG2_1 0x4E00 |
954 | #define WM8962_RETUNEDAC_PG2_0 0x4E01 |
955 | #define WM8962_RETUNEDAC_PG_1 0x4E02 |
956 | #define WM8962_RETUNEDAC_PG_0 0x4E03 |
957 | #define WM8962_DACR_RETUNE_C1_1 0x5000 |
958 | #define WM8962_DACR_RETUNE_C1_0 0x5001 |
959 | #define WM8962_DACR_RETUNE_C2_1 0x5002 |
960 | #define WM8962_DACR_RETUNE_C2_0 0x5003 |
961 | #define WM8962_DACR_RETUNE_C3_1 0x5004 |
962 | #define WM8962_DACR_RETUNE_C3_0 0x5005 |
963 | #define WM8962_DACR_RETUNE_C4_1 0x5006 |
964 | #define WM8962_DACR_RETUNE_C4_0 0x5007 |
965 | #define WM8962_DACR_RETUNE_C5_1 0x5008 |
966 | #define WM8962_DACR_RETUNE_C5_0 0x5009 |
967 | #define WM8962_DACR_RETUNE_C6_1 0x500A |
968 | #define WM8962_DACR_RETUNE_C6_0 0x500B |
969 | #define WM8962_DACR_RETUNE_C7_1 0x500C |
970 | #define WM8962_DACR_RETUNE_C7_0 0x500D |
971 | #define WM8962_DACR_RETUNE_C8_1 0x500E |
972 | #define WM8962_DACR_RETUNE_C8_0 0x500F |
973 | #define WM8962_DACR_RETUNE_C9_1 0x5010 |
974 | #define WM8962_DACR_RETUNE_C9_0 0x5011 |
975 | #define WM8962_DACR_RETUNE_C10_1 0x5012 |
976 | #define WM8962_DACR_RETUNE_C10_0 0x5013 |
977 | #define WM8962_DACR_RETUNE_C11_1 0x5014 |
978 | #define WM8962_DACR_RETUNE_C11_0 0x5015 |
979 | #define WM8962_DACR_RETUNE_C12_1 0x5016 |
980 | #define WM8962_DACR_RETUNE_C12_0 0x5017 |
981 | #define WM8962_DACR_RETUNE_C13_1 0x5018 |
982 | #define WM8962_DACR_RETUNE_C13_0 0x5019 |
983 | #define WM8962_DACR_RETUNE_C14_1 0x501A |
984 | #define WM8962_DACR_RETUNE_C14_0 0x501B |
985 | #define WM8962_DACR_RETUNE_C15_1 0x501C |
986 | #define WM8962_DACR_RETUNE_C15_0 0x501D |
987 | #define WM8962_DACR_RETUNE_C16_1 0x501E |
988 | #define WM8962_DACR_RETUNE_C16_0 0x501F |
989 | #define WM8962_DACR_RETUNE_C17_1 0x5020 |
990 | #define WM8962_DACR_RETUNE_C17_0 0x5021 |
991 | #define WM8962_DACR_RETUNE_C18_1 0x5022 |
992 | #define WM8962_DACR_RETUNE_C18_0 0x5023 |
993 | #define WM8962_DACR_RETUNE_C19_1 0x5024 |
994 | #define WM8962_DACR_RETUNE_C19_0 0x5025 |
995 | #define WM8962_DACR_RETUNE_C20_1 0x5026 |
996 | #define WM8962_DACR_RETUNE_C20_0 0x5027 |
997 | #define WM8962_DACR_RETUNE_C21_1 0x5028 |
998 | #define WM8962_DACR_RETUNE_C21_0 0x5029 |
999 | #define WM8962_DACR_RETUNE_C22_1 0x502A |
1000 | #define WM8962_DACR_RETUNE_C22_0 0x502B |
1001 | #define WM8962_DACR_RETUNE_C23_1 0x502C |
1002 | #define WM8962_DACR_RETUNE_C23_0 0x502D |
1003 | #define WM8962_DACR_RETUNE_C24_1 0x502E |
1004 | #define WM8962_DACR_RETUNE_C24_0 0x502F |
1005 | #define WM8962_DACR_RETUNE_C25_1 0x5030 |
1006 | #define WM8962_DACR_RETUNE_C25_0 0x5031 |
1007 | #define WM8962_DACR_RETUNE_C26_1 0x5032 |
1008 | #define WM8962_DACR_RETUNE_C26_0 0x5033 |
1009 | #define WM8962_DACR_RETUNE_C27_1 0x5034 |
1010 | #define WM8962_DACR_RETUNE_C27_0 0x5035 |
1011 | #define WM8962_DACR_RETUNE_C28_1 0x5036 |
1012 | #define WM8962_DACR_RETUNE_C28_0 0x5037 |
1013 | #define WM8962_DACR_RETUNE_C29_1 0x5038 |
1014 | #define WM8962_DACR_RETUNE_C29_0 0x5039 |
1015 | #define WM8962_DACR_RETUNE_C30_1 0x503A |
1016 | #define WM8962_DACR_RETUNE_C30_0 0x503B |
1017 | #define WM8962_DACR_RETUNE_C31_1 0x503C |
1018 | #define WM8962_DACR_RETUNE_C31_0 0x503D |
1019 | #define WM8962_DACR_RETUNE_C32_1 0x503E |
1020 | #define WM8962_DACR_RETUNE_C32_0 0x503F |
1021 | #define WM8962_VSS_XHD2_1 0x5200 |
1022 | #define WM8962_VSS_XHD2_0 0x5201 |
1023 | #define WM8962_VSS_XHD3_1 0x5202 |
1024 | #define WM8962_VSS_XHD3_0 0x5203 |
1025 | #define WM8962_VSS_XHN1_1 0x5204 |
1026 | #define WM8962_VSS_XHN1_0 0x5205 |
1027 | #define WM8962_VSS_XHN2_1 0x5206 |
1028 | #define WM8962_VSS_XHN2_0 0x5207 |
1029 | #define WM8962_VSS_XHN3_1 0x5208 |
1030 | #define WM8962_VSS_XHN3_0 0x5209 |
1031 | #define WM8962_VSS_XLA_1 0x520A |
1032 | #define WM8962_VSS_XLA_0 0x520B |
1033 | #define WM8962_VSS_XLB_1 0x520C |
1034 | #define WM8962_VSS_XLB_0 0x520D |
1035 | #define WM8962_VSS_XLG_1 0x520E |
1036 | #define WM8962_VSS_XLG_0 0x520F |
1037 | #define WM8962_VSS_PG2_1 0x5210 |
1038 | #define WM8962_VSS_PG2_0 0x5211 |
1039 | #define WM8962_VSS_PG_1 0x5212 |
1040 | #define WM8962_VSS_PG_0 0x5213 |
1041 | #define WM8962_VSS_XTD1_1 0x5214 |
1042 | #define WM8962_VSS_XTD1_0 0x5215 |
1043 | #define WM8962_VSS_XTD2_1 0x5216 |
1044 | #define WM8962_VSS_XTD2_0 0x5217 |
1045 | #define WM8962_VSS_XTD3_1 0x5218 |
1046 | #define WM8962_VSS_XTD3_0 0x5219 |
1047 | #define WM8962_VSS_XTD4_1 0x521A |
1048 | #define WM8962_VSS_XTD4_0 0x521B |
1049 | #define WM8962_VSS_XTD5_1 0x521C |
1050 | #define WM8962_VSS_XTD5_0 0x521D |
1051 | #define WM8962_VSS_XTD6_1 0x521E |
1052 | #define WM8962_VSS_XTD6_0 0x521F |
1053 | #define WM8962_VSS_XTD7_1 0x5220 |
1054 | #define WM8962_VSS_XTD7_0 0x5221 |
1055 | #define WM8962_VSS_XTD8_1 0x5222 |
1056 | #define WM8962_VSS_XTD8_0 0x5223 |
1057 | #define WM8962_VSS_XTD9_1 0x5224 |
1058 | #define WM8962_VSS_XTD9_0 0x5225 |
1059 | #define WM8962_VSS_XTD10_1 0x5226 |
1060 | #define WM8962_VSS_XTD10_0 0x5227 |
1061 | #define WM8962_VSS_XTD11_1 0x5228 |
1062 | #define WM8962_VSS_XTD11_0 0x5229 |
1063 | #define WM8962_VSS_XTD12_1 0x522A |
1064 | #define WM8962_VSS_XTD12_0 0x522B |
1065 | #define WM8962_VSS_XTD13_1 0x522C |
1066 | #define WM8962_VSS_XTD13_0 0x522D |
1067 | #define WM8962_VSS_XTD14_1 0x522E |
1068 | #define WM8962_VSS_XTD14_0 0x522F |
1069 | #define WM8962_VSS_XTD15_1 0x5230 |
1070 | #define WM8962_VSS_XTD15_0 0x5231 |
1071 | #define WM8962_VSS_XTD16_1 0x5232 |
1072 | #define WM8962_VSS_XTD16_0 0x5233 |
1073 | #define WM8962_VSS_XTD17_1 0x5234 |
1074 | #define WM8962_VSS_XTD17_0 0x5235 |
1075 | #define WM8962_VSS_XTD18_1 0x5236 |
1076 | #define WM8962_VSS_XTD18_0 0x5237 |
1077 | #define WM8962_VSS_XTD19_1 0x5238 |
1078 | #define WM8962_VSS_XTD19_0 0x5239 |
1079 | #define WM8962_VSS_XTD20_1 0x523A |
1080 | #define WM8962_VSS_XTD20_0 0x523B |
1081 | #define WM8962_VSS_XTD21_1 0x523C |
1082 | #define WM8962_VSS_XTD21_0 0x523D |
1083 | #define WM8962_VSS_XTD22_1 0x523E |
1084 | #define WM8962_VSS_XTD22_0 0x523F |
1085 | #define WM8962_VSS_XTD23_1 0x5240 |
1086 | #define WM8962_VSS_XTD23_0 0x5241 |
1087 | #define WM8962_VSS_XTD24_1 0x5242 |
1088 | #define WM8962_VSS_XTD24_0 0x5243 |
1089 | #define WM8962_VSS_XTD25_1 0x5244 |
1090 | #define WM8962_VSS_XTD25_0 0x5245 |
1091 | #define WM8962_VSS_XTD26_1 0x5246 |
1092 | #define WM8962_VSS_XTD26_0 0x5247 |
1093 | #define WM8962_VSS_XTD27_1 0x5248 |
1094 | #define WM8962_VSS_XTD27_0 0x5249 |
1095 | #define WM8962_VSS_XTD28_1 0x524A |
1096 | #define WM8962_VSS_XTD28_0 0x524B |
1097 | #define WM8962_VSS_XTD29_1 0x524C |
1098 | #define WM8962_VSS_XTD29_0 0x524D |
1099 | #define WM8962_VSS_XTD30_1 0x524E |
1100 | #define WM8962_VSS_XTD30_0 0x524F |
1101 | #define WM8962_VSS_XTD31_1 0x5250 |
1102 | #define WM8962_VSS_XTD31_0 0x5251 |
1103 | #define WM8962_VSS_XTD32_1 0x5252 |
1104 | #define WM8962_VSS_XTD32_0 0x5253 |
1105 | #define WM8962_VSS_XTS1_1 0x5254 |
1106 | #define WM8962_VSS_XTS1_0 0x5255 |
1107 | #define WM8962_VSS_XTS2_1 0x5256 |
1108 | #define WM8962_VSS_XTS2_0 0x5257 |
1109 | #define WM8962_VSS_XTS3_1 0x5258 |
1110 | #define WM8962_VSS_XTS3_0 0x5259 |
1111 | #define WM8962_VSS_XTS4_1 0x525A |
1112 | #define WM8962_VSS_XTS4_0 0x525B |
1113 | #define WM8962_VSS_XTS5_1 0x525C |
1114 | #define WM8962_VSS_XTS5_0 0x525D |
1115 | #define WM8962_VSS_XTS6_1 0x525E |
1116 | #define WM8962_VSS_XTS6_0 0x525F |
1117 | #define WM8962_VSS_XTS7_1 0x5260 |
1118 | #define WM8962_VSS_XTS7_0 0x5261 |
1119 | #define WM8962_VSS_XTS8_1 0x5262 |
1120 | #define WM8962_VSS_XTS8_0 0x5263 |
1121 | #define WM8962_VSS_XTS9_1 0x5264 |
1122 | #define WM8962_VSS_XTS9_0 0x5265 |
1123 | #define WM8962_VSS_XTS10_1 0x5266 |
1124 | #define WM8962_VSS_XTS10_0 0x5267 |
1125 | #define WM8962_VSS_XTS11_1 0x5268 |
1126 | #define WM8962_VSS_XTS11_0 0x5269 |
1127 | #define WM8962_VSS_XTS12_1 0x526A |
1128 | #define WM8962_VSS_XTS12_0 0x526B |
1129 | #define WM8962_VSS_XTS13_1 0x526C |
1130 | #define WM8962_VSS_XTS13_0 0x526D |
1131 | #define WM8962_VSS_XTS14_1 0x526E |
1132 | #define WM8962_VSS_XTS14_0 0x526F |
1133 | #define WM8962_VSS_XTS15_1 0x5270 |
1134 | #define WM8962_VSS_XTS15_0 0x5271 |
1135 | #define WM8962_VSS_XTS16_1 0x5272 |
1136 | #define WM8962_VSS_XTS16_0 0x5273 |
1137 | #define WM8962_VSS_XTS17_1 0x5274 |
1138 | #define WM8962_VSS_XTS17_0 0x5275 |
1139 | #define WM8962_VSS_XTS18_1 0x5276 |
1140 | #define WM8962_VSS_XTS18_0 0x5277 |
1141 | #define WM8962_VSS_XTS19_1 0x5278 |
1142 | #define WM8962_VSS_XTS19_0 0x5279 |
1143 | #define WM8962_VSS_XTS20_1 0x527A |
1144 | #define WM8962_VSS_XTS20_0 0x527B |
1145 | #define WM8962_VSS_XTS21_1 0x527C |
1146 | #define WM8962_VSS_XTS21_0 0x527D |
1147 | #define WM8962_VSS_XTS22_1 0x527E |
1148 | #define WM8962_VSS_XTS22_0 0x527F |
1149 | #define WM8962_VSS_XTS23_1 0x5280 |
1150 | #define WM8962_VSS_XTS23_0 0x5281 |
1151 | #define WM8962_VSS_XTS24_1 0x5282 |
1152 | #define WM8962_VSS_XTS24_0 0x5283 |
1153 | #define WM8962_VSS_XTS25_1 0x5284 |
1154 | #define WM8962_VSS_XTS25_0 0x5285 |
1155 | #define WM8962_VSS_XTS26_1 0x5286 |
1156 | #define WM8962_VSS_XTS26_0 0x5287 |
1157 | #define WM8962_VSS_XTS27_1 0x5288 |
1158 | #define WM8962_VSS_XTS27_0 0x5289 |
1159 | #define WM8962_VSS_XTS28_1 0x528A |
1160 | #define WM8962_VSS_XTS28_0 0x528B |
1161 | #define WM8962_VSS_XTS29_1 0x528C |
1162 | #define WM8962_VSS_XTS29_0 0x528D |
1163 | #define WM8962_VSS_XTS30_1 0x528E |
1164 | #define WM8962_VSS_XTS30_0 0x528F |
1165 | #define WM8962_VSS_XTS31_1 0x5290 |
1166 | #define WM8962_VSS_XTS31_0 0x5291 |
1167 | #define WM8962_VSS_XTS32_1 0x5292 |
1168 | #define WM8962_VSS_XTS32_0 0x5293 |
1169 | |
1170 | #define WM8962_REGISTER_COUNT 1138 |
1171 | #define WM8962_MAX_REGISTER 0x5293 |
1172 | |
1173 | /* |
1174 | * Field Definitions. |
1175 | */ |
1176 | |
1177 | /* |
1178 | * R0 (0x00) - Left Input volume |
1179 | */ |
1180 | #define WM8962_IN_VU 0x0100 /* IN_VU */ |
1181 | #define WM8962_IN_VU_MASK 0x0100 /* IN_VU */ |
1182 | #define WM8962_IN_VU_SHIFT 8 /* IN_VU */ |
1183 | #define WM8962_IN_VU_WIDTH 1 /* IN_VU */ |
1184 | #define WM8962_INPGAL_MUTE 0x0080 /* INPGAL_MUTE */ |
1185 | #define WM8962_INPGAL_MUTE_MASK 0x0080 /* INPGAL_MUTE */ |
1186 | #define WM8962_INPGAL_MUTE_SHIFT 7 /* INPGAL_MUTE */ |
1187 | #define WM8962_INPGAL_MUTE_WIDTH 1 /* INPGAL_MUTE */ |
1188 | #define WM8962_INL_ZC 0x0040 /* INL_ZC */ |
1189 | #define WM8962_INL_ZC_MASK 0x0040 /* INL_ZC */ |
1190 | #define WM8962_INL_ZC_SHIFT 6 /* INL_ZC */ |
1191 | #define WM8962_INL_ZC_WIDTH 1 /* INL_ZC */ |
1192 | #define WM8962_INL_VOL_MASK 0x003F /* INL_VOL - [5:0] */ |
1193 | #define WM8962_INL_VOL_SHIFT 0 /* INL_VOL - [5:0] */ |
1194 | #define WM8962_INL_VOL_WIDTH 6 /* INL_VOL - [5:0] */ |
1195 | |
1196 | /* |
1197 | * R1 (0x01) - Right Input volume |
1198 | */ |
1199 | #define WM8962_CUST_ID_MASK 0xF000 /* CUST_ID - [15:12] */ |
1200 | #define WM8962_CUST_ID_SHIFT 12 /* CUST_ID - [15:12] */ |
1201 | #define WM8962_CUST_ID_WIDTH 4 /* CUST_ID - [15:12] */ |
1202 | #define WM8962_CHIP_REV_MASK 0x0E00 /* CHIP_REV - [11:9] */ |
1203 | #define WM8962_CHIP_REV_SHIFT 9 /* CHIP_REV - [11:9] */ |
1204 | #define WM8962_CHIP_REV_WIDTH 3 /* CHIP_REV - [11:9] */ |
1205 | #define WM8962_IN_VU 0x0100 /* IN_VU */ |
1206 | #define WM8962_IN_VU_MASK 0x0100 /* IN_VU */ |
1207 | #define WM8962_IN_VU_SHIFT 8 /* IN_VU */ |
1208 | #define WM8962_IN_VU_WIDTH 1 /* IN_VU */ |
1209 | #define WM8962_INPGAR_MUTE 0x0080 /* INPGAR_MUTE */ |
1210 | #define WM8962_INPGAR_MUTE_MASK 0x0080 /* INPGAR_MUTE */ |
1211 | #define WM8962_INPGAR_MUTE_SHIFT 7 /* INPGAR_MUTE */ |
1212 | #define WM8962_INPGAR_MUTE_WIDTH 1 /* INPGAR_MUTE */ |
1213 | #define WM8962_INR_ZC 0x0040 /* INR_ZC */ |
1214 | #define WM8962_INR_ZC_MASK 0x0040 /* INR_ZC */ |
1215 | #define WM8962_INR_ZC_SHIFT 6 /* INR_ZC */ |
1216 | #define WM8962_INR_ZC_WIDTH 1 /* INR_ZC */ |
1217 | #define WM8962_INR_VOL_MASK 0x003F /* INR_VOL - [5:0] */ |
1218 | #define WM8962_INR_VOL_SHIFT 0 /* INR_VOL - [5:0] */ |
1219 | #define WM8962_INR_VOL_WIDTH 6 /* INR_VOL - [5:0] */ |
1220 | |
1221 | /* |
1222 | * R2 (0x02) - HPOUTL volume |
1223 | */ |
1224 | #define WM8962_HPOUT_VU 0x0100 /* HPOUT_VU */ |
1225 | #define WM8962_HPOUT_VU_MASK 0x0100 /* HPOUT_VU */ |
1226 | #define WM8962_HPOUT_VU_SHIFT 8 /* HPOUT_VU */ |
1227 | #define WM8962_HPOUT_VU_WIDTH 1 /* HPOUT_VU */ |
1228 | #define WM8962_HPOUTL_ZC 0x0080 /* HPOUTL_ZC */ |
1229 | #define WM8962_HPOUTL_ZC_MASK 0x0080 /* HPOUTL_ZC */ |
1230 | #define WM8962_HPOUTL_ZC_SHIFT 7 /* HPOUTL_ZC */ |
1231 | #define WM8962_HPOUTL_ZC_WIDTH 1 /* HPOUTL_ZC */ |
1232 | #define WM8962_HPOUTL_VOL_MASK 0x007F /* HPOUTL_VOL - [6:0] */ |
1233 | #define WM8962_HPOUTL_VOL_SHIFT 0 /* HPOUTL_VOL - [6:0] */ |
1234 | #define WM8962_HPOUTL_VOL_WIDTH 7 /* HPOUTL_VOL - [6:0] */ |
1235 | |
1236 | /* |
1237 | * R3 (0x03) - HPOUTR volume |
1238 | */ |
1239 | #define WM8962_HPOUT_VU 0x0100 /* HPOUT_VU */ |
1240 | #define WM8962_HPOUT_VU_MASK 0x0100 /* HPOUT_VU */ |
1241 | #define WM8962_HPOUT_VU_SHIFT 8 /* HPOUT_VU */ |
1242 | #define WM8962_HPOUT_VU_WIDTH 1 /* HPOUT_VU */ |
1243 | #define WM8962_HPOUTR_ZC 0x0080 /* HPOUTR_ZC */ |
1244 | #define WM8962_HPOUTR_ZC_MASK 0x0080 /* HPOUTR_ZC */ |
1245 | #define WM8962_HPOUTR_ZC_SHIFT 7 /* HPOUTR_ZC */ |
1246 | #define WM8962_HPOUTR_ZC_WIDTH 1 /* HPOUTR_ZC */ |
1247 | #define WM8962_HPOUTR_VOL_MASK 0x007F /* HPOUTR_VOL - [6:0] */ |
1248 | #define WM8962_HPOUTR_VOL_SHIFT 0 /* HPOUTR_VOL - [6:0] */ |
1249 | #define WM8962_HPOUTR_VOL_WIDTH 7 /* HPOUTR_VOL - [6:0] */ |
1250 | |
1251 | /* |
1252 | * R4 (0x04) - Clocking1 |
1253 | */ |
1254 | #define WM8962_DSPCLK_DIV_MASK 0x0600 /* DSPCLK_DIV - [10:9] */ |
1255 | #define WM8962_DSPCLK_DIV_SHIFT 9 /* DSPCLK_DIV - [10:9] */ |
1256 | #define WM8962_DSPCLK_DIV_WIDTH 2 /* DSPCLK_DIV - [10:9] */ |
1257 | #define WM8962_ADCSYS_CLK_DIV_MASK 0x01C0 /* ADCSYS_CLK_DIV - [8:6] */ |
1258 | #define WM8962_ADCSYS_CLK_DIV_SHIFT 6 /* ADCSYS_CLK_DIV - [8:6] */ |
1259 | #define WM8962_ADCSYS_CLK_DIV_WIDTH 3 /* ADCSYS_CLK_DIV - [8:6] */ |
1260 | #define WM8962_DACSYS_CLK_DIV_MASK 0x0038 /* DACSYS_CLK_DIV - [5:3] */ |
1261 | #define WM8962_DACSYS_CLK_DIV_SHIFT 3 /* DACSYS_CLK_DIV - [5:3] */ |
1262 | #define WM8962_DACSYS_CLK_DIV_WIDTH 3 /* DACSYS_CLK_DIV - [5:3] */ |
1263 | #define WM8962_MCLKDIV_MASK 0x0006 /* MCLKDIV - [2:1] */ |
1264 | #define WM8962_MCLKDIV_SHIFT 1 /* MCLKDIV - [2:1] */ |
1265 | #define WM8962_MCLKDIV_WIDTH 2 /* MCLKDIV - [2:1] */ |
1266 | |
1267 | /* |
1268 | * R5 (0x05) - ADC & DAC Control 1 |
1269 | */ |
1270 | #define WM8962_ADCR_DAT_INV 0x0040 /* ADCR_DAT_INV */ |
1271 | #define WM8962_ADCR_DAT_INV_MASK 0x0040 /* ADCR_DAT_INV */ |
1272 | #define WM8962_ADCR_DAT_INV_SHIFT 6 /* ADCR_DAT_INV */ |
1273 | #define WM8962_ADCR_DAT_INV_WIDTH 1 /* ADCR_DAT_INV */ |
1274 | #define WM8962_ADCL_DAT_INV 0x0020 /* ADCL_DAT_INV */ |
1275 | #define WM8962_ADCL_DAT_INV_MASK 0x0020 /* ADCL_DAT_INV */ |
1276 | #define WM8962_ADCL_DAT_INV_SHIFT 5 /* ADCL_DAT_INV */ |
1277 | #define WM8962_ADCL_DAT_INV_WIDTH 1 /* ADCL_DAT_INV */ |
1278 | #define WM8962_DAC_MUTE_RAMP 0x0010 /* DAC_MUTE_RAMP */ |
1279 | #define WM8962_DAC_MUTE_RAMP_MASK 0x0010 /* DAC_MUTE_RAMP */ |
1280 | #define WM8962_DAC_MUTE_RAMP_SHIFT 4 /* DAC_MUTE_RAMP */ |
1281 | #define WM8962_DAC_MUTE_RAMP_WIDTH 1 /* DAC_MUTE_RAMP */ |
1282 | #define WM8962_DAC_MUTE 0x0008 /* DAC_MUTE */ |
1283 | #define WM8962_DAC_MUTE_MASK 0x0008 /* DAC_MUTE */ |
1284 | #define WM8962_DAC_MUTE_SHIFT 3 /* DAC_MUTE */ |
1285 | #define WM8962_DAC_MUTE_WIDTH 1 /* DAC_MUTE */ |
1286 | #define WM8962_DAC_DEEMP_MASK 0x0006 /* DAC_DEEMP - [2:1] */ |
1287 | #define WM8962_DAC_DEEMP_SHIFT 1 /* DAC_DEEMP - [2:1] */ |
1288 | #define WM8962_DAC_DEEMP_WIDTH 2 /* DAC_DEEMP - [2:1] */ |
1289 | #define WM8962_ADC_HPF_DIS 0x0001 /* ADC_HPF_DIS */ |
1290 | #define WM8962_ADC_HPF_DIS_MASK 0x0001 /* ADC_HPF_DIS */ |
1291 | #define WM8962_ADC_HPF_DIS_SHIFT 0 /* ADC_HPF_DIS */ |
1292 | #define WM8962_ADC_HPF_DIS_WIDTH 1 /* ADC_HPF_DIS */ |
1293 | |
1294 | /* |
1295 | * R6 (0x06) - ADC & DAC Control 2 |
1296 | */ |
1297 | #define WM8962_ADC_HPF_SR_MASK 0x3000 /* ADC_HPF_SR - [13:12] */ |
1298 | #define WM8962_ADC_HPF_SR_SHIFT 12 /* ADC_HPF_SR - [13:12] */ |
1299 | #define WM8962_ADC_HPF_SR_WIDTH 2 /* ADC_HPF_SR - [13:12] */ |
1300 | #define WM8962_ADC_HPF_MODE 0x0400 /* ADC_HPF_MODE */ |
1301 | #define WM8962_ADC_HPF_MODE_MASK 0x0400 /* ADC_HPF_MODE */ |
1302 | #define WM8962_ADC_HPF_MODE_SHIFT 10 /* ADC_HPF_MODE */ |
1303 | #define WM8962_ADC_HPF_MODE_WIDTH 1 /* ADC_HPF_MODE */ |
1304 | #define WM8962_ADC_HPF_CUT_MASK 0x0380 /* ADC_HPF_CUT - [9:7] */ |
1305 | #define WM8962_ADC_HPF_CUT_SHIFT 7 /* ADC_HPF_CUT - [9:7] */ |
1306 | #define WM8962_ADC_HPF_CUT_WIDTH 3 /* ADC_HPF_CUT - [9:7] */ |
1307 | #define WM8962_DACR_DAT_INV 0x0040 /* DACR_DAT_INV */ |
1308 | #define WM8962_DACR_DAT_INV_MASK 0x0040 /* DACR_DAT_INV */ |
1309 | #define WM8962_DACR_DAT_INV_SHIFT 6 /* DACR_DAT_INV */ |
1310 | #define WM8962_DACR_DAT_INV_WIDTH 1 /* DACR_DAT_INV */ |
1311 | #define WM8962_DACL_DAT_INV 0x0020 /* DACL_DAT_INV */ |
1312 | #define WM8962_DACL_DAT_INV_MASK 0x0020 /* DACL_DAT_INV */ |
1313 | #define WM8962_DACL_DAT_INV_SHIFT 5 /* DACL_DAT_INV */ |
1314 | #define WM8962_DACL_DAT_INV_WIDTH 1 /* DACL_DAT_INV */ |
1315 | #define WM8962_DAC_UNMUTE_RAMP 0x0008 /* DAC_UNMUTE_RAMP */ |
1316 | #define WM8962_DAC_UNMUTE_RAMP_MASK 0x0008 /* DAC_UNMUTE_RAMP */ |
1317 | #define WM8962_DAC_UNMUTE_RAMP_SHIFT 3 /* DAC_UNMUTE_RAMP */ |
1318 | #define WM8962_DAC_UNMUTE_RAMP_WIDTH 1 /* DAC_UNMUTE_RAMP */ |
1319 | #define WM8962_DAC_MUTERATE 0x0004 /* DAC_MUTERATE */ |
1320 | #define WM8962_DAC_MUTERATE_MASK 0x0004 /* DAC_MUTERATE */ |
1321 | #define WM8962_DAC_MUTERATE_SHIFT 2 /* DAC_MUTERATE */ |
1322 | #define WM8962_DAC_MUTERATE_WIDTH 1 /* DAC_MUTERATE */ |
1323 | #define WM8962_DAC_HP 0x0001 /* DAC_HP */ |
1324 | #define WM8962_DAC_HP_MASK 0x0001 /* DAC_HP */ |
1325 | #define WM8962_DAC_HP_SHIFT 0 /* DAC_HP */ |
1326 | #define WM8962_DAC_HP_WIDTH 1 /* DAC_HP */ |
1327 | |
1328 | /* |
1329 | * R7 (0x07) - Audio Interface 0 |
1330 | */ |
1331 | #define WM8962_AIFDAC_TDM_MODE 0x1000 /* AIFDAC_TDM_MODE */ |
1332 | #define WM8962_AIFDAC_TDM_MODE_MASK 0x1000 /* AIFDAC_TDM_MODE */ |
1333 | #define WM8962_AIFDAC_TDM_MODE_SHIFT 12 /* AIFDAC_TDM_MODE */ |
1334 | #define WM8962_AIFDAC_TDM_MODE_WIDTH 1 /* AIFDAC_TDM_MODE */ |
1335 | #define WM8962_AIFDAC_TDM_SLOT 0x0800 /* AIFDAC_TDM_SLOT */ |
1336 | #define WM8962_AIFDAC_TDM_SLOT_MASK 0x0800 /* AIFDAC_TDM_SLOT */ |
1337 | #define WM8962_AIFDAC_TDM_SLOT_SHIFT 11 /* AIFDAC_TDM_SLOT */ |
1338 | #define WM8962_AIFDAC_TDM_SLOT_WIDTH 1 /* AIFDAC_TDM_SLOT */ |
1339 | #define WM8962_AIFADC_TDM_MODE 0x0400 /* AIFADC_TDM_MODE */ |
1340 | #define WM8962_AIFADC_TDM_MODE_MASK 0x0400 /* AIFADC_TDM_MODE */ |
1341 | #define WM8962_AIFADC_TDM_MODE_SHIFT 10 /* AIFADC_TDM_MODE */ |
1342 | #define WM8962_AIFADC_TDM_MODE_WIDTH 1 /* AIFADC_TDM_MODE */ |
1343 | #define WM8962_AIFADC_TDM_SLOT 0x0200 /* AIFADC_TDM_SLOT */ |
1344 | #define WM8962_AIFADC_TDM_SLOT_MASK 0x0200 /* AIFADC_TDM_SLOT */ |
1345 | #define WM8962_AIFADC_TDM_SLOT_SHIFT 9 /* AIFADC_TDM_SLOT */ |
1346 | #define WM8962_AIFADC_TDM_SLOT_WIDTH 1 /* AIFADC_TDM_SLOT */ |
1347 | #define WM8962_ADC_LRSWAP 0x0100 /* ADC_LRSWAP */ |
1348 | #define WM8962_ADC_LRSWAP_MASK 0x0100 /* ADC_LRSWAP */ |
1349 | #define WM8962_ADC_LRSWAP_SHIFT 8 /* ADC_LRSWAP */ |
1350 | #define WM8962_ADC_LRSWAP_WIDTH 1 /* ADC_LRSWAP */ |
1351 | #define WM8962_BCLK_INV 0x0080 /* BCLK_INV */ |
1352 | #define WM8962_BCLK_INV_MASK 0x0080 /* BCLK_INV */ |
1353 | #define WM8962_BCLK_INV_SHIFT 7 /* BCLK_INV */ |
1354 | #define WM8962_BCLK_INV_WIDTH 1 /* BCLK_INV */ |
1355 | #define WM8962_MSTR 0x0040 /* MSTR */ |
1356 | #define WM8962_MSTR_MASK 0x0040 /* MSTR */ |
1357 | #define WM8962_MSTR_SHIFT 6 /* MSTR */ |
1358 | #define WM8962_MSTR_WIDTH 1 /* MSTR */ |
1359 | #define WM8962_DAC_LRSWAP 0x0020 /* DAC_LRSWAP */ |
1360 | #define WM8962_DAC_LRSWAP_MASK 0x0020 /* DAC_LRSWAP */ |
1361 | #define WM8962_DAC_LRSWAP_SHIFT 5 /* DAC_LRSWAP */ |
1362 | #define WM8962_DAC_LRSWAP_WIDTH 1 /* DAC_LRSWAP */ |
1363 | #define WM8962_LRCLK_INV 0x0010 /* LRCLK_INV */ |
1364 | #define WM8962_LRCLK_INV_MASK 0x0010 /* LRCLK_INV */ |
1365 | #define WM8962_LRCLK_INV_SHIFT 4 /* LRCLK_INV */ |
1366 | #define WM8962_LRCLK_INV_WIDTH 1 /* LRCLK_INV */ |
1367 | #define WM8962_WL_MASK 0x000C /* WL - [3:2] */ |
1368 | #define WM8962_WL_SHIFT 2 /* WL - [3:2] */ |
1369 | #define WM8962_WL_WIDTH 2 /* WL - [3:2] */ |
1370 | #define WM8962_FMT_MASK 0x0003 /* FMT - [1:0] */ |
1371 | #define WM8962_FMT_SHIFT 0 /* FMT - [1:0] */ |
1372 | #define WM8962_FMT_WIDTH 2 /* FMT - [1:0] */ |
1373 | |
1374 | /* |
1375 | * R8 (0x08) - Clocking2 |
1376 | */ |
1377 | #define WM8962_CLKREG_OVD 0x0800 /* CLKREG_OVD */ |
1378 | #define WM8962_CLKREG_OVD_MASK 0x0800 /* CLKREG_OVD */ |
1379 | #define WM8962_CLKREG_OVD_SHIFT 11 /* CLKREG_OVD */ |
1380 | #define WM8962_CLKREG_OVD_WIDTH 1 /* CLKREG_OVD */ |
1381 | #define WM8962_SYSCLK_SRC_MASK 0x0600 /* SYSCLK_SRC - [10:9] */ |
1382 | #define WM8962_SYSCLK_SRC_SHIFT 9 /* SYSCLK_SRC - [10:9] */ |
1383 | #define WM8962_SYSCLK_SRC_WIDTH 2 /* SYSCLK_SRC - [10:9] */ |
1384 | #define WM8962_CLASSD_CLK_DIV_MASK 0x01C0 /* CLASSD_CLK_DIV - [8:6] */ |
1385 | #define WM8962_CLASSD_CLK_DIV_SHIFT 6 /* CLASSD_CLK_DIV - [8:6] */ |
1386 | #define WM8962_CLASSD_CLK_DIV_WIDTH 3 /* CLASSD_CLK_DIV - [8:6] */ |
1387 | #define WM8962_SYSCLK_ENA 0x0020 /* SYSCLK_ENA */ |
1388 | #define WM8962_SYSCLK_ENA_MASK 0x0020 /* SYSCLK_ENA */ |
1389 | #define WM8962_SYSCLK_ENA_SHIFT 5 /* SYSCLK_ENA */ |
1390 | #define WM8962_SYSCLK_ENA_WIDTH 1 /* SYSCLK_ENA */ |
1391 | #define WM8962_BCLK_DIV_MASK 0x000F /* BCLK_DIV - [3:0] */ |
1392 | #define WM8962_BCLK_DIV_SHIFT 0 /* BCLK_DIV - [3:0] */ |
1393 | #define WM8962_BCLK_DIV_WIDTH 4 /* BCLK_DIV - [3:0] */ |
1394 | |
1395 | /* |
1396 | * R9 (0x09) - Audio Interface 1 |
1397 | */ |
1398 | #define WM8962_AUTOMUTE_STS 0x0800 /* AUTOMUTE_STS */ |
1399 | #define WM8962_AUTOMUTE_STS_MASK 0x0800 /* AUTOMUTE_STS */ |
1400 | #define WM8962_AUTOMUTE_STS_SHIFT 11 /* AUTOMUTE_STS */ |
1401 | #define WM8962_AUTOMUTE_STS_WIDTH 1 /* AUTOMUTE_STS */ |
1402 | #define WM8962_DAC_AUTOMUTE_SAMPLES_MASK 0x0300 /* DAC_AUTOMUTE_SAMPLES - [9:8] */ |
1403 | #define WM8962_DAC_AUTOMUTE_SAMPLES_SHIFT 8 /* DAC_AUTOMUTE_SAMPLES - [9:8] */ |
1404 | #define WM8962_DAC_AUTOMUTE_SAMPLES_WIDTH 2 /* DAC_AUTOMUTE_SAMPLES - [9:8] */ |
1405 | #define WM8962_DAC_AUTOMUTE 0x0080 /* DAC_AUTOMUTE */ |
1406 | #define WM8962_DAC_AUTOMUTE_MASK 0x0080 /* DAC_AUTOMUTE */ |
1407 | #define WM8962_DAC_AUTOMUTE_SHIFT 7 /* DAC_AUTOMUTE */ |
1408 | #define WM8962_DAC_AUTOMUTE_WIDTH 1 /* DAC_AUTOMUTE */ |
1409 | #define WM8962_DAC_COMP 0x0010 /* DAC_COMP */ |
1410 | #define WM8962_DAC_COMP_MASK 0x0010 /* DAC_COMP */ |
1411 | #define WM8962_DAC_COMP_SHIFT 4 /* DAC_COMP */ |
1412 | #define WM8962_DAC_COMP_WIDTH 1 /* DAC_COMP */ |
1413 | #define WM8962_DAC_COMPMODE 0x0008 /* DAC_COMPMODE */ |
1414 | #define WM8962_DAC_COMPMODE_MASK 0x0008 /* DAC_COMPMODE */ |
1415 | #define WM8962_DAC_COMPMODE_SHIFT 3 /* DAC_COMPMODE */ |
1416 | #define WM8962_DAC_COMPMODE_WIDTH 1 /* DAC_COMPMODE */ |
1417 | #define WM8962_ADC_COMP 0x0004 /* ADC_COMP */ |
1418 | #define WM8962_ADC_COMP_MASK 0x0004 /* ADC_COMP */ |
1419 | #define WM8962_ADC_COMP_SHIFT 2 /* ADC_COMP */ |
1420 | #define WM8962_ADC_COMP_WIDTH 1 /* ADC_COMP */ |
1421 | #define WM8962_ADC_COMPMODE 0x0002 /* ADC_COMPMODE */ |
1422 | #define WM8962_ADC_COMPMODE_MASK 0x0002 /* ADC_COMPMODE */ |
1423 | #define WM8962_ADC_COMPMODE_SHIFT 1 /* ADC_COMPMODE */ |
1424 | #define WM8962_ADC_COMPMODE_WIDTH 1 /* ADC_COMPMODE */ |
1425 | #define WM8962_LOOPBACK 0x0001 /* LOOPBACK */ |
1426 | #define WM8962_LOOPBACK_MASK 0x0001 /* LOOPBACK */ |
1427 | #define WM8962_LOOPBACK_SHIFT 0 /* LOOPBACK */ |
1428 | #define WM8962_LOOPBACK_WIDTH 1 /* LOOPBACK */ |
1429 | |
1430 | /* |
1431 | * R10 (0x0A) - Left DAC volume |
1432 | */ |
1433 | #define WM8962_DAC_VU 0x0100 /* DAC_VU */ |
1434 | #define WM8962_DAC_VU_MASK 0x0100 /* DAC_VU */ |
1435 | #define WM8962_DAC_VU_SHIFT 8 /* DAC_VU */ |
1436 | #define WM8962_DAC_VU_WIDTH 1 /* DAC_VU */ |
1437 | #define WM8962_DACL_VOL_MASK 0x00FF /* DACL_VOL - [7:0] */ |
1438 | #define WM8962_DACL_VOL_SHIFT 0 /* DACL_VOL - [7:0] */ |
1439 | #define WM8962_DACL_VOL_WIDTH 8 /* DACL_VOL - [7:0] */ |
1440 | |
1441 | /* |
1442 | * R11 (0x0B) - Right DAC volume |
1443 | */ |
1444 | #define WM8962_DAC_VU 0x0100 /* DAC_VU */ |
1445 | #define WM8962_DAC_VU_MASK 0x0100 /* DAC_VU */ |
1446 | #define WM8962_DAC_VU_SHIFT 8 /* DAC_VU */ |
1447 | #define WM8962_DAC_VU_WIDTH 1 /* DAC_VU */ |
1448 | #define WM8962_DACR_VOL_MASK 0x00FF /* DACR_VOL - [7:0] */ |
1449 | #define WM8962_DACR_VOL_SHIFT 0 /* DACR_VOL - [7:0] */ |
1450 | #define WM8962_DACR_VOL_WIDTH 8 /* DACR_VOL - [7:0] */ |
1451 | |
1452 | /* |
1453 | * R14 (0x0E) - Audio Interface 2 |
1454 | */ |
1455 | #define WM8962_AIF_RATE_MASK 0x07FF /* AIF_RATE - [10:0] */ |
1456 | #define WM8962_AIF_RATE_SHIFT 0 /* AIF_RATE - [10:0] */ |
1457 | #define WM8962_AIF_RATE_WIDTH 11 /* AIF_RATE - [10:0] */ |
1458 | |
1459 | /* |
1460 | * R15 (0x0F) - Software Reset |
1461 | */ |
1462 | #define WM8962_SW_RESET_MASK 0xFFFF /* SW_RESET - [15:0] */ |
1463 | #define WM8962_SW_RESET_SHIFT 0 /* SW_RESET - [15:0] */ |
1464 | #define WM8962_SW_RESET_WIDTH 16 /* SW_RESET - [15:0] */ |
1465 | |
1466 | /* |
1467 | * R17 (0x11) - ALC1 |
1468 | */ |
1469 | #define WM8962_ALC_INACTIVE_ENA 0x0400 /* ALC_INACTIVE_ENA */ |
1470 | #define WM8962_ALC_INACTIVE_ENA_MASK 0x0400 /* ALC_INACTIVE_ENA */ |
1471 | #define WM8962_ALC_INACTIVE_ENA_SHIFT 10 /* ALC_INACTIVE_ENA */ |
1472 | #define WM8962_ALC_INACTIVE_ENA_WIDTH 1 /* ALC_INACTIVE_ENA */ |
1473 | #define WM8962_ALC_LVL_MODE 0x0200 /* ALC_LVL_MODE */ |
1474 | #define WM8962_ALC_LVL_MODE_MASK 0x0200 /* ALC_LVL_MODE */ |
1475 | #define WM8962_ALC_LVL_MODE_SHIFT 9 /* ALC_LVL_MODE */ |
1476 | #define WM8962_ALC_LVL_MODE_WIDTH 1 /* ALC_LVL_MODE */ |
1477 | #define WM8962_ALCL_ENA 0x0100 /* ALCL_ENA */ |
1478 | #define WM8962_ALCL_ENA_MASK 0x0100 /* ALCL_ENA */ |
1479 | #define WM8962_ALCL_ENA_SHIFT 8 /* ALCL_ENA */ |
1480 | #define WM8962_ALCL_ENA_WIDTH 1 /* ALCL_ENA */ |
1481 | #define WM8962_ALCR_ENA 0x0080 /* ALCR_ENA */ |
1482 | #define WM8962_ALCR_ENA_MASK 0x0080 /* ALCR_ENA */ |
1483 | #define WM8962_ALCR_ENA_SHIFT 7 /* ALCR_ENA */ |
1484 | #define WM8962_ALCR_ENA_WIDTH 1 /* ALCR_ENA */ |
1485 | #define WM8962_ALC_MAXGAIN_MASK 0x0070 /* ALC_MAXGAIN - [6:4] */ |
1486 | #define WM8962_ALC_MAXGAIN_SHIFT 4 /* ALC_MAXGAIN - [6:4] */ |
1487 | #define WM8962_ALC_MAXGAIN_WIDTH 3 /* ALC_MAXGAIN - [6:4] */ |
1488 | #define WM8962_ALC_LVL_MASK 0x000F /* ALC_LVL - [3:0] */ |
1489 | #define WM8962_ALC_LVL_SHIFT 0 /* ALC_LVL - [3:0] */ |
1490 | #define WM8962_ALC_LVL_WIDTH 4 /* ALC_LVL - [3:0] */ |
1491 | |
1492 | /* |
1493 | * R18 (0x12) - ALC2 |
1494 | */ |
1495 | #define WM8962_ALC_LOCK_STS 0x8000 /* ALC_LOCK_STS */ |
1496 | #define WM8962_ALC_LOCK_STS_MASK 0x8000 /* ALC_LOCK_STS */ |
1497 | #define WM8962_ALC_LOCK_STS_SHIFT 15 /* ALC_LOCK_STS */ |
1498 | #define WM8962_ALC_LOCK_STS_WIDTH 1 /* ALC_LOCK_STS */ |
1499 | #define WM8962_ALC_THRESH_STS 0x4000 /* ALC_THRESH_STS */ |
1500 | #define WM8962_ALC_THRESH_STS_MASK 0x4000 /* ALC_THRESH_STS */ |
1501 | #define WM8962_ALC_THRESH_STS_SHIFT 14 /* ALC_THRESH_STS */ |
1502 | #define WM8962_ALC_THRESH_STS_WIDTH 1 /* ALC_THRESH_STS */ |
1503 | #define WM8962_ALC_SAT_STS 0x2000 /* ALC_SAT_STS */ |
1504 | #define WM8962_ALC_SAT_STS_MASK 0x2000 /* ALC_SAT_STS */ |
1505 | #define WM8962_ALC_SAT_STS_SHIFT 13 /* ALC_SAT_STS */ |
1506 | #define WM8962_ALC_SAT_STS_WIDTH 1 /* ALC_SAT_STS */ |
1507 | #define WM8962_ALC_PKOVR_STS 0x1000 /* ALC_PKOVR_STS */ |
1508 | #define WM8962_ALC_PKOVR_STS_MASK 0x1000 /* ALC_PKOVR_STS */ |
1509 | #define WM8962_ALC_PKOVR_STS_SHIFT 12 /* ALC_PKOVR_STS */ |
1510 | #define WM8962_ALC_PKOVR_STS_WIDTH 1 /* ALC_PKOVR_STS */ |
1511 | #define WM8962_ALC_NGATE_STS 0x0800 /* ALC_NGATE_STS */ |
1512 | #define WM8962_ALC_NGATE_STS_MASK 0x0800 /* ALC_NGATE_STS */ |
1513 | #define WM8962_ALC_NGATE_STS_SHIFT 11 /* ALC_NGATE_STS */ |
1514 | #define WM8962_ALC_NGATE_STS_WIDTH 1 /* ALC_NGATE_STS */ |
1515 | #define WM8962_ALC_ZC 0x0080 /* ALC_ZC */ |
1516 | #define WM8962_ALC_ZC_MASK 0x0080 /* ALC_ZC */ |
1517 | #define WM8962_ALC_ZC_SHIFT 7 /* ALC_ZC */ |
1518 | #define WM8962_ALC_ZC_WIDTH 1 /* ALC_ZC */ |
1519 | #define WM8962_ALC_MINGAIN_MASK 0x0070 /* ALC_MINGAIN - [6:4] */ |
1520 | #define WM8962_ALC_MINGAIN_SHIFT 4 /* ALC_MINGAIN - [6:4] */ |
1521 | #define WM8962_ALC_MINGAIN_WIDTH 3 /* ALC_MINGAIN - [6:4] */ |
1522 | #define WM8962_ALC_HLD_MASK 0x000F /* ALC_HLD - [3:0] */ |
1523 | #define WM8962_ALC_HLD_SHIFT 0 /* ALC_HLD - [3:0] */ |
1524 | #define WM8962_ALC_HLD_WIDTH 4 /* ALC_HLD - [3:0] */ |
1525 | |
1526 | /* |
1527 | * R19 (0x13) - ALC3 |
1528 | */ |
1529 | #define WM8962_ALC_NGATE_GAIN_MASK 0x1C00 /* ALC_NGATE_GAIN - [12:10] */ |
1530 | #define WM8962_ALC_NGATE_GAIN_SHIFT 10 /* ALC_NGATE_GAIN - [12:10] */ |
1531 | #define WM8962_ALC_NGATE_GAIN_WIDTH 3 /* ALC_NGATE_GAIN - [12:10] */ |
1532 | #define WM8962_ALC_MODE 0x0100 /* ALC_MODE */ |
1533 | #define WM8962_ALC_MODE_MASK 0x0100 /* ALC_MODE */ |
1534 | #define WM8962_ALC_MODE_SHIFT 8 /* ALC_MODE */ |
1535 | #define WM8962_ALC_MODE_WIDTH 1 /* ALC_MODE */ |
1536 | #define WM8962_ALC_DCY_MASK 0x00F0 /* ALC_DCY - [7:4] */ |
1537 | #define WM8962_ALC_DCY_SHIFT 4 /* ALC_DCY - [7:4] */ |
1538 | #define WM8962_ALC_DCY_WIDTH 4 /* ALC_DCY - [7:4] */ |
1539 | #define WM8962_ALC_ATK_MASK 0x000F /* ALC_ATK - [3:0] */ |
1540 | #define WM8962_ALC_ATK_SHIFT 0 /* ALC_ATK - [3:0] */ |
1541 | #define WM8962_ALC_ATK_WIDTH 4 /* ALC_ATK - [3:0] */ |
1542 | |
1543 | /* |
1544 | * R20 (0x14) - Noise Gate |
1545 | */ |
1546 | #define WM8962_ALC_NGATE_DCY_MASK 0xF000 /* ALC_NGATE_DCY - [15:12] */ |
1547 | #define WM8962_ALC_NGATE_DCY_SHIFT 12 /* ALC_NGATE_DCY - [15:12] */ |
1548 | #define WM8962_ALC_NGATE_DCY_WIDTH 4 /* ALC_NGATE_DCY - [15:12] */ |
1549 | #define WM8962_ALC_NGATE_ATK_MASK 0x0F00 /* ALC_NGATE_ATK - [11:8] */ |
1550 | #define WM8962_ALC_NGATE_ATK_SHIFT 8 /* ALC_NGATE_ATK - [11:8] */ |
1551 | #define WM8962_ALC_NGATE_ATK_WIDTH 4 /* ALC_NGATE_ATK - [11:8] */ |
1552 | #define WM8962_ALC_NGATE_THR_MASK 0x00F8 /* ALC_NGATE_THR - [7:3] */ |
1553 | #define WM8962_ALC_NGATE_THR_SHIFT 3 /* ALC_NGATE_THR - [7:3] */ |
1554 | #define WM8962_ALC_NGATE_THR_WIDTH 5 /* ALC_NGATE_THR - [7:3] */ |
1555 | #define WM8962_ALC_NGATE_MODE_MASK 0x0006 /* ALC_NGATE_MODE - [2:1] */ |
1556 | #define WM8962_ALC_NGATE_MODE_SHIFT 1 /* ALC_NGATE_MODE - [2:1] */ |
1557 | #define WM8962_ALC_NGATE_MODE_WIDTH 2 /* ALC_NGATE_MODE - [2:1] */ |
1558 | #define WM8962_ALC_NGATE_ENA 0x0001 /* ALC_NGATE_ENA */ |
1559 | #define WM8962_ALC_NGATE_ENA_MASK 0x0001 /* ALC_NGATE_ENA */ |
1560 | #define WM8962_ALC_NGATE_ENA_SHIFT 0 /* ALC_NGATE_ENA */ |
1561 | #define WM8962_ALC_NGATE_ENA_WIDTH 1 /* ALC_NGATE_ENA */ |
1562 | |
1563 | /* |
1564 | * R21 (0x15) - Left ADC volume |
1565 | */ |
1566 | #define WM8962_ADC_VU 0x0100 /* ADC_VU */ |
1567 | #define WM8962_ADC_VU_MASK 0x0100 /* ADC_VU */ |
1568 | #define WM8962_ADC_VU_SHIFT 8 /* ADC_VU */ |
1569 | #define WM8962_ADC_VU_WIDTH 1 /* ADC_VU */ |
1570 | #define WM8962_ADCL_VOL_MASK 0x00FF /* ADCL_VOL - [7:0] */ |
1571 | #define WM8962_ADCL_VOL_SHIFT 0 /* ADCL_VOL - [7:0] */ |
1572 | #define WM8962_ADCL_VOL_WIDTH 8 /* ADCL_VOL - [7:0] */ |
1573 | |
1574 | /* |
1575 | * R22 (0x16) - Right ADC volume |
1576 | */ |
1577 | #define WM8962_ADC_VU 0x0100 /* ADC_VU */ |
1578 | #define WM8962_ADC_VU_MASK 0x0100 /* ADC_VU */ |
1579 | #define WM8962_ADC_VU_SHIFT 8 /* ADC_VU */ |
1580 | #define WM8962_ADC_VU_WIDTH 1 /* ADC_VU */ |
1581 | #define WM8962_ADCR_VOL_MASK 0x00FF /* ADCR_VOL - [7:0] */ |
1582 | #define WM8962_ADCR_VOL_SHIFT 0 /* ADCR_VOL - [7:0] */ |
1583 | #define WM8962_ADCR_VOL_WIDTH 8 /* ADCR_VOL - [7:0] */ |
1584 | |
1585 | /* |
1586 | * R23 (0x17) - Additional control(1) |
1587 | */ |
1588 | #define WM8962_THERR_ACT 0x0100 /* THERR_ACT */ |
1589 | #define WM8962_THERR_ACT_MASK 0x0100 /* THERR_ACT */ |
1590 | #define WM8962_THERR_ACT_SHIFT 8 /* THERR_ACT */ |
1591 | #define WM8962_THERR_ACT_WIDTH 1 /* THERR_ACT */ |
1592 | #define WM8962_ADC_BIAS 0x0040 /* ADC_BIAS */ |
1593 | #define WM8962_ADC_BIAS_MASK 0x0040 /* ADC_BIAS */ |
1594 | #define WM8962_ADC_BIAS_SHIFT 6 /* ADC_BIAS */ |
1595 | #define WM8962_ADC_BIAS_WIDTH 1 /* ADC_BIAS */ |
1596 | #define WM8962_ADC_HP 0x0020 /* ADC_HP */ |
1597 | #define WM8962_ADC_HP_MASK 0x0020 /* ADC_HP */ |
1598 | #define WM8962_ADC_HP_SHIFT 5 /* ADC_HP */ |
1599 | #define WM8962_ADC_HP_WIDTH 1 /* ADC_HP */ |
1600 | #define WM8962_TOCLK_ENA 0x0001 /* TOCLK_ENA */ |
1601 | #define WM8962_TOCLK_ENA_MASK 0x0001 /* TOCLK_ENA */ |
1602 | #define WM8962_TOCLK_ENA_SHIFT 0 /* TOCLK_ENA */ |
1603 | #define WM8962_TOCLK_ENA_WIDTH 1 /* TOCLK_ENA */ |
1604 | |
1605 | /* |
1606 | * R24 (0x18) - Additional control(2) |
1607 | */ |
1608 | #define WM8962_AIF_TRI 0x0008 /* AIF_TRI */ |
1609 | #define WM8962_AIF_TRI_MASK 0x0008 /* AIF_TRI */ |
1610 | #define WM8962_AIF_TRI_SHIFT 3 /* AIF_TRI */ |
1611 | #define WM8962_AIF_TRI_WIDTH 1 /* AIF_TRI */ |
1612 | |
1613 | /* |
1614 | * R25 (0x19) - Pwr Mgmt (1) |
1615 | */ |
1616 | #define WM8962_DMIC_ENA 0x0400 /* DMIC_ENA */ |
1617 | #define WM8962_DMIC_ENA_MASK 0x0400 /* DMIC_ENA */ |
1618 | #define WM8962_DMIC_ENA_SHIFT 10 /* DMIC_ENA */ |
1619 | #define WM8962_DMIC_ENA_WIDTH 1 /* DMIC_ENA */ |
1620 | #define WM8962_OPCLK_ENA 0x0200 /* OPCLK_ENA */ |
1621 | #define WM8962_OPCLK_ENA_MASK 0x0200 /* OPCLK_ENA */ |
1622 | #define WM8962_OPCLK_ENA_SHIFT 9 /* OPCLK_ENA */ |
1623 | #define WM8962_OPCLK_ENA_WIDTH 1 /* OPCLK_ENA */ |
1624 | #define WM8962_VMID_SEL_MASK 0x0180 /* VMID_SEL - [8:7] */ |
1625 | #define WM8962_VMID_SEL_SHIFT 7 /* VMID_SEL - [8:7] */ |
1626 | #define WM8962_VMID_SEL_WIDTH 2 /* VMID_SEL - [8:7] */ |
1627 | #define WM8962_BIAS_ENA 0x0040 /* BIAS_ENA */ |
1628 | #define WM8962_BIAS_ENA_MASK 0x0040 /* BIAS_ENA */ |
1629 | #define WM8962_BIAS_ENA_SHIFT 6 /* BIAS_ENA */ |
1630 | #define WM8962_BIAS_ENA_WIDTH 1 /* BIAS_ENA */ |
1631 | #define WM8962_INL_ENA 0x0020 /* INL_ENA */ |
1632 | #define WM8962_INL_ENA_MASK 0x0020 /* INL_ENA */ |
1633 | #define WM8962_INL_ENA_SHIFT 5 /* INL_ENA */ |
1634 | #define WM8962_INL_ENA_WIDTH 1 /* INL_ENA */ |
1635 | #define WM8962_INR_ENA 0x0010 /* INR_ENA */ |
1636 | #define WM8962_INR_ENA_MASK 0x0010 /* INR_ENA */ |
1637 | #define WM8962_INR_ENA_SHIFT 4 /* INR_ENA */ |
1638 | #define WM8962_INR_ENA_WIDTH 1 /* INR_ENA */ |
1639 | #define WM8962_ADCL_ENA 0x0008 /* ADCL_ENA */ |
1640 | #define WM8962_ADCL_ENA_MASK 0x0008 /* ADCL_ENA */ |
1641 | #define WM8962_ADCL_ENA_SHIFT 3 /* ADCL_ENA */ |
1642 | #define WM8962_ADCL_ENA_WIDTH 1 /* ADCL_ENA */ |
1643 | #define WM8962_ADCR_ENA 0x0004 /* ADCR_ENA */ |
1644 | #define WM8962_ADCR_ENA_MASK 0x0004 /* ADCR_ENA */ |
1645 | #define WM8962_ADCR_ENA_SHIFT 2 /* ADCR_ENA */ |
1646 | #define WM8962_ADCR_ENA_WIDTH 1 /* ADCR_ENA */ |
1647 | #define WM8962_MICBIAS_ENA 0x0002 /* MICBIAS_ENA */ |
1648 | #define WM8962_MICBIAS_ENA_MASK 0x0002 /* MICBIAS_ENA */ |
1649 | #define WM8962_MICBIAS_ENA_SHIFT 1 /* MICBIAS_ENA */ |
1650 | #define WM8962_MICBIAS_ENA_WIDTH 1 /* MICBIAS_ENA */ |
1651 | |
1652 | /* |
1653 | * R26 (0x1A) - Pwr Mgmt (2) |
1654 | */ |
1655 | #define WM8962_DACL_ENA 0x0100 /* DACL_ENA */ |
1656 | #define WM8962_DACL_ENA_MASK 0x0100 /* DACL_ENA */ |
1657 | #define WM8962_DACL_ENA_SHIFT 8 /* DACL_ENA */ |
1658 | #define WM8962_DACL_ENA_WIDTH 1 /* DACL_ENA */ |
1659 | #define WM8962_DACR_ENA 0x0080 /* DACR_ENA */ |
1660 | #define WM8962_DACR_ENA_MASK 0x0080 /* DACR_ENA */ |
1661 | #define WM8962_DACR_ENA_SHIFT 7 /* DACR_ENA */ |
1662 | #define WM8962_DACR_ENA_WIDTH 1 /* DACR_ENA */ |
1663 | #define WM8962_HPOUTL_PGA_ENA 0x0040 /* HPOUTL_PGA_ENA */ |
1664 | #define WM8962_HPOUTL_PGA_ENA_MASK 0x0040 /* HPOUTL_PGA_ENA */ |
1665 | #define WM8962_HPOUTL_PGA_ENA_SHIFT 6 /* HPOUTL_PGA_ENA */ |
1666 | #define WM8962_HPOUTL_PGA_ENA_WIDTH 1 /* HPOUTL_PGA_ENA */ |
1667 | #define WM8962_HPOUTR_PGA_ENA 0x0020 /* HPOUTR_PGA_ENA */ |
1668 | #define WM8962_HPOUTR_PGA_ENA_MASK 0x0020 /* HPOUTR_PGA_ENA */ |
1669 | #define WM8962_HPOUTR_PGA_ENA_SHIFT 5 /* HPOUTR_PGA_ENA */ |
1670 | #define WM8962_HPOUTR_PGA_ENA_WIDTH 1 /* HPOUTR_PGA_ENA */ |
1671 | #define WM8962_SPKOUTL_PGA_ENA 0x0010 /* SPKOUTL_PGA_ENA */ |
1672 | #define WM8962_SPKOUTL_PGA_ENA_MASK 0x0010 /* SPKOUTL_PGA_ENA */ |
1673 | #define WM8962_SPKOUTL_PGA_ENA_SHIFT 4 /* SPKOUTL_PGA_ENA */ |
1674 | #define WM8962_SPKOUTL_PGA_ENA_WIDTH 1 /* SPKOUTL_PGA_ENA */ |
1675 | #define WM8962_SPKOUTR_PGA_ENA 0x0008 /* SPKOUTR_PGA_ENA */ |
1676 | #define WM8962_SPKOUTR_PGA_ENA_MASK 0x0008 /* SPKOUTR_PGA_ENA */ |
1677 | #define WM8962_SPKOUTR_PGA_ENA_SHIFT 3 /* SPKOUTR_PGA_ENA */ |
1678 | #define WM8962_SPKOUTR_PGA_ENA_WIDTH 1 /* SPKOUTR_PGA_ENA */ |
1679 | #define WM8962_HPOUTL_PGA_MUTE 0x0002 /* HPOUTL_PGA_MUTE */ |
1680 | #define WM8962_HPOUTL_PGA_MUTE_MASK 0x0002 /* HPOUTL_PGA_MUTE */ |
1681 | #define WM8962_HPOUTL_PGA_MUTE_SHIFT 1 /* HPOUTL_PGA_MUTE */ |
1682 | #define WM8962_HPOUTL_PGA_MUTE_WIDTH 1 /* HPOUTL_PGA_MUTE */ |
1683 | #define WM8962_HPOUTR_PGA_MUTE 0x0001 /* HPOUTR_PGA_MUTE */ |
1684 | #define WM8962_HPOUTR_PGA_MUTE_MASK 0x0001 /* HPOUTR_PGA_MUTE */ |
1685 | #define WM8962_HPOUTR_PGA_MUTE_SHIFT 0 /* HPOUTR_PGA_MUTE */ |
1686 | #define WM8962_HPOUTR_PGA_MUTE_WIDTH 1 /* HPOUTR_PGA_MUTE */ |
1687 | |
1688 | /* |
1689 | * R27 (0x1B) - Additional Control (3) |
1690 | */ |
1691 | #define WM8962_SAMPLE_RATE_INT_MODE 0x0010 /* SAMPLE_RATE_INT_MODE */ |
1692 | #define WM8962_SAMPLE_RATE_INT_MODE_MASK 0x0010 /* SAMPLE_RATE_INT_MODE */ |
1693 | #define WM8962_SAMPLE_RATE_INT_MODE_SHIFT 4 /* SAMPLE_RATE_INT_MODE */ |
1694 | #define WM8962_SAMPLE_RATE_INT_MODE_WIDTH 1 /* SAMPLE_RATE_INT_MODE */ |
1695 | #define WM8962_SAMPLE_RATE_MASK 0x0007 /* SAMPLE_RATE - [2:0] */ |
1696 | #define WM8962_SAMPLE_RATE_SHIFT 0 /* SAMPLE_RATE - [2:0] */ |
1697 | #define WM8962_SAMPLE_RATE_WIDTH 3 /* SAMPLE_RATE - [2:0] */ |
1698 | |
1699 | /* |
1700 | * R28 (0x1C) - Anti-pop |
1701 | */ |
1702 | #define WM8962_STARTUP_BIAS_ENA 0x0010 /* STARTUP_BIAS_ENA */ |
1703 | #define WM8962_STARTUP_BIAS_ENA_MASK 0x0010 /* STARTUP_BIAS_ENA */ |
1704 | #define WM8962_STARTUP_BIAS_ENA_SHIFT 4 /* STARTUP_BIAS_ENA */ |
1705 | #define WM8962_STARTUP_BIAS_ENA_WIDTH 1 /* STARTUP_BIAS_ENA */ |
1706 | #define WM8962_VMID_BUF_ENA 0x0008 /* VMID_BUF_ENA */ |
1707 | #define WM8962_VMID_BUF_ENA_MASK 0x0008 /* VMID_BUF_ENA */ |
1708 | #define WM8962_VMID_BUF_ENA_SHIFT 3 /* VMID_BUF_ENA */ |
1709 | #define WM8962_VMID_BUF_ENA_WIDTH 1 /* VMID_BUF_ENA */ |
1710 | #define WM8962_VMID_RAMP 0x0004 /* VMID_RAMP */ |
1711 | #define WM8962_VMID_RAMP_MASK 0x0004 /* VMID_RAMP */ |
1712 | #define WM8962_VMID_RAMP_SHIFT 2 /* VMID_RAMP */ |
1713 | #define WM8962_VMID_RAMP_WIDTH 1 /* VMID_RAMP */ |
1714 | |
1715 | /* |
1716 | * R30 (0x1E) - Clocking 3 |
1717 | */ |
1718 | #define WM8962_DBCLK_DIV_MASK 0xE000 /* DBCLK_DIV - [15:13] */ |
1719 | #define WM8962_DBCLK_DIV_SHIFT 13 /* DBCLK_DIV - [15:13] */ |
1720 | #define WM8962_DBCLK_DIV_WIDTH 3 /* DBCLK_DIV - [15:13] */ |
1721 | #define WM8962_OPCLK_DIV_MASK 0x1C00 /* OPCLK_DIV - [12:10] */ |
1722 | #define WM8962_OPCLK_DIV_SHIFT 10 /* OPCLK_DIV - [12:10] */ |
1723 | #define WM8962_OPCLK_DIV_WIDTH 3 /* OPCLK_DIV - [12:10] */ |
1724 | #define WM8962_TOCLK_DIV_MASK 0x0380 /* TOCLK_DIV - [9:7] */ |
1725 | #define WM8962_TOCLK_DIV_SHIFT 7 /* TOCLK_DIV - [9:7] */ |
1726 | #define WM8962_TOCLK_DIV_WIDTH 3 /* TOCLK_DIV - [9:7] */ |
1727 | #define WM8962_F256KCLK_DIV_MASK 0x007E /* F256KCLK_DIV - [6:1] */ |
1728 | #define WM8962_F256KCLK_DIV_SHIFT 1 /* F256KCLK_DIV - [6:1] */ |
1729 | #define WM8962_F256KCLK_DIV_WIDTH 6 /* F256KCLK_DIV - [6:1] */ |
1730 | |
1731 | /* |
1732 | * R31 (0x1F) - Input mixer control (1) |
1733 | */ |
1734 | #define WM8962_MIXINL_MUTE 0x0008 /* MIXINL_MUTE */ |
1735 | #define WM8962_MIXINL_MUTE_MASK 0x0008 /* MIXINL_MUTE */ |
1736 | #define WM8962_MIXINL_MUTE_SHIFT 3 /* MIXINL_MUTE */ |
1737 | #define WM8962_MIXINL_MUTE_WIDTH 1 /* MIXINL_MUTE */ |
1738 | #define WM8962_MIXINR_MUTE 0x0004 /* MIXINR_MUTE */ |
1739 | #define WM8962_MIXINR_MUTE_MASK 0x0004 /* MIXINR_MUTE */ |
1740 | #define WM8962_MIXINR_MUTE_SHIFT 2 /* MIXINR_MUTE */ |
1741 | #define WM8962_MIXINR_MUTE_WIDTH 1 /* MIXINR_MUTE */ |
1742 | #define WM8962_MIXINL_ENA 0x0002 /* MIXINL_ENA */ |
1743 | #define WM8962_MIXINL_ENA_MASK 0x0002 /* MIXINL_ENA */ |
1744 | #define WM8962_MIXINL_ENA_SHIFT 1 /* MIXINL_ENA */ |
1745 | #define WM8962_MIXINL_ENA_WIDTH 1 /* MIXINL_ENA */ |
1746 | #define WM8962_MIXINR_ENA 0x0001 /* MIXINR_ENA */ |
1747 | #define WM8962_MIXINR_ENA_MASK 0x0001 /* MIXINR_ENA */ |
1748 | #define WM8962_MIXINR_ENA_SHIFT 0 /* MIXINR_ENA */ |
1749 | #define WM8962_MIXINR_ENA_WIDTH 1 /* MIXINR_ENA */ |
1750 | |
1751 | /* |
1752 | * R32 (0x20) - Left input mixer volume |
1753 | */ |
1754 | #define WM8962_IN2L_MIXINL_VOL_MASK 0x01C0 /* IN2L_MIXINL_VOL - [8:6] */ |
1755 | #define WM8962_IN2L_MIXINL_VOL_SHIFT 6 /* IN2L_MIXINL_VOL - [8:6] */ |
1756 | #define WM8962_IN2L_MIXINL_VOL_WIDTH 3 /* IN2L_MIXINL_VOL - [8:6] */ |
1757 | #define WM8962_INPGAL_MIXINL_VOL_MASK 0x0038 /* INPGAL_MIXINL_VOL - [5:3] */ |
1758 | #define WM8962_INPGAL_MIXINL_VOL_SHIFT 3 /* INPGAL_MIXINL_VOL - [5:3] */ |
1759 | #define WM8962_INPGAL_MIXINL_VOL_WIDTH 3 /* INPGAL_MIXINL_VOL - [5:3] */ |
1760 | #define WM8962_IN3L_MIXINL_VOL_MASK 0x0007 /* IN3L_MIXINL_VOL - [2:0] */ |
1761 | #define WM8962_IN3L_MIXINL_VOL_SHIFT 0 /* IN3L_MIXINL_VOL - [2:0] */ |
1762 | #define WM8962_IN3L_MIXINL_VOL_WIDTH 3 /* IN3L_MIXINL_VOL - [2:0] */ |
1763 | |
1764 | /* |
1765 | * R33 (0x21) - Right input mixer volume |
1766 | */ |
1767 | #define WM8962_IN2R_MIXINR_VOL_MASK 0x01C0 /* IN2R_MIXINR_VOL - [8:6] */ |
1768 | #define WM8962_IN2R_MIXINR_VOL_SHIFT 6 /* IN2R_MIXINR_VOL - [8:6] */ |
1769 | #define WM8962_IN2R_MIXINR_VOL_WIDTH 3 /* IN2R_MIXINR_VOL - [8:6] */ |
1770 | #define WM8962_INPGAR_MIXINR_VOL_MASK 0x0038 /* INPGAR_MIXINR_VOL - [5:3] */ |
1771 | #define WM8962_INPGAR_MIXINR_VOL_SHIFT 3 /* INPGAR_MIXINR_VOL - [5:3] */ |
1772 | #define WM8962_INPGAR_MIXINR_VOL_WIDTH 3 /* INPGAR_MIXINR_VOL - [5:3] */ |
1773 | #define WM8962_IN3R_MIXINR_VOL_MASK 0x0007 /* IN3R_MIXINR_VOL - [2:0] */ |
1774 | #define WM8962_IN3R_MIXINR_VOL_SHIFT 0 /* IN3R_MIXINR_VOL - [2:0] */ |
1775 | #define WM8962_IN3R_MIXINR_VOL_WIDTH 3 /* IN3R_MIXINR_VOL - [2:0] */ |
1776 | |
1777 | /* |
1778 | * R34 (0x22) - Input mixer control (2) |
1779 | */ |
1780 | #define WM8962_IN2L_TO_MIXINL 0x0020 /* IN2L_TO_MIXINL */ |
1781 | #define WM8962_IN2L_TO_MIXINL_MASK 0x0020 /* IN2L_TO_MIXINL */ |
1782 | #define WM8962_IN2L_TO_MIXINL_SHIFT 5 /* IN2L_TO_MIXINL */ |
1783 | #define WM8962_IN2L_TO_MIXINL_WIDTH 1 /* IN2L_TO_MIXINL */ |
1784 | #define WM8962_IN3L_TO_MIXINL 0x0010 /* IN3L_TO_MIXINL */ |
1785 | #define WM8962_IN3L_TO_MIXINL_MASK 0x0010 /* IN3L_TO_MIXINL */ |
1786 | #define WM8962_IN3L_TO_MIXINL_SHIFT 4 /* IN3L_TO_MIXINL */ |
1787 | #define WM8962_IN3L_TO_MIXINL_WIDTH 1 /* IN3L_TO_MIXINL */ |
1788 | #define WM8962_INPGAL_TO_MIXINL 0x0008 /* INPGAL_TO_MIXINL */ |
1789 | #define WM8962_INPGAL_TO_MIXINL_MASK 0x0008 /* INPGAL_TO_MIXINL */ |
1790 | #define WM8962_INPGAL_TO_MIXINL_SHIFT 3 /* INPGAL_TO_MIXINL */ |
1791 | #define WM8962_INPGAL_TO_MIXINL_WIDTH 1 /* INPGAL_TO_MIXINL */ |
1792 | #define WM8962_IN2R_TO_MIXINR 0x0004 /* IN2R_TO_MIXINR */ |
1793 | #define WM8962_IN2R_TO_MIXINR_MASK 0x0004 /* IN2R_TO_MIXINR */ |
1794 | #define WM8962_IN2R_TO_MIXINR_SHIFT 2 /* IN2R_TO_MIXINR */ |
1795 | #define WM8962_IN2R_TO_MIXINR_WIDTH 1 /* IN2R_TO_MIXINR */ |
1796 | #define WM8962_IN3R_TO_MIXINR 0x0002 /* IN3R_TO_MIXINR */ |
1797 | #define WM8962_IN3R_TO_MIXINR_MASK 0x0002 /* IN3R_TO_MIXINR */ |
1798 | #define WM8962_IN3R_TO_MIXINR_SHIFT 1 /* IN3R_TO_MIXINR */ |
1799 | #define WM8962_IN3R_TO_MIXINR_WIDTH 1 /* IN3R_TO_MIXINR */ |
1800 | #define WM8962_INPGAR_TO_MIXINR 0x0001 /* INPGAR_TO_MIXINR */ |
1801 | #define WM8962_INPGAR_TO_MIXINR_MASK 0x0001 /* INPGAR_TO_MIXINR */ |
1802 | #define WM8962_INPGAR_TO_MIXINR_SHIFT 0 /* INPGAR_TO_MIXINR */ |
1803 | #define WM8962_INPGAR_TO_MIXINR_WIDTH 1 /* INPGAR_TO_MIXINR */ |
1804 | |
1805 | /* |
1806 | * R35 (0x23) - Input bias control |
1807 | */ |
1808 | #define WM8962_MIXIN_BIAS_MASK 0x0038 /* MIXIN_BIAS - [5:3] */ |
1809 | #define WM8962_MIXIN_BIAS_SHIFT 3 /* MIXIN_BIAS - [5:3] */ |
1810 | #define WM8962_MIXIN_BIAS_WIDTH 3 /* MIXIN_BIAS - [5:3] */ |
1811 | #define WM8962_INPGA_BIAS_MASK 0x0007 /* INPGA_BIAS - [2:0] */ |
1812 | #define WM8962_INPGA_BIAS_SHIFT 0 /* INPGA_BIAS - [2:0] */ |
1813 | #define WM8962_INPGA_BIAS_WIDTH 3 /* INPGA_BIAS - [2:0] */ |
1814 | |
1815 | /* |
1816 | * R37 (0x25) - Left input PGA control |
1817 | */ |
1818 | #define WM8962_INPGAL_ENA 0x0010 /* INPGAL_ENA */ |
1819 | #define WM8962_INPGAL_ENA_MASK 0x0010 /* INPGAL_ENA */ |
1820 | #define WM8962_INPGAL_ENA_SHIFT 4 /* INPGAL_ENA */ |
1821 | #define WM8962_INPGAL_ENA_WIDTH 1 /* INPGAL_ENA */ |
1822 | #define WM8962_IN1L_TO_INPGAL 0x0008 /* IN1L_TO_INPGAL */ |
1823 | #define WM8962_IN1L_TO_INPGAL_MASK 0x0008 /* IN1L_TO_INPGAL */ |
1824 | #define WM8962_IN1L_TO_INPGAL_SHIFT 3 /* IN1L_TO_INPGAL */ |
1825 | #define WM8962_IN1L_TO_INPGAL_WIDTH 1 /* IN1L_TO_INPGAL */ |
1826 | #define WM8962_IN2L_TO_INPGAL 0x0004 /* IN2L_TO_INPGAL */ |
1827 | #define WM8962_IN2L_TO_INPGAL_MASK 0x0004 /* IN2L_TO_INPGAL */ |
1828 | #define WM8962_IN2L_TO_INPGAL_SHIFT 2 /* IN2L_TO_INPGAL */ |
1829 | #define WM8962_IN2L_TO_INPGAL_WIDTH 1 /* IN2L_TO_INPGAL */ |
1830 | #define WM8962_IN3L_TO_INPGAL 0x0002 /* IN3L_TO_INPGAL */ |
1831 | #define WM8962_IN3L_TO_INPGAL_MASK 0x0002 /* IN3L_TO_INPGAL */ |
1832 | #define WM8962_IN3L_TO_INPGAL_SHIFT 1 /* IN3L_TO_INPGAL */ |
1833 | #define WM8962_IN3L_TO_INPGAL_WIDTH 1 /* IN3L_TO_INPGAL */ |
1834 | #define WM8962_IN4L_TO_INPGAL 0x0001 /* IN4L_TO_INPGAL */ |
1835 | #define WM8962_IN4L_TO_INPGAL_MASK 0x0001 /* IN4L_TO_INPGAL */ |
1836 | #define WM8962_IN4L_TO_INPGAL_SHIFT 0 /* IN4L_TO_INPGAL */ |
1837 | #define WM8962_IN4L_TO_INPGAL_WIDTH 1 /* IN4L_TO_INPGAL */ |
1838 | |
1839 | /* |
1840 | * R38 (0x26) - Right input PGA control |
1841 | */ |
1842 | #define WM8962_INPGAR_ENA 0x0010 /* INPGAR_ENA */ |
1843 | #define WM8962_INPGAR_ENA_MASK 0x0010 /* INPGAR_ENA */ |
1844 | #define WM8962_INPGAR_ENA_SHIFT 4 /* INPGAR_ENA */ |
1845 | #define WM8962_INPGAR_ENA_WIDTH 1 /* INPGAR_ENA */ |
1846 | #define WM8962_IN1R_TO_INPGAR 0x0008 /* IN1R_TO_INPGAR */ |
1847 | #define WM8962_IN1R_TO_INPGAR_MASK 0x0008 /* IN1R_TO_INPGAR */ |
1848 | #define WM8962_IN1R_TO_INPGAR_SHIFT 3 /* IN1R_TO_INPGAR */ |
1849 | #define WM8962_IN1R_TO_INPGAR_WIDTH 1 /* IN1R_TO_INPGAR */ |
1850 | #define WM8962_IN2R_TO_INPGAR 0x0004 /* IN2R_TO_INPGAR */ |
1851 | #define WM8962_IN2R_TO_INPGAR_MASK 0x0004 /* IN2R_TO_INPGAR */ |
1852 | #define WM8962_IN2R_TO_INPGAR_SHIFT 2 /* IN2R_TO_INPGAR */ |
1853 | #define WM8962_IN2R_TO_INPGAR_WIDTH 1 /* IN2R_TO_INPGAR */ |
1854 | #define WM8962_IN3R_TO_INPGAR 0x0002 /* IN3R_TO_INPGAR */ |
1855 | #define WM8962_IN3R_TO_INPGAR_MASK 0x0002 /* IN3R_TO_INPGAR */ |
1856 | #define WM8962_IN3R_TO_INPGAR_SHIFT 1 /* IN3R_TO_INPGAR */ |
1857 | #define WM8962_IN3R_TO_INPGAR_WIDTH 1 /* IN3R_TO_INPGAR */ |
1858 | #define WM8962_IN4R_TO_INPGAR 0x0001 /* IN4R_TO_INPGAR */ |
1859 | #define WM8962_IN4R_TO_INPGAR_MASK 0x0001 /* IN4R_TO_INPGAR */ |
1860 | #define WM8962_IN4R_TO_INPGAR_SHIFT 0 /* IN4R_TO_INPGAR */ |
1861 | #define WM8962_IN4R_TO_INPGAR_WIDTH 1 /* IN4R_TO_INPGAR */ |
1862 | |
1863 | /* |
1864 | * R40 (0x28) - SPKOUTL volume |
1865 | */ |
1866 | #define WM8962_SPKOUT_VU 0x0100 /* SPKOUT_VU */ |
1867 | #define WM8962_SPKOUT_VU_MASK 0x0100 /* SPKOUT_VU */ |
1868 | #define WM8962_SPKOUT_VU_SHIFT 8 /* SPKOUT_VU */ |
1869 | #define WM8962_SPKOUT_VU_WIDTH 1 /* SPKOUT_VU */ |
1870 | #define WM8962_SPKOUTL_ZC 0x0080 /* SPKOUTL_ZC */ |
1871 | #define WM8962_SPKOUTL_ZC_MASK 0x0080 /* SPKOUTL_ZC */ |
1872 | #define WM8962_SPKOUTL_ZC_SHIFT 7 /* SPKOUTL_ZC */ |
1873 | #define WM8962_SPKOUTL_ZC_WIDTH 1 /* SPKOUTL_ZC */ |
1874 | #define WM8962_SPKOUTL_VOL_MASK 0x007F /* SPKOUTL_VOL - [6:0] */ |
1875 | #define WM8962_SPKOUTL_VOL_SHIFT 0 /* SPKOUTL_VOL - [6:0] */ |
1876 | #define WM8962_SPKOUTL_VOL_WIDTH 7 /* SPKOUTL_VOL - [6:0] */ |
1877 | |
1878 | /* |
1879 | * R41 (0x29) - SPKOUTR volume |
1880 | */ |
1881 | #define WM8962_SPKOUTR_ZC 0x0080 /* SPKOUTR_ZC */ |
1882 | #define WM8962_SPKOUTR_ZC_MASK 0x0080 /* SPKOUTR_ZC */ |
1883 | #define WM8962_SPKOUTR_ZC_SHIFT 7 /* SPKOUTR_ZC */ |
1884 | #define WM8962_SPKOUTR_ZC_WIDTH 1 /* SPKOUTR_ZC */ |
1885 | #define WM8962_SPKOUTR_VOL_MASK 0x007F /* SPKOUTR_VOL - [6:0] */ |
1886 | #define WM8962_SPKOUTR_VOL_SHIFT 0 /* SPKOUTR_VOL - [6:0] */ |
1887 | #define WM8962_SPKOUTR_VOL_WIDTH 7 /* SPKOUTR_VOL - [6:0] */ |
1888 | |
1889 | /* |
1890 | * R47 (0x2F) - Thermal Shutdown Status |
1891 | */ |
1892 | #define WM8962_TEMP_ERR_HP 0x0008 /* TEMP_ERR_HP */ |
1893 | #define WM8962_TEMP_ERR_HP_MASK 0x0008 /* TEMP_ERR_HP */ |
1894 | #define WM8962_TEMP_ERR_HP_SHIFT 3 /* TEMP_ERR_HP */ |
1895 | #define WM8962_TEMP_ERR_HP_WIDTH 1 /* TEMP_ERR_HP */ |
1896 | #define WM8962_TEMP_WARN_HP 0x0004 /* TEMP_WARN_HP */ |
1897 | #define WM8962_TEMP_WARN_HP_MASK 0x0004 /* TEMP_WARN_HP */ |
1898 | #define WM8962_TEMP_WARN_HP_SHIFT 2 /* TEMP_WARN_HP */ |
1899 | #define WM8962_TEMP_WARN_HP_WIDTH 1 /* TEMP_WARN_HP */ |
1900 | #define WM8962_TEMP_ERR_SPK 0x0002 /* TEMP_ERR_SPK */ |
1901 | #define WM8962_TEMP_ERR_SPK_MASK 0x0002 /* TEMP_ERR_SPK */ |
1902 | #define WM8962_TEMP_ERR_SPK_SHIFT 1 /* TEMP_ERR_SPK */ |
1903 | #define WM8962_TEMP_ERR_SPK_WIDTH 1 /* TEMP_ERR_SPK */ |
1904 | #define WM8962_TEMP_WARN_SPK 0x0001 /* TEMP_WARN_SPK */ |
1905 | #define WM8962_TEMP_WARN_SPK_MASK 0x0001 /* TEMP_WARN_SPK */ |
1906 | #define WM8962_TEMP_WARN_SPK_SHIFT 0 /* TEMP_WARN_SPK */ |
1907 | #define WM8962_TEMP_WARN_SPK_WIDTH 1 /* TEMP_WARN_SPK */ |
1908 | |
1909 | /* |
1910 | * R48 (0x30) - Additional Control (4) |
1911 | */ |
1912 | #define WM8962_MICDET_THR_MASK 0x7000 /* MICDET_THR - [14:12] */ |
1913 | #define WM8962_MICDET_THR_SHIFT 12 /* MICDET_THR - [14:12] */ |
1914 | #define WM8962_MICDET_THR_WIDTH 3 /* MICDET_THR - [14:12] */ |
1915 | #define WM8962_MICSHORT_THR_MASK 0x0C00 /* MICSHORT_THR - [11:10] */ |
1916 | #define WM8962_MICSHORT_THR_SHIFT 10 /* MICSHORT_THR - [11:10] */ |
1917 | #define WM8962_MICSHORT_THR_WIDTH 2 /* MICSHORT_THR - [11:10] */ |
1918 | #define WM8962_MICDET_ENA 0x0200 /* MICDET_ENA */ |
1919 | #define WM8962_MICDET_ENA_MASK 0x0200 /* MICDET_ENA */ |
1920 | #define WM8962_MICDET_ENA_SHIFT 9 /* MICDET_ENA */ |
1921 | #define WM8962_MICDET_ENA_WIDTH 1 /* MICDET_ENA */ |
1922 | #define WM8962_MICDET_STS 0x0080 /* MICDET_STS */ |
1923 | #define WM8962_MICDET_STS_MASK 0x0080 /* MICDET_STS */ |
1924 | #define WM8962_MICDET_STS_SHIFT 7 /* MICDET_STS */ |
1925 | #define WM8962_MICDET_STS_WIDTH 1 /* MICDET_STS */ |
1926 | #define WM8962_MICSHORT_STS 0x0040 /* MICSHORT_STS */ |
1927 | #define WM8962_MICSHORT_STS_MASK 0x0040 /* MICSHORT_STS */ |
1928 | #define WM8962_MICSHORT_STS_SHIFT 6 /* MICSHORT_STS */ |
1929 | #define WM8962_MICSHORT_STS_WIDTH 1 /* MICSHORT_STS */ |
1930 | #define WM8962_TEMP_ENA_HP 0x0004 /* TEMP_ENA_HP */ |
1931 | #define WM8962_TEMP_ENA_HP_MASK 0x0004 /* TEMP_ENA_HP */ |
1932 | #define WM8962_TEMP_ENA_HP_SHIFT 2 /* TEMP_ENA_HP */ |
1933 | #define WM8962_TEMP_ENA_HP_WIDTH 1 /* TEMP_ENA_HP */ |
1934 | #define WM8962_TEMP_ENA_SPK 0x0002 /* TEMP_ENA_SPK */ |
1935 | #define WM8962_TEMP_ENA_SPK_MASK 0x0002 /* TEMP_ENA_SPK */ |
1936 | #define WM8962_TEMP_ENA_SPK_SHIFT 1 /* TEMP_ENA_SPK */ |
1937 | #define WM8962_TEMP_ENA_SPK_WIDTH 1 /* TEMP_ENA_SPK */ |
1938 | #define WM8962_MICBIAS_LVL 0x0001 /* MICBIAS_LVL */ |
1939 | #define WM8962_MICBIAS_LVL_MASK 0x0001 /* MICBIAS_LVL */ |
1940 | #define WM8962_MICBIAS_LVL_SHIFT 0 /* MICBIAS_LVL */ |
1941 | #define WM8962_MICBIAS_LVL_WIDTH 1 /* MICBIAS_LVL */ |
1942 | |
1943 | /* |
1944 | * R49 (0x31) - Class D Control 1 |
1945 | */ |
1946 | #define WM8962_SPKOUTR_ENA 0x0080 /* SPKOUTR_ENA */ |
1947 | #define WM8962_SPKOUTR_ENA_MASK 0x0080 /* SPKOUTR_ENA */ |
1948 | #define WM8962_SPKOUTR_ENA_SHIFT 7 /* SPKOUTR_ENA */ |
1949 | #define WM8962_SPKOUTR_ENA_WIDTH 1 /* SPKOUTR_ENA */ |
1950 | #define WM8962_SPKOUTL_ENA 0x0040 /* SPKOUTL_ENA */ |
1951 | #define WM8962_SPKOUTL_ENA_MASK 0x0040 /* SPKOUTL_ENA */ |
1952 | #define WM8962_SPKOUTL_ENA_SHIFT 6 /* SPKOUTL_ENA */ |
1953 | #define WM8962_SPKOUTL_ENA_WIDTH 1 /* SPKOUTL_ENA */ |
1954 | #define WM8962_DAC_MUTE_ALT 0x0010 /* DAC_MUTE */ |
1955 | #define WM8962_DAC_MUTE_ALT_MASK 0x0010 /* DAC_MUTE */ |
1956 | #define WM8962_DAC_MUTE_ALT_SHIFT 4 /* DAC_MUTE */ |
1957 | #define WM8962_DAC_MUTE_ALT_WIDTH 1 /* DAC_MUTE */ |
1958 | #define WM8962_SPKOUTL_PGA_MUTE 0x0002 /* SPKOUTL_PGA_MUTE */ |
1959 | #define WM8962_SPKOUTL_PGA_MUTE_MASK 0x0002 /* SPKOUTL_PGA_MUTE */ |
1960 | #define WM8962_SPKOUTL_PGA_MUTE_SHIFT 1 /* SPKOUTL_PGA_MUTE */ |
1961 | #define WM8962_SPKOUTL_PGA_MUTE_WIDTH 1 /* SPKOUTL_PGA_MUTE */ |
1962 | #define WM8962_SPKOUTR_PGA_MUTE 0x0001 /* SPKOUTR_PGA_MUTE */ |
1963 | #define WM8962_SPKOUTR_PGA_MUTE_MASK 0x0001 /* SPKOUTR_PGA_MUTE */ |
1964 | #define WM8962_SPKOUTR_PGA_MUTE_SHIFT 0 /* SPKOUTR_PGA_MUTE */ |
1965 | #define WM8962_SPKOUTR_PGA_MUTE_WIDTH 1 /* SPKOUTR_PGA_MUTE */ |
1966 | |
1967 | /* |
1968 | * R51 (0x33) - Class D Control 2 |
1969 | */ |
1970 | #define WM8962_SPK_MONO 0x0040 /* SPK_MONO */ |
1971 | #define WM8962_SPK_MONO_MASK 0x0040 /* SPK_MONO */ |
1972 | #define WM8962_SPK_MONO_SHIFT 6 /* SPK_MONO */ |
1973 | #define WM8962_SPK_MONO_WIDTH 1 /* SPK_MONO */ |
1974 | #define WM8962_CLASSD_VOL_MASK 0x0007 /* CLASSD_VOL - [2:0] */ |
1975 | #define WM8962_CLASSD_VOL_SHIFT 0 /* CLASSD_VOL - [2:0] */ |
1976 | #define WM8962_CLASSD_VOL_WIDTH 3 /* CLASSD_VOL - [2:0] */ |
1977 | |
1978 | /* |
1979 | * R56 (0x38) - Clocking 4 |
1980 | */ |
1981 | #define WM8962_SYSCLK_RATE_MASK 0x001E /* SYSCLK_RATE - [4:1] */ |
1982 | #define WM8962_SYSCLK_RATE_SHIFT 1 /* SYSCLK_RATE - [4:1] */ |
1983 | #define WM8962_SYSCLK_RATE_WIDTH 4 /* SYSCLK_RATE - [4:1] */ |
1984 | |
1985 | /* |
1986 | * R57 (0x39) - DAC DSP Mixing (1) |
1987 | */ |
1988 | #define WM8962_DAC_MONOMIX 0x0200 /* DAC_MONOMIX */ |
1989 | #define WM8962_DAC_MONOMIX_MASK 0x0200 /* DAC_MONOMIX */ |
1990 | #define WM8962_DAC_MONOMIX_SHIFT 9 /* DAC_MONOMIX */ |
1991 | #define WM8962_DAC_MONOMIX_WIDTH 1 /* DAC_MONOMIX */ |
1992 | #define WM8962_ADCR_DAC_SVOL_MASK 0x00F0 /* ADCR_DAC_SVOL - [7:4] */ |
1993 | #define WM8962_ADCR_DAC_SVOL_SHIFT 4 /* ADCR_DAC_SVOL - [7:4] */ |
1994 | #define WM8962_ADCR_DAC_SVOL_WIDTH 4 /* ADCR_DAC_SVOL - [7:4] */ |
1995 | #define WM8962_ADC_TO_DACR_MASK 0x000C /* ADC_TO_DACR - [3:2] */ |
1996 | #define WM8962_ADC_TO_DACR_SHIFT 2 /* ADC_TO_DACR - [3:2] */ |
1997 | #define WM8962_ADC_TO_DACR_WIDTH 2 /* ADC_TO_DACR - [3:2] */ |
1998 | |
1999 | /* |
2000 | * R58 (0x3A) - DAC DSP Mixing (2) |
2001 | */ |
2002 | #define WM8962_ADCL_DAC_SVOL_MASK 0x00F0 /* ADCL_DAC_SVOL - [7:4] */ |
2003 | #define WM8962_ADCL_DAC_SVOL_SHIFT 4 /* ADCL_DAC_SVOL - [7:4] */ |
2004 | #define WM8962_ADCL_DAC_SVOL_WIDTH 4 /* ADCL_DAC_SVOL - [7:4] */ |
2005 | #define WM8962_ADC_TO_DACL_MASK 0x000C /* ADC_TO_DACL - [3:2] */ |
2006 | #define WM8962_ADC_TO_DACL_SHIFT 2 /* ADC_TO_DACL - [3:2] */ |
2007 | #define WM8962_ADC_TO_DACL_WIDTH 2 /* ADC_TO_DACL - [3:2] */ |
2008 | |
2009 | /* |
2010 | * R60 (0x3C) - DC Servo 0 |
2011 | */ |
2012 | #define WM8962_INL_DCS_ENA 0x0080 /* INL_DCS_ENA */ |
2013 | #define WM8962_INL_DCS_ENA_MASK 0x0080 /* INL_DCS_ENA */ |
2014 | #define WM8962_INL_DCS_ENA_SHIFT 7 /* INL_DCS_ENA */ |
2015 | #define WM8962_INL_DCS_ENA_WIDTH 1 /* INL_DCS_ENA */ |
2016 | #define WM8962_INL_DCS_STARTUP 0x0040 /* INL_DCS_STARTUP */ |
2017 | #define WM8962_INL_DCS_STARTUP_MASK 0x0040 /* INL_DCS_STARTUP */ |
2018 | #define WM8962_INL_DCS_STARTUP_SHIFT 6 /* INL_DCS_STARTUP */ |
2019 | #define WM8962_INL_DCS_STARTUP_WIDTH 1 /* INL_DCS_STARTUP */ |
2020 | #define WM8962_INR_DCS_ENA 0x0008 /* INR_DCS_ENA */ |
2021 | #define WM8962_INR_DCS_ENA_MASK 0x0008 /* INR_DCS_ENA */ |
2022 | #define WM8962_INR_DCS_ENA_SHIFT 3 /* INR_DCS_ENA */ |
2023 | #define WM8962_INR_DCS_ENA_WIDTH 1 /* INR_DCS_ENA */ |
2024 | #define WM8962_INR_DCS_STARTUP 0x0004 /* INR_DCS_STARTUP */ |
2025 | #define WM8962_INR_DCS_STARTUP_MASK 0x0004 /* INR_DCS_STARTUP */ |
2026 | #define WM8962_INR_DCS_STARTUP_SHIFT 2 /* INR_DCS_STARTUP */ |
2027 | #define WM8962_INR_DCS_STARTUP_WIDTH 1 /* INR_DCS_STARTUP */ |
2028 | |
2029 | /* |
2030 | * R61 (0x3D) - DC Servo 1 |
2031 | */ |
2032 | #define WM8962_HP1L_DCS_ENA 0x0080 /* HP1L_DCS_ENA */ |
2033 | #define WM8962_HP1L_DCS_ENA_MASK 0x0080 /* HP1L_DCS_ENA */ |
2034 | #define WM8962_HP1L_DCS_ENA_SHIFT 7 /* HP1L_DCS_ENA */ |
2035 | #define WM8962_HP1L_DCS_ENA_WIDTH 1 /* HP1L_DCS_ENA */ |
2036 | #define WM8962_HP1L_DCS_STARTUP 0x0040 /* HP1L_DCS_STARTUP */ |
2037 | #define WM8962_HP1L_DCS_STARTUP_MASK 0x0040 /* HP1L_DCS_STARTUP */ |
2038 | #define WM8962_HP1L_DCS_STARTUP_SHIFT 6 /* HP1L_DCS_STARTUP */ |
2039 | #define WM8962_HP1L_DCS_STARTUP_WIDTH 1 /* HP1L_DCS_STARTUP */ |
2040 | #define WM8962_HP1L_DCS_SYNC 0x0010 /* HP1L_DCS_SYNC */ |
2041 | #define WM8962_HP1L_DCS_SYNC_MASK 0x0010 /* HP1L_DCS_SYNC */ |
2042 | #define WM8962_HP1L_DCS_SYNC_SHIFT 4 /* HP1L_DCS_SYNC */ |
2043 | #define WM8962_HP1L_DCS_SYNC_WIDTH 1 /* HP1L_DCS_SYNC */ |
2044 | #define WM8962_HP1R_DCS_ENA 0x0008 /* HP1R_DCS_ENA */ |
2045 | #define WM8962_HP1R_DCS_ENA_MASK 0x0008 /* HP1R_DCS_ENA */ |
2046 | #define WM8962_HP1R_DCS_ENA_SHIFT 3 /* HP1R_DCS_ENA */ |
2047 | #define WM8962_HP1R_DCS_ENA_WIDTH 1 /* HP1R_DCS_ENA */ |
2048 | #define WM8962_HP1R_DCS_STARTUP 0x0004 /* HP1R_DCS_STARTUP */ |
2049 | #define WM8962_HP1R_DCS_STARTUP_MASK 0x0004 /* HP1R_DCS_STARTUP */ |
2050 | #define WM8962_HP1R_DCS_STARTUP_SHIFT 2 /* HP1R_DCS_STARTUP */ |
2051 | #define WM8962_HP1R_DCS_STARTUP_WIDTH 1 /* HP1R_DCS_STARTUP */ |
2052 | #define WM8962_HP1R_DCS_SYNC 0x0001 /* HP1R_DCS_SYNC */ |
2053 | #define WM8962_HP1R_DCS_SYNC_MASK 0x0001 /* HP1R_DCS_SYNC */ |
2054 | #define WM8962_HP1R_DCS_SYNC_SHIFT 0 /* HP1R_DCS_SYNC */ |
2055 | #define WM8962_HP1R_DCS_SYNC_WIDTH 1 /* HP1R_DCS_SYNC */ |
2056 | |
2057 | /* |
2058 | * R64 (0x40) - DC Servo 4 |
2059 | */ |
2060 | #define WM8962_HP1_DCS_SYNC_STEPS_MASK 0x3F80 /* HP1_DCS_SYNC_STEPS - [13:7] */ |
2061 | #define WM8962_HP1_DCS_SYNC_STEPS_SHIFT 7 /* HP1_DCS_SYNC_STEPS - [13:7] */ |
2062 | #define WM8962_HP1_DCS_SYNC_STEPS_WIDTH 7 /* HP1_DCS_SYNC_STEPS - [13:7] */ |
2063 | |
2064 | /* |
2065 | * R66 (0x42) - DC Servo 6 |
2066 | */ |
2067 | #define WM8962_DCS_STARTUP_DONE_INL 0x0400 /* DCS_STARTUP_DONE_INL */ |
2068 | #define WM8962_DCS_STARTUP_DONE_INL_MASK 0x0400 /* DCS_STARTUP_DONE_INL */ |
2069 | #define WM8962_DCS_STARTUP_DONE_INL_SHIFT 10 /* DCS_STARTUP_DONE_INL */ |
2070 | #define WM8962_DCS_STARTUP_DONE_INL_WIDTH 1 /* DCS_STARTUP_DONE_INL */ |
2071 | #define WM8962_DCS_STARTUP_DONE_INR 0x0200 /* DCS_STARTUP_DONE_INR */ |
2072 | #define WM8962_DCS_STARTUP_DONE_INR_MASK 0x0200 /* DCS_STARTUP_DONE_INR */ |
2073 | #define WM8962_DCS_STARTUP_DONE_INR_SHIFT 9 /* DCS_STARTUP_DONE_INR */ |
2074 | #define WM8962_DCS_STARTUP_DONE_INR_WIDTH 1 /* DCS_STARTUP_DONE_INR */ |
2075 | #define WM8962_DCS_STARTUP_DONE_HP1L 0x0100 /* DCS_STARTUP_DONE_HP1L */ |
2076 | #define WM8962_DCS_STARTUP_DONE_HP1L_MASK 0x0100 /* DCS_STARTUP_DONE_HP1L */ |
2077 | #define WM8962_DCS_STARTUP_DONE_HP1L_SHIFT 8 /* DCS_STARTUP_DONE_HP1L */ |
2078 | #define WM8962_DCS_STARTUP_DONE_HP1L_WIDTH 1 /* DCS_STARTUP_DONE_HP1L */ |
2079 | #define WM8962_DCS_STARTUP_DONE_HP1R 0x0080 /* DCS_STARTUP_DONE_HP1R */ |
2080 | #define WM8962_DCS_STARTUP_DONE_HP1R_MASK 0x0080 /* DCS_STARTUP_DONE_HP1R */ |
2081 | #define WM8962_DCS_STARTUP_DONE_HP1R_SHIFT 7 /* DCS_STARTUP_DONE_HP1R */ |
2082 | #define WM8962_DCS_STARTUP_DONE_HP1R_WIDTH 1 /* DCS_STARTUP_DONE_HP1R */ |
2083 | |
2084 | /* |
2085 | * R68 (0x44) - Analogue PGA Bias |
2086 | */ |
2087 | #define WM8962_HP_PGAS_BIAS_MASK 0x0007 /* HP_PGAS_BIAS - [2:0] */ |
2088 | #define WM8962_HP_PGAS_BIAS_SHIFT 0 /* HP_PGAS_BIAS - [2:0] */ |
2089 | #define WM8962_HP_PGAS_BIAS_WIDTH 3 /* HP_PGAS_BIAS - [2:0] */ |
2090 | |
2091 | /* |
2092 | * R69 (0x45) - Analogue HP 0 |
2093 | */ |
2094 | #define WM8962_HP1L_RMV_SHORT 0x0080 /* HP1L_RMV_SHORT */ |
2095 | #define WM8962_HP1L_RMV_SHORT_MASK 0x0080 /* HP1L_RMV_SHORT */ |
2096 | #define WM8962_HP1L_RMV_SHORT_SHIFT 7 /* HP1L_RMV_SHORT */ |
2097 | #define WM8962_HP1L_RMV_SHORT_WIDTH 1 /* HP1L_RMV_SHORT */ |
2098 | #define WM8962_HP1L_ENA_OUTP 0x0040 /* HP1L_ENA_OUTP */ |
2099 | #define WM8962_HP1L_ENA_OUTP_MASK 0x0040 /* HP1L_ENA_OUTP */ |
2100 | #define WM8962_HP1L_ENA_OUTP_SHIFT 6 /* HP1L_ENA_OUTP */ |
2101 | #define WM8962_HP1L_ENA_OUTP_WIDTH 1 /* HP1L_ENA_OUTP */ |
2102 | #define WM8962_HP1L_ENA_DLY 0x0020 /* HP1L_ENA_DLY */ |
2103 | #define WM8962_HP1L_ENA_DLY_MASK 0x0020 /* HP1L_ENA_DLY */ |
2104 | #define WM8962_HP1L_ENA_DLY_SHIFT 5 /* HP1L_ENA_DLY */ |
2105 | #define WM8962_HP1L_ENA_DLY_WIDTH 1 /* HP1L_ENA_DLY */ |
2106 | #define WM8962_HP1L_ENA 0x0010 /* HP1L_ENA */ |
2107 | #define WM8962_HP1L_ENA_MASK 0x0010 /* HP1L_ENA */ |
2108 | #define WM8962_HP1L_ENA_SHIFT 4 /* HP1L_ENA */ |
2109 | #define WM8962_HP1L_ENA_WIDTH 1 /* HP1L_ENA */ |
2110 | #define WM8962_HP1R_RMV_SHORT 0x0008 /* HP1R_RMV_SHORT */ |
2111 | #define WM8962_HP1R_RMV_SHORT_MASK 0x0008 /* HP1R_RMV_SHORT */ |
2112 | #define WM8962_HP1R_RMV_SHORT_SHIFT 3 /* HP1R_RMV_SHORT */ |
2113 | #define WM8962_HP1R_RMV_SHORT_WIDTH 1 /* HP1R_RMV_SHORT */ |
2114 | #define WM8962_HP1R_ENA_OUTP 0x0004 /* HP1R_ENA_OUTP */ |
2115 | #define WM8962_HP1R_ENA_OUTP_MASK 0x0004 /* HP1R_ENA_OUTP */ |
2116 | #define WM8962_HP1R_ENA_OUTP_SHIFT 2 /* HP1R_ENA_OUTP */ |
2117 | #define WM8962_HP1R_ENA_OUTP_WIDTH 1 /* HP1R_ENA_OUTP */ |
2118 | #define WM8962_HP1R_ENA_DLY 0x0002 /* HP1R_ENA_DLY */ |
2119 | #define WM8962_HP1R_ENA_DLY_MASK 0x0002 /* HP1R_ENA_DLY */ |
2120 | #define WM8962_HP1R_ENA_DLY_SHIFT 1 /* HP1R_ENA_DLY */ |
2121 | #define WM8962_HP1R_ENA_DLY_WIDTH 1 /* HP1R_ENA_DLY */ |
2122 | #define WM8962_HP1R_ENA 0x0001 /* HP1R_ENA */ |
2123 | #define WM8962_HP1R_ENA_MASK 0x0001 /* HP1R_ENA */ |
2124 | #define WM8962_HP1R_ENA_SHIFT 0 /* HP1R_ENA */ |
2125 | #define WM8962_HP1R_ENA_WIDTH 1 /* HP1R_ENA */ |
2126 | |
2127 | /* |
2128 | * R71 (0x47) - Analogue HP 2 |
2129 | */ |
2130 | #define WM8962_HP1L_VOL_MASK 0x01C0 /* HP1L_VOL - [8:6] */ |
2131 | #define WM8962_HP1L_VOL_SHIFT 6 /* HP1L_VOL - [8:6] */ |
2132 | #define WM8962_HP1L_VOL_WIDTH 3 /* HP1L_VOL - [8:6] */ |
2133 | #define WM8962_HP1R_VOL_MASK 0x0038 /* HP1R_VOL - [5:3] */ |
2134 | #define WM8962_HP1R_VOL_SHIFT 3 /* HP1R_VOL - [5:3] */ |
2135 | #define WM8962_HP1R_VOL_WIDTH 3 /* HP1R_VOL - [5:3] */ |
2136 | #define WM8962_HP_BIAS_BOOST_MASK 0x0007 /* HP_BIAS_BOOST - [2:0] */ |
2137 | #define WM8962_HP_BIAS_BOOST_SHIFT 0 /* HP_BIAS_BOOST - [2:0] */ |
2138 | #define WM8962_HP_BIAS_BOOST_WIDTH 3 /* HP_BIAS_BOOST - [2:0] */ |
2139 | |
2140 | /* |
2141 | * R72 (0x48) - Charge Pump 1 |
2142 | */ |
2143 | #define WM8962_CP_ENA 0x0001 /* CP_ENA */ |
2144 | #define WM8962_CP_ENA_MASK 0x0001 /* CP_ENA */ |
2145 | #define WM8962_CP_ENA_SHIFT 0 /* CP_ENA */ |
2146 | #define WM8962_CP_ENA_WIDTH 1 /* CP_ENA */ |
2147 | |
2148 | /* |
2149 | * R82 (0x52) - Charge Pump B |
2150 | */ |
2151 | #define WM8962_CP_DYN_PWR 0x0001 /* CP_DYN_PWR */ |
2152 | #define WM8962_CP_DYN_PWR_MASK 0x0001 /* CP_DYN_PWR */ |
2153 | #define WM8962_CP_DYN_PWR_SHIFT 0 /* CP_DYN_PWR */ |
2154 | #define WM8962_CP_DYN_PWR_WIDTH 1 /* CP_DYN_PWR */ |
2155 | |
2156 | /* |
2157 | * R87 (0x57) - Write Sequencer Control 1 |
2158 | */ |
2159 | #define WM8962_WSEQ_AUTOSEQ_ENA 0x0080 /* WSEQ_AUTOSEQ_ENA */ |
2160 | #define WM8962_WSEQ_AUTOSEQ_ENA_MASK 0x0080 /* WSEQ_AUTOSEQ_ENA */ |
2161 | #define WM8962_WSEQ_AUTOSEQ_ENA_SHIFT 7 /* WSEQ_AUTOSEQ_ENA */ |
2162 | #define WM8962_WSEQ_AUTOSEQ_ENA_WIDTH 1 /* WSEQ_AUTOSEQ_ENA */ |
2163 | #define WM8962_WSEQ_ENA 0x0020 /* WSEQ_ENA */ |
2164 | #define WM8962_WSEQ_ENA_MASK 0x0020 /* WSEQ_ENA */ |
2165 | #define WM8962_WSEQ_ENA_SHIFT 5 /* WSEQ_ENA */ |
2166 | #define WM8962_WSEQ_ENA_WIDTH 1 /* WSEQ_ENA */ |
2167 | |
2168 | /* |
2169 | * R90 (0x5A) - Write Sequencer Control 2 |
2170 | */ |
2171 | #define WM8962_WSEQ_ABORT 0x0100 /* WSEQ_ABORT */ |
2172 | #define WM8962_WSEQ_ABORT_MASK 0x0100 /* WSEQ_ABORT */ |
2173 | #define WM8962_WSEQ_ABORT_SHIFT 8 /* WSEQ_ABORT */ |
2174 | #define WM8962_WSEQ_ABORT_WIDTH 1 /* WSEQ_ABORT */ |
2175 | #define WM8962_WSEQ_START 0x0080 /* WSEQ_START */ |
2176 | #define WM8962_WSEQ_START_MASK 0x0080 /* WSEQ_START */ |
2177 | #define WM8962_WSEQ_START_SHIFT 7 /* WSEQ_START */ |
2178 | #define WM8962_WSEQ_START_WIDTH 1 /* WSEQ_START */ |
2179 | #define WM8962_WSEQ_START_INDEX_MASK 0x007F /* WSEQ_START_INDEX - [6:0] */ |
2180 | #define WM8962_WSEQ_START_INDEX_SHIFT 0 /* WSEQ_START_INDEX - [6:0] */ |
2181 | #define WM8962_WSEQ_START_INDEX_WIDTH 7 /* WSEQ_START_INDEX - [6:0] */ |
2182 | |
2183 | /* |
2184 | * R93 (0x5D) - Write Sequencer Control 3 |
2185 | */ |
2186 | #define WM8962_WSEQ_CURRENT_INDEX_MASK 0x03F8 /* WSEQ_CURRENT_INDEX - [9:3] */ |
2187 | #define WM8962_WSEQ_CURRENT_INDEX_SHIFT 3 /* WSEQ_CURRENT_INDEX - [9:3] */ |
2188 | #define WM8962_WSEQ_CURRENT_INDEX_WIDTH 7 /* WSEQ_CURRENT_INDEX - [9:3] */ |
2189 | #define WM8962_WSEQ_BUSY 0x0001 /* WSEQ_BUSY */ |
2190 | #define WM8962_WSEQ_BUSY_MASK 0x0001 /* WSEQ_BUSY */ |
2191 | #define WM8962_WSEQ_BUSY_SHIFT 0 /* WSEQ_BUSY */ |
2192 | #define WM8962_WSEQ_BUSY_WIDTH 1 /* WSEQ_BUSY */ |
2193 | |
2194 | /* |
2195 | * R94 (0x5E) - Control Interface |
2196 | */ |
2197 | #define WM8962_SPI_CONTRD 0x0040 /* SPI_CONTRD */ |
2198 | #define WM8962_SPI_CONTRD_MASK 0x0040 /* SPI_CONTRD */ |
2199 | #define WM8962_SPI_CONTRD_SHIFT 6 /* SPI_CONTRD */ |
2200 | #define WM8962_SPI_CONTRD_WIDTH 1 /* SPI_CONTRD */ |
2201 | #define WM8962_SPI_4WIRE 0x0020 /* SPI_4WIRE */ |
2202 | #define WM8962_SPI_4WIRE_MASK 0x0020 /* SPI_4WIRE */ |
2203 | #define WM8962_SPI_4WIRE_SHIFT 5 /* SPI_4WIRE */ |
2204 | #define WM8962_SPI_4WIRE_WIDTH 1 /* SPI_4WIRE */ |
2205 | #define WM8962_SPI_CFG 0x0010 /* SPI_CFG */ |
2206 | #define WM8962_SPI_CFG_MASK 0x0010 /* SPI_CFG */ |
2207 | #define WM8962_SPI_CFG_SHIFT 4 /* SPI_CFG */ |
2208 | #define WM8962_SPI_CFG_WIDTH 1 /* SPI_CFG */ |
2209 | |
2210 | /* |
2211 | * R99 (0x63) - Mixer Enables |
2212 | */ |
2213 | #define WM8962_HPMIXL_ENA 0x0008 /* HPMIXL_ENA */ |
2214 | #define WM8962_HPMIXL_ENA_MASK 0x0008 /* HPMIXL_ENA */ |
2215 | #define WM8962_HPMIXL_ENA_SHIFT 3 /* HPMIXL_ENA */ |
2216 | #define WM8962_HPMIXL_ENA_WIDTH 1 /* HPMIXL_ENA */ |
2217 | #define WM8962_HPMIXR_ENA 0x0004 /* HPMIXR_ENA */ |
2218 | #define WM8962_HPMIXR_ENA_MASK 0x0004 /* HPMIXR_ENA */ |
2219 | #define WM8962_HPMIXR_ENA_SHIFT 2 /* HPMIXR_ENA */ |
2220 | #define WM8962_HPMIXR_ENA_WIDTH 1 /* HPMIXR_ENA */ |
2221 | #define WM8962_SPKMIXL_ENA 0x0002 /* SPKMIXL_ENA */ |
2222 | #define WM8962_SPKMIXL_ENA_MASK 0x0002 /* SPKMIXL_ENA */ |
2223 | #define WM8962_SPKMIXL_ENA_SHIFT 1 /* SPKMIXL_ENA */ |
2224 | #define WM8962_SPKMIXL_ENA_WIDTH 1 /* SPKMIXL_ENA */ |
2225 | #define WM8962_SPKMIXR_ENA 0x0001 /* SPKMIXR_ENA */ |
2226 | #define WM8962_SPKMIXR_ENA_MASK 0x0001 /* SPKMIXR_ENA */ |
2227 | #define WM8962_SPKMIXR_ENA_SHIFT 0 /* SPKMIXR_ENA */ |
2228 | #define WM8962_SPKMIXR_ENA_WIDTH 1 /* SPKMIXR_ENA */ |
2229 | |
2230 | /* |
2231 | * R100 (0x64) - Headphone Mixer (1) |
2232 | */ |
2233 | #define WM8962_HPMIXL_TO_HPOUTL_PGA 0x0080 /* HPMIXL_TO_HPOUTL_PGA */ |
2234 | #define WM8962_HPMIXL_TO_HPOUTL_PGA_MASK 0x0080 /* HPMIXL_TO_HPOUTL_PGA */ |
2235 | #define WM8962_HPMIXL_TO_HPOUTL_PGA_SHIFT 7 /* HPMIXL_TO_HPOUTL_PGA */ |
2236 | #define WM8962_HPMIXL_TO_HPOUTL_PGA_WIDTH 1 /* HPMIXL_TO_HPOUTL_PGA */ |
2237 | #define WM8962_DACL_TO_HPMIXL 0x0020 /* DACL_TO_HPMIXL */ |
2238 | #define WM8962_DACL_TO_HPMIXL_MASK 0x0020 /* DACL_TO_HPMIXL */ |
2239 | #define WM8962_DACL_TO_HPMIXL_SHIFT 5 /* DACL_TO_HPMIXL */ |
2240 | #define WM8962_DACL_TO_HPMIXL_WIDTH 1 /* DACL_TO_HPMIXL */ |
2241 | #define WM8962_DACR_TO_HPMIXL 0x0010 /* DACR_TO_HPMIXL */ |
2242 | #define WM8962_DACR_TO_HPMIXL_MASK 0x0010 /* DACR_TO_HPMIXL */ |
2243 | #define WM8962_DACR_TO_HPMIXL_SHIFT 4 /* DACR_TO_HPMIXL */ |
2244 | #define WM8962_DACR_TO_HPMIXL_WIDTH 1 /* DACR_TO_HPMIXL */ |
2245 | #define WM8962_MIXINL_TO_HPMIXL 0x0008 /* MIXINL_TO_HPMIXL */ |
2246 | #define WM8962_MIXINL_TO_HPMIXL_MASK 0x0008 /* MIXINL_TO_HPMIXL */ |
2247 | #define WM8962_MIXINL_TO_HPMIXL_SHIFT 3 /* MIXINL_TO_HPMIXL */ |
2248 | #define WM8962_MIXINL_TO_HPMIXL_WIDTH 1 /* MIXINL_TO_HPMIXL */ |
2249 | #define WM8962_MIXINR_TO_HPMIXL 0x0004 /* MIXINR_TO_HPMIXL */ |
2250 | #define WM8962_MIXINR_TO_HPMIXL_MASK 0x0004 /* MIXINR_TO_HPMIXL */ |
2251 | #define WM8962_MIXINR_TO_HPMIXL_SHIFT 2 /* MIXINR_TO_HPMIXL */ |
2252 | #define WM8962_MIXINR_TO_HPMIXL_WIDTH 1 /* MIXINR_TO_HPMIXL */ |
2253 | #define WM8962_IN4L_TO_HPMIXL 0x0002 /* IN4L_TO_HPMIXL */ |
2254 | #define WM8962_IN4L_TO_HPMIXL_MASK 0x0002 /* IN4L_TO_HPMIXL */ |
2255 | #define WM8962_IN4L_TO_HPMIXL_SHIFT 1 /* IN4L_TO_HPMIXL */ |
2256 | #define WM8962_IN4L_TO_HPMIXL_WIDTH 1 /* IN4L_TO_HPMIXL */ |
2257 | #define WM8962_IN4R_TO_HPMIXL 0x0001 /* IN4R_TO_HPMIXL */ |
2258 | #define WM8962_IN4R_TO_HPMIXL_MASK 0x0001 /* IN4R_TO_HPMIXL */ |
2259 | #define WM8962_IN4R_TO_HPMIXL_SHIFT 0 /* IN4R_TO_HPMIXL */ |
2260 | #define WM8962_IN4R_TO_HPMIXL_WIDTH 1 /* IN4R_TO_HPMIXL */ |
2261 | |
2262 | /* |
2263 | * R101 (0x65) - Headphone Mixer (2) |
2264 | */ |
2265 | #define WM8962_HPMIXR_TO_HPOUTR_PGA 0x0080 /* HPMIXR_TO_HPOUTR_PGA */ |
2266 | #define WM8962_HPMIXR_TO_HPOUTR_PGA_MASK 0x0080 /* HPMIXR_TO_HPOUTR_PGA */ |
2267 | #define WM8962_HPMIXR_TO_HPOUTR_PGA_SHIFT 7 /* HPMIXR_TO_HPOUTR_PGA */ |
2268 | #define WM8962_HPMIXR_TO_HPOUTR_PGA_WIDTH 1 /* HPMIXR_TO_HPOUTR_PGA */ |
2269 | #define WM8962_DACL_TO_HPMIXR 0x0020 /* DACL_TO_HPMIXR */ |
2270 | #define WM8962_DACL_TO_HPMIXR_MASK 0x0020 /* DACL_TO_HPMIXR */ |
2271 | #define WM8962_DACL_TO_HPMIXR_SHIFT 5 /* DACL_TO_HPMIXR */ |
2272 | #define WM8962_DACL_TO_HPMIXR_WIDTH 1 /* DACL_TO_HPMIXR */ |
2273 | #define WM8962_DACR_TO_HPMIXR 0x0010 /* DACR_TO_HPMIXR */ |
2274 | #define WM8962_DACR_TO_HPMIXR_MASK 0x0010 /* DACR_TO_HPMIXR */ |
2275 | #define WM8962_DACR_TO_HPMIXR_SHIFT 4 /* DACR_TO_HPMIXR */ |
2276 | #define WM8962_DACR_TO_HPMIXR_WIDTH 1 /* DACR_TO_HPMIXR */ |
2277 | #define WM8962_MIXINL_TO_HPMIXR 0x0008 /* MIXINL_TO_HPMIXR */ |
2278 | #define WM8962_MIXINL_TO_HPMIXR_MASK 0x0008 /* MIXINL_TO_HPMIXR */ |
2279 | #define WM8962_MIXINL_TO_HPMIXR_SHIFT 3 /* MIXINL_TO_HPMIXR */ |
2280 | #define WM8962_MIXINL_TO_HPMIXR_WIDTH 1 /* MIXINL_TO_HPMIXR */ |
2281 | #define WM8962_MIXINR_TO_HPMIXR 0x0004 /* MIXINR_TO_HPMIXR */ |
2282 | #define WM8962_MIXINR_TO_HPMIXR_MASK 0x0004 /* MIXINR_TO_HPMIXR */ |
2283 | #define WM8962_MIXINR_TO_HPMIXR_SHIFT 2 /* MIXINR_TO_HPMIXR */ |
2284 | #define WM8962_MIXINR_TO_HPMIXR_WIDTH 1 /* MIXINR_TO_HPMIXR */ |
2285 | #define WM8962_IN4L_TO_HPMIXR 0x0002 /* IN4L_TO_HPMIXR */ |
2286 | #define WM8962_IN4L_TO_HPMIXR_MASK 0x0002 /* IN4L_TO_HPMIXR */ |
2287 | #define WM8962_IN4L_TO_HPMIXR_SHIFT 1 /* IN4L_TO_HPMIXR */ |
2288 | #define WM8962_IN4L_TO_HPMIXR_WIDTH 1 /* IN4L_TO_HPMIXR */ |
2289 | #define WM8962_IN4R_TO_HPMIXR 0x0001 /* IN4R_TO_HPMIXR */ |
2290 | #define WM8962_IN4R_TO_HPMIXR_MASK 0x0001 /* IN4R_TO_HPMIXR */ |
2291 | #define WM8962_IN4R_TO_HPMIXR_SHIFT 0 /* IN4R_TO_HPMIXR */ |
2292 | #define WM8962_IN4R_TO_HPMIXR_WIDTH 1 /* IN4R_TO_HPMIXR */ |
2293 | |
2294 | /* |
2295 | * R102 (0x66) - Headphone Mixer (3) |
2296 | */ |
2297 | #define WM8962_HPMIXL_MUTE 0x0100 /* HPMIXL_MUTE */ |
2298 | #define WM8962_HPMIXL_MUTE_MASK 0x0100 /* HPMIXL_MUTE */ |
2299 | #define WM8962_HPMIXL_MUTE_SHIFT 8 /* HPMIXL_MUTE */ |
2300 | #define WM8962_HPMIXL_MUTE_WIDTH 1 /* HPMIXL_MUTE */ |
2301 | #define WM8962_MIXINL_HPMIXL_VOL 0x0080 /* MIXINL_HPMIXL_VOL */ |
2302 | #define WM8962_MIXINL_HPMIXL_VOL_MASK 0x0080 /* MIXINL_HPMIXL_VOL */ |
2303 | #define WM8962_MIXINL_HPMIXL_VOL_SHIFT 7 /* MIXINL_HPMIXL_VOL */ |
2304 | #define WM8962_MIXINL_HPMIXL_VOL_WIDTH 1 /* MIXINL_HPMIXL_VOL */ |
2305 | #define WM8962_MIXINR_HPMIXL_VOL 0x0040 /* MIXINR_HPMIXL_VOL */ |
2306 | #define WM8962_MIXINR_HPMIXL_VOL_MASK 0x0040 /* MIXINR_HPMIXL_VOL */ |
2307 | #define WM8962_MIXINR_HPMIXL_VOL_SHIFT 6 /* MIXINR_HPMIXL_VOL */ |
2308 | #define WM8962_MIXINR_HPMIXL_VOL_WIDTH 1 /* MIXINR_HPMIXL_VOL */ |
2309 | #define WM8962_IN4L_HPMIXL_VOL_MASK 0x0038 /* IN4L_HPMIXL_VOL - [5:3] */ |
2310 | #define WM8962_IN4L_HPMIXL_VOL_SHIFT 3 /* IN4L_HPMIXL_VOL - [5:3] */ |
2311 | #define WM8962_IN4L_HPMIXL_VOL_WIDTH 3 /* IN4L_HPMIXL_VOL - [5:3] */ |
2312 | #define WM8962_IN4R_HPMIXL_VOL_MASK 0x0007 /* IN4R_HPMIXL_VOL - [2:0] */ |
2313 | #define WM8962_IN4R_HPMIXL_VOL_SHIFT 0 /* IN4R_HPMIXL_VOL - [2:0] */ |
2314 | #define WM8962_IN4R_HPMIXL_VOL_WIDTH 3 /* IN4R_HPMIXL_VOL - [2:0] */ |
2315 | |
2316 | /* |
2317 | * R103 (0x67) - Headphone Mixer (4) |
2318 | */ |
2319 | #define WM8962_HPMIXR_MUTE 0x0100 /* HPMIXR_MUTE */ |
2320 | #define WM8962_HPMIXR_MUTE_MASK 0x0100 /* HPMIXR_MUTE */ |
2321 | #define WM8962_HPMIXR_MUTE_SHIFT 8 /* HPMIXR_MUTE */ |
2322 | #define WM8962_HPMIXR_MUTE_WIDTH 1 /* HPMIXR_MUTE */ |
2323 | #define WM8962_MIXINL_HPMIXR_VOL 0x0080 /* MIXINL_HPMIXR_VOL */ |
2324 | #define WM8962_MIXINL_HPMIXR_VOL_MASK 0x0080 /* MIXINL_HPMIXR_VOL */ |
2325 | #define WM8962_MIXINL_HPMIXR_VOL_SHIFT 7 /* MIXINL_HPMIXR_VOL */ |
2326 | #define WM8962_MIXINL_HPMIXR_VOL_WIDTH 1 /* MIXINL_HPMIXR_VOL */ |
2327 | #define WM8962_MIXINR_HPMIXR_VOL 0x0040 /* MIXINR_HPMIXR_VOL */ |
2328 | #define WM8962_MIXINR_HPMIXR_VOL_MASK 0x0040 /* MIXINR_HPMIXR_VOL */ |
2329 | #define WM8962_MIXINR_HPMIXR_VOL_SHIFT 6 /* MIXINR_HPMIXR_VOL */ |
2330 | #define WM8962_MIXINR_HPMIXR_VOL_WIDTH 1 /* MIXINR_HPMIXR_VOL */ |
2331 | #define WM8962_IN4L_HPMIXR_VOL_MASK 0x0038 /* IN4L_HPMIXR_VOL - [5:3] */ |
2332 | #define WM8962_IN4L_HPMIXR_VOL_SHIFT 3 /* IN4L_HPMIXR_VOL - [5:3] */ |
2333 | #define WM8962_IN4L_HPMIXR_VOL_WIDTH 3 /* IN4L_HPMIXR_VOL - [5:3] */ |
2334 | #define WM8962_IN4R_HPMIXR_VOL_MASK 0x0007 /* IN4R_HPMIXR_VOL - [2:0] */ |
2335 | #define WM8962_IN4R_HPMIXR_VOL_SHIFT 0 /* IN4R_HPMIXR_VOL - [2:0] */ |
2336 | #define WM8962_IN4R_HPMIXR_VOL_WIDTH 3 /* IN4R_HPMIXR_VOL - [2:0] */ |
2337 | |
2338 | /* |
2339 | * R105 (0x69) - Speaker Mixer (1) |
2340 | */ |
2341 | #define WM8962_SPKMIXL_TO_SPKOUTL_PGA 0x0080 /* SPKMIXL_TO_SPKOUTL_PGA */ |
2342 | #define WM8962_SPKMIXL_TO_SPKOUTL_PGA_MASK 0x0080 /* SPKMIXL_TO_SPKOUTL_PGA */ |
2343 | #define WM8962_SPKMIXL_TO_SPKOUTL_PGA_SHIFT 7 /* SPKMIXL_TO_SPKOUTL_PGA */ |
2344 | #define WM8962_SPKMIXL_TO_SPKOUTL_PGA_WIDTH 1 /* SPKMIXL_TO_SPKOUTL_PGA */ |
2345 | #define WM8962_DACL_TO_SPKMIXL 0x0020 /* DACL_TO_SPKMIXL */ |
2346 | #define WM8962_DACL_TO_SPKMIXL_MASK 0x0020 /* DACL_TO_SPKMIXL */ |
2347 | #define WM8962_DACL_TO_SPKMIXL_SHIFT 5 /* DACL_TO_SPKMIXL */ |
2348 | #define WM8962_DACL_TO_SPKMIXL_WIDTH 1 /* DACL_TO_SPKMIXL */ |
2349 | #define WM8962_DACR_TO_SPKMIXL 0x0010 /* DACR_TO_SPKMIXL */ |
2350 | #define WM8962_DACR_TO_SPKMIXL_MASK 0x0010 /* DACR_TO_SPKMIXL */ |
2351 | #define WM8962_DACR_TO_SPKMIXL_SHIFT 4 /* DACR_TO_SPKMIXL */ |
2352 | #define WM8962_DACR_TO_SPKMIXL_WIDTH 1 /* DACR_TO_SPKMIXL */ |
2353 | #define WM8962_MIXINL_TO_SPKMIXL 0x0008 /* MIXINL_TO_SPKMIXL */ |
2354 | #define WM8962_MIXINL_TO_SPKMIXL_MASK 0x0008 /* MIXINL_TO_SPKMIXL */ |
2355 | #define WM8962_MIXINL_TO_SPKMIXL_SHIFT 3 /* MIXINL_TO_SPKMIXL */ |
2356 | #define WM8962_MIXINL_TO_SPKMIXL_WIDTH 1 /* MIXINL_TO_SPKMIXL */ |
2357 | #define WM8962_MIXINR_TO_SPKMIXL 0x0004 /* MIXINR_TO_SPKMIXL */ |
2358 | #define WM8962_MIXINR_TO_SPKMIXL_MASK 0x0004 /* MIXINR_TO_SPKMIXL */ |
2359 | #define WM8962_MIXINR_TO_SPKMIXL_SHIFT 2 /* MIXINR_TO_SPKMIXL */ |
2360 | #define WM8962_MIXINR_TO_SPKMIXL_WIDTH 1 /* MIXINR_TO_SPKMIXL */ |
2361 | #define WM8962_IN4L_TO_SPKMIXL 0x0002 /* IN4L_TO_SPKMIXL */ |
2362 | #define WM8962_IN4L_TO_SPKMIXL_MASK 0x0002 /* IN4L_TO_SPKMIXL */ |
2363 | #define WM8962_IN4L_TO_SPKMIXL_SHIFT 1 /* IN4L_TO_SPKMIXL */ |
2364 | #define WM8962_IN4L_TO_SPKMIXL_WIDTH 1 /* IN4L_TO_SPKMIXL */ |
2365 | #define WM8962_IN4R_TO_SPKMIXL 0x0001 /* IN4R_TO_SPKMIXL */ |
2366 | #define WM8962_IN4R_TO_SPKMIXL_MASK 0x0001 /* IN4R_TO_SPKMIXL */ |
2367 | #define WM8962_IN4R_TO_SPKMIXL_SHIFT 0 /* IN4R_TO_SPKMIXL */ |
2368 | #define WM8962_IN4R_TO_SPKMIXL_WIDTH 1 /* IN4R_TO_SPKMIXL */ |
2369 | |
2370 | /* |
2371 | * R106 (0x6A) - Speaker Mixer (2) |
2372 | */ |
2373 | #define WM8962_SPKMIXR_TO_SPKOUTR_PGA 0x0080 /* SPKMIXR_TO_SPKOUTR_PGA */ |
2374 | #define WM8962_SPKMIXR_TO_SPKOUTR_PGA_MASK 0x0080 /* SPKMIXR_TO_SPKOUTR_PGA */ |
2375 | #define WM8962_SPKMIXR_TO_SPKOUTR_PGA_SHIFT 7 /* SPKMIXR_TO_SPKOUTR_PGA */ |
2376 | #define WM8962_SPKMIXR_TO_SPKOUTR_PGA_WIDTH 1 /* SPKMIXR_TO_SPKOUTR_PGA */ |
2377 | #define WM8962_DACL_TO_SPKMIXR 0x0020 /* DACL_TO_SPKMIXR */ |
2378 | #define WM8962_DACL_TO_SPKMIXR_MASK 0x0020 /* DACL_TO_SPKMIXR */ |
2379 | #define WM8962_DACL_TO_SPKMIXR_SHIFT 5 /* DACL_TO_SPKMIXR */ |
2380 | #define WM8962_DACL_TO_SPKMIXR_WIDTH 1 /* DACL_TO_SPKMIXR */ |
2381 | #define WM8962_DACR_TO_SPKMIXR 0x0010 /* DACR_TO_SPKMIXR */ |
2382 | #define WM8962_DACR_TO_SPKMIXR_MASK 0x0010 /* DACR_TO_SPKMIXR */ |
2383 | #define WM8962_DACR_TO_SPKMIXR_SHIFT 4 /* DACR_TO_SPKMIXR */ |
2384 | #define WM8962_DACR_TO_SPKMIXR_WIDTH 1 /* DACR_TO_SPKMIXR */ |
2385 | #define WM8962_MIXINL_TO_SPKMIXR 0x0008 /* MIXINL_TO_SPKMIXR */ |
2386 | #define WM8962_MIXINL_TO_SPKMIXR_MASK 0x0008 /* MIXINL_TO_SPKMIXR */ |
2387 | #define WM8962_MIXINL_TO_SPKMIXR_SHIFT 3 /* MIXINL_TO_SPKMIXR */ |
2388 | #define WM8962_MIXINL_TO_SPKMIXR_WIDTH 1 /* MIXINL_TO_SPKMIXR */ |
2389 | #define WM8962_MIXINR_TO_SPKMIXR 0x0004 /* MIXINR_TO_SPKMIXR */ |
2390 | #define WM8962_MIXINR_TO_SPKMIXR_MASK 0x0004 /* MIXINR_TO_SPKMIXR */ |
2391 | #define WM8962_MIXINR_TO_SPKMIXR_SHIFT 2 /* MIXINR_TO_SPKMIXR */ |
2392 | #define WM8962_MIXINR_TO_SPKMIXR_WIDTH 1 /* MIXINR_TO_SPKMIXR */ |
2393 | #define WM8962_IN4L_TO_SPKMIXR 0x0002 /* IN4L_TO_SPKMIXR */ |
2394 | #define WM8962_IN4L_TO_SPKMIXR_MASK 0x0002 /* IN4L_TO_SPKMIXR */ |
2395 | #define WM8962_IN4L_TO_SPKMIXR_SHIFT 1 /* IN4L_TO_SPKMIXR */ |
2396 | #define WM8962_IN4L_TO_SPKMIXR_WIDTH 1 /* IN4L_TO_SPKMIXR */ |
2397 | #define WM8962_IN4R_TO_SPKMIXR 0x0001 /* IN4R_TO_SPKMIXR */ |
2398 | #define WM8962_IN4R_TO_SPKMIXR_MASK 0x0001 /* IN4R_TO_SPKMIXR */ |
2399 | #define WM8962_IN4R_TO_SPKMIXR_SHIFT 0 /* IN4R_TO_SPKMIXR */ |
2400 | #define WM8962_IN4R_TO_SPKMIXR_WIDTH 1 /* IN4R_TO_SPKMIXR */ |
2401 | |
2402 | /* |
2403 | * R107 (0x6B) - Speaker Mixer (3) |
2404 | */ |
2405 | #define WM8962_SPKMIXL_MUTE 0x0100 /* SPKMIXL_MUTE */ |
2406 | #define WM8962_SPKMIXL_MUTE_MASK 0x0100 /* SPKMIXL_MUTE */ |
2407 | #define WM8962_SPKMIXL_MUTE_SHIFT 8 /* SPKMIXL_MUTE */ |
2408 | #define WM8962_SPKMIXL_MUTE_WIDTH 1 /* SPKMIXL_MUTE */ |
2409 | #define WM8962_MIXINL_SPKMIXL_VOL 0x0080 /* MIXINL_SPKMIXL_VOL */ |
2410 | #define WM8962_MIXINL_SPKMIXL_VOL_MASK 0x0080 /* MIXINL_SPKMIXL_VOL */ |
2411 | #define WM8962_MIXINL_SPKMIXL_VOL_SHIFT 7 /* MIXINL_SPKMIXL_VOL */ |
2412 | #define WM8962_MIXINL_SPKMIXL_VOL_WIDTH 1 /* MIXINL_SPKMIXL_VOL */ |
2413 | #define WM8962_MIXINR_SPKMIXL_VOL 0x0040 /* MIXINR_SPKMIXL_VOL */ |
2414 | #define WM8962_MIXINR_SPKMIXL_VOL_MASK 0x0040 /* MIXINR_SPKMIXL_VOL */ |
2415 | #define WM8962_MIXINR_SPKMIXL_VOL_SHIFT 6 /* MIXINR_SPKMIXL_VOL */ |
2416 | #define WM8962_MIXINR_SPKMIXL_VOL_WIDTH 1 /* MIXINR_SPKMIXL_VOL */ |
2417 | #define WM8962_IN4L_SPKMIXL_VOL_MASK 0x0038 /* IN4L_SPKMIXL_VOL - [5:3] */ |
2418 | #define WM8962_IN4L_SPKMIXL_VOL_SHIFT 3 /* IN4L_SPKMIXL_VOL - [5:3] */ |
2419 | #define WM8962_IN4L_SPKMIXL_VOL_WIDTH 3 /* IN4L_SPKMIXL_VOL - [5:3] */ |
2420 | #define WM8962_IN4R_SPKMIXL_VOL_MASK 0x0007 /* IN4R_SPKMIXL_VOL - [2:0] */ |
2421 | #define WM8962_IN4R_SPKMIXL_VOL_SHIFT 0 /* IN4R_SPKMIXL_VOL - [2:0] */ |
2422 | #define WM8962_IN4R_SPKMIXL_VOL_WIDTH 3 /* IN4R_SPKMIXL_VOL - [2:0] */ |
2423 | |
2424 | /* |
2425 | * R108 (0x6C) - Speaker Mixer (4) |
2426 | */ |
2427 | #define WM8962_SPKMIXR_MUTE 0x0100 /* SPKMIXR_MUTE */ |
2428 | #define WM8962_SPKMIXR_MUTE_MASK 0x0100 /* SPKMIXR_MUTE */ |
2429 | #define WM8962_SPKMIXR_MUTE_SHIFT 8 /* SPKMIXR_MUTE */ |
2430 | #define WM8962_SPKMIXR_MUTE_WIDTH 1 /* SPKMIXR_MUTE */ |
2431 | #define WM8962_MIXINL_SPKMIXR_VOL 0x0080 /* MIXINL_SPKMIXR_VOL */ |
2432 | #define WM8962_MIXINL_SPKMIXR_VOL_MASK 0x0080 /* MIXINL_SPKMIXR_VOL */ |
2433 | #define WM8962_MIXINL_SPKMIXR_VOL_SHIFT 7 /* MIXINL_SPKMIXR_VOL */ |
2434 | #define WM8962_MIXINL_SPKMIXR_VOL_WIDTH 1 /* MIXINL_SPKMIXR_VOL */ |
2435 | #define WM8962_MIXINR_SPKMIXR_VOL 0x0040 /* MIXINR_SPKMIXR_VOL */ |
2436 | #define WM8962_MIXINR_SPKMIXR_VOL_MASK 0x0040 /* MIXINR_SPKMIXR_VOL */ |
2437 | #define WM8962_MIXINR_SPKMIXR_VOL_SHIFT 6 /* MIXINR_SPKMIXR_VOL */ |
2438 | #define WM8962_MIXINR_SPKMIXR_VOL_WIDTH 1 /* MIXINR_SPKMIXR_VOL */ |
2439 | #define WM8962_IN4L_SPKMIXR_VOL_MASK 0x0038 /* IN4L_SPKMIXR_VOL - [5:3] */ |
2440 | #define WM8962_IN4L_SPKMIXR_VOL_SHIFT 3 /* IN4L_SPKMIXR_VOL - [5:3] */ |
2441 | #define WM8962_IN4L_SPKMIXR_VOL_WIDTH 3 /* IN4L_SPKMIXR_VOL - [5:3] */ |
2442 | #define WM8962_IN4R_SPKMIXR_VOL_MASK 0x0007 /* IN4R_SPKMIXR_VOL - [2:0] */ |
2443 | #define WM8962_IN4R_SPKMIXR_VOL_SHIFT 0 /* IN4R_SPKMIXR_VOL - [2:0] */ |
2444 | #define WM8962_IN4R_SPKMIXR_VOL_WIDTH 3 /* IN4R_SPKMIXR_VOL - [2:0] */ |
2445 | |
2446 | /* |
2447 | * R109 (0x6D) - Speaker Mixer (5) |
2448 | */ |
2449 | #define WM8962_DACL_SPKMIXL_VOL 0x0080 /* DACL_SPKMIXL_VOL */ |
2450 | #define WM8962_DACL_SPKMIXL_VOL_MASK 0x0080 /* DACL_SPKMIXL_VOL */ |
2451 | #define WM8962_DACL_SPKMIXL_VOL_SHIFT 7 /* DACL_SPKMIXL_VOL */ |
2452 | #define WM8962_DACL_SPKMIXL_VOL_WIDTH 1 /* DACL_SPKMIXL_VOL */ |
2453 | #define WM8962_DACR_SPKMIXL_VOL 0x0040 /* DACR_SPKMIXL_VOL */ |
2454 | #define WM8962_DACR_SPKMIXL_VOL_MASK 0x0040 /* DACR_SPKMIXL_VOL */ |
2455 | #define WM8962_DACR_SPKMIXL_VOL_SHIFT 6 /* DACR_SPKMIXL_VOL */ |
2456 | #define WM8962_DACR_SPKMIXL_VOL_WIDTH 1 /* DACR_SPKMIXL_VOL */ |
2457 | #define WM8962_DACL_SPKMIXR_VOL 0x0020 /* DACL_SPKMIXR_VOL */ |
2458 | #define WM8962_DACL_SPKMIXR_VOL_MASK 0x0020 /* DACL_SPKMIXR_VOL */ |
2459 | #define WM8962_DACL_SPKMIXR_VOL_SHIFT 5 /* DACL_SPKMIXR_VOL */ |
2460 | #define WM8962_DACL_SPKMIXR_VOL_WIDTH 1 /* DACL_SPKMIXR_VOL */ |
2461 | #define WM8962_DACR_SPKMIXR_VOL 0x0010 /* DACR_SPKMIXR_VOL */ |
2462 | #define WM8962_DACR_SPKMIXR_VOL_MASK 0x0010 /* DACR_SPKMIXR_VOL */ |
2463 | #define WM8962_DACR_SPKMIXR_VOL_SHIFT 4 /* DACR_SPKMIXR_VOL */ |
2464 | #define WM8962_DACR_SPKMIXR_VOL_WIDTH 1 /* DACR_SPKMIXR_VOL */ |
2465 | |
2466 | /* |
2467 | * R110 (0x6E) - Beep Generator (1) |
2468 | */ |
2469 | #define WM8962_BEEP_GAIN_MASK 0x00F0 /* BEEP_GAIN - [7:4] */ |
2470 | #define WM8962_BEEP_GAIN_SHIFT 4 /* BEEP_GAIN - [7:4] */ |
2471 | #define WM8962_BEEP_GAIN_WIDTH 4 /* BEEP_GAIN - [7:4] */ |
2472 | #define WM8962_BEEP_RATE_MASK 0x0006 /* BEEP_RATE - [2:1] */ |
2473 | #define WM8962_BEEP_RATE_SHIFT 1 /* BEEP_RATE - [2:1] */ |
2474 | #define WM8962_BEEP_RATE_WIDTH 2 /* BEEP_RATE - [2:1] */ |
2475 | #define WM8962_BEEP_ENA 0x0001 /* BEEP_ENA */ |
2476 | #define WM8962_BEEP_ENA_MASK 0x0001 /* BEEP_ENA */ |
2477 | #define WM8962_BEEP_ENA_SHIFT 0 /* BEEP_ENA */ |
2478 | #define WM8962_BEEP_ENA_WIDTH 1 /* BEEP_ENA */ |
2479 | |
2480 | /* |
2481 | * R115 (0x73) - Oscillator Trim (3) |
2482 | */ |
2483 | #define WM8962_OSC_TRIM_XTI_MASK 0x001F /* OSC_TRIM_XTI - [4:0] */ |
2484 | #define WM8962_OSC_TRIM_XTI_SHIFT 0 /* OSC_TRIM_XTI - [4:0] */ |
2485 | #define WM8962_OSC_TRIM_XTI_WIDTH 5 /* OSC_TRIM_XTI - [4:0] */ |
2486 | |
2487 | /* |
2488 | * R116 (0x74) - Oscillator Trim (4) |
2489 | */ |
2490 | #define WM8962_OSC_TRIM_XTO_MASK 0x001F /* OSC_TRIM_XTO - [4:0] */ |
2491 | #define WM8962_OSC_TRIM_XTO_SHIFT 0 /* OSC_TRIM_XTO - [4:0] */ |
2492 | #define WM8962_OSC_TRIM_XTO_WIDTH 5 /* OSC_TRIM_XTO - [4:0] */ |
2493 | |
2494 | /* |
2495 | * R119 (0x77) - Oscillator Trim (7) |
2496 | */ |
2497 | #define WM8962_XTO_CAP_SEL_MASK 0x00F0 /* XTO_CAP_SEL - [7:4] */ |
2498 | #define WM8962_XTO_CAP_SEL_SHIFT 4 /* XTO_CAP_SEL - [7:4] */ |
2499 | #define WM8962_XTO_CAP_SEL_WIDTH 4 /* XTO_CAP_SEL - [7:4] */ |
2500 | #define WM8962_XTI_CAP_SEL_MASK 0x000F /* XTI_CAP_SEL - [3:0] */ |
2501 | #define WM8962_XTI_CAP_SEL_SHIFT 0 /* XTI_CAP_SEL - [3:0] */ |
2502 | #define WM8962_XTI_CAP_SEL_WIDTH 4 /* XTI_CAP_SEL - [3:0] */ |
2503 | |
2504 | /* |
2505 | * R124 (0x7C) - Analogue Clocking1 |
2506 | */ |
2507 | #define WM8962_CLKOUT2_SEL_MASK 0x0060 /* CLKOUT2_SEL - [6:5] */ |
2508 | #define WM8962_CLKOUT2_SEL_SHIFT 5 /* CLKOUT2_SEL - [6:5] */ |
2509 | #define WM8962_CLKOUT2_SEL_WIDTH 2 /* CLKOUT2_SEL - [6:5] */ |
2510 | #define WM8962_CLKOUT3_SEL_MASK 0x0018 /* CLKOUT3_SEL - [4:3] */ |
2511 | #define WM8962_CLKOUT3_SEL_SHIFT 3 /* CLKOUT3_SEL - [4:3] */ |
2512 | #define WM8962_CLKOUT3_SEL_WIDTH 2 /* CLKOUT3_SEL - [4:3] */ |
2513 | #define WM8962_CLKOUT5_SEL 0x0001 /* CLKOUT5_SEL */ |
2514 | #define WM8962_CLKOUT5_SEL_MASK 0x0001 /* CLKOUT5_SEL */ |
2515 | #define WM8962_CLKOUT5_SEL_SHIFT 0 /* CLKOUT5_SEL */ |
2516 | #define WM8962_CLKOUT5_SEL_WIDTH 1 /* CLKOUT5_SEL */ |
2517 | |
2518 | /* |
2519 | * R125 (0x7D) - Analogue Clocking2 |
2520 | */ |
2521 | #define WM8962_PLL2_OUTDIV 0x0080 /* PLL2_OUTDIV */ |
2522 | #define WM8962_PLL2_OUTDIV_MASK 0x0080 /* PLL2_OUTDIV */ |
2523 | #define WM8962_PLL2_OUTDIV_SHIFT 7 /* PLL2_OUTDIV */ |
2524 | #define WM8962_PLL2_OUTDIV_WIDTH 1 /* PLL2_OUTDIV */ |
2525 | #define WM8962_PLL3_OUTDIV 0x0040 /* PLL3_OUTDIV */ |
2526 | #define WM8962_PLL3_OUTDIV_MASK 0x0040 /* PLL3_OUTDIV */ |
2527 | #define WM8962_PLL3_OUTDIV_SHIFT 6 /* PLL3_OUTDIV */ |
2528 | #define WM8962_PLL3_OUTDIV_WIDTH 1 /* PLL3_OUTDIV */ |
2529 | #define WM8962_PLL_SYSCLK_DIV_MASK 0x0018 /* PLL_SYSCLK_DIV - [4:3] */ |
2530 | #define WM8962_PLL_SYSCLK_DIV_SHIFT 3 /* PLL_SYSCLK_DIV - [4:3] */ |
2531 | #define WM8962_PLL_SYSCLK_DIV_WIDTH 2 /* PLL_SYSCLK_DIV - [4:3] */ |
2532 | #define WM8962_CLKOUT3_DIV 0x0004 /* CLKOUT3_DIV */ |
2533 | #define WM8962_CLKOUT3_DIV_MASK 0x0004 /* CLKOUT3_DIV */ |
2534 | #define WM8962_CLKOUT3_DIV_SHIFT 2 /* CLKOUT3_DIV */ |
2535 | #define WM8962_CLKOUT3_DIV_WIDTH 1 /* CLKOUT3_DIV */ |
2536 | #define WM8962_CLKOUT2_DIV 0x0002 /* CLKOUT2_DIV */ |
2537 | #define WM8962_CLKOUT2_DIV_MASK 0x0002 /* CLKOUT2_DIV */ |
2538 | #define WM8962_CLKOUT2_DIV_SHIFT 1 /* CLKOUT2_DIV */ |
2539 | #define WM8962_CLKOUT2_DIV_WIDTH 1 /* CLKOUT2_DIV */ |
2540 | #define WM8962_CLKOUT5_DIV 0x0001 /* CLKOUT5_DIV */ |
2541 | #define WM8962_CLKOUT5_DIV_MASK 0x0001 /* CLKOUT5_DIV */ |
2542 | #define WM8962_CLKOUT5_DIV_SHIFT 0 /* CLKOUT5_DIV */ |
2543 | #define WM8962_CLKOUT5_DIV_WIDTH 1 /* CLKOUT5_DIV */ |
2544 | |
2545 | /* |
2546 | * R126 (0x7E) - Analogue Clocking3 |
2547 | */ |
2548 | #define WM8962_CLKOUT2_OE 0x0008 /* CLKOUT2_OE */ |
2549 | #define WM8962_CLKOUT2_OE_MASK 0x0008 /* CLKOUT2_OE */ |
2550 | #define WM8962_CLKOUT2_OE_SHIFT 3 /* CLKOUT2_OE */ |
2551 | #define WM8962_CLKOUT2_OE_WIDTH 1 /* CLKOUT2_OE */ |
2552 | #define WM8962_CLKOUT3_OE 0x0004 /* CLKOUT3_OE */ |
2553 | #define WM8962_CLKOUT3_OE_MASK 0x0004 /* CLKOUT3_OE */ |
2554 | #define WM8962_CLKOUT3_OE_SHIFT 2 /* CLKOUT3_OE */ |
2555 | #define WM8962_CLKOUT3_OE_WIDTH 1 /* CLKOUT3_OE */ |
2556 | #define WM8962_CLKOUT5_OE 0x0001 /* CLKOUT5_OE */ |
2557 | #define WM8962_CLKOUT5_OE_MASK 0x0001 /* CLKOUT5_OE */ |
2558 | #define WM8962_CLKOUT5_OE_SHIFT 0 /* CLKOUT5_OE */ |
2559 | #define WM8962_CLKOUT5_OE_WIDTH 1 /* CLKOUT5_OE */ |
2560 | |
2561 | /* |
2562 | * R127 (0x7F) - PLL Software Reset |
2563 | */ |
2564 | #define WM8962_SW_RESET_PLL_MASK 0xFFFF /* SW_RESET_PLL - [15:0] */ |
2565 | #define WM8962_SW_RESET_PLL_SHIFT 0 /* SW_RESET_PLL - [15:0] */ |
2566 | #define WM8962_SW_RESET_PLL_WIDTH 16 /* SW_RESET_PLL - [15:0] */ |
2567 | |
2568 | /* |
2569 | * R129 (0x81) - PLL2 |
2570 | */ |
2571 | #define WM8962_OSC_ENA 0x0080 /* OSC_ENA */ |
2572 | #define WM8962_OSC_ENA_MASK 0x0080 /* OSC_ENA */ |
2573 | #define WM8962_OSC_ENA_SHIFT 7 /* OSC_ENA */ |
2574 | #define WM8962_OSC_ENA_WIDTH 1 /* OSC_ENA */ |
2575 | #define WM8962_PLL2_ENA 0x0020 /* PLL2_ENA */ |
2576 | #define WM8962_PLL2_ENA_MASK 0x0020 /* PLL2_ENA */ |
2577 | #define WM8962_PLL2_ENA_SHIFT 5 /* PLL2_ENA */ |
2578 | #define WM8962_PLL2_ENA_WIDTH 1 /* PLL2_ENA */ |
2579 | #define WM8962_PLL3_ENA 0x0010 /* PLL3_ENA */ |
2580 | #define WM8962_PLL3_ENA_MASK 0x0010 /* PLL3_ENA */ |
2581 | #define WM8962_PLL3_ENA_SHIFT 4 /* PLL3_ENA */ |
2582 | #define WM8962_PLL3_ENA_WIDTH 1 /* PLL3_ENA */ |
2583 | |
2584 | /* |
2585 | * R131 (0x83) - PLL 4 |
2586 | */ |
2587 | #define WM8962_PLL_CLK_SRC 0x0002 /* PLL_CLK_SRC */ |
2588 | #define WM8962_PLL_CLK_SRC_MASK 0x0002 /* PLL_CLK_SRC */ |
2589 | #define WM8962_PLL_CLK_SRC_SHIFT 1 /* PLL_CLK_SRC */ |
2590 | #define WM8962_PLL_CLK_SRC_WIDTH 1 /* PLL_CLK_SRC */ |
2591 | #define WM8962_FLL_TO_PLL3 0x0001 /* FLL_TO_PLL3 */ |
2592 | #define WM8962_FLL_TO_PLL3_MASK 0x0001 /* FLL_TO_PLL3 */ |
2593 | #define WM8962_FLL_TO_PLL3_SHIFT 0 /* FLL_TO_PLL3 */ |
2594 | #define WM8962_FLL_TO_PLL3_WIDTH 1 /* FLL_TO_PLL3 */ |
2595 | |
2596 | /* |
2597 | * R136 (0x88) - PLL 9 |
2598 | */ |
2599 | #define WM8962_PLL2_FRAC 0x0040 /* PLL2_FRAC */ |
2600 | #define WM8962_PLL2_FRAC_MASK 0x0040 /* PLL2_FRAC */ |
2601 | #define WM8962_PLL2_FRAC_SHIFT 6 /* PLL2_FRAC */ |
2602 | #define WM8962_PLL2_FRAC_WIDTH 1 /* PLL2_FRAC */ |
2603 | #define WM8962_PLL2_N_MASK 0x001F /* PLL2_N - [4:0] */ |
2604 | #define WM8962_PLL2_N_SHIFT 0 /* PLL2_N - [4:0] */ |
2605 | #define WM8962_PLL2_N_WIDTH 5 /* PLL2_N - [4:0] */ |
2606 | |
2607 | /* |
2608 | * R137 (0x89) - PLL 10 |
2609 | */ |
2610 | #define WM8962_PLL2_K_MASK 0x00FF /* PLL2_K - [7:0] */ |
2611 | #define WM8962_PLL2_K_SHIFT 0 /* PLL2_K - [7:0] */ |
2612 | #define WM8962_PLL2_K_WIDTH 8 /* PLL2_K - [7:0] */ |
2613 | |
2614 | /* |
2615 | * R138 (0x8A) - PLL 11 |
2616 | */ |
2617 | #define WM8962_PLL2_K_MASK 0x00FF /* PLL2_K - [7:0] */ |
2618 | #define WM8962_PLL2_K_SHIFT 0 /* PLL2_K - [7:0] */ |
2619 | #define WM8962_PLL2_K_WIDTH 8 /* PLL2_K - [7:0] */ |
2620 | |
2621 | /* |
2622 | * R139 (0x8B) - PLL 12 |
2623 | */ |
2624 | #define WM8962_PLL2_K_MASK 0x00FF /* PLL2_K - [7:0] */ |
2625 | #define WM8962_PLL2_K_SHIFT 0 /* PLL2_K - [7:0] */ |
2626 | #define WM8962_PLL2_K_WIDTH 8 /* PLL2_K - [7:0] */ |
2627 | |
2628 | /* |
2629 | * R140 (0x8C) - PLL 13 |
2630 | */ |
2631 | #define WM8962_PLL3_FRAC 0x0040 /* PLL3_FRAC */ |
2632 | #define WM8962_PLL3_FRAC_MASK 0x0040 /* PLL3_FRAC */ |
2633 | #define WM8962_PLL3_FRAC_SHIFT 6 /* PLL3_FRAC */ |
2634 | #define WM8962_PLL3_FRAC_WIDTH 1 /* PLL3_FRAC */ |
2635 | #define WM8962_PLL3_N_MASK 0x001F /* PLL3_N - [4:0] */ |
2636 | #define WM8962_PLL3_N_SHIFT 0 /* PLL3_N - [4:0] */ |
2637 | #define WM8962_PLL3_N_WIDTH 5 /* PLL3_N - [4:0] */ |
2638 | |
2639 | /* |
2640 | * R141 (0x8D) - PLL 14 |
2641 | */ |
2642 | #define WM8962_PLL3_K_MASK 0x00FF /* PLL3_K - [7:0] */ |
2643 | #define WM8962_PLL3_K_SHIFT 0 /* PLL3_K - [7:0] */ |
2644 | #define WM8962_PLL3_K_WIDTH 8 /* PLL3_K - [7:0] */ |
2645 | |
2646 | /* |
2647 | * R142 (0x8E) - PLL 15 |
2648 | */ |
2649 | #define WM8962_PLL3_K_MASK 0x00FF /* PLL3_K - [7:0] */ |
2650 | #define WM8962_PLL3_K_SHIFT 0 /* PLL3_K - [7:0] */ |
2651 | #define WM8962_PLL3_K_WIDTH 8 /* PLL3_K - [7:0] */ |
2652 | |
2653 | /* |
2654 | * R143 (0x8F) - PLL 16 |
2655 | */ |
2656 | #define WM8962_PLL3_K_MASK 0x00FF /* PLL3_K - [7:0] */ |
2657 | #define WM8962_PLL3_K_SHIFT 0 /* PLL3_K - [7:0] */ |
2658 | #define WM8962_PLL3_K_WIDTH 8 /* PLL3_K - [7:0] */ |
2659 | |
2660 | /* |
2661 | * R155 (0x9B) - FLL Control (1) |
2662 | */ |
2663 | #define WM8962_FLL_REFCLK_SRC_MASK 0x0060 /* FLL_REFCLK_SRC - [6:5] */ |
2664 | #define WM8962_FLL_REFCLK_SRC_SHIFT 5 /* FLL_REFCLK_SRC - [6:5] */ |
2665 | #define WM8962_FLL_REFCLK_SRC_WIDTH 2 /* FLL_REFCLK_SRC - [6:5] */ |
2666 | #define WM8962_FLL_FRAC 0x0004 /* FLL_FRAC */ |
2667 | #define WM8962_FLL_FRAC_MASK 0x0004 /* FLL_FRAC */ |
2668 | #define WM8962_FLL_FRAC_SHIFT 2 /* FLL_FRAC */ |
2669 | #define WM8962_FLL_FRAC_WIDTH 1 /* FLL_FRAC */ |
2670 | #define WM8962_FLL_OSC_ENA 0x0002 /* FLL_OSC_ENA */ |
2671 | #define WM8962_FLL_OSC_ENA_MASK 0x0002 /* FLL_OSC_ENA */ |
2672 | #define WM8962_FLL_OSC_ENA_SHIFT 1 /* FLL_OSC_ENA */ |
2673 | #define WM8962_FLL_OSC_ENA_WIDTH 1 /* FLL_OSC_ENA */ |
2674 | #define WM8962_FLL_ENA 0x0001 /* FLL_ENA */ |
2675 | #define WM8962_FLL_ENA_MASK 0x0001 /* FLL_ENA */ |
2676 | #define WM8962_FLL_ENA_SHIFT 0 /* FLL_ENA */ |
2677 | #define WM8962_FLL_ENA_WIDTH 1 /* FLL_ENA */ |
2678 | |
2679 | /* |
2680 | * R156 (0x9C) - FLL Control (2) |
2681 | */ |
2682 | #define WM8962_FLL_OUTDIV_MASK 0x01F8 /* FLL_OUTDIV - [8:3] */ |
2683 | #define WM8962_FLL_OUTDIV_SHIFT 3 /* FLL_OUTDIV - [8:3] */ |
2684 | #define WM8962_FLL_OUTDIV_WIDTH 6 /* FLL_OUTDIV - [8:3] */ |
2685 | #define WM8962_FLL_REFCLK_DIV_MASK 0x0003 /* FLL_REFCLK_DIV - [1:0] */ |
2686 | #define WM8962_FLL_REFCLK_DIV_SHIFT 0 /* FLL_REFCLK_DIV - [1:0] */ |
2687 | #define WM8962_FLL_REFCLK_DIV_WIDTH 2 /* FLL_REFCLK_DIV - [1:0] */ |
2688 | |
2689 | /* |
2690 | * R157 (0x9D) - FLL Control (3) |
2691 | */ |
2692 | #define WM8962_FLL_FRATIO_MASK 0x0007 /* FLL_FRATIO - [2:0] */ |
2693 | #define WM8962_FLL_FRATIO_SHIFT 0 /* FLL_FRATIO - [2:0] */ |
2694 | #define WM8962_FLL_FRATIO_WIDTH 3 /* FLL_FRATIO - [2:0] */ |
2695 | |
2696 | /* |
2697 | * R159 (0x9F) - FLL Control (5) |
2698 | */ |
2699 | #define WM8962_FLL_FRC_NCO_VAL_MASK 0x007E /* FLL_FRC_NCO_VAL - [6:1] */ |
2700 | #define WM8962_FLL_FRC_NCO_VAL_SHIFT 1 /* FLL_FRC_NCO_VAL - [6:1] */ |
2701 | #define WM8962_FLL_FRC_NCO_VAL_WIDTH 6 /* FLL_FRC_NCO_VAL - [6:1] */ |
2702 | #define WM8962_FLL_FRC_NCO 0x0001 /* FLL_FRC_NCO */ |
2703 | #define WM8962_FLL_FRC_NCO_MASK 0x0001 /* FLL_FRC_NCO */ |
2704 | #define WM8962_FLL_FRC_NCO_SHIFT 0 /* FLL_FRC_NCO */ |
2705 | #define WM8962_FLL_FRC_NCO_WIDTH 1 /* FLL_FRC_NCO */ |
2706 | |
2707 | /* |
2708 | * R160 (0xA0) - FLL Control (6) |
2709 | */ |
2710 | #define WM8962_FLL_THETA_MASK 0xFFFF /* FLL_THETA - [15:0] */ |
2711 | #define WM8962_FLL_THETA_SHIFT 0 /* FLL_THETA - [15:0] */ |
2712 | #define WM8962_FLL_THETA_WIDTH 16 /* FLL_THETA - [15:0] */ |
2713 | |
2714 | /* |
2715 | * R161 (0xA1) - FLL Control (7) |
2716 | */ |
2717 | #define WM8962_FLL_LAMBDA_MASK 0xFFFF /* FLL_LAMBDA - [15:0] */ |
2718 | #define WM8962_FLL_LAMBDA_SHIFT 0 /* FLL_LAMBDA - [15:0] */ |
2719 | #define WM8962_FLL_LAMBDA_WIDTH 16 /* FLL_LAMBDA - [15:0] */ |
2720 | |
2721 | /* |
2722 | * R162 (0xA2) - FLL Control (8) |
2723 | */ |
2724 | #define WM8962_FLL_N_MASK 0x03FF /* FLL_N - [9:0] */ |
2725 | #define WM8962_FLL_N_SHIFT 0 /* FLL_N - [9:0] */ |
2726 | #define WM8962_FLL_N_WIDTH 10 /* FLL_N - [9:0] */ |
2727 | |
2728 | /* |
2729 | * R252 (0xFC) - General test 1 |
2730 | */ |
2731 | #define WM8962_REG_SYNC 0x0004 /* REG_SYNC */ |
2732 | #define WM8962_REG_SYNC_MASK 0x0004 /* REG_SYNC */ |
2733 | #define WM8962_REG_SYNC_SHIFT 2 /* REG_SYNC */ |
2734 | #define WM8962_REG_SYNC_WIDTH 1 /* REG_SYNC */ |
2735 | #define WM8962_AUTO_INC 0x0001 /* AUTO_INC */ |
2736 | #define WM8962_AUTO_INC_MASK 0x0001 /* AUTO_INC */ |
2737 | #define WM8962_AUTO_INC_SHIFT 0 /* AUTO_INC */ |
2738 | #define WM8962_AUTO_INC_WIDTH 1 /* AUTO_INC */ |
2739 | |
2740 | /* |
2741 | * R256 (0x100) - DF1 |
2742 | */ |
2743 | #define WM8962_DRC_DF1_ENA 0x0008 /* DRC_DF1_ENA */ |
2744 | #define WM8962_DRC_DF1_ENA_MASK 0x0008 /* DRC_DF1_ENA */ |
2745 | #define WM8962_DRC_DF1_ENA_SHIFT 3 /* DRC_DF1_ENA */ |
2746 | #define WM8962_DRC_DF1_ENA_WIDTH 1 /* DRC_DF1_ENA */ |
2747 | #define WM8962_DF1_SHARED_COEFF 0x0004 /* DF1_SHARED_COEFF */ |
2748 | #define WM8962_DF1_SHARED_COEFF_MASK 0x0004 /* DF1_SHARED_COEFF */ |
2749 | #define WM8962_DF1_SHARED_COEFF_SHIFT 2 /* DF1_SHARED_COEFF */ |
2750 | #define WM8962_DF1_SHARED_COEFF_WIDTH 1 /* DF1_SHARED_COEFF */ |
2751 | #define WM8962_DF1_SHARED_COEFF_SEL 0x0002 /* DF1_SHARED_COEFF_SEL */ |
2752 | #define WM8962_DF1_SHARED_COEFF_SEL_MASK 0x0002 /* DF1_SHARED_COEFF_SEL */ |
2753 | #define WM8962_DF1_SHARED_COEFF_SEL_SHIFT 1 /* DF1_SHARED_COEFF_SEL */ |
2754 | #define WM8962_DF1_SHARED_COEFF_SEL_WIDTH 1 /* DF1_SHARED_COEFF_SEL */ |
2755 | #define WM8962_DF1_ENA 0x0001 /* DF1_ENA */ |
2756 | #define WM8962_DF1_ENA_MASK 0x0001 /* DF1_ENA */ |
2757 | #define WM8962_DF1_ENA_SHIFT 0 /* DF1_ENA */ |
2758 | #define WM8962_DF1_ENA_WIDTH 1 /* DF1_ENA */ |
2759 | |
2760 | /* |
2761 | * R257 (0x101) - DF2 |
2762 | */ |
2763 | #define WM8962_DF1_COEFF_L0_MASK 0xFFFF /* DF1_COEFF_L0 - [15:0] */ |
2764 | #define WM8962_DF1_COEFF_L0_SHIFT 0 /* DF1_COEFF_L0 - [15:0] */ |
2765 | #define WM8962_DF1_COEFF_L0_WIDTH 16 /* DF1_COEFF_L0 - [15:0] */ |
2766 | |
2767 | /* |
2768 | * R258 (0x102) - DF3 |
2769 | */ |
2770 | #define WM8962_DF1_COEFF_L1_MASK 0xFFFF /* DF1_COEFF_L1 - [15:0] */ |
2771 | #define WM8962_DF1_COEFF_L1_SHIFT 0 /* DF1_COEFF_L1 - [15:0] */ |
2772 | #define WM8962_DF1_COEFF_L1_WIDTH 16 /* DF1_COEFF_L1 - [15:0] */ |
2773 | |
2774 | /* |
2775 | * R259 (0x103) - DF4 |
2776 | */ |
2777 | #define WM8962_DF1_COEFF_L2_MASK 0xFFFF /* DF1_COEFF_L2 - [15:0] */ |
2778 | #define WM8962_DF1_COEFF_L2_SHIFT 0 /* DF1_COEFF_L2 - [15:0] */ |
2779 | #define WM8962_DF1_COEFF_L2_WIDTH 16 /* DF1_COEFF_L2 - [15:0] */ |
2780 | |
2781 | /* |
2782 | * R260 (0x104) - DF5 |
2783 | */ |
2784 | #define WM8962_DF1_COEFF_R0_MASK 0xFFFF /* DF1_COEFF_R0 - [15:0] */ |
2785 | #define WM8962_DF1_COEFF_R0_SHIFT 0 /* DF1_COEFF_R0 - [15:0] */ |
2786 | #define WM8962_DF1_COEFF_R0_WIDTH 16 /* DF1_COEFF_R0 - [15:0] */ |
2787 | |
2788 | /* |
2789 | * R261 (0x105) - DF6 |
2790 | */ |
2791 | #define WM8962_DF1_COEFF_R1_MASK 0xFFFF /* DF1_COEFF_R1 - [15:0] */ |
2792 | #define WM8962_DF1_COEFF_R1_SHIFT 0 /* DF1_COEFF_R1 - [15:0] */ |
2793 | #define WM8962_DF1_COEFF_R1_WIDTH 16 /* DF1_COEFF_R1 - [15:0] */ |
2794 | |
2795 | /* |
2796 | * R262 (0x106) - DF7 |
2797 | */ |
2798 | #define WM8962_DF1_COEFF_R2_MASK 0xFFFF /* DF1_COEFF_R2 - [15:0] */ |
2799 | #define WM8962_DF1_COEFF_R2_SHIFT 0 /* DF1_COEFF_R2 - [15:0] */ |
2800 | #define WM8962_DF1_COEFF_R2_WIDTH 16 /* DF1_COEFF_R2 - [15:0] */ |
2801 | |
2802 | /* |
2803 | * R264 (0x108) - LHPF1 |
2804 | */ |
2805 | #define WM8962_LHPF_MODE 0x0002 /* LHPF_MODE */ |
2806 | #define WM8962_LHPF_MODE_MASK 0x0002 /* LHPF_MODE */ |
2807 | #define WM8962_LHPF_MODE_SHIFT 1 /* LHPF_MODE */ |
2808 | #define WM8962_LHPF_MODE_WIDTH 1 /* LHPF_MODE */ |
2809 | #define WM8962_LHPF_ENA 0x0001 /* LHPF_ENA */ |
2810 | #define WM8962_LHPF_ENA_MASK 0x0001 /* LHPF_ENA */ |
2811 | #define WM8962_LHPF_ENA_SHIFT 0 /* LHPF_ENA */ |
2812 | #define WM8962_LHPF_ENA_WIDTH 1 /* LHPF_ENA */ |
2813 | |
2814 | /* |
2815 | * R265 (0x109) - LHPF2 |
2816 | */ |
2817 | #define WM8962_LHPF_COEFF_MASK 0xFFFF /* LHPF_COEFF - [15:0] */ |
2818 | #define WM8962_LHPF_COEFF_SHIFT 0 /* LHPF_COEFF - [15:0] */ |
2819 | #define WM8962_LHPF_COEFF_WIDTH 16 /* LHPF_COEFF - [15:0] */ |
2820 | |
2821 | /* |
2822 | * R268 (0x10C) - THREED1 |
2823 | */ |
2824 | #define WM8962_ADC_MONOMIX 0x0040 /* ADC_MONOMIX */ |
2825 | #define WM8962_ADC_MONOMIX_MASK 0x0040 /* ADC_MONOMIX */ |
2826 | #define WM8962_ADC_MONOMIX_SHIFT 6 /* ADC_MONOMIX */ |
2827 | #define WM8962_ADC_MONOMIX_WIDTH 1 /* ADC_MONOMIX */ |
2828 | #define WM8962_THREED_SIGN_L 0x0020 /* THREED_SIGN_L */ |
2829 | #define WM8962_THREED_SIGN_L_MASK 0x0020 /* THREED_SIGN_L */ |
2830 | #define WM8962_THREED_SIGN_L_SHIFT 5 /* THREED_SIGN_L */ |
2831 | #define WM8962_THREED_SIGN_L_WIDTH 1 /* THREED_SIGN_L */ |
2832 | #define WM8962_THREED_SIGN_R 0x0010 /* THREED_SIGN_R */ |
2833 | #define WM8962_THREED_SIGN_R_MASK 0x0010 /* THREED_SIGN_R */ |
2834 | #define WM8962_THREED_SIGN_R_SHIFT 4 /* THREED_SIGN_R */ |
2835 | #define WM8962_THREED_SIGN_R_WIDTH 1 /* THREED_SIGN_R */ |
2836 | #define WM8962_THREED_LHPF_MODE 0x0004 /* THREED_LHPF_MODE */ |
2837 | #define WM8962_THREED_LHPF_MODE_MASK 0x0004 /* THREED_LHPF_MODE */ |
2838 | #define WM8962_THREED_LHPF_MODE_SHIFT 2 /* THREED_LHPF_MODE */ |
2839 | #define WM8962_THREED_LHPF_MODE_WIDTH 1 /* THREED_LHPF_MODE */ |
2840 | #define WM8962_THREED_LHPF_ENA 0x0002 /* THREED_LHPF_ENA */ |
2841 | #define WM8962_THREED_LHPF_ENA_MASK 0x0002 /* THREED_LHPF_ENA */ |
2842 | #define WM8962_THREED_LHPF_ENA_SHIFT 1 /* THREED_LHPF_ENA */ |
2843 | #define WM8962_THREED_LHPF_ENA_WIDTH 1 /* THREED_LHPF_ENA */ |
2844 | #define WM8962_THREED_ENA 0x0001 /* THREED_ENA */ |
2845 | #define WM8962_THREED_ENA_MASK 0x0001 /* THREED_ENA */ |
2846 | #define WM8962_THREED_ENA_SHIFT 0 /* THREED_ENA */ |
2847 | #define WM8962_THREED_ENA_WIDTH 1 /* THREED_ENA */ |
2848 | |
2849 | /* |
2850 | * R269 (0x10D) - THREED2 |
2851 | */ |
2852 | #define WM8962_THREED_FGAINL_MASK 0xF800 /* THREED_FGAINL - [15:11] */ |
2853 | #define WM8962_THREED_FGAINL_SHIFT 11 /* THREED_FGAINL - [15:11] */ |
2854 | #define WM8962_THREED_FGAINL_WIDTH 5 /* THREED_FGAINL - [15:11] */ |
2855 | #define WM8962_THREED_CGAINL_MASK 0x07C0 /* THREED_CGAINL - [10:6] */ |
2856 | #define WM8962_THREED_CGAINL_SHIFT 6 /* THREED_CGAINL - [10:6] */ |
2857 | #define WM8962_THREED_CGAINL_WIDTH 5 /* THREED_CGAINL - [10:6] */ |
2858 | #define WM8962_THREED_DELAYL_MASK 0x003C /* THREED_DELAYL - [5:2] */ |
2859 | #define WM8962_THREED_DELAYL_SHIFT 2 /* THREED_DELAYL - [5:2] */ |
2860 | #define WM8962_THREED_DELAYL_WIDTH 4 /* THREED_DELAYL - [5:2] */ |
2861 | |
2862 | /* |
2863 | * R270 (0x10E) - THREED3 |
2864 | */ |
2865 | #define WM8962_THREED_LHPF_COEFF_MASK 0xFFFF /* THREED_LHPF_COEFF - [15:0] */ |
2866 | #define WM8962_THREED_LHPF_COEFF_SHIFT 0 /* THREED_LHPF_COEFF - [15:0] */ |
2867 | #define WM8962_THREED_LHPF_COEFF_WIDTH 16 /* THREED_LHPF_COEFF - [15:0] */ |
2868 | |
2869 | /* |
2870 | * R271 (0x10F) - THREED4 |
2871 | */ |
2872 | #define WM8962_THREED_FGAINR_MASK 0xF800 /* THREED_FGAINR - [15:11] */ |
2873 | #define WM8962_THREED_FGAINR_SHIFT 11 /* THREED_FGAINR - [15:11] */ |
2874 | #define WM8962_THREED_FGAINR_WIDTH 5 /* THREED_FGAINR - [15:11] */ |
2875 | #define WM8962_THREED_CGAINR_MASK 0x07C0 /* THREED_CGAINR - [10:6] */ |
2876 | #define WM8962_THREED_CGAINR_SHIFT 6 /* THREED_CGAINR - [10:6] */ |
2877 | #define WM8962_THREED_CGAINR_WIDTH 5 /* THREED_CGAINR - [10:6] */ |
2878 | #define WM8962_THREED_DELAYR_MASK 0x003C /* THREED_DELAYR - [5:2] */ |
2879 | #define WM8962_THREED_DELAYR_SHIFT 2 /* THREED_DELAYR - [5:2] */ |
2880 | #define WM8962_THREED_DELAYR_WIDTH 4 /* THREED_DELAYR - [5:2] */ |
2881 | |
2882 | /* |
2883 | * R276 (0x114) - DRC 1 |
2884 | */ |
2885 | #define WM8962_DRC_SIG_DET_RMS_MASK 0x7C00 /* DRC_SIG_DET_RMS - [14:10] */ |
2886 | #define WM8962_DRC_SIG_DET_RMS_SHIFT 10 /* DRC_SIG_DET_RMS - [14:10] */ |
2887 | #define WM8962_DRC_SIG_DET_RMS_WIDTH 5 /* DRC_SIG_DET_RMS - [14:10] */ |
2888 | #define WM8962_DRC_SIG_DET_PK_MASK 0x0300 /* DRC_SIG_DET_PK - [9:8] */ |
2889 | #define WM8962_DRC_SIG_DET_PK_SHIFT 8 /* DRC_SIG_DET_PK - [9:8] */ |
2890 | #define WM8962_DRC_SIG_DET_PK_WIDTH 2 /* DRC_SIG_DET_PK - [9:8] */ |
2891 | #define WM8962_DRC_NG_ENA 0x0080 /* DRC_NG_ENA */ |
2892 | #define WM8962_DRC_NG_ENA_MASK 0x0080 /* DRC_NG_ENA */ |
2893 | #define WM8962_DRC_NG_ENA_SHIFT 7 /* DRC_NG_ENA */ |
2894 | #define WM8962_DRC_NG_ENA_WIDTH 1 /* DRC_NG_ENA */ |
2895 | #define WM8962_DRC_SIG_DET_MODE 0x0040 /* DRC_SIG_DET_MODE */ |
2896 | #define WM8962_DRC_SIG_DET_MODE_MASK 0x0040 /* DRC_SIG_DET_MODE */ |
2897 | #define WM8962_DRC_SIG_DET_MODE_SHIFT 6 /* DRC_SIG_DET_MODE */ |
2898 | #define WM8962_DRC_SIG_DET_MODE_WIDTH 1 /* DRC_SIG_DET_MODE */ |
2899 | #define WM8962_DRC_SIG_DET 0x0020 /* DRC_SIG_DET */ |
2900 | #define WM8962_DRC_SIG_DET_MASK 0x0020 /* DRC_SIG_DET */ |
2901 | #define WM8962_DRC_SIG_DET_SHIFT 5 /* DRC_SIG_DET */ |
2902 | #define WM8962_DRC_SIG_DET_WIDTH 1 /* DRC_SIG_DET */ |
2903 | #define WM8962_DRC_KNEE2_OP_ENA 0x0010 /* DRC_KNEE2_OP_ENA */ |
2904 | #define WM8962_DRC_KNEE2_OP_ENA_MASK 0x0010 /* DRC_KNEE2_OP_ENA */ |
2905 | #define WM8962_DRC_KNEE2_OP_ENA_SHIFT 4 /* DRC_KNEE2_OP_ENA */ |
2906 | #define WM8962_DRC_KNEE2_OP_ENA_WIDTH 1 /* DRC_KNEE2_OP_ENA */ |
2907 | #define WM8962_DRC_QR 0x0008 /* DRC_QR */ |
2908 | #define WM8962_DRC_QR_MASK 0x0008 /* DRC_QR */ |
2909 | #define WM8962_DRC_QR_SHIFT 3 /* DRC_QR */ |
2910 | #define WM8962_DRC_QR_WIDTH 1 /* DRC_QR */ |
2911 | #define WM8962_DRC_ANTICLIP 0x0004 /* DRC_ANTICLIP */ |
2912 | #define WM8962_DRC_ANTICLIP_MASK 0x0004 /* DRC_ANTICLIP */ |
2913 | #define WM8962_DRC_ANTICLIP_SHIFT 2 /* DRC_ANTICLIP */ |
2914 | #define WM8962_DRC_ANTICLIP_WIDTH 1 /* DRC_ANTICLIP */ |
2915 | #define WM8962_DRC_MODE 0x0002 /* DRC_MODE */ |
2916 | #define WM8962_DRC_MODE_MASK 0x0002 /* DRC_MODE */ |
2917 | #define WM8962_DRC_MODE_SHIFT 1 /* DRC_MODE */ |
2918 | #define WM8962_DRC_MODE_WIDTH 1 /* DRC_MODE */ |
2919 | #define WM8962_DRC_ENA 0x0001 /* DRC_ENA */ |
2920 | #define WM8962_DRC_ENA_MASK 0x0001 /* DRC_ENA */ |
2921 | #define WM8962_DRC_ENA_SHIFT 0 /* DRC_ENA */ |
2922 | #define WM8962_DRC_ENA_WIDTH 1 /* DRC_ENA */ |
2923 | |
2924 | /* |
2925 | * R277 (0x115) - DRC 2 |
2926 | */ |
2927 | #define WM8962_DRC_ATK_MASK 0x1E00 /* DRC_ATK - [12:9] */ |
2928 | #define WM8962_DRC_ATK_SHIFT 9 /* DRC_ATK - [12:9] */ |
2929 | #define WM8962_DRC_ATK_WIDTH 4 /* DRC_ATK - [12:9] */ |
2930 | #define WM8962_DRC_DCY_MASK 0x01E0 /* DRC_DCY - [8:5] */ |
2931 | #define WM8962_DRC_DCY_SHIFT 5 /* DRC_DCY - [8:5] */ |
2932 | #define WM8962_DRC_DCY_WIDTH 4 /* DRC_DCY - [8:5] */ |
2933 | #define WM8962_DRC_MINGAIN_MASK 0x001C /* DRC_MINGAIN - [4:2] */ |
2934 | #define WM8962_DRC_MINGAIN_SHIFT 2 /* DRC_MINGAIN - [4:2] */ |
2935 | #define WM8962_DRC_MINGAIN_WIDTH 3 /* DRC_MINGAIN - [4:2] */ |
2936 | #define WM8962_DRC_MAXGAIN_MASK 0x0003 /* DRC_MAXGAIN - [1:0] */ |
2937 | #define WM8962_DRC_MAXGAIN_SHIFT 0 /* DRC_MAXGAIN - [1:0] */ |
2938 | #define WM8962_DRC_MAXGAIN_WIDTH 2 /* DRC_MAXGAIN - [1:0] */ |
2939 | |
2940 | /* |
2941 | * R278 (0x116) - DRC 3 |
2942 | */ |
2943 | #define WM8962_DRC_NG_MINGAIN_MASK 0xF000 /* DRC_NG_MINGAIN - [15:12] */ |
2944 | #define WM8962_DRC_NG_MINGAIN_SHIFT 12 /* DRC_NG_MINGAIN - [15:12] */ |
2945 | #define WM8962_DRC_NG_MINGAIN_WIDTH 4 /* DRC_NG_MINGAIN - [15:12] */ |
2946 | #define WM8962_DRC_QR_THR_MASK 0x0C00 /* DRC_QR_THR - [11:10] */ |
2947 | #define WM8962_DRC_QR_THR_SHIFT 10 /* DRC_QR_THR - [11:10] */ |
2948 | #define WM8962_DRC_QR_THR_WIDTH 2 /* DRC_QR_THR - [11:10] */ |
2949 | #define WM8962_DRC_QR_DCY_MASK 0x0300 /* DRC_QR_DCY - [9:8] */ |
2950 | #define WM8962_DRC_QR_DCY_SHIFT 8 /* DRC_QR_DCY - [9:8] */ |
2951 | #define WM8962_DRC_QR_DCY_WIDTH 2 /* DRC_QR_DCY - [9:8] */ |
2952 | #define WM8962_DRC_NG_EXP_MASK 0x00C0 /* DRC_NG_EXP - [7:6] */ |
2953 | #define WM8962_DRC_NG_EXP_SHIFT 6 /* DRC_NG_EXP - [7:6] */ |
2954 | #define WM8962_DRC_NG_EXP_WIDTH 2 /* DRC_NG_EXP - [7:6] */ |
2955 | #define WM8962_DRC_HI_COMP_MASK 0x0038 /* DRC_HI_COMP - [5:3] */ |
2956 | #define WM8962_DRC_HI_COMP_SHIFT 3 /* DRC_HI_COMP - [5:3] */ |
2957 | #define WM8962_DRC_HI_COMP_WIDTH 3 /* DRC_HI_COMP - [5:3] */ |
2958 | #define WM8962_DRC_LO_COMP_MASK 0x0007 /* DRC_LO_COMP - [2:0] */ |
2959 | #define WM8962_DRC_LO_COMP_SHIFT 0 /* DRC_LO_COMP - [2:0] */ |
2960 | #define WM8962_DRC_LO_COMP_WIDTH 3 /* DRC_LO_COMP - [2:0] */ |
2961 | |
2962 | /* |
2963 | * R279 (0x117) - DRC 4 |
2964 | */ |
2965 | #define WM8962_DRC_KNEE_IP_MASK 0x07E0 /* DRC_KNEE_IP - [10:5] */ |
2966 | #define WM8962_DRC_KNEE_IP_SHIFT 5 /* DRC_KNEE_IP - [10:5] */ |
2967 | #define WM8962_DRC_KNEE_IP_WIDTH 6 /* DRC_KNEE_IP - [10:5] */ |
2968 | #define WM8962_DRC_KNEE_OP_MASK 0x001F /* DRC_KNEE_OP - [4:0] */ |
2969 | #define WM8962_DRC_KNEE_OP_SHIFT 0 /* DRC_KNEE_OP - [4:0] */ |
2970 | #define WM8962_DRC_KNEE_OP_WIDTH 5 /* DRC_KNEE_OP - [4:0] */ |
2971 | |
2972 | /* |
2973 | * R280 (0x118) - DRC 5 |
2974 | */ |
2975 | #define WM8962_DRC_KNEE2_IP_MASK 0x03E0 /* DRC_KNEE2_IP - [9:5] */ |
2976 | #define WM8962_DRC_KNEE2_IP_SHIFT 5 /* DRC_KNEE2_IP - [9:5] */ |
2977 | #define WM8962_DRC_KNEE2_IP_WIDTH 5 /* DRC_KNEE2_IP - [9:5] */ |
2978 | #define WM8962_DRC_KNEE2_OP_MASK 0x001F /* DRC_KNEE2_OP - [4:0] */ |
2979 | #define WM8962_DRC_KNEE2_OP_SHIFT 0 /* DRC_KNEE2_OP - [4:0] */ |
2980 | #define WM8962_DRC_KNEE2_OP_WIDTH 5 /* DRC_KNEE2_OP - [4:0] */ |
2981 | |
2982 | /* |
2983 | * R285 (0x11D) - Tloopback |
2984 | */ |
2985 | #define WM8962_TLB_ENA 0x0002 /* TLB_ENA */ |
2986 | #define WM8962_TLB_ENA_MASK 0x0002 /* TLB_ENA */ |
2987 | #define WM8962_TLB_ENA_SHIFT 1 /* TLB_ENA */ |
2988 | #define WM8962_TLB_ENA_WIDTH 1 /* TLB_ENA */ |
2989 | #define WM8962_TLB_MODE 0x0001 /* TLB_MODE */ |
2990 | #define WM8962_TLB_MODE_MASK 0x0001 /* TLB_MODE */ |
2991 | #define WM8962_TLB_MODE_SHIFT 0 /* TLB_MODE */ |
2992 | #define WM8962_TLB_MODE_WIDTH 1 /* TLB_MODE */ |
2993 | |
2994 | /* |
2995 | * R335 (0x14F) - EQ1 |
2996 | */ |
2997 | #define WM8962_EQ_SHARED_COEFF 0x0004 /* EQ_SHARED_COEFF */ |
2998 | #define WM8962_EQ_SHARED_COEFF_MASK 0x0004 /* EQ_SHARED_COEFF */ |
2999 | #define WM8962_EQ_SHARED_COEFF_SHIFT 2 /* EQ_SHARED_COEFF */ |
3000 | #define WM8962_EQ_SHARED_COEFF_WIDTH 1 /* EQ_SHARED_COEFF */ |
3001 | #define WM8962_EQ_SHARED_COEFF_SEL 0x0002 /* EQ_SHARED_COEFF_SEL */ |
3002 | #define WM8962_EQ_SHARED_COEFF_SEL_MASK 0x0002 /* EQ_SHARED_COEFF_SEL */ |
3003 | #define WM8962_EQ_SHARED_COEFF_SEL_SHIFT 1 /* EQ_SHARED_COEFF_SEL */ |
3004 | #define WM8962_EQ_SHARED_COEFF_SEL_WIDTH 1 /* EQ_SHARED_COEFF_SEL */ |
3005 | #define WM8962_EQ_ENA 0x0001 /* EQ_ENA */ |
3006 | #define WM8962_EQ_ENA_MASK 0x0001 /* EQ_ENA */ |
3007 | #define WM8962_EQ_ENA_SHIFT 0 /* EQ_ENA */ |
3008 | #define WM8962_EQ_ENA_WIDTH 1 /* EQ_ENA */ |
3009 | |
3010 | /* |
3011 | * R336 (0x150) - EQ2 |
3012 | */ |
3013 | #define WM8962_EQL_B1_GAIN_MASK 0xF800 /* EQL_B1_GAIN - [15:11] */ |
3014 | #define WM8962_EQL_B1_GAIN_SHIFT 11 /* EQL_B1_GAIN - [15:11] */ |
3015 | #define WM8962_EQL_B1_GAIN_WIDTH 5 /* EQL_B1_GAIN - [15:11] */ |
3016 | #define WM8962_EQL_B2_GAIN_MASK 0x07C0 /* EQL_B2_GAIN - [10:6] */ |
3017 | #define WM8962_EQL_B2_GAIN_SHIFT 6 /* EQL_B2_GAIN - [10:6] */ |
3018 | #define WM8962_EQL_B2_GAIN_WIDTH 5 /* EQL_B2_GAIN - [10:6] */ |
3019 | #define WM8962_EQL_B3_GAIN_MASK 0x003E /* EQL_B3_GAIN - [5:1] */ |
3020 | #define WM8962_EQL_B3_GAIN_SHIFT 1 /* EQL_B3_GAIN - [5:1] */ |
3021 | #define WM8962_EQL_B3_GAIN_WIDTH 5 /* EQL_B3_GAIN - [5:1] */ |
3022 | |
3023 | /* |
3024 | * R337 (0x151) - EQ3 |
3025 | */ |
3026 | #define WM8962_EQL_B4_GAIN_MASK 0xF800 /* EQL_B4_GAIN - [15:11] */ |
3027 | #define WM8962_EQL_B4_GAIN_SHIFT 11 /* EQL_B4_GAIN - [15:11] */ |
3028 | #define WM8962_EQL_B4_GAIN_WIDTH 5 /* EQL_B4_GAIN - [15:11] */ |
3029 | #define WM8962_EQL_B5_GAIN_MASK 0x07C0 /* EQL_B5_GAIN - [10:6] */ |
3030 | #define WM8962_EQL_B5_GAIN_SHIFT 6 /* EQL_B5_GAIN - [10:6] */ |
3031 | #define WM8962_EQL_B5_GAIN_WIDTH 5 /* EQL_B5_GAIN - [10:6] */ |
3032 | |
3033 | /* |
3034 | * R338 (0x152) - EQ4 |
3035 | */ |
3036 | #define WM8962_EQL_B1_A_MASK 0xFFFF /* EQL_B1_A - [15:0] */ |
3037 | #define WM8962_EQL_B1_A_SHIFT 0 /* EQL_B1_A - [15:0] */ |
3038 | #define WM8962_EQL_B1_A_WIDTH 16 /* EQL_B1_A - [15:0] */ |
3039 | |
3040 | /* |
3041 | * R339 (0x153) - EQ5 |
3042 | */ |
3043 | #define WM8962_EQL_B1_B_MASK 0xFFFF /* EQL_B1_B - [15:0] */ |
3044 | #define WM8962_EQL_B1_B_SHIFT 0 /* EQL_B1_B - [15:0] */ |
3045 | #define WM8962_EQL_B1_B_WIDTH 16 /* EQL_B1_B - [15:0] */ |
3046 | |
3047 | /* |
3048 | * R340 (0x154) - EQ6 |
3049 | */ |
3050 | #define WM8962_EQL_B1_PG_MASK 0xFFFF /* EQL_B1_PG - [15:0] */ |
3051 | #define WM8962_EQL_B1_PG_SHIFT 0 /* EQL_B1_PG - [15:0] */ |
3052 | #define WM8962_EQL_B1_PG_WIDTH 16 /* EQL_B1_PG - [15:0] */ |
3053 | |
3054 | /* |
3055 | * R341 (0x155) - EQ7 |
3056 | */ |
3057 | #define WM8962_EQL_B2_A_MASK 0xFFFF /* EQL_B2_A - [15:0] */ |
3058 | #define WM8962_EQL_B2_A_SHIFT 0 /* EQL_B2_A - [15:0] */ |
3059 | #define WM8962_EQL_B2_A_WIDTH 16 /* EQL_B2_A - [15:0] */ |
3060 | |
3061 | /* |
3062 | * R342 (0x156) - EQ8 |
3063 | */ |
3064 | #define WM8962_EQL_B2_B_MASK 0xFFFF /* EQL_B2_B - [15:0] */ |
3065 | #define WM8962_EQL_B2_B_SHIFT 0 /* EQL_B2_B - [15:0] */ |
3066 | #define WM8962_EQL_B2_B_WIDTH 16 /* EQL_B2_B - [15:0] */ |
3067 | |
3068 | /* |
3069 | * R343 (0x157) - EQ9 |
3070 | */ |
3071 | #define WM8962_EQL_B2_C_MASK 0xFFFF /* EQL_B2_C - [15:0] */ |
3072 | #define WM8962_EQL_B2_C_SHIFT 0 /* EQL_B2_C - [15:0] */ |
3073 | #define WM8962_EQL_B2_C_WIDTH 16 /* EQL_B2_C - [15:0] */ |
3074 | |
3075 | /* |
3076 | * R344 (0x158) - EQ10 |
3077 | */ |
3078 | #define WM8962_EQL_B2_PG_MASK 0xFFFF /* EQL_B2_PG - [15:0] */ |
3079 | #define WM8962_EQL_B2_PG_SHIFT 0 /* EQL_B2_PG - [15:0] */ |
3080 | #define WM8962_EQL_B2_PG_WIDTH 16 /* EQL_B2_PG - [15:0] */ |
3081 | |
3082 | /* |
3083 | * R345 (0x159) - EQ11 |
3084 | */ |
3085 | #define WM8962_EQL_B3_A_MASK 0xFFFF /* EQL_B3_A - [15:0] */ |
3086 | #define WM8962_EQL_B3_A_SHIFT 0 /* EQL_B3_A - [15:0] */ |
3087 | #define WM8962_EQL_B3_A_WIDTH 16 /* EQL_B3_A - [15:0] */ |
3088 | |
3089 | /* |
3090 | * R346 (0x15A) - EQ12 |
3091 | */ |
3092 | #define WM8962_EQL_B3_B_MASK 0xFFFF /* EQL_B3_B - [15:0] */ |
3093 | #define WM8962_EQL_B3_B_SHIFT 0 /* EQL_B3_B - [15:0] */ |
3094 | #define WM8962_EQL_B3_B_WIDTH 16 /* EQL_B3_B - [15:0] */ |
3095 | |
3096 | /* |
3097 | * R347 (0x15B) - EQ13 |
3098 | */ |
3099 | #define WM8962_EQL_B3_C_MASK 0xFFFF /* EQL_B3_C - [15:0] */ |
3100 | #define WM8962_EQL_B3_C_SHIFT 0 /* EQL_B3_C - [15:0] */ |
3101 | #define WM8962_EQL_B3_C_WIDTH 16 /* EQL_B3_C - [15:0] */ |
3102 | |
3103 | /* |
3104 | * R348 (0x15C) - EQ14 |
3105 | */ |
3106 | #define WM8962_EQL_B3_PG_MASK 0xFFFF /* EQL_B3_PG - [15:0] */ |
3107 | #define WM8962_EQL_B3_PG_SHIFT 0 /* EQL_B3_PG - [15:0] */ |
3108 | #define WM8962_EQL_B3_PG_WIDTH 16 /* EQL_B3_PG - [15:0] */ |
3109 | |
3110 | /* |
3111 | * R349 (0x15D) - EQ15 |
3112 | */ |
3113 | #define WM8962_EQL_B4_A_MASK 0xFFFF /* EQL_B4_A - [15:0] */ |
3114 | #define WM8962_EQL_B4_A_SHIFT 0 /* EQL_B4_A - [15:0] */ |
3115 | #define WM8962_EQL_B4_A_WIDTH 16 /* EQL_B4_A - [15:0] */ |
3116 | |
3117 | /* |
3118 | * R350 (0x15E) - EQ16 |
3119 | */ |
3120 | #define WM8962_EQL_B4_B_MASK 0xFFFF /* EQL_B4_B - [15:0] */ |
3121 | #define WM8962_EQL_B4_B_SHIFT 0 /* EQL_B4_B - [15:0] */ |
3122 | #define WM8962_EQL_B4_B_WIDTH 16 /* EQL_B4_B - [15:0] */ |
3123 | |
3124 | /* |
3125 | * R351 (0x15F) - EQ17 |
3126 | */ |
3127 | #define WM8962_EQL_B4_C_MASK 0xFFFF /* EQL_B4_C - [15:0] */ |
3128 | #define WM8962_EQL_B4_C_SHIFT 0 /* EQL_B4_C - [15:0] */ |
3129 | #define WM8962_EQL_B4_C_WIDTH 16 /* EQL_B4_C - [15:0] */ |
3130 | |
3131 | /* |
3132 | * R352 (0x160) - EQ18 |
3133 | */ |
3134 | #define WM8962_EQL_B4_PG_MASK 0xFFFF /* EQL_B4_PG - [15:0] */ |
3135 | #define WM8962_EQL_B4_PG_SHIFT 0 /* EQL_B4_PG - [15:0] */ |
3136 | #define WM8962_EQL_B4_PG_WIDTH 16 /* EQL_B4_PG - [15:0] */ |
3137 | |
3138 | /* |
3139 | * R353 (0x161) - EQ19 |
3140 | */ |
3141 | #define WM8962_EQL_B5_A_MASK 0xFFFF /* EQL_B5_A - [15:0] */ |
3142 | #define WM8962_EQL_B5_A_SHIFT 0 /* EQL_B5_A - [15:0] */ |
3143 | #define WM8962_EQL_B5_A_WIDTH 16 /* EQL_B5_A - [15:0] */ |
3144 | |
3145 | /* |
3146 | * R354 (0x162) - EQ20 |
3147 | */ |
3148 | #define WM8962_EQL_B5_B_MASK 0xFFFF /* EQL_B5_B - [15:0] */ |
3149 | #define WM8962_EQL_B5_B_SHIFT 0 /* EQL_B5_B - [15:0] */ |
3150 | #define WM8962_EQL_B5_B_WIDTH 16 /* EQL_B5_B - [15:0] */ |
3151 | |
3152 | /* |
3153 | * R355 (0x163) - EQ21 |
3154 | */ |
3155 | #define WM8962_EQL_B5_PG_MASK 0xFFFF /* EQL_B5_PG - [15:0] */ |
3156 | #define WM8962_EQL_B5_PG_SHIFT 0 /* EQL_B5_PG - [15:0] */ |
3157 | #define WM8962_EQL_B5_PG_WIDTH 16 /* EQL_B5_PG - [15:0] */ |
3158 | |
3159 | /* |
3160 | * R356 (0x164) - EQ22 |
3161 | */ |
3162 | #define WM8962_EQR_B1_GAIN_MASK 0xF800 /* EQR_B1_GAIN - [15:11] */ |
3163 | #define WM8962_EQR_B1_GAIN_SHIFT 11 /* EQR_B1_GAIN - [15:11] */ |
3164 | #define WM8962_EQR_B1_GAIN_WIDTH 5 /* EQR_B1_GAIN - [15:11] */ |
3165 | #define WM8962_EQR_B2_GAIN_MASK 0x07C0 /* EQR_B2_GAIN - [10:6] */ |
3166 | #define WM8962_EQR_B2_GAIN_SHIFT 6 /* EQR_B2_GAIN - [10:6] */ |
3167 | #define WM8962_EQR_B2_GAIN_WIDTH 5 /* EQR_B2_GAIN - [10:6] */ |
3168 | #define WM8962_EQR_B3_GAIN_MASK 0x003E /* EQR_B3_GAIN - [5:1] */ |
3169 | #define WM8962_EQR_B3_GAIN_SHIFT 1 /* EQR_B3_GAIN - [5:1] */ |
3170 | #define WM8962_EQR_B3_GAIN_WIDTH 5 /* EQR_B3_GAIN - [5:1] */ |
3171 | |
3172 | /* |
3173 | * R357 (0x165) - EQ23 |
3174 | */ |
3175 | #define WM8962_EQR_B4_GAIN_MASK 0xF800 /* EQR_B4_GAIN - [15:11] */ |
3176 | #define WM8962_EQR_B4_GAIN_SHIFT 11 /* EQR_B4_GAIN - [15:11] */ |
3177 | #define WM8962_EQR_B4_GAIN_WIDTH 5 /* EQR_B4_GAIN - [15:11] */ |
3178 | #define WM8962_EQR_B5_GAIN_MASK 0x07C0 /* EQR_B5_GAIN - [10:6] */ |
3179 | #define WM8962_EQR_B5_GAIN_SHIFT 6 /* EQR_B5_GAIN - [10:6] */ |
3180 | #define WM8962_EQR_B5_GAIN_WIDTH 5 /* EQR_B5_GAIN - [10:6] */ |
3181 | |
3182 | /* |
3183 | * R358 (0x166) - EQ24 |
3184 | */ |
3185 | #define WM8962_EQR_B1_A_MASK 0xFFFF /* EQR_B1_A - [15:0] */ |
3186 | #define WM8962_EQR_B1_A_SHIFT 0 /* EQR_B1_A - [15:0] */ |
3187 | #define WM8962_EQR_B1_A_WIDTH 16 /* EQR_B1_A - [15:0] */ |
3188 | |
3189 | /* |
3190 | * R359 (0x167) - EQ25 |
3191 | */ |
3192 | #define WM8962_EQR_B1_B_MASK 0xFFFF /* EQR_B1_B - [15:0] */ |
3193 | #define WM8962_EQR_B1_B_SHIFT 0 /* EQR_B1_B - [15:0] */ |
3194 | #define WM8962_EQR_B1_B_WIDTH 16 /* EQR_B1_B - [15:0] */ |
3195 | |
3196 | /* |
3197 | * R360 (0x168) - EQ26 |
3198 | */ |
3199 | #define WM8962_EQR_B1_PG_MASK 0xFFFF /* EQR_B1_PG - [15:0] */ |
3200 | #define WM8962_EQR_B1_PG_SHIFT 0 /* EQR_B1_PG - [15:0] */ |
3201 | #define WM8962_EQR_B1_PG_WIDTH 16 /* EQR_B1_PG - [15:0] */ |
3202 | |
3203 | /* |
3204 | * R361 (0x169) - EQ27 |
3205 | */ |
3206 | #define WM8962_EQR_B2_A_MASK 0xFFFF /* EQR_B2_A - [15:0] */ |
3207 | #define WM8962_EQR_B2_A_SHIFT 0 /* EQR_B2_A - [15:0] */ |
3208 | #define WM8962_EQR_B2_A_WIDTH 16 /* EQR_B2_A - [15:0] */ |
3209 | |
3210 | /* |
3211 | * R362 (0x16A) - EQ28 |
3212 | */ |
3213 | #define WM8962_EQR_B2_B_MASK 0xFFFF /* EQR_B2_B - [15:0] */ |
3214 | #define WM8962_EQR_B2_B_SHIFT 0 /* EQR_B2_B - [15:0] */ |
3215 | #define WM8962_EQR_B2_B_WIDTH 16 /* EQR_B2_B - [15:0] */ |
3216 | |
3217 | /* |
3218 | * R363 (0x16B) - EQ29 |
3219 | */ |
3220 | #define WM8962_EQR_B2_C_MASK 0xFFFF /* EQR_B2_C - [15:0] */ |
3221 | #define WM8962_EQR_B2_C_SHIFT 0 /* EQR_B2_C - [15:0] */ |
3222 | #define WM8962_EQR_B2_C_WIDTH 16 /* EQR_B2_C - [15:0] */ |
3223 | |
3224 | /* |
3225 | * R364 (0x16C) - EQ30 |
3226 | */ |
3227 | #define WM8962_EQR_B2_PG_MASK 0xFFFF /* EQR_B2_PG - [15:0] */ |
3228 | #define WM8962_EQR_B2_PG_SHIFT 0 /* EQR_B2_PG - [15:0] */ |
3229 | #define WM8962_EQR_B2_PG_WIDTH 16 /* EQR_B2_PG - [15:0] */ |
3230 | |
3231 | /* |
3232 | * R365 (0x16D) - EQ31 |
3233 | */ |
3234 | #define WM8962_EQR_B3_A_MASK 0xFFFF /* EQR_B3_A - [15:0] */ |
3235 | #define WM8962_EQR_B3_A_SHIFT 0 /* EQR_B3_A - [15:0] */ |
3236 | #define WM8962_EQR_B3_A_WIDTH 16 /* EQR_B3_A - [15:0] */ |
3237 | |
3238 | /* |
3239 | * R366 (0x16E) - EQ32 |
3240 | */ |
3241 | #define WM8962_EQR_B3_B_MASK 0xFFFF /* EQR_B3_B - [15:0] */ |
3242 | #define WM8962_EQR_B3_B_SHIFT 0 /* EQR_B3_B - [15:0] */ |
3243 | #define WM8962_EQR_B3_B_WIDTH 16 /* EQR_B3_B - [15:0] */ |
3244 | |
3245 | /* |
3246 | * R367 (0x16F) - EQ33 |
3247 | */ |
3248 | #define WM8962_EQR_B3_C_MASK 0xFFFF /* EQR_B3_C - [15:0] */ |
3249 | #define WM8962_EQR_B3_C_SHIFT 0 /* EQR_B3_C - [15:0] */ |
3250 | #define WM8962_EQR_B3_C_WIDTH 16 /* EQR_B3_C - [15:0] */ |
3251 | |
3252 | /* |
3253 | * R368 (0x170) - EQ34 |
3254 | */ |
3255 | #define WM8962_EQR_B3_PG_MASK 0xFFFF /* EQR_B3_PG - [15:0] */ |
3256 | #define WM8962_EQR_B3_PG_SHIFT 0 /* EQR_B3_PG - [15:0] */ |
3257 | #define WM8962_EQR_B3_PG_WIDTH 16 /* EQR_B3_PG - [15:0] */ |
3258 | |
3259 | /* |
3260 | * R369 (0x171) - EQ35 |
3261 | */ |
3262 | #define WM8962_EQR_B4_A_MASK 0xFFFF /* EQR_B4_A - [15:0] */ |
3263 | #define WM8962_EQR_B4_A_SHIFT 0 /* EQR_B4_A - [15:0] */ |
3264 | #define WM8962_EQR_B4_A_WIDTH 16 /* EQR_B4_A - [15:0] */ |
3265 | |
3266 | /* |
3267 | * R370 (0x172) - EQ36 |
3268 | */ |
3269 | #define WM8962_EQR_B4_B_MASK 0xFFFF /* EQR_B4_B - [15:0] */ |
3270 | #define WM8962_EQR_B4_B_SHIFT 0 /* EQR_B4_B - [15:0] */ |
3271 | #define WM8962_EQR_B4_B_WIDTH 16 /* EQR_B4_B - [15:0] */ |
3272 | |
3273 | /* |
3274 | * R371 (0x173) - EQ37 |
3275 | */ |
3276 | #define WM8962_EQR_B4_C_MASK 0xFFFF /* EQR_B4_C - [15:0] */ |
3277 | #define WM8962_EQR_B4_C_SHIFT 0 /* EQR_B4_C - [15:0] */ |
3278 | #define WM8962_EQR_B4_C_WIDTH 16 /* EQR_B4_C - [15:0] */ |
3279 | |
3280 | /* |
3281 | * R372 (0x174) - EQ38 |
3282 | */ |
3283 | #define WM8962_EQR_B4_PG_MASK 0xFFFF /* EQR_B4_PG - [15:0] */ |
3284 | #define WM8962_EQR_B4_PG_SHIFT 0 /* EQR_B4_PG - [15:0] */ |
3285 | #define WM8962_EQR_B4_PG_WIDTH 16 /* EQR_B4_PG - [15:0] */ |
3286 | |
3287 | /* |
3288 | * R373 (0x175) - EQ39 |
3289 | */ |
3290 | #define WM8962_EQR_B5_A_MASK 0xFFFF /* EQR_B5_A - [15:0] */ |
3291 | #define WM8962_EQR_B5_A_SHIFT 0 /* EQR_B5_A - [15:0] */ |
3292 | #define WM8962_EQR_B5_A_WIDTH 16 /* EQR_B5_A - [15:0] */ |
3293 | |
3294 | /* |
3295 | * R374 (0x176) - EQ40 |
3296 | */ |
3297 | #define WM8962_EQR_B5_B_MASK 0xFFFF /* EQR_B5_B - [15:0] */ |
3298 | #define WM8962_EQR_B5_B_SHIFT 0 /* EQR_B5_B - [15:0] */ |
3299 | #define WM8962_EQR_B5_B_WIDTH 16 /* EQR_B5_B - [15:0] */ |
3300 | |
3301 | /* |
3302 | * R375 (0x177) - EQ41 |
3303 | */ |
3304 | #define WM8962_EQR_B5_PG_MASK 0xFFFF /* EQR_B5_PG - [15:0] */ |
3305 | #define WM8962_EQR_B5_PG_SHIFT 0 /* EQR_B5_PG - [15:0] */ |
3306 | #define WM8962_EQR_B5_PG_WIDTH 16 /* EQR_B5_PG - [15:0] */ |
3307 | |
3308 | /* |
3309 | * R513 (0x201) - GPIO 2 |
3310 | */ |
3311 | #define WM8962_GP2_POL 0x0400 /* GP2_POL */ |
3312 | #define WM8962_GP2_POL_MASK 0x0400 /* GP2_POL */ |
3313 | #define WM8962_GP2_POL_SHIFT 10 /* GP2_POL */ |
3314 | #define WM8962_GP2_POL_WIDTH 1 /* GP2_POL */ |
3315 | #define WM8962_GP2_LVL 0x0040 /* GP2_LVL */ |
3316 | #define WM8962_GP2_LVL_MASK 0x0040 /* GP2_LVL */ |
3317 | #define WM8962_GP2_LVL_SHIFT 6 /* GP2_LVL */ |
3318 | #define WM8962_GP2_LVL_WIDTH 1 /* GP2_LVL */ |
3319 | #define WM8962_GP2_FN_MASK 0x001F /* GP2_FN - [4:0] */ |
3320 | #define WM8962_GP2_FN_SHIFT 0 /* GP2_FN - [4:0] */ |
3321 | #define WM8962_GP2_FN_WIDTH 5 /* GP2_FN - [4:0] */ |
3322 | |
3323 | /* |
3324 | * R514 (0x202) - GPIO 3 |
3325 | */ |
3326 | #define WM8962_GP3_POL 0x0400 /* GP3_POL */ |
3327 | #define WM8962_GP3_POL_MASK 0x0400 /* GP3_POL */ |
3328 | #define WM8962_GP3_POL_SHIFT 10 /* GP3_POL */ |
3329 | #define WM8962_GP3_POL_WIDTH 1 /* GP3_POL */ |
3330 | #define WM8962_GP3_LVL 0x0040 /* GP3_LVL */ |
3331 | #define WM8962_GP3_LVL_MASK 0x0040 /* GP3_LVL */ |
3332 | #define WM8962_GP3_LVL_SHIFT 6 /* GP3_LVL */ |
3333 | #define WM8962_GP3_LVL_WIDTH 1 /* GP3_LVL */ |
3334 | #define WM8962_GP3_FN_MASK 0x001F /* GP3_FN - [4:0] */ |
3335 | #define WM8962_GP3_FN_SHIFT 0 /* GP3_FN - [4:0] */ |
3336 | #define WM8962_GP3_FN_WIDTH 5 /* GP3_FN - [4:0] */ |
3337 | |
3338 | /* |
3339 | * R516 (0x204) - GPIO 5 |
3340 | */ |
3341 | #define WM8962_GP5_DIR 0x8000 /* GP5_DIR */ |
3342 | #define WM8962_GP5_DIR_MASK 0x8000 /* GP5_DIR */ |
3343 | #define WM8962_GP5_DIR_SHIFT 15 /* GP5_DIR */ |
3344 | #define WM8962_GP5_DIR_WIDTH 1 /* GP5_DIR */ |
3345 | #define WM8962_GP5_PU 0x4000 /* GP5_PU */ |
3346 | #define WM8962_GP5_PU_MASK 0x4000 /* GP5_PU */ |
3347 | #define WM8962_GP5_PU_SHIFT 14 /* GP5_PU */ |
3348 | #define WM8962_GP5_PU_WIDTH 1 /* GP5_PU */ |
3349 | #define WM8962_GP5_PD 0x2000 /* GP5_PD */ |
3350 | #define WM8962_GP5_PD_MASK 0x2000 /* GP5_PD */ |
3351 | #define WM8962_GP5_PD_SHIFT 13 /* GP5_PD */ |
3352 | #define WM8962_GP5_PD_WIDTH 1 /* GP5_PD */ |
3353 | #define WM8962_GP5_POL 0x0400 /* GP5_POL */ |
3354 | #define WM8962_GP5_POL_MASK 0x0400 /* GP5_POL */ |
3355 | #define WM8962_GP5_POL_SHIFT 10 /* GP5_POL */ |
3356 | #define WM8962_GP5_POL_WIDTH 1 /* GP5_POL */ |
3357 | #define WM8962_GP5_OP_CFG 0x0200 /* GP5_OP_CFG */ |
3358 | #define WM8962_GP5_OP_CFG_MASK 0x0200 /* GP5_OP_CFG */ |
3359 | #define WM8962_GP5_OP_CFG_SHIFT 9 /* GP5_OP_CFG */ |
3360 | #define WM8962_GP5_OP_CFG_WIDTH 1 /* GP5_OP_CFG */ |
3361 | #define WM8962_GP5_DB 0x0100 /* GP5_DB */ |
3362 | #define WM8962_GP5_DB_MASK 0x0100 /* GP5_DB */ |
3363 | #define WM8962_GP5_DB_SHIFT 8 /* GP5_DB */ |
3364 | #define WM8962_GP5_DB_WIDTH 1 /* GP5_DB */ |
3365 | #define WM8962_GP5_LVL 0x0040 /* GP5_LVL */ |
3366 | #define WM8962_GP5_LVL_MASK 0x0040 /* GP5_LVL */ |
3367 | #define WM8962_GP5_LVL_SHIFT 6 /* GP5_LVL */ |
3368 | #define WM8962_GP5_LVL_WIDTH 1 /* GP5_LVL */ |
3369 | #define WM8962_GP5_FN_MASK 0x001F /* GP5_FN - [4:0] */ |
3370 | #define WM8962_GP5_FN_SHIFT 0 /* GP5_FN - [4:0] */ |
3371 | #define WM8962_GP5_FN_WIDTH 5 /* GP5_FN - [4:0] */ |
3372 | |
3373 | /* |
3374 | * R517 (0x205) - GPIO 6 |
3375 | */ |
3376 | #define WM8962_GP6_DIR 0x8000 /* GP6_DIR */ |
3377 | #define WM8962_GP6_DIR_MASK 0x8000 /* GP6_DIR */ |
3378 | #define WM8962_GP6_DIR_SHIFT 15 /* GP6_DIR */ |
3379 | #define WM8962_GP6_DIR_WIDTH 1 /* GP6_DIR */ |
3380 | #define WM8962_GP6_PU 0x4000 /* GP6_PU */ |
3381 | #define WM8962_GP6_PU_MASK 0x4000 /* GP6_PU */ |
3382 | #define WM8962_GP6_PU_SHIFT 14 /* GP6_PU */ |
3383 | #define WM8962_GP6_PU_WIDTH 1 /* GP6_PU */ |
3384 | #define WM8962_GP6_PD 0x2000 /* GP6_PD */ |
3385 | #define WM8962_GP6_PD_MASK 0x2000 /* GP6_PD */ |
3386 | #define WM8962_GP6_PD_SHIFT 13 /* GP6_PD */ |
3387 | #define WM8962_GP6_PD_WIDTH 1 /* GP6_PD */ |
3388 | #define WM8962_GP6_POL 0x0400 /* GP6_POL */ |
3389 | #define WM8962_GP6_POL_MASK 0x0400 /* GP6_POL */ |
3390 | #define WM8962_GP6_POL_SHIFT 10 /* GP6_POL */ |
3391 | #define WM8962_GP6_POL_WIDTH 1 /* GP6_POL */ |
3392 | #define WM8962_GP6_OP_CFG 0x0200 /* GP6_OP_CFG */ |
3393 | #define WM8962_GP6_OP_CFG_MASK 0x0200 /* GP6_OP_CFG */ |
3394 | #define WM8962_GP6_OP_CFG_SHIFT 9 /* GP6_OP_CFG */ |
3395 | #define WM8962_GP6_OP_CFG_WIDTH 1 /* GP6_OP_CFG */ |
3396 | #define WM8962_GP6_DB 0x0100 /* GP6_DB */ |
3397 | #define WM8962_GP6_DB_MASK 0x0100 /* GP6_DB */ |
3398 | #define WM8962_GP6_DB_SHIFT 8 /* GP6_DB */ |
3399 | #define WM8962_GP6_DB_WIDTH 1 /* GP6_DB */ |
3400 | #define WM8962_GP6_LVL 0x0040 /* GP6_LVL */ |
3401 | #define WM8962_GP6_LVL_MASK 0x0040 /* GP6_LVL */ |
3402 | #define WM8962_GP6_LVL_SHIFT 6 /* GP6_LVL */ |
3403 | #define WM8962_GP6_LVL_WIDTH 1 /* GP6_LVL */ |
3404 | #define WM8962_GP6_FN_MASK 0x001F /* GP6_FN - [4:0] */ |
3405 | #define WM8962_GP6_FN_SHIFT 0 /* GP6_FN - [4:0] */ |
3406 | #define WM8962_GP6_FN_WIDTH 5 /* GP6_FN - [4:0] */ |
3407 | |
3408 | /* |
3409 | * R560 (0x230) - Interrupt Status 1 |
3410 | */ |
3411 | #define WM8962_GP6_EINT 0x0020 /* GP6_EINT */ |
3412 | #define WM8962_GP6_EINT_MASK 0x0020 /* GP6_EINT */ |
3413 | #define WM8962_GP6_EINT_SHIFT 5 /* GP6_EINT */ |
3414 | #define WM8962_GP6_EINT_WIDTH 1 /* GP6_EINT */ |
3415 | #define WM8962_GP5_EINT 0x0010 /* GP5_EINT */ |
3416 | #define WM8962_GP5_EINT_MASK 0x0010 /* GP5_EINT */ |
3417 | #define WM8962_GP5_EINT_SHIFT 4 /* GP5_EINT */ |
3418 | #define WM8962_GP5_EINT_WIDTH 1 /* GP5_EINT */ |
3419 | |
3420 | /* |
3421 | * R561 (0x231) - Interrupt Status 2 |
3422 | */ |
3423 | #define WM8962_MICSCD_EINT 0x8000 /* MICSCD_EINT */ |
3424 | #define WM8962_MICSCD_EINT_MASK 0x8000 /* MICSCD_EINT */ |
3425 | #define WM8962_MICSCD_EINT_SHIFT 15 /* MICSCD_EINT */ |
3426 | #define WM8962_MICSCD_EINT_WIDTH 1 /* MICSCD_EINT */ |
3427 | #define WM8962_MICD_EINT 0x4000 /* MICD_EINT */ |
3428 | #define WM8962_MICD_EINT_MASK 0x4000 /* MICD_EINT */ |
3429 | #define WM8962_MICD_EINT_SHIFT 14 /* MICD_EINT */ |
3430 | #define WM8962_MICD_EINT_WIDTH 1 /* MICD_EINT */ |
3431 | #define WM8962_FIFOS_ERR_EINT 0x2000 /* FIFOS_ERR_EINT */ |
3432 | #define WM8962_FIFOS_ERR_EINT_MASK 0x2000 /* FIFOS_ERR_EINT */ |
3433 | #define WM8962_FIFOS_ERR_EINT_SHIFT 13 /* FIFOS_ERR_EINT */ |
3434 | #define WM8962_FIFOS_ERR_EINT_WIDTH 1 /* FIFOS_ERR_EINT */ |
3435 | #define WM8962_ALC_LOCK_EINT 0x1000 /* ALC_LOCK_EINT */ |
3436 | #define WM8962_ALC_LOCK_EINT_MASK 0x1000 /* ALC_LOCK_EINT */ |
3437 | #define WM8962_ALC_LOCK_EINT_SHIFT 12 /* ALC_LOCK_EINT */ |
3438 | #define WM8962_ALC_LOCK_EINT_WIDTH 1 /* ALC_LOCK_EINT */ |
3439 | #define WM8962_ALC_THRESH_EINT 0x0800 /* ALC_THRESH_EINT */ |
3440 | #define WM8962_ALC_THRESH_EINT_MASK 0x0800 /* ALC_THRESH_EINT */ |
3441 | #define WM8962_ALC_THRESH_EINT_SHIFT 11 /* ALC_THRESH_EINT */ |
3442 | #define WM8962_ALC_THRESH_EINT_WIDTH 1 /* ALC_THRESH_EINT */ |
3443 | #define WM8962_ALC_SAT_EINT 0x0400 /* ALC_SAT_EINT */ |
3444 | #define WM8962_ALC_SAT_EINT_MASK 0x0400 /* ALC_SAT_EINT */ |
3445 | #define WM8962_ALC_SAT_EINT_SHIFT 10 /* ALC_SAT_EINT */ |
3446 | #define WM8962_ALC_SAT_EINT_WIDTH 1 /* ALC_SAT_EINT */ |
3447 | #define WM8962_ALC_PKOVR_EINT 0x0200 /* ALC_PKOVR_EINT */ |
3448 | #define WM8962_ALC_PKOVR_EINT_MASK 0x0200 /* ALC_PKOVR_EINT */ |
3449 | #define WM8962_ALC_PKOVR_EINT_SHIFT 9 /* ALC_PKOVR_EINT */ |
3450 | #define WM8962_ALC_PKOVR_EINT_WIDTH 1 /* ALC_PKOVR_EINT */ |
3451 | #define WM8962_ALC_NGATE_EINT 0x0100 /* ALC_NGATE_EINT */ |
3452 | #define WM8962_ALC_NGATE_EINT_MASK 0x0100 /* ALC_NGATE_EINT */ |
3453 | #define WM8962_ALC_NGATE_EINT_SHIFT 8 /* ALC_NGATE_EINT */ |
3454 | #define WM8962_ALC_NGATE_EINT_WIDTH 1 /* ALC_NGATE_EINT */ |
3455 | #define WM8962_WSEQ_DONE_EINT 0x0080 /* WSEQ_DONE_EINT */ |
3456 | #define WM8962_WSEQ_DONE_EINT_MASK 0x0080 /* WSEQ_DONE_EINT */ |
3457 | #define WM8962_WSEQ_DONE_EINT_SHIFT 7 /* WSEQ_DONE_EINT */ |
3458 | #define WM8962_WSEQ_DONE_EINT_WIDTH 1 /* WSEQ_DONE_EINT */ |
3459 | #define WM8962_DRC_ACTDET_EINT 0x0040 /* DRC_ACTDET_EINT */ |
3460 | #define WM8962_DRC_ACTDET_EINT_MASK 0x0040 /* DRC_ACTDET_EINT */ |
3461 | #define WM8962_DRC_ACTDET_EINT_SHIFT 6 /* DRC_ACTDET_EINT */ |
3462 | #define WM8962_DRC_ACTDET_EINT_WIDTH 1 /* DRC_ACTDET_EINT */ |
3463 | #define WM8962_FLL_LOCK_EINT 0x0020 /* FLL_LOCK_EINT */ |
3464 | #define WM8962_FLL_LOCK_EINT_MASK 0x0020 /* FLL_LOCK_EINT */ |
3465 | #define WM8962_FLL_LOCK_EINT_SHIFT 5 /* FLL_LOCK_EINT */ |
3466 | #define WM8962_FLL_LOCK_EINT_WIDTH 1 /* FLL_LOCK_EINT */ |
3467 | #define WM8962_PLL3_LOCK_EINT 0x0008 /* PLL3_LOCK_EINT */ |
3468 | #define WM8962_PLL3_LOCK_EINT_MASK 0x0008 /* PLL3_LOCK_EINT */ |
3469 | #define WM8962_PLL3_LOCK_EINT_SHIFT 3 /* PLL3_LOCK_EINT */ |
3470 | #define WM8962_PLL3_LOCK_EINT_WIDTH 1 /* PLL3_LOCK_EINT */ |
3471 | #define WM8962_PLL2_LOCK_EINT 0x0004 /* PLL2_LOCK_EINT */ |
3472 | #define WM8962_PLL2_LOCK_EINT_MASK 0x0004 /* PLL2_LOCK_EINT */ |
3473 | #define WM8962_PLL2_LOCK_EINT_SHIFT 2 /* PLL2_LOCK_EINT */ |
3474 | #define WM8962_PLL2_LOCK_EINT_WIDTH 1 /* PLL2_LOCK_EINT */ |
3475 | #define WM8962_TEMP_SHUT_EINT 0x0001 /* TEMP_SHUT_EINT */ |
3476 | #define WM8962_TEMP_SHUT_EINT_MASK 0x0001 /* TEMP_SHUT_EINT */ |
3477 | #define WM8962_TEMP_SHUT_EINT_SHIFT 0 /* TEMP_SHUT_EINT */ |
3478 | #define WM8962_TEMP_SHUT_EINT_WIDTH 1 /* TEMP_SHUT_EINT */ |
3479 | |
3480 | /* |
3481 | * R568 (0x238) - Interrupt Status 1 Mask |
3482 | */ |
3483 | #define WM8962_IM_GP6_EINT 0x0020 /* IM_GP6_EINT */ |
3484 | #define WM8962_IM_GP6_EINT_MASK 0x0020 /* IM_GP6_EINT */ |
3485 | #define WM8962_IM_GP6_EINT_SHIFT 5 /* IM_GP6_EINT */ |
3486 | #define WM8962_IM_GP6_EINT_WIDTH 1 /* IM_GP6_EINT */ |
3487 | #define WM8962_IM_GP5_EINT 0x0010 /* IM_GP5_EINT */ |
3488 | #define WM8962_IM_GP5_EINT_MASK 0x0010 /* IM_GP5_EINT */ |
3489 | #define WM8962_IM_GP5_EINT_SHIFT 4 /* IM_GP5_EINT */ |
3490 | #define WM8962_IM_GP5_EINT_WIDTH 1 /* IM_GP5_EINT */ |
3491 | |
3492 | /* |
3493 | * R569 (0x239) - Interrupt Status 2 Mask |
3494 | */ |
3495 | #define WM8962_IM_MICSCD_EINT 0x8000 /* IM_MICSCD_EINT */ |
3496 | #define WM8962_IM_MICSCD_EINT_MASK 0x8000 /* IM_MICSCD_EINT */ |
3497 | #define WM8962_IM_MICSCD_EINT_SHIFT 15 /* IM_MICSCD_EINT */ |
3498 | #define WM8962_IM_MICSCD_EINT_WIDTH 1 /* IM_MICSCD_EINT */ |
3499 | #define WM8962_IM_MICD_EINT 0x4000 /* IM_MICD_EINT */ |
3500 | #define WM8962_IM_MICD_EINT_MASK 0x4000 /* IM_MICD_EINT */ |
3501 | #define WM8962_IM_MICD_EINT_SHIFT 14 /* IM_MICD_EINT */ |
3502 | #define WM8962_IM_MICD_EINT_WIDTH 1 /* IM_MICD_EINT */ |
3503 | #define WM8962_IM_FIFOS_ERR_EINT 0x2000 /* IM_FIFOS_ERR_EINT */ |
3504 | #define WM8962_IM_FIFOS_ERR_EINT_MASK 0x2000 /* IM_FIFOS_ERR_EINT */ |
3505 | #define WM8962_IM_FIFOS_ERR_EINT_SHIFT 13 /* IM_FIFOS_ERR_EINT */ |
3506 | #define WM8962_IM_FIFOS_ERR_EINT_WIDTH 1 /* IM_FIFOS_ERR_EINT */ |
3507 | #define WM8962_IM_ALC_LOCK_EINT 0x1000 /* IM_ALC_LOCK_EINT */ |
3508 | #define WM8962_IM_ALC_LOCK_EINT_MASK 0x1000 /* IM_ALC_LOCK_EINT */ |
3509 | #define WM8962_IM_ALC_LOCK_EINT_SHIFT 12 /* IM_ALC_LOCK_EINT */ |
3510 | #define WM8962_IM_ALC_LOCK_EINT_WIDTH 1 /* IM_ALC_LOCK_EINT */ |
3511 | #define WM8962_IM_ALC_THRESH_EINT 0x0800 /* IM_ALC_THRESH_EINT */ |
3512 | #define WM8962_IM_ALC_THRESH_EINT_MASK 0x0800 /* IM_ALC_THRESH_EINT */ |
3513 | #define WM8962_IM_ALC_THRESH_EINT_SHIFT 11 /* IM_ALC_THRESH_EINT */ |
3514 | #define WM8962_IM_ALC_THRESH_EINT_WIDTH 1 /* IM_ALC_THRESH_EINT */ |
3515 | #define WM8962_IM_ALC_SAT_EINT 0x0400 /* IM_ALC_SAT_EINT */ |
3516 | #define WM8962_IM_ALC_SAT_EINT_MASK 0x0400 /* IM_ALC_SAT_EINT */ |
3517 | #define WM8962_IM_ALC_SAT_EINT_SHIFT 10 /* IM_ALC_SAT_EINT */ |
3518 | #define WM8962_IM_ALC_SAT_EINT_WIDTH 1 /* IM_ALC_SAT_EINT */ |
3519 | #define WM8962_IM_ALC_PKOVR_EINT 0x0200 /* IM_ALC_PKOVR_EINT */ |
3520 | #define WM8962_IM_ALC_PKOVR_EINT_MASK 0x0200 /* IM_ALC_PKOVR_EINT */ |
3521 | #define WM8962_IM_ALC_PKOVR_EINT_SHIFT 9 /* IM_ALC_PKOVR_EINT */ |
3522 | #define WM8962_IM_ALC_PKOVR_EINT_WIDTH 1 /* IM_ALC_PKOVR_EINT */ |
3523 | #define WM8962_IM_ALC_NGATE_EINT 0x0100 /* IM_ALC_NGATE_EINT */ |
3524 | #define WM8962_IM_ALC_NGATE_EINT_MASK 0x0100 /* IM_ALC_NGATE_EINT */ |
3525 | #define WM8962_IM_ALC_NGATE_EINT_SHIFT 8 /* IM_ALC_NGATE_EINT */ |
3526 | #define WM8962_IM_ALC_NGATE_EINT_WIDTH 1 /* IM_ALC_NGATE_EINT */ |
3527 | #define WM8962_IM_WSEQ_DONE_EINT 0x0080 /* IM_WSEQ_DONE_EINT */ |
3528 | #define WM8962_IM_WSEQ_DONE_EINT_MASK 0x0080 /* IM_WSEQ_DONE_EINT */ |
3529 | #define WM8962_IM_WSEQ_DONE_EINT_SHIFT 7 /* IM_WSEQ_DONE_EINT */ |
3530 | #define WM8962_IM_WSEQ_DONE_EINT_WIDTH 1 /* IM_WSEQ_DONE_EINT */ |
3531 | #define WM8962_IM_DRC_ACTDET_EINT 0x0040 /* IM_DRC_ACTDET_EINT */ |
3532 | #define WM8962_IM_DRC_ACTDET_EINT_MASK 0x0040 /* IM_DRC_ACTDET_EINT */ |
3533 | #define WM8962_IM_DRC_ACTDET_EINT_SHIFT 6 /* IM_DRC_ACTDET_EINT */ |
3534 | #define WM8962_IM_DRC_ACTDET_EINT_WIDTH 1 /* IM_DRC_ACTDET_EINT */ |
3535 | #define WM8962_IM_FLL_LOCK_EINT 0x0020 /* IM_FLL_LOCK_EINT */ |
3536 | #define WM8962_IM_FLL_LOCK_EINT_MASK 0x0020 /* IM_FLL_LOCK_EINT */ |
3537 | #define WM8962_IM_FLL_LOCK_EINT_SHIFT 5 /* IM_FLL_LOCK_EINT */ |
3538 | #define WM8962_IM_FLL_LOCK_EINT_WIDTH 1 /* IM_FLL_LOCK_EINT */ |
3539 | #define WM8962_IM_PLL3_LOCK_EINT 0x0008 /* IM_PLL3_LOCK_EINT */ |
3540 | #define WM8962_IM_PLL3_LOCK_EINT_MASK 0x0008 /* IM_PLL3_LOCK_EINT */ |
3541 | #define WM8962_IM_PLL3_LOCK_EINT_SHIFT 3 /* IM_PLL3_LOCK_EINT */ |
3542 | #define WM8962_IM_PLL3_LOCK_EINT_WIDTH 1 /* IM_PLL3_LOCK_EINT */ |
3543 | #define WM8962_IM_PLL2_LOCK_EINT 0x0004 /* IM_PLL2_LOCK_EINT */ |
3544 | #define WM8962_IM_PLL2_LOCK_EINT_MASK 0x0004 /* IM_PLL2_LOCK_EINT */ |
3545 | #define WM8962_IM_PLL2_LOCK_EINT_SHIFT 2 /* IM_PLL2_LOCK_EINT */ |
3546 | #define WM8962_IM_PLL2_LOCK_EINT_WIDTH 1 /* IM_PLL2_LOCK_EINT */ |
3547 | #define WM8962_IM_TEMP_SHUT_EINT 0x0001 /* IM_TEMP_SHUT_EINT */ |
3548 | #define WM8962_IM_TEMP_SHUT_EINT_MASK 0x0001 /* IM_TEMP_SHUT_EINT */ |
3549 | #define WM8962_IM_TEMP_SHUT_EINT_SHIFT 0 /* IM_TEMP_SHUT_EINT */ |
3550 | #define WM8962_IM_TEMP_SHUT_EINT_WIDTH 1 /* IM_TEMP_SHUT_EINT */ |
3551 | |
3552 | /* |
3553 | * R576 (0x240) - Interrupt Control |
3554 | */ |
3555 | #define WM8962_IRQ_POL 0x0001 /* IRQ_POL */ |
3556 | #define WM8962_IRQ_POL_MASK 0x0001 /* IRQ_POL */ |
3557 | #define WM8962_IRQ_POL_SHIFT 0 /* IRQ_POL */ |
3558 | #define WM8962_IRQ_POL_WIDTH 1 /* IRQ_POL */ |
3559 | |
3560 | /* |
3561 | * R584 (0x248) - IRQ Debounce |
3562 | */ |
3563 | #define WM8962_FLL_LOCK_DB 0x0020 /* FLL_LOCK_DB */ |
3564 | #define WM8962_FLL_LOCK_DB_MASK 0x0020 /* FLL_LOCK_DB */ |
3565 | #define WM8962_FLL_LOCK_DB_SHIFT 5 /* FLL_LOCK_DB */ |
3566 | #define WM8962_FLL_LOCK_DB_WIDTH 1 /* FLL_LOCK_DB */ |
3567 | #define WM8962_PLL3_LOCK_DB 0x0008 /* PLL3_LOCK_DB */ |
3568 | #define WM8962_PLL3_LOCK_DB_MASK 0x0008 /* PLL3_LOCK_DB */ |
3569 | #define WM8962_PLL3_LOCK_DB_SHIFT 3 /* PLL3_LOCK_DB */ |
3570 | #define WM8962_PLL3_LOCK_DB_WIDTH 1 /* PLL3_LOCK_DB */ |
3571 | #define WM8962_PLL2_LOCK_DB 0x0004 /* PLL2_LOCK_DB */ |
3572 | #define WM8962_PLL2_LOCK_DB_MASK 0x0004 /* PLL2_LOCK_DB */ |
3573 | #define WM8962_PLL2_LOCK_DB_SHIFT 2 /* PLL2_LOCK_DB */ |
3574 | #define WM8962_PLL2_LOCK_DB_WIDTH 1 /* PLL2_LOCK_DB */ |
3575 | #define WM8962_TEMP_SHUT_DB 0x0001 /* TEMP_SHUT_DB */ |
3576 | #define WM8962_TEMP_SHUT_DB_MASK 0x0001 /* TEMP_SHUT_DB */ |
3577 | #define WM8962_TEMP_SHUT_DB_SHIFT 0 /* TEMP_SHUT_DB */ |
3578 | #define WM8962_TEMP_SHUT_DB_WIDTH 1 /* TEMP_SHUT_DB */ |
3579 | |
3580 | /* |
3581 | * R586 (0x24A) - MICINT Source Pol |
3582 | */ |
3583 | #define WM8962_MICSCD_IRQ_POL 0x8000 /* MICSCD_IRQ_POL */ |
3584 | #define WM8962_MICSCD_IRQ_POL_MASK 0x8000 /* MICSCD_IRQ_POL */ |
3585 | #define WM8962_MICSCD_IRQ_POL_SHIFT 15 /* MICSCD_IRQ_POL */ |
3586 | #define WM8962_MICSCD_IRQ_POL_WIDTH 1 /* MICSCD_IRQ_POL */ |
3587 | #define WM8962_MICD_IRQ_POL 0x4000 /* MICD_IRQ_POL */ |
3588 | #define WM8962_MICD_IRQ_POL_MASK 0x4000 /* MICD_IRQ_POL */ |
3589 | #define WM8962_MICD_IRQ_POL_SHIFT 14 /* MICD_IRQ_POL */ |
3590 | #define WM8962_MICD_IRQ_POL_WIDTH 1 /* MICD_IRQ_POL */ |
3591 | |
3592 | /* |
3593 | * R768 (0x300) - DSP2 Power Management |
3594 | */ |
3595 | #define WM8962_DSP2_ENA 0x0001 /* DSP2_ENA */ |
3596 | #define WM8962_DSP2_ENA_MASK 0x0001 /* DSP2_ENA */ |
3597 | #define WM8962_DSP2_ENA_SHIFT 0 /* DSP2_ENA */ |
3598 | #define WM8962_DSP2_ENA_WIDTH 1 /* DSP2_ENA */ |
3599 | |
3600 | /* |
3601 | * R1037 (0x40D) - DSP2_ExecControl |
3602 | */ |
3603 | #define WM8962_DSP2_STOPC 0x0020 /* DSP2_STOPC */ |
3604 | #define WM8962_DSP2_STOPC_MASK 0x0020 /* DSP2_STOPC */ |
3605 | #define WM8962_DSP2_STOPC_SHIFT 5 /* DSP2_STOPC */ |
3606 | #define WM8962_DSP2_STOPC_WIDTH 1 /* DSP2_STOPC */ |
3607 | #define WM8962_DSP2_STOPS 0x0010 /* DSP2_STOPS */ |
3608 | #define WM8962_DSP2_STOPS_MASK 0x0010 /* DSP2_STOPS */ |
3609 | #define WM8962_DSP2_STOPS_SHIFT 4 /* DSP2_STOPS */ |
3610 | #define WM8962_DSP2_STOPS_WIDTH 1 /* DSP2_STOPS */ |
3611 | #define WM8962_DSP2_STOPI 0x0008 /* DSP2_STOPI */ |
3612 | #define WM8962_DSP2_STOPI_MASK 0x0008 /* DSP2_STOPI */ |
3613 | #define WM8962_DSP2_STOPI_SHIFT 3 /* DSP2_STOPI */ |
3614 | #define WM8962_DSP2_STOPI_WIDTH 1 /* DSP2_STOPI */ |
3615 | #define WM8962_DSP2_STOP 0x0004 /* DSP2_STOP */ |
3616 | #define WM8962_DSP2_STOP_MASK 0x0004 /* DSP2_STOP */ |
3617 | #define WM8962_DSP2_STOP_SHIFT 2 /* DSP2_STOP */ |
3618 | #define WM8962_DSP2_STOP_WIDTH 1 /* DSP2_STOP */ |
3619 | #define WM8962_DSP2_RUNR 0x0002 /* DSP2_RUNR */ |
3620 | #define WM8962_DSP2_RUNR_MASK 0x0002 /* DSP2_RUNR */ |
3621 | #define WM8962_DSP2_RUNR_SHIFT 1 /* DSP2_RUNR */ |
3622 | #define WM8962_DSP2_RUNR_WIDTH 1 /* DSP2_RUNR */ |
3623 | #define WM8962_DSP2_RUN 0x0001 /* DSP2_RUN */ |
3624 | #define WM8962_DSP2_RUN_MASK 0x0001 /* DSP2_RUN */ |
3625 | #define WM8962_DSP2_RUN_SHIFT 0 /* DSP2_RUN */ |
3626 | #define WM8962_DSP2_RUN_WIDTH 1 /* DSP2_RUN */ |
3627 | |
3628 | /* |
3629 | * R8192 (0x2000) - DSP2 Instruction RAM 0 |
3630 | */ |
3631 | #define WM8962_DSP2_INSTR_RAM_1024_10_9_0_MASK 0x03FF /* DSP2_INSTR_RAM_1024_10_9_0 - [9:0] */ |
3632 | #define WM8962_DSP2_INSTR_RAM_1024_10_9_0_SHIFT 0 /* DSP2_INSTR_RAM_1024_10_9_0 - [9:0] */ |
3633 | #define WM8962_DSP2_INSTR_RAM_1024_10_9_0_WIDTH 10 /* DSP2_INSTR_RAM_1024_10_9_0 - [9:0] */ |
3634 | |
3635 | /* |
3636 | * R9216 (0x2400) - DSP2 Address RAM 2 |
3637 | */ |
3638 | #define WM8962_DSP2_ADDR_RAM_1024_38_37_32_MASK 0x003F /* DSP2_ADDR_RAM_1024_38_37_32 - [5:0] */ |
3639 | #define WM8962_DSP2_ADDR_RAM_1024_38_37_32_SHIFT 0 /* DSP2_ADDR_RAM_1024_38_37_32 - [5:0] */ |
3640 | #define WM8962_DSP2_ADDR_RAM_1024_38_37_32_WIDTH 6 /* DSP2_ADDR_RAM_1024_38_37_32 - [5:0] */ |
3641 | |
3642 | /* |
3643 | * R9217 (0x2401) - DSP2 Address RAM 1 |
3644 | */ |
3645 | #define WM8962_DSP2_ADDR_RAM_1024_38_31_16_MASK 0xFFFF /* DSP2_ADDR_RAM_1024_38_31_16 - [15:0] */ |
3646 | #define WM8962_DSP2_ADDR_RAM_1024_38_31_16_SHIFT 0 /* DSP2_ADDR_RAM_1024_38_31_16 - [15:0] */ |
3647 | #define WM8962_DSP2_ADDR_RAM_1024_38_31_16_WIDTH 16 /* DSP2_ADDR_RAM_1024_38_31_16 - [15:0] */ |
3648 | |
3649 | /* |
3650 | * R9218 (0x2402) - DSP2 Address RAM 0 |
3651 | */ |
3652 | #define WM8962_DSP2_ADDR_RAM_1024_38_15_0_MASK 0xFFFF /* DSP2_ADDR_RAM_1024_38_15_0 - [15:0] */ |
3653 | #define WM8962_DSP2_ADDR_RAM_1024_38_15_0_SHIFT 0 /* DSP2_ADDR_RAM_1024_38_15_0 - [15:0] */ |
3654 | #define WM8962_DSP2_ADDR_RAM_1024_38_15_0_WIDTH 16 /* DSP2_ADDR_RAM_1024_38_15_0 - [15:0] */ |
3655 | |
3656 | /* |
3657 | * R12288 (0x3000) - DSP2 Data1 RAM 1 |
3658 | */ |
3659 | #define WM8962_DSP2_DATA1_RAM_384_24_23_16_MASK 0x00FF /* DSP2_DATA1_RAM_384_24_23_16 - [7:0] */ |
3660 | #define WM8962_DSP2_DATA1_RAM_384_24_23_16_SHIFT 0 /* DSP2_DATA1_RAM_384_24_23_16 - [7:0] */ |
3661 | #define WM8962_DSP2_DATA1_RAM_384_24_23_16_WIDTH 8 /* DSP2_DATA1_RAM_384_24_23_16 - [7:0] */ |
3662 | |
3663 | /* |
3664 | * R12289 (0x3001) - DSP2 Data1 RAM 0 |
3665 | */ |
3666 | #define WM8962_DSP2_DATA1_RAM_384_24_15_0_MASK 0xFFFF /* DSP2_DATA1_RAM_384_24_15_0 - [15:0] */ |
3667 | #define WM8962_DSP2_DATA1_RAM_384_24_15_0_SHIFT 0 /* DSP2_DATA1_RAM_384_24_15_0 - [15:0] */ |
3668 | #define WM8962_DSP2_DATA1_RAM_384_24_15_0_WIDTH 16 /* DSP2_DATA1_RAM_384_24_15_0 - [15:0] */ |
3669 | |
3670 | /* |
3671 | * R13312 (0x3400) - DSP2 Data2 RAM 1 |
3672 | */ |
3673 | #define WM8962_DSP2_DATA2_RAM_384_24_23_16_MASK 0x00FF /* DSP2_DATA2_RAM_384_24_23_16 - [7:0] */ |
3674 | #define WM8962_DSP2_DATA2_RAM_384_24_23_16_SHIFT 0 /* DSP2_DATA2_RAM_384_24_23_16 - [7:0] */ |
3675 | #define WM8962_DSP2_DATA2_RAM_384_24_23_16_WIDTH 8 /* DSP2_DATA2_RAM_384_24_23_16 - [7:0] */ |
3676 | |
3677 | /* |
3678 | * R13313 (0x3401) - DSP2 Data2 RAM 0 |
3679 | */ |
3680 | #define WM8962_DSP2_DATA2_RAM_384_24_15_0_MASK 0xFFFF /* DSP2_DATA2_RAM_384_24_15_0 - [15:0] */ |
3681 | #define WM8962_DSP2_DATA2_RAM_384_24_15_0_SHIFT 0 /* DSP2_DATA2_RAM_384_24_15_0 - [15:0] */ |
3682 | #define WM8962_DSP2_DATA2_RAM_384_24_15_0_WIDTH 16 /* DSP2_DATA2_RAM_384_24_15_0 - [15:0] */ |
3683 | |
3684 | /* |
3685 | * R14336 (0x3800) - DSP2 Data3 RAM 1 |
3686 | */ |
3687 | #define WM8962_DSP2_DATA3_RAM_384_24_23_16_MASK 0x00FF /* DSP2_DATA3_RAM_384_24_23_16 - [7:0] */ |
3688 | #define WM8962_DSP2_DATA3_RAM_384_24_23_16_SHIFT 0 /* DSP2_DATA3_RAM_384_24_23_16 - [7:0] */ |
3689 | #define WM8962_DSP2_DATA3_RAM_384_24_23_16_WIDTH 8 /* DSP2_DATA3_RAM_384_24_23_16 - [7:0] */ |
3690 | |
3691 | /* |
3692 | * R14337 (0x3801) - DSP2 Data3 RAM 0 |
3693 | */ |
3694 | #define WM8962_DSP2_DATA3_RAM_384_24_15_0_MASK 0xFFFF /* DSP2_DATA3_RAM_384_24_15_0 - [15:0] */ |
3695 | #define WM8962_DSP2_DATA3_RAM_384_24_15_0_SHIFT 0 /* DSP2_DATA3_RAM_384_24_15_0 - [15:0] */ |
3696 | #define WM8962_DSP2_DATA3_RAM_384_24_15_0_WIDTH 16 /* DSP2_DATA3_RAM_384_24_15_0 - [15:0] */ |
3697 | |
3698 | /* |
3699 | * R15360 (0x3C00) - DSP2 Coeff RAM 0 |
3700 | */ |
3701 | #define WM8962_DSP2_CMAP_RAM_384_11_10_0_MASK 0x07FF /* DSP2_CMAP_RAM_384_11_10_0 - [10:0] */ |
3702 | #define WM8962_DSP2_CMAP_RAM_384_11_10_0_SHIFT 0 /* DSP2_CMAP_RAM_384_11_10_0 - [10:0] */ |
3703 | #define WM8962_DSP2_CMAP_RAM_384_11_10_0_WIDTH 11 /* DSP2_CMAP_RAM_384_11_10_0 - [10:0] */ |
3704 | |
3705 | /* |
3706 | * R16384 (0x4000) - RETUNEADC_SHARED_COEFF_1 |
3707 | */ |
3708 | #define WM8962_ADC_RETUNE_SCV 0x0080 /* ADC_RETUNE_SCV */ |
3709 | #define WM8962_ADC_RETUNE_SCV_MASK 0x0080 /* ADC_RETUNE_SCV */ |
3710 | #define WM8962_ADC_RETUNE_SCV_SHIFT 7 /* ADC_RETUNE_SCV */ |
3711 | #define WM8962_ADC_RETUNE_SCV_WIDTH 1 /* ADC_RETUNE_SCV */ |
3712 | #define WM8962_RETUNEADC_SHARED_COEFF_22_16_MASK 0x007F /* RETUNEADC_SHARED_COEFF_22_16 - [6:0] */ |
3713 | #define WM8962_RETUNEADC_SHARED_COEFF_22_16_SHIFT 0 /* RETUNEADC_SHARED_COEFF_22_16 - [6:0] */ |
3714 | #define WM8962_RETUNEADC_SHARED_COEFF_22_16_WIDTH 7 /* RETUNEADC_SHARED_COEFF_22_16 - [6:0] */ |
3715 | |
3716 | /* |
3717 | * R16385 (0x4001) - RETUNEADC_SHARED_COEFF_0 |
3718 | */ |
3719 | #define WM8962_RETUNEADC_SHARED_COEFF_15_00_MASK 0xFFFF /* RETUNEADC_SHARED_COEFF_15_00 - [15:0] */ |
3720 | #define WM8962_RETUNEADC_SHARED_COEFF_15_00_SHIFT 0 /* RETUNEADC_SHARED_COEFF_15_00 - [15:0] */ |
3721 | #define WM8962_RETUNEADC_SHARED_COEFF_15_00_WIDTH 16 /* RETUNEADC_SHARED_COEFF_15_00 - [15:0] */ |
3722 | |
3723 | /* |
3724 | * R16386 (0x4002) - RETUNEDAC_SHARED_COEFF_1 |
3725 | */ |
3726 | #define WM8962_DAC_RETUNE_SCV 0x0080 /* DAC_RETUNE_SCV */ |
3727 | #define WM8962_DAC_RETUNE_SCV_MASK 0x0080 /* DAC_RETUNE_SCV */ |
3728 | #define WM8962_DAC_RETUNE_SCV_SHIFT 7 /* DAC_RETUNE_SCV */ |
3729 | #define WM8962_DAC_RETUNE_SCV_WIDTH 1 /* DAC_RETUNE_SCV */ |
3730 | #define WM8962_RETUNEDAC_SHARED_COEFF_23_16_MASK 0x007F /* RETUNEDAC_SHARED_COEFF_23_16 - [6:0] */ |
3731 | #define WM8962_RETUNEDAC_SHARED_COEFF_23_16_SHIFT 0 /* RETUNEDAC_SHARED_COEFF_23_16 - [6:0] */ |
3732 | #define WM8962_RETUNEDAC_SHARED_COEFF_23_16_WIDTH 7 /* RETUNEDAC_SHARED_COEFF_23_16 - [6:0] */ |
3733 | |
3734 | /* |
3735 | * R16387 (0x4003) - RETUNEDAC_SHARED_COEFF_0 |
3736 | */ |
3737 | #define WM8962_RETUNEDAC_SHARED_COEFF_15_00_MASK 0xFFFF /* RETUNEDAC_SHARED_COEFF_15_00 - [15:0] */ |
3738 | #define WM8962_RETUNEDAC_SHARED_COEFF_15_00_SHIFT 0 /* RETUNEDAC_SHARED_COEFF_15_00 - [15:0] */ |
3739 | #define WM8962_RETUNEDAC_SHARED_COEFF_15_00_WIDTH 16 /* RETUNEDAC_SHARED_COEFF_15_00 - [15:0] */ |
3740 | |
3741 | /* |
3742 | * R16388 (0x4004) - SOUNDSTAGE_ENABLES_1 |
3743 | */ |
3744 | #define WM8962_SOUNDSTAGE_ENABLES_23_16_MASK 0x00FF /* SOUNDSTAGE_ENABLES_23_16 - [7:0] */ |
3745 | #define WM8962_SOUNDSTAGE_ENABLES_23_16_SHIFT 0 /* SOUNDSTAGE_ENABLES_23_16 - [7:0] */ |
3746 | #define WM8962_SOUNDSTAGE_ENABLES_23_16_WIDTH 8 /* SOUNDSTAGE_ENABLES_23_16 - [7:0] */ |
3747 | |
3748 | /* |
3749 | * R16389 (0x4005) - SOUNDSTAGE_ENABLES_0 |
3750 | */ |
3751 | #define WM8962_SOUNDSTAGE_ENABLES_15_06_MASK 0xFFC0 /* SOUNDSTAGE_ENABLES_15_06 - [15:6] */ |
3752 | #define WM8962_SOUNDSTAGE_ENABLES_15_06_SHIFT 6 /* SOUNDSTAGE_ENABLES_15_06 - [15:6] */ |
3753 | #define WM8962_SOUNDSTAGE_ENABLES_15_06_WIDTH 10 /* SOUNDSTAGE_ENABLES_15_06 - [15:6] */ |
3754 | #define WM8962_RTN_ADC_ENA 0x0020 /* RTN_ADC_ENA */ |
3755 | #define WM8962_RTN_ADC_ENA_MASK 0x0020 /* RTN_ADC_ENA */ |
3756 | #define WM8962_RTN_ADC_ENA_SHIFT 5 /* RTN_ADC_ENA */ |
3757 | #define WM8962_RTN_ADC_ENA_WIDTH 1 /* RTN_ADC_ENA */ |
3758 | #define WM8962_RTN_DAC_ENA 0x0010 /* RTN_DAC_ENA */ |
3759 | #define WM8962_RTN_DAC_ENA_MASK 0x0010 /* RTN_DAC_ENA */ |
3760 | #define WM8962_RTN_DAC_ENA_SHIFT 4 /* RTN_DAC_ENA */ |
3761 | #define WM8962_RTN_DAC_ENA_WIDTH 1 /* RTN_DAC_ENA */ |
3762 | #define WM8962_HDBASS_ENA 0x0008 /* HDBASS_ENA */ |
3763 | #define WM8962_HDBASS_ENA_MASK 0x0008 /* HDBASS_ENA */ |
3764 | #define WM8962_HDBASS_ENA_SHIFT 3 /* HDBASS_ENA */ |
3765 | #define WM8962_HDBASS_ENA_WIDTH 1 /* HDBASS_ENA */ |
3766 | #define WM8962_HPF2_ENA 0x0004 /* HPF2_ENA */ |
3767 | #define WM8962_HPF2_ENA_MASK 0x0004 /* HPF2_ENA */ |
3768 | #define WM8962_HPF2_ENA_SHIFT 2 /* HPF2_ENA */ |
3769 | #define WM8962_HPF2_ENA_WIDTH 1 /* HPF2_ENA */ |
3770 | #define WM8962_HPF1_ENA 0x0002 /* HPF1_ENA */ |
3771 | #define WM8962_HPF1_ENA_MASK 0x0002 /* HPF1_ENA */ |
3772 | #define WM8962_HPF1_ENA_SHIFT 1 /* HPF1_ENA */ |
3773 | #define WM8962_HPF1_ENA_WIDTH 1 /* HPF1_ENA */ |
3774 | #define WM8962_VSS_ENA 0x0001 /* VSS_ENA */ |
3775 | #define WM8962_VSS_ENA_MASK 0x0001 /* VSS_ENA */ |
3776 | #define WM8962_VSS_ENA_SHIFT 0 /* VSS_ENA */ |
3777 | #define WM8962_VSS_ENA_WIDTH 1 /* VSS_ENA */ |
3778 | |
3779 | int wm8962_mic_detect(struct snd_soc_component *component, struct snd_soc_jack *jack); |
3780 | |
3781 | #endif |
3782 | |