1 | // SPDX-License-Identifier: GPL-2.0-only |
2 | /* |
3 | * wm8962.c -- WM8962 ALSA SoC Audio driver |
4 | * |
5 | * Copyright 2010-2 Wolfson Microelectronics plc |
6 | * |
7 | * Author: Mark Brown <broonie@opensource.wolfsonmicro.com> |
8 | */ |
9 | |
10 | #include <linux/module.h> |
11 | #include <linux/moduleparam.h> |
12 | #include <linux/init.h> |
13 | #include <linux/clk.h> |
14 | #include <linux/delay.h> |
15 | #include <linux/pm.h> |
16 | #include <linux/gcd.h> |
17 | #include <linux/gpio/driver.h> |
18 | #include <linux/i2c.h> |
19 | #include <linux/input.h> |
20 | #include <linux/pm_runtime.h> |
21 | #include <linux/regmap.h> |
22 | #include <linux/regulator/consumer.h> |
23 | #include <linux/slab.h> |
24 | #include <linux/workqueue.h> |
25 | #include <linux/mutex.h> |
26 | #include <sound/core.h> |
27 | #include <sound/jack.h> |
28 | #include <sound/pcm.h> |
29 | #include <sound/pcm_params.h> |
30 | #include <sound/soc.h> |
31 | #include <sound/initval.h> |
32 | #include <sound/tlv.h> |
33 | #include <sound/wm8962.h> |
34 | #include <trace/events/asoc.h> |
35 | |
36 | #include "wm8962.h" |
37 | |
38 | #define WM8962_NUM_SUPPLIES 8 |
39 | static const char *wm8962_supply_names[WM8962_NUM_SUPPLIES] = { |
40 | "DCVDD" , |
41 | "DBVDD" , |
42 | "AVDD" , |
43 | "CPVDD" , |
44 | "MICVDD" , |
45 | "PLLVDD" , |
46 | "SPKVDD1" , |
47 | "SPKVDD2" , |
48 | }; |
49 | |
50 | /* codec private data */ |
51 | struct wm8962_priv { |
52 | struct wm8962_pdata pdata; |
53 | struct regmap *regmap; |
54 | struct snd_soc_component *component; |
55 | |
56 | int sysclk; |
57 | int sysclk_rate; |
58 | |
59 | int bclk; /* Desired BCLK */ |
60 | int lrclk; |
61 | |
62 | struct completion fll_lock; |
63 | int fll_src; |
64 | int fll_fref; |
65 | int fll_fout; |
66 | |
67 | struct mutex dsp2_ena_lock; |
68 | u16 dsp2_ena; |
69 | |
70 | struct delayed_work mic_work; |
71 | struct snd_soc_jack *jack; |
72 | |
73 | struct regulator_bulk_data supplies[WM8962_NUM_SUPPLIES]; |
74 | struct notifier_block disable_nb[WM8962_NUM_SUPPLIES]; |
75 | |
76 | struct input_dev *beep; |
77 | struct work_struct beep_work; |
78 | int beep_rate; |
79 | |
80 | #ifdef CONFIG_GPIOLIB |
81 | struct gpio_chip gpio_chip; |
82 | #endif |
83 | |
84 | int irq; |
85 | }; |
86 | |
87 | /* We can't use the same notifier block for more than one supply and |
88 | * there's no way I can see to get from a callback to the caller |
89 | * except container_of(). |
90 | */ |
91 | #define WM8962_REGULATOR_EVENT(n) \ |
92 | static int wm8962_regulator_event_##n(struct notifier_block *nb, \ |
93 | unsigned long event, void *data) \ |
94 | { \ |
95 | struct wm8962_priv *wm8962 = container_of(nb, struct wm8962_priv, \ |
96 | disable_nb[n]); \ |
97 | if (event & REGULATOR_EVENT_DISABLE) { \ |
98 | regcache_mark_dirty(wm8962->regmap); \ |
99 | } \ |
100 | return 0; \ |
101 | } |
102 | |
103 | WM8962_REGULATOR_EVENT(0) |
104 | WM8962_REGULATOR_EVENT(1) |
105 | WM8962_REGULATOR_EVENT(2) |
106 | WM8962_REGULATOR_EVENT(3) |
107 | WM8962_REGULATOR_EVENT(4) |
108 | WM8962_REGULATOR_EVENT(5) |
109 | WM8962_REGULATOR_EVENT(6) |
110 | WM8962_REGULATOR_EVENT(7) |
111 | |
112 | static const struct reg_default wm8962_reg[] = { |
113 | { 0, 0x009F }, /* R0 - Left Input volume */ |
114 | { 1, 0x049F }, /* R1 - Right Input volume */ |
115 | { 2, 0x0000 }, /* R2 - HPOUTL volume */ |
116 | { 3, 0x0000 }, /* R3 - HPOUTR volume */ |
117 | |
118 | { 5, 0x0018 }, /* R5 - ADC & DAC Control 1 */ |
119 | { 6, 0x2008 }, /* R6 - ADC & DAC Control 2 */ |
120 | { 7, 0x000A }, /* R7 - Audio Interface 0 */ |
121 | { 8, 0x01E4 }, /* R8 - Clocking2 */ |
122 | { 9, 0x0300 }, /* R9 - Audio Interface 1 */ |
123 | { 10, 0x00C0 }, /* R10 - Left DAC volume */ |
124 | { 11, 0x00C0 }, /* R11 - Right DAC volume */ |
125 | |
126 | { 14, 0x0040 }, /* R14 - Audio Interface 2 */ |
127 | { 15, 0x6243 }, /* R15 - Software Reset */ |
128 | |
129 | { 17, 0x007B }, /* R17 - ALC1 */ |
130 | { 18, 0x0000 }, /* R18 - ALC2 */ |
131 | { 19, 0x1C32 }, /* R19 - ALC3 */ |
132 | { 20, 0x3200 }, /* R20 - Noise Gate */ |
133 | { 21, 0x00C0 }, /* R21 - Left ADC volume */ |
134 | { 22, 0x00C0 }, /* R22 - Right ADC volume */ |
135 | { 23, 0x0160 }, /* R23 - Additional control(1) */ |
136 | { 24, 0x0000 }, /* R24 - Additional control(2) */ |
137 | { 25, 0x0000 }, /* R25 - Pwr Mgmt (1) */ |
138 | { 26, 0x0000 }, /* R26 - Pwr Mgmt (2) */ |
139 | { 27, 0x0010 }, /* R27 - Additional Control (3) */ |
140 | { 28, 0x0000 }, /* R28 - Anti-pop */ |
141 | |
142 | { 30, 0x005E }, /* R30 - Clocking 3 */ |
143 | { 31, 0x0000 }, /* R31 - Input mixer control (1) */ |
144 | { 32, 0x0145 }, /* R32 - Left input mixer volume */ |
145 | { 33, 0x0145 }, /* R33 - Right input mixer volume */ |
146 | { 34, 0x0009 }, /* R34 - Input mixer control (2) */ |
147 | { 35, 0x0003 }, /* R35 - Input bias control */ |
148 | { 37, 0x0008 }, /* R37 - Left input PGA control */ |
149 | { 38, 0x0008 }, /* R38 - Right input PGA control */ |
150 | |
151 | { 40, 0x0000 }, /* R40 - SPKOUTL volume */ |
152 | { 41, 0x0000 }, /* R41 - SPKOUTR volume */ |
153 | |
154 | { 49, 0x0010 }, /* R49 - Class D Control 1 */ |
155 | { 51, 0x0003 }, /* R51 - Class D Control 2 */ |
156 | |
157 | { 56, 0x0506 }, /* R56 - Clocking 4 */ |
158 | { 57, 0x0000 }, /* R57 - DAC DSP Mixing (1) */ |
159 | { 58, 0x0000 }, /* R58 - DAC DSP Mixing (2) */ |
160 | |
161 | { 60, 0x0300 }, /* R60 - DC Servo 0 */ |
162 | { 61, 0x0300 }, /* R61 - DC Servo 1 */ |
163 | |
164 | { 64, 0x0810 }, /* R64 - DC Servo 4 */ |
165 | |
166 | { 68, 0x001B }, /* R68 - Analogue PGA Bias */ |
167 | { 69, 0x0000 }, /* R69 - Analogue HP 0 */ |
168 | |
169 | { 71, 0x01FB }, /* R71 - Analogue HP 2 */ |
170 | { 72, 0x0000 }, /* R72 - Charge Pump 1 */ |
171 | |
172 | { 82, 0x0004 }, /* R82 - Charge Pump B */ |
173 | |
174 | { 87, 0x0000 }, /* R87 - Write Sequencer Control 1 */ |
175 | |
176 | { 90, 0x0000 }, /* R90 - Write Sequencer Control 2 */ |
177 | |
178 | { 93, 0x0000 }, /* R93 - Write Sequencer Control 3 */ |
179 | { 94, 0x0000 }, /* R94 - Control Interface */ |
180 | |
181 | { 99, 0x0000 }, /* R99 - Mixer Enables */ |
182 | { 100, 0x0000 }, /* R100 - Headphone Mixer (1) */ |
183 | { 101, 0x0000 }, /* R101 - Headphone Mixer (2) */ |
184 | { 102, 0x013F }, /* R102 - Headphone Mixer (3) */ |
185 | { 103, 0x013F }, /* R103 - Headphone Mixer (4) */ |
186 | |
187 | { 105, 0x0000 }, /* R105 - Speaker Mixer (1) */ |
188 | { 106, 0x0000 }, /* R106 - Speaker Mixer (2) */ |
189 | { 107, 0x013F }, /* R107 - Speaker Mixer (3) */ |
190 | { 108, 0x013F }, /* R108 - Speaker Mixer (4) */ |
191 | { 109, 0x0003 }, /* R109 - Speaker Mixer (5) */ |
192 | { 110, 0x0002 }, /* R110 - Beep Generator (1) */ |
193 | |
194 | { 115, 0x0006 }, /* R115 - Oscillator Trim (3) */ |
195 | { 116, 0x0026 }, /* R116 - Oscillator Trim (4) */ |
196 | |
197 | { 119, 0x0000 }, /* R119 - Oscillator Trim (7) */ |
198 | |
199 | { 124, 0x0011 }, /* R124 - Analogue Clocking1 */ |
200 | { 125, 0x004B }, /* R125 - Analogue Clocking2 */ |
201 | { 126, 0x000D }, /* R126 - Analogue Clocking3 */ |
202 | { 127, 0x0000 }, /* R127 - PLL Software Reset */ |
203 | |
204 | { 131, 0x0000 }, /* R131 - PLL 4 */ |
205 | |
206 | { 136, 0x0067 }, /* R136 - PLL 9 */ |
207 | { 137, 0x001C }, /* R137 - PLL 10 */ |
208 | { 138, 0x0071 }, /* R138 - PLL 11 */ |
209 | { 139, 0x00C7 }, /* R139 - PLL 12 */ |
210 | { 140, 0x0067 }, /* R140 - PLL 13 */ |
211 | { 141, 0x0048 }, /* R141 - PLL 14 */ |
212 | { 142, 0x0022 }, /* R142 - PLL 15 */ |
213 | { 143, 0x0097 }, /* R143 - PLL 16 */ |
214 | |
215 | { 155, 0x000C }, /* R155 - FLL Control (1) */ |
216 | { 156, 0x0039 }, /* R156 - FLL Control (2) */ |
217 | { 157, 0x0180 }, /* R157 - FLL Control (3) */ |
218 | |
219 | { 159, 0x0032 }, /* R159 - FLL Control (5) */ |
220 | { 160, 0x0018 }, /* R160 - FLL Control (6) */ |
221 | { 161, 0x007D }, /* R161 - FLL Control (7) */ |
222 | { 162, 0x0008 }, /* R162 - FLL Control (8) */ |
223 | |
224 | { 252, 0x0005 }, /* R252 - General test 1 */ |
225 | |
226 | { 256, 0x0000 }, /* R256 - DF1 */ |
227 | { 257, 0x0000 }, /* R257 - DF2 */ |
228 | { 258, 0x0000 }, /* R258 - DF3 */ |
229 | { 259, 0x0000 }, /* R259 - DF4 */ |
230 | { 260, 0x0000 }, /* R260 - DF5 */ |
231 | { 261, 0x0000 }, /* R261 - DF6 */ |
232 | { 262, 0x0000 }, /* R262 - DF7 */ |
233 | |
234 | { 264, 0x0000 }, /* R264 - LHPF1 */ |
235 | { 265, 0x0000 }, /* R265 - LHPF2 */ |
236 | |
237 | { 268, 0x0000 }, /* R268 - THREED1 */ |
238 | { 269, 0x0000 }, /* R269 - THREED2 */ |
239 | { 270, 0x0000 }, /* R270 - THREED3 */ |
240 | { 271, 0x0000 }, /* R271 - THREED4 */ |
241 | |
242 | { 276, 0x000C }, /* R276 - DRC 1 */ |
243 | { 277, 0x0925 }, /* R277 - DRC 2 */ |
244 | { 278, 0x0000 }, /* R278 - DRC 3 */ |
245 | { 279, 0x0000 }, /* R279 - DRC 4 */ |
246 | { 280, 0x0000 }, /* R280 - DRC 5 */ |
247 | |
248 | { 285, 0x0000 }, /* R285 - Tloopback */ |
249 | |
250 | { 335, 0x0004 }, /* R335 - EQ1 */ |
251 | { 336, 0x6318 }, /* R336 - EQ2 */ |
252 | { 337, 0x6300 }, /* R337 - EQ3 */ |
253 | { 338, 0x0FCA }, /* R338 - EQ4 */ |
254 | { 339, 0x0400 }, /* R339 - EQ5 */ |
255 | { 340, 0x00D8 }, /* R340 - EQ6 */ |
256 | { 341, 0x1EB5 }, /* R341 - EQ7 */ |
257 | { 342, 0xF145 }, /* R342 - EQ8 */ |
258 | { 343, 0x0B75 }, /* R343 - EQ9 */ |
259 | { 344, 0x01C5 }, /* R344 - EQ10 */ |
260 | { 345, 0x1C58 }, /* R345 - EQ11 */ |
261 | { 346, 0xF373 }, /* R346 - EQ12 */ |
262 | { 347, 0x0A54 }, /* R347 - EQ13 */ |
263 | { 348, 0x0558 }, /* R348 - EQ14 */ |
264 | { 349, 0x168E }, /* R349 - EQ15 */ |
265 | { 350, 0xF829 }, /* R350 - EQ16 */ |
266 | { 351, 0x07AD }, /* R351 - EQ17 */ |
267 | { 352, 0x1103 }, /* R352 - EQ18 */ |
268 | { 353, 0x0564 }, /* R353 - EQ19 */ |
269 | { 354, 0x0559 }, /* R354 - EQ20 */ |
270 | { 355, 0x4000 }, /* R355 - EQ21 */ |
271 | { 356, 0x6318 }, /* R356 - EQ22 */ |
272 | { 357, 0x6300 }, /* R357 - EQ23 */ |
273 | { 358, 0x0FCA }, /* R358 - EQ24 */ |
274 | { 359, 0x0400 }, /* R359 - EQ25 */ |
275 | { 360, 0x00D8 }, /* R360 - EQ26 */ |
276 | { 361, 0x1EB5 }, /* R361 - EQ27 */ |
277 | { 362, 0xF145 }, /* R362 - EQ28 */ |
278 | { 363, 0x0B75 }, /* R363 - EQ29 */ |
279 | { 364, 0x01C5 }, /* R364 - EQ30 */ |
280 | { 365, 0x1C58 }, /* R365 - EQ31 */ |
281 | { 366, 0xF373 }, /* R366 - EQ32 */ |
282 | { 367, 0x0A54 }, /* R367 - EQ33 */ |
283 | { 368, 0x0558 }, /* R368 - EQ34 */ |
284 | { 369, 0x168E }, /* R369 - EQ35 */ |
285 | { 370, 0xF829 }, /* R370 - EQ36 */ |
286 | { 371, 0x07AD }, /* R371 - EQ37 */ |
287 | { 372, 0x1103 }, /* R372 - EQ38 */ |
288 | { 373, 0x0564 }, /* R373 - EQ39 */ |
289 | { 374, 0x0559 }, /* R374 - EQ40 */ |
290 | { 375, 0x4000 }, /* R375 - EQ41 */ |
291 | |
292 | { 513, 0x0000 }, /* R513 - GPIO 2 */ |
293 | { 514, 0x0000 }, /* R514 - GPIO 3 */ |
294 | |
295 | { 516, 0x8100 }, /* R516 - GPIO 5 */ |
296 | { 517, 0x8100 }, /* R517 - GPIO 6 */ |
297 | |
298 | { 568, 0x0030 }, /* R568 - Interrupt Status 1 Mask */ |
299 | { 569, 0xFFED }, /* R569 - Interrupt Status 2 Mask */ |
300 | |
301 | { 576, 0x0000 }, /* R576 - Interrupt Control */ |
302 | |
303 | { 584, 0x002D }, /* R584 - IRQ Debounce */ |
304 | |
305 | { 586, 0x0000 }, /* R586 - MICINT Source Pol */ |
306 | |
307 | { 768, 0x1C00 }, /* R768 - DSP2 Power Management */ |
308 | |
309 | { 8192, 0x0000 }, /* R8192 - DSP2 Instruction RAM 0 */ |
310 | |
311 | { 9216, 0x0030 }, /* R9216 - DSP2 Address RAM 2 */ |
312 | { 9217, 0x0000 }, /* R9217 - DSP2 Address RAM 1 */ |
313 | { 9218, 0x0000 }, /* R9218 - DSP2 Address RAM 0 */ |
314 | |
315 | { 12288, 0x0000 }, /* R12288 - DSP2 Data1 RAM 1 */ |
316 | { 12289, 0x0000 }, /* R12289 - DSP2 Data1 RAM 0 */ |
317 | |
318 | { 13312, 0x0000 }, /* R13312 - DSP2 Data2 RAM 1 */ |
319 | { 13313, 0x0000 }, /* R13313 - DSP2 Data2 RAM 0 */ |
320 | |
321 | { 14336, 0x0000 }, /* R14336 - DSP2 Data3 RAM 1 */ |
322 | { 14337, 0x0000 }, /* R14337 - DSP2 Data3 RAM 0 */ |
323 | |
324 | { 15360, 0x000A }, /* R15360 - DSP2 Coeff RAM 0 */ |
325 | |
326 | { 16384, 0x0000 }, /* R16384 - RETUNEADC_SHARED_COEFF_1 */ |
327 | { 16385, 0x0000 }, /* R16385 - RETUNEADC_SHARED_COEFF_0 */ |
328 | { 16386, 0x0000 }, /* R16386 - RETUNEDAC_SHARED_COEFF_1 */ |
329 | { 16387, 0x0000 }, /* R16387 - RETUNEDAC_SHARED_COEFF_0 */ |
330 | { 16388, 0x0000 }, /* R16388 - SOUNDSTAGE_ENABLES_1 */ |
331 | { 16389, 0x0000 }, /* R16389 - SOUNDSTAGE_ENABLES_0 */ |
332 | |
333 | { 16896, 0x0002 }, /* R16896 - HDBASS_AI_1 */ |
334 | { 16897, 0xBD12 }, /* R16897 - HDBASS_AI_0 */ |
335 | { 16898, 0x007C }, /* R16898 - HDBASS_AR_1 */ |
336 | { 16899, 0x586C }, /* R16899 - HDBASS_AR_0 */ |
337 | { 16900, 0x0053 }, /* R16900 - HDBASS_B_1 */ |
338 | { 16901, 0x8121 }, /* R16901 - HDBASS_B_0 */ |
339 | { 16902, 0x003F }, /* R16902 - HDBASS_K_1 */ |
340 | { 16903, 0x8BD8 }, /* R16903 - HDBASS_K_0 */ |
341 | { 16904, 0x0032 }, /* R16904 - HDBASS_N1_1 */ |
342 | { 16905, 0xF52D }, /* R16905 - HDBASS_N1_0 */ |
343 | { 16906, 0x0065 }, /* R16906 - HDBASS_N2_1 */ |
344 | { 16907, 0xAC8C }, /* R16907 - HDBASS_N2_0 */ |
345 | { 16908, 0x006B }, /* R16908 - HDBASS_N3_1 */ |
346 | { 16909, 0xE087 }, /* R16909 - HDBASS_N3_0 */ |
347 | { 16910, 0x0072 }, /* R16910 - HDBASS_N4_1 */ |
348 | { 16911, 0x1483 }, /* R16911 - HDBASS_N4_0 */ |
349 | { 16912, 0x0072 }, /* R16912 - HDBASS_N5_1 */ |
350 | { 16913, 0x1483 }, /* R16913 - HDBASS_N5_0 */ |
351 | { 16914, 0x0043 }, /* R16914 - HDBASS_X1_1 */ |
352 | { 16915, 0x3525 }, /* R16915 - HDBASS_X1_0 */ |
353 | { 16916, 0x0006 }, /* R16916 - HDBASS_X2_1 */ |
354 | { 16917, 0x6A4A }, /* R16917 - HDBASS_X2_0 */ |
355 | { 16918, 0x0043 }, /* R16918 - HDBASS_X3_1 */ |
356 | { 16919, 0x6079 }, /* R16919 - HDBASS_X3_0 */ |
357 | { 16920, 0x0008 }, /* R16920 - HDBASS_ATK_1 */ |
358 | { 16921, 0x0000 }, /* R16921 - HDBASS_ATK_0 */ |
359 | { 16922, 0x0001 }, /* R16922 - HDBASS_DCY_1 */ |
360 | { 16923, 0x0000 }, /* R16923 - HDBASS_DCY_0 */ |
361 | { 16924, 0x0059 }, /* R16924 - HDBASS_PG_1 */ |
362 | { 16925, 0x999A }, /* R16925 - HDBASS_PG_0 */ |
363 | |
364 | { 17408, 0x0083 }, /* R17408 - HPF_C_1 */ |
365 | { 17409, 0x98AD }, /* R17409 - HPF_C_0 */ |
366 | |
367 | { 17920, 0x007F }, /* R17920 - ADCL_RETUNE_C1_1 */ |
368 | { 17921, 0xFFFF }, /* R17921 - ADCL_RETUNE_C1_0 */ |
369 | { 17922, 0x0000 }, /* R17922 - ADCL_RETUNE_C2_1 */ |
370 | { 17923, 0x0000 }, /* R17923 - ADCL_RETUNE_C2_0 */ |
371 | { 17924, 0x0000 }, /* R17924 - ADCL_RETUNE_C3_1 */ |
372 | { 17925, 0x0000 }, /* R17925 - ADCL_RETUNE_C3_0 */ |
373 | { 17926, 0x0000 }, /* R17926 - ADCL_RETUNE_C4_1 */ |
374 | { 17927, 0x0000 }, /* R17927 - ADCL_RETUNE_C4_0 */ |
375 | { 17928, 0x0000 }, /* R17928 - ADCL_RETUNE_C5_1 */ |
376 | { 17929, 0x0000 }, /* R17929 - ADCL_RETUNE_C5_0 */ |
377 | { 17930, 0x0000 }, /* R17930 - ADCL_RETUNE_C6_1 */ |
378 | { 17931, 0x0000 }, /* R17931 - ADCL_RETUNE_C6_0 */ |
379 | { 17932, 0x0000 }, /* R17932 - ADCL_RETUNE_C7_1 */ |
380 | { 17933, 0x0000 }, /* R17933 - ADCL_RETUNE_C7_0 */ |
381 | { 17934, 0x0000 }, /* R17934 - ADCL_RETUNE_C8_1 */ |
382 | { 17935, 0x0000 }, /* R17935 - ADCL_RETUNE_C8_0 */ |
383 | { 17936, 0x0000 }, /* R17936 - ADCL_RETUNE_C9_1 */ |
384 | { 17937, 0x0000 }, /* R17937 - ADCL_RETUNE_C9_0 */ |
385 | { 17938, 0x0000 }, /* R17938 - ADCL_RETUNE_C10_1 */ |
386 | { 17939, 0x0000 }, /* R17939 - ADCL_RETUNE_C10_0 */ |
387 | { 17940, 0x0000 }, /* R17940 - ADCL_RETUNE_C11_1 */ |
388 | { 17941, 0x0000 }, /* R17941 - ADCL_RETUNE_C11_0 */ |
389 | { 17942, 0x0000 }, /* R17942 - ADCL_RETUNE_C12_1 */ |
390 | { 17943, 0x0000 }, /* R17943 - ADCL_RETUNE_C12_0 */ |
391 | { 17944, 0x0000 }, /* R17944 - ADCL_RETUNE_C13_1 */ |
392 | { 17945, 0x0000 }, /* R17945 - ADCL_RETUNE_C13_0 */ |
393 | { 17946, 0x0000 }, /* R17946 - ADCL_RETUNE_C14_1 */ |
394 | { 17947, 0x0000 }, /* R17947 - ADCL_RETUNE_C14_0 */ |
395 | { 17948, 0x0000 }, /* R17948 - ADCL_RETUNE_C15_1 */ |
396 | { 17949, 0x0000 }, /* R17949 - ADCL_RETUNE_C15_0 */ |
397 | { 17950, 0x0000 }, /* R17950 - ADCL_RETUNE_C16_1 */ |
398 | { 17951, 0x0000 }, /* R17951 - ADCL_RETUNE_C16_0 */ |
399 | { 17952, 0x0000 }, /* R17952 - ADCL_RETUNE_C17_1 */ |
400 | { 17953, 0x0000 }, /* R17953 - ADCL_RETUNE_C17_0 */ |
401 | { 17954, 0x0000 }, /* R17954 - ADCL_RETUNE_C18_1 */ |
402 | { 17955, 0x0000 }, /* R17955 - ADCL_RETUNE_C18_0 */ |
403 | { 17956, 0x0000 }, /* R17956 - ADCL_RETUNE_C19_1 */ |
404 | { 17957, 0x0000 }, /* R17957 - ADCL_RETUNE_C19_0 */ |
405 | { 17958, 0x0000 }, /* R17958 - ADCL_RETUNE_C20_1 */ |
406 | { 17959, 0x0000 }, /* R17959 - ADCL_RETUNE_C20_0 */ |
407 | { 17960, 0x0000 }, /* R17960 - ADCL_RETUNE_C21_1 */ |
408 | { 17961, 0x0000 }, /* R17961 - ADCL_RETUNE_C21_0 */ |
409 | { 17962, 0x0000 }, /* R17962 - ADCL_RETUNE_C22_1 */ |
410 | { 17963, 0x0000 }, /* R17963 - ADCL_RETUNE_C22_0 */ |
411 | { 17964, 0x0000 }, /* R17964 - ADCL_RETUNE_C23_1 */ |
412 | { 17965, 0x0000 }, /* R17965 - ADCL_RETUNE_C23_0 */ |
413 | { 17966, 0x0000 }, /* R17966 - ADCL_RETUNE_C24_1 */ |
414 | { 17967, 0x0000 }, /* R17967 - ADCL_RETUNE_C24_0 */ |
415 | { 17968, 0x0000 }, /* R17968 - ADCL_RETUNE_C25_1 */ |
416 | { 17969, 0x0000 }, /* R17969 - ADCL_RETUNE_C25_0 */ |
417 | { 17970, 0x0000 }, /* R17970 - ADCL_RETUNE_C26_1 */ |
418 | { 17971, 0x0000 }, /* R17971 - ADCL_RETUNE_C26_0 */ |
419 | { 17972, 0x0000 }, /* R17972 - ADCL_RETUNE_C27_1 */ |
420 | { 17973, 0x0000 }, /* R17973 - ADCL_RETUNE_C27_0 */ |
421 | { 17974, 0x0000 }, /* R17974 - ADCL_RETUNE_C28_1 */ |
422 | { 17975, 0x0000 }, /* R17975 - ADCL_RETUNE_C28_0 */ |
423 | { 17976, 0x0000 }, /* R17976 - ADCL_RETUNE_C29_1 */ |
424 | { 17977, 0x0000 }, /* R17977 - ADCL_RETUNE_C29_0 */ |
425 | { 17978, 0x0000 }, /* R17978 - ADCL_RETUNE_C30_1 */ |
426 | { 17979, 0x0000 }, /* R17979 - ADCL_RETUNE_C30_0 */ |
427 | { 17980, 0x0000 }, /* R17980 - ADCL_RETUNE_C31_1 */ |
428 | { 17981, 0x0000 }, /* R17981 - ADCL_RETUNE_C31_0 */ |
429 | { 17982, 0x0000 }, /* R17982 - ADCL_RETUNE_C32_1 */ |
430 | { 17983, 0x0000 }, /* R17983 - ADCL_RETUNE_C32_0 */ |
431 | |
432 | { 18432, 0x0020 }, /* R18432 - RETUNEADC_PG2_1 */ |
433 | { 18433, 0x0000 }, /* R18433 - RETUNEADC_PG2_0 */ |
434 | { 18434, 0x0040 }, /* R18434 - RETUNEADC_PG_1 */ |
435 | { 18435, 0x0000 }, /* R18435 - RETUNEADC_PG_0 */ |
436 | |
437 | { 18944, 0x007F }, /* R18944 - ADCR_RETUNE_C1_1 */ |
438 | { 18945, 0xFFFF }, /* R18945 - ADCR_RETUNE_C1_0 */ |
439 | { 18946, 0x0000 }, /* R18946 - ADCR_RETUNE_C2_1 */ |
440 | { 18947, 0x0000 }, /* R18947 - ADCR_RETUNE_C2_0 */ |
441 | { 18948, 0x0000 }, /* R18948 - ADCR_RETUNE_C3_1 */ |
442 | { 18949, 0x0000 }, /* R18949 - ADCR_RETUNE_C3_0 */ |
443 | { 18950, 0x0000 }, /* R18950 - ADCR_RETUNE_C4_1 */ |
444 | { 18951, 0x0000 }, /* R18951 - ADCR_RETUNE_C4_0 */ |
445 | { 18952, 0x0000 }, /* R18952 - ADCR_RETUNE_C5_1 */ |
446 | { 18953, 0x0000 }, /* R18953 - ADCR_RETUNE_C5_0 */ |
447 | { 18954, 0x0000 }, /* R18954 - ADCR_RETUNE_C6_1 */ |
448 | { 18955, 0x0000 }, /* R18955 - ADCR_RETUNE_C6_0 */ |
449 | { 18956, 0x0000 }, /* R18956 - ADCR_RETUNE_C7_1 */ |
450 | { 18957, 0x0000 }, /* R18957 - ADCR_RETUNE_C7_0 */ |
451 | { 18958, 0x0000 }, /* R18958 - ADCR_RETUNE_C8_1 */ |
452 | { 18959, 0x0000 }, /* R18959 - ADCR_RETUNE_C8_0 */ |
453 | { 18960, 0x0000 }, /* R18960 - ADCR_RETUNE_C9_1 */ |
454 | { 18961, 0x0000 }, /* R18961 - ADCR_RETUNE_C9_0 */ |
455 | { 18962, 0x0000 }, /* R18962 - ADCR_RETUNE_C10_1 */ |
456 | { 18963, 0x0000 }, /* R18963 - ADCR_RETUNE_C10_0 */ |
457 | { 18964, 0x0000 }, /* R18964 - ADCR_RETUNE_C11_1 */ |
458 | { 18965, 0x0000 }, /* R18965 - ADCR_RETUNE_C11_0 */ |
459 | { 18966, 0x0000 }, /* R18966 - ADCR_RETUNE_C12_1 */ |
460 | { 18967, 0x0000 }, /* R18967 - ADCR_RETUNE_C12_0 */ |
461 | { 18968, 0x0000 }, /* R18968 - ADCR_RETUNE_C13_1 */ |
462 | { 18969, 0x0000 }, /* R18969 - ADCR_RETUNE_C13_0 */ |
463 | { 18970, 0x0000 }, /* R18970 - ADCR_RETUNE_C14_1 */ |
464 | { 18971, 0x0000 }, /* R18971 - ADCR_RETUNE_C14_0 */ |
465 | { 18972, 0x0000 }, /* R18972 - ADCR_RETUNE_C15_1 */ |
466 | { 18973, 0x0000 }, /* R18973 - ADCR_RETUNE_C15_0 */ |
467 | { 18974, 0x0000 }, /* R18974 - ADCR_RETUNE_C16_1 */ |
468 | { 18975, 0x0000 }, /* R18975 - ADCR_RETUNE_C16_0 */ |
469 | { 18976, 0x0000 }, /* R18976 - ADCR_RETUNE_C17_1 */ |
470 | { 18977, 0x0000 }, /* R18977 - ADCR_RETUNE_C17_0 */ |
471 | { 18978, 0x0000 }, /* R18978 - ADCR_RETUNE_C18_1 */ |
472 | { 18979, 0x0000 }, /* R18979 - ADCR_RETUNE_C18_0 */ |
473 | { 18980, 0x0000 }, /* R18980 - ADCR_RETUNE_C19_1 */ |
474 | { 18981, 0x0000 }, /* R18981 - ADCR_RETUNE_C19_0 */ |
475 | { 18982, 0x0000 }, /* R18982 - ADCR_RETUNE_C20_1 */ |
476 | { 18983, 0x0000 }, /* R18983 - ADCR_RETUNE_C20_0 */ |
477 | { 18984, 0x0000 }, /* R18984 - ADCR_RETUNE_C21_1 */ |
478 | { 18985, 0x0000 }, /* R18985 - ADCR_RETUNE_C21_0 */ |
479 | { 18986, 0x0000 }, /* R18986 - ADCR_RETUNE_C22_1 */ |
480 | { 18987, 0x0000 }, /* R18987 - ADCR_RETUNE_C22_0 */ |
481 | { 18988, 0x0000 }, /* R18988 - ADCR_RETUNE_C23_1 */ |
482 | { 18989, 0x0000 }, /* R18989 - ADCR_RETUNE_C23_0 */ |
483 | { 18990, 0x0000 }, /* R18990 - ADCR_RETUNE_C24_1 */ |
484 | { 18991, 0x0000 }, /* R18991 - ADCR_RETUNE_C24_0 */ |
485 | { 18992, 0x0000 }, /* R18992 - ADCR_RETUNE_C25_1 */ |
486 | { 18993, 0x0000 }, /* R18993 - ADCR_RETUNE_C25_0 */ |
487 | { 18994, 0x0000 }, /* R18994 - ADCR_RETUNE_C26_1 */ |
488 | { 18995, 0x0000 }, /* R18995 - ADCR_RETUNE_C26_0 */ |
489 | { 18996, 0x0000 }, /* R18996 - ADCR_RETUNE_C27_1 */ |
490 | { 18997, 0x0000 }, /* R18997 - ADCR_RETUNE_C27_0 */ |
491 | { 18998, 0x0000 }, /* R18998 - ADCR_RETUNE_C28_1 */ |
492 | { 18999, 0x0000 }, /* R18999 - ADCR_RETUNE_C28_0 */ |
493 | { 19000, 0x0000 }, /* R19000 - ADCR_RETUNE_C29_1 */ |
494 | { 19001, 0x0000 }, /* R19001 - ADCR_RETUNE_C29_0 */ |
495 | { 19002, 0x0000 }, /* R19002 - ADCR_RETUNE_C30_1 */ |
496 | { 19003, 0x0000 }, /* R19003 - ADCR_RETUNE_C30_0 */ |
497 | { 19004, 0x0000 }, /* R19004 - ADCR_RETUNE_C31_1 */ |
498 | { 19005, 0x0000 }, /* R19005 - ADCR_RETUNE_C31_0 */ |
499 | { 19006, 0x0000 }, /* R19006 - ADCR_RETUNE_C32_1 */ |
500 | { 19007, 0x0000 }, /* R19007 - ADCR_RETUNE_C32_0 */ |
501 | |
502 | { 19456, 0x007F }, /* R19456 - DACL_RETUNE_C1_1 */ |
503 | { 19457, 0xFFFF }, /* R19457 - DACL_RETUNE_C1_0 */ |
504 | { 19458, 0x0000 }, /* R19458 - DACL_RETUNE_C2_1 */ |
505 | { 19459, 0x0000 }, /* R19459 - DACL_RETUNE_C2_0 */ |
506 | { 19460, 0x0000 }, /* R19460 - DACL_RETUNE_C3_1 */ |
507 | { 19461, 0x0000 }, /* R19461 - DACL_RETUNE_C3_0 */ |
508 | { 19462, 0x0000 }, /* R19462 - DACL_RETUNE_C4_1 */ |
509 | { 19463, 0x0000 }, /* R19463 - DACL_RETUNE_C4_0 */ |
510 | { 19464, 0x0000 }, /* R19464 - DACL_RETUNE_C5_1 */ |
511 | { 19465, 0x0000 }, /* R19465 - DACL_RETUNE_C5_0 */ |
512 | { 19466, 0x0000 }, /* R19466 - DACL_RETUNE_C6_1 */ |
513 | { 19467, 0x0000 }, /* R19467 - DACL_RETUNE_C6_0 */ |
514 | { 19468, 0x0000 }, /* R19468 - DACL_RETUNE_C7_1 */ |
515 | { 19469, 0x0000 }, /* R19469 - DACL_RETUNE_C7_0 */ |
516 | { 19470, 0x0000 }, /* R19470 - DACL_RETUNE_C8_1 */ |
517 | { 19471, 0x0000 }, /* R19471 - DACL_RETUNE_C8_0 */ |
518 | { 19472, 0x0000 }, /* R19472 - DACL_RETUNE_C9_1 */ |
519 | { 19473, 0x0000 }, /* R19473 - DACL_RETUNE_C9_0 */ |
520 | { 19474, 0x0000 }, /* R19474 - DACL_RETUNE_C10_1 */ |
521 | { 19475, 0x0000 }, /* R19475 - DACL_RETUNE_C10_0 */ |
522 | { 19476, 0x0000 }, /* R19476 - DACL_RETUNE_C11_1 */ |
523 | { 19477, 0x0000 }, /* R19477 - DACL_RETUNE_C11_0 */ |
524 | { 19478, 0x0000 }, /* R19478 - DACL_RETUNE_C12_1 */ |
525 | { 19479, 0x0000 }, /* R19479 - DACL_RETUNE_C12_0 */ |
526 | { 19480, 0x0000 }, /* R19480 - DACL_RETUNE_C13_1 */ |
527 | { 19481, 0x0000 }, /* R19481 - DACL_RETUNE_C13_0 */ |
528 | { 19482, 0x0000 }, /* R19482 - DACL_RETUNE_C14_1 */ |
529 | { 19483, 0x0000 }, /* R19483 - DACL_RETUNE_C14_0 */ |
530 | { 19484, 0x0000 }, /* R19484 - DACL_RETUNE_C15_1 */ |
531 | { 19485, 0x0000 }, /* R19485 - DACL_RETUNE_C15_0 */ |
532 | { 19486, 0x0000 }, /* R19486 - DACL_RETUNE_C16_1 */ |
533 | { 19487, 0x0000 }, /* R19487 - DACL_RETUNE_C16_0 */ |
534 | { 19488, 0x0000 }, /* R19488 - DACL_RETUNE_C17_1 */ |
535 | { 19489, 0x0000 }, /* R19489 - DACL_RETUNE_C17_0 */ |
536 | { 19490, 0x0000 }, /* R19490 - DACL_RETUNE_C18_1 */ |
537 | { 19491, 0x0000 }, /* R19491 - DACL_RETUNE_C18_0 */ |
538 | { 19492, 0x0000 }, /* R19492 - DACL_RETUNE_C19_1 */ |
539 | { 19493, 0x0000 }, /* R19493 - DACL_RETUNE_C19_0 */ |
540 | { 19494, 0x0000 }, /* R19494 - DACL_RETUNE_C20_1 */ |
541 | { 19495, 0x0000 }, /* R19495 - DACL_RETUNE_C20_0 */ |
542 | { 19496, 0x0000 }, /* R19496 - DACL_RETUNE_C21_1 */ |
543 | { 19497, 0x0000 }, /* R19497 - DACL_RETUNE_C21_0 */ |
544 | { 19498, 0x0000 }, /* R19498 - DACL_RETUNE_C22_1 */ |
545 | { 19499, 0x0000 }, /* R19499 - DACL_RETUNE_C22_0 */ |
546 | { 19500, 0x0000 }, /* R19500 - DACL_RETUNE_C23_1 */ |
547 | { 19501, 0x0000 }, /* R19501 - DACL_RETUNE_C23_0 */ |
548 | { 19502, 0x0000 }, /* R19502 - DACL_RETUNE_C24_1 */ |
549 | { 19503, 0x0000 }, /* R19503 - DACL_RETUNE_C24_0 */ |
550 | { 19504, 0x0000 }, /* R19504 - DACL_RETUNE_C25_1 */ |
551 | { 19505, 0x0000 }, /* R19505 - DACL_RETUNE_C25_0 */ |
552 | { 19506, 0x0000 }, /* R19506 - DACL_RETUNE_C26_1 */ |
553 | { 19507, 0x0000 }, /* R19507 - DACL_RETUNE_C26_0 */ |
554 | { 19508, 0x0000 }, /* R19508 - DACL_RETUNE_C27_1 */ |
555 | { 19509, 0x0000 }, /* R19509 - DACL_RETUNE_C27_0 */ |
556 | { 19510, 0x0000 }, /* R19510 - DACL_RETUNE_C28_1 */ |
557 | { 19511, 0x0000 }, /* R19511 - DACL_RETUNE_C28_0 */ |
558 | { 19512, 0x0000 }, /* R19512 - DACL_RETUNE_C29_1 */ |
559 | { 19513, 0x0000 }, /* R19513 - DACL_RETUNE_C29_0 */ |
560 | { 19514, 0x0000 }, /* R19514 - DACL_RETUNE_C30_1 */ |
561 | { 19515, 0x0000 }, /* R19515 - DACL_RETUNE_C30_0 */ |
562 | { 19516, 0x0000 }, /* R19516 - DACL_RETUNE_C31_1 */ |
563 | { 19517, 0x0000 }, /* R19517 - DACL_RETUNE_C31_0 */ |
564 | { 19518, 0x0000 }, /* R19518 - DACL_RETUNE_C32_1 */ |
565 | { 19519, 0x0000 }, /* R19519 - DACL_RETUNE_C32_0 */ |
566 | |
567 | { 19968, 0x0020 }, /* R19968 - RETUNEDAC_PG2_1 */ |
568 | { 19969, 0x0000 }, /* R19969 - RETUNEDAC_PG2_0 */ |
569 | { 19970, 0x0040 }, /* R19970 - RETUNEDAC_PG_1 */ |
570 | { 19971, 0x0000 }, /* R19971 - RETUNEDAC_PG_0 */ |
571 | |
572 | { 20480, 0x007F }, /* R20480 - DACR_RETUNE_C1_1 */ |
573 | { 20481, 0xFFFF }, /* R20481 - DACR_RETUNE_C1_0 */ |
574 | { 20482, 0x0000 }, /* R20482 - DACR_RETUNE_C2_1 */ |
575 | { 20483, 0x0000 }, /* R20483 - DACR_RETUNE_C2_0 */ |
576 | { 20484, 0x0000 }, /* R20484 - DACR_RETUNE_C3_1 */ |
577 | { 20485, 0x0000 }, /* R20485 - DACR_RETUNE_C3_0 */ |
578 | { 20486, 0x0000 }, /* R20486 - DACR_RETUNE_C4_1 */ |
579 | { 20487, 0x0000 }, /* R20487 - DACR_RETUNE_C4_0 */ |
580 | { 20488, 0x0000 }, /* R20488 - DACR_RETUNE_C5_1 */ |
581 | { 20489, 0x0000 }, /* R20489 - DACR_RETUNE_C5_0 */ |
582 | { 20490, 0x0000 }, /* R20490 - DACR_RETUNE_C6_1 */ |
583 | { 20491, 0x0000 }, /* R20491 - DACR_RETUNE_C6_0 */ |
584 | { 20492, 0x0000 }, /* R20492 - DACR_RETUNE_C7_1 */ |
585 | { 20493, 0x0000 }, /* R20493 - DACR_RETUNE_C7_0 */ |
586 | { 20494, 0x0000 }, /* R20494 - DACR_RETUNE_C8_1 */ |
587 | { 20495, 0x0000 }, /* R20495 - DACR_RETUNE_C8_0 */ |
588 | { 20496, 0x0000 }, /* R20496 - DACR_RETUNE_C9_1 */ |
589 | { 20497, 0x0000 }, /* R20497 - DACR_RETUNE_C9_0 */ |
590 | { 20498, 0x0000 }, /* R20498 - DACR_RETUNE_C10_1 */ |
591 | { 20499, 0x0000 }, /* R20499 - DACR_RETUNE_C10_0 */ |
592 | { 20500, 0x0000 }, /* R20500 - DACR_RETUNE_C11_1 */ |
593 | { 20501, 0x0000 }, /* R20501 - DACR_RETUNE_C11_0 */ |
594 | { 20502, 0x0000 }, /* R20502 - DACR_RETUNE_C12_1 */ |
595 | { 20503, 0x0000 }, /* R20503 - DACR_RETUNE_C12_0 */ |
596 | { 20504, 0x0000 }, /* R20504 - DACR_RETUNE_C13_1 */ |
597 | { 20505, 0x0000 }, /* R20505 - DACR_RETUNE_C13_0 */ |
598 | { 20506, 0x0000 }, /* R20506 - DACR_RETUNE_C14_1 */ |
599 | { 20507, 0x0000 }, /* R20507 - DACR_RETUNE_C14_0 */ |
600 | { 20508, 0x0000 }, /* R20508 - DACR_RETUNE_C15_1 */ |
601 | { 20509, 0x0000 }, /* R20509 - DACR_RETUNE_C15_0 */ |
602 | { 20510, 0x0000 }, /* R20510 - DACR_RETUNE_C16_1 */ |
603 | { 20511, 0x0000 }, /* R20511 - DACR_RETUNE_C16_0 */ |
604 | { 20512, 0x0000 }, /* R20512 - DACR_RETUNE_C17_1 */ |
605 | { 20513, 0x0000 }, /* R20513 - DACR_RETUNE_C17_0 */ |
606 | { 20514, 0x0000 }, /* R20514 - DACR_RETUNE_C18_1 */ |
607 | { 20515, 0x0000 }, /* R20515 - DACR_RETUNE_C18_0 */ |
608 | { 20516, 0x0000 }, /* R20516 - DACR_RETUNE_C19_1 */ |
609 | { 20517, 0x0000 }, /* R20517 - DACR_RETUNE_C19_0 */ |
610 | { 20518, 0x0000 }, /* R20518 - DACR_RETUNE_C20_1 */ |
611 | { 20519, 0x0000 }, /* R20519 - DACR_RETUNE_C20_0 */ |
612 | { 20520, 0x0000 }, /* R20520 - DACR_RETUNE_C21_1 */ |
613 | { 20521, 0x0000 }, /* R20521 - DACR_RETUNE_C21_0 */ |
614 | { 20522, 0x0000 }, /* R20522 - DACR_RETUNE_C22_1 */ |
615 | { 20523, 0x0000 }, /* R20523 - DACR_RETUNE_C22_0 */ |
616 | { 20524, 0x0000 }, /* R20524 - DACR_RETUNE_C23_1 */ |
617 | { 20525, 0x0000 }, /* R20525 - DACR_RETUNE_C23_0 */ |
618 | { 20526, 0x0000 }, /* R20526 - DACR_RETUNE_C24_1 */ |
619 | { 20527, 0x0000 }, /* R20527 - DACR_RETUNE_C24_0 */ |
620 | { 20528, 0x0000 }, /* R20528 - DACR_RETUNE_C25_1 */ |
621 | { 20529, 0x0000 }, /* R20529 - DACR_RETUNE_C25_0 */ |
622 | { 20530, 0x0000 }, /* R20530 - DACR_RETUNE_C26_1 */ |
623 | { 20531, 0x0000 }, /* R20531 - DACR_RETUNE_C26_0 */ |
624 | { 20532, 0x0000 }, /* R20532 - DACR_RETUNE_C27_1 */ |
625 | { 20533, 0x0000 }, /* R20533 - DACR_RETUNE_C27_0 */ |
626 | { 20534, 0x0000 }, /* R20534 - DACR_RETUNE_C28_1 */ |
627 | { 20535, 0x0000 }, /* R20535 - DACR_RETUNE_C28_0 */ |
628 | { 20536, 0x0000 }, /* R20536 - DACR_RETUNE_C29_1 */ |
629 | { 20537, 0x0000 }, /* R20537 - DACR_RETUNE_C29_0 */ |
630 | { 20538, 0x0000 }, /* R20538 - DACR_RETUNE_C30_1 */ |
631 | { 20539, 0x0000 }, /* R20539 - DACR_RETUNE_C30_0 */ |
632 | { 20540, 0x0000 }, /* R20540 - DACR_RETUNE_C31_1 */ |
633 | { 20541, 0x0000 }, /* R20541 - DACR_RETUNE_C31_0 */ |
634 | { 20542, 0x0000 }, /* R20542 - DACR_RETUNE_C32_1 */ |
635 | { 20543, 0x0000 }, /* R20543 - DACR_RETUNE_C32_0 */ |
636 | |
637 | { 20992, 0x008C }, /* R20992 - VSS_XHD2_1 */ |
638 | { 20993, 0x0200 }, /* R20993 - VSS_XHD2_0 */ |
639 | { 20994, 0x0035 }, /* R20994 - VSS_XHD3_1 */ |
640 | { 20995, 0x0700 }, /* R20995 - VSS_XHD3_0 */ |
641 | { 20996, 0x003A }, /* R20996 - VSS_XHN1_1 */ |
642 | { 20997, 0x4100 }, /* R20997 - VSS_XHN1_0 */ |
643 | { 20998, 0x008B }, /* R20998 - VSS_XHN2_1 */ |
644 | { 20999, 0x7D00 }, /* R20999 - VSS_XHN2_0 */ |
645 | { 21000, 0x003A }, /* R21000 - VSS_XHN3_1 */ |
646 | { 21001, 0x4100 }, /* R21001 - VSS_XHN3_0 */ |
647 | { 21002, 0x008C }, /* R21002 - VSS_XLA_1 */ |
648 | { 21003, 0xFEE8 }, /* R21003 - VSS_XLA_0 */ |
649 | { 21004, 0x0078 }, /* R21004 - VSS_XLB_1 */ |
650 | { 21005, 0x0000 }, /* R21005 - VSS_XLB_0 */ |
651 | { 21006, 0x003F }, /* R21006 - VSS_XLG_1 */ |
652 | { 21007, 0xB260 }, /* R21007 - VSS_XLG_0 */ |
653 | { 21008, 0x002D }, /* R21008 - VSS_PG2_1 */ |
654 | { 21009, 0x1818 }, /* R21009 - VSS_PG2_0 */ |
655 | { 21010, 0x0020 }, /* R21010 - VSS_PG_1 */ |
656 | { 21011, 0x0000 }, /* R21011 - VSS_PG_0 */ |
657 | { 21012, 0x00F1 }, /* R21012 - VSS_XTD1_1 */ |
658 | { 21013, 0x8340 }, /* R21013 - VSS_XTD1_0 */ |
659 | { 21014, 0x00FB }, /* R21014 - VSS_XTD2_1 */ |
660 | { 21015, 0x8300 }, /* R21015 - VSS_XTD2_0 */ |
661 | { 21016, 0x00EE }, /* R21016 - VSS_XTD3_1 */ |
662 | { 21017, 0xAEC0 }, /* R21017 - VSS_XTD3_0 */ |
663 | { 21018, 0x00FB }, /* R21018 - VSS_XTD4_1 */ |
664 | { 21019, 0xAC40 }, /* R21019 - VSS_XTD4_0 */ |
665 | { 21020, 0x00F1 }, /* R21020 - VSS_XTD5_1 */ |
666 | { 21021, 0x7F80 }, /* R21021 - VSS_XTD5_0 */ |
667 | { 21022, 0x00F4 }, /* R21022 - VSS_XTD6_1 */ |
668 | { 21023, 0x3B40 }, /* R21023 - VSS_XTD6_0 */ |
669 | { 21024, 0x00F5 }, /* R21024 - VSS_XTD7_1 */ |
670 | { 21025, 0xFB00 }, /* R21025 - VSS_XTD7_0 */ |
671 | { 21026, 0x00EA }, /* R21026 - VSS_XTD8_1 */ |
672 | { 21027, 0x10C0 }, /* R21027 - VSS_XTD8_0 */ |
673 | { 21028, 0x00FC }, /* R21028 - VSS_XTD9_1 */ |
674 | { 21029, 0xC580 }, /* R21029 - VSS_XTD9_0 */ |
675 | { 21030, 0x00E2 }, /* R21030 - VSS_XTD10_1 */ |
676 | { 21031, 0x75C0 }, /* R21031 - VSS_XTD10_0 */ |
677 | { 21032, 0x0004 }, /* R21032 - VSS_XTD11_1 */ |
678 | { 21033, 0xB480 }, /* R21033 - VSS_XTD11_0 */ |
679 | { 21034, 0x00D4 }, /* R21034 - VSS_XTD12_1 */ |
680 | { 21035, 0xF980 }, /* R21035 - VSS_XTD12_0 */ |
681 | { 21036, 0x0004 }, /* R21036 - VSS_XTD13_1 */ |
682 | { 21037, 0x9140 }, /* R21037 - VSS_XTD13_0 */ |
683 | { 21038, 0x00D8 }, /* R21038 - VSS_XTD14_1 */ |
684 | { 21039, 0xA480 }, /* R21039 - VSS_XTD14_0 */ |
685 | { 21040, 0x0002 }, /* R21040 - VSS_XTD15_1 */ |
686 | { 21041, 0x3DC0 }, /* R21041 - VSS_XTD15_0 */ |
687 | { 21042, 0x00CF }, /* R21042 - VSS_XTD16_1 */ |
688 | { 21043, 0x7A80 }, /* R21043 - VSS_XTD16_0 */ |
689 | { 21044, 0x00DC }, /* R21044 - VSS_XTD17_1 */ |
690 | { 21045, 0x0600 }, /* R21045 - VSS_XTD17_0 */ |
691 | { 21046, 0x00F2 }, /* R21046 - VSS_XTD18_1 */ |
692 | { 21047, 0xDAC0 }, /* R21047 - VSS_XTD18_0 */ |
693 | { 21048, 0x00BA }, /* R21048 - VSS_XTD19_1 */ |
694 | { 21049, 0xF340 }, /* R21049 - VSS_XTD19_0 */ |
695 | { 21050, 0x000A }, /* R21050 - VSS_XTD20_1 */ |
696 | { 21051, 0x7940 }, /* R21051 - VSS_XTD20_0 */ |
697 | { 21052, 0x001C }, /* R21052 - VSS_XTD21_1 */ |
698 | { 21053, 0x0680 }, /* R21053 - VSS_XTD21_0 */ |
699 | { 21054, 0x00FD }, /* R21054 - VSS_XTD22_1 */ |
700 | { 21055, 0x2D00 }, /* R21055 - VSS_XTD22_0 */ |
701 | { 21056, 0x001C }, /* R21056 - VSS_XTD23_1 */ |
702 | { 21057, 0xE840 }, /* R21057 - VSS_XTD23_0 */ |
703 | { 21058, 0x000D }, /* R21058 - VSS_XTD24_1 */ |
704 | { 21059, 0xDC40 }, /* R21059 - VSS_XTD24_0 */ |
705 | { 21060, 0x00FC }, /* R21060 - VSS_XTD25_1 */ |
706 | { 21061, 0x9D00 }, /* R21061 - VSS_XTD25_0 */ |
707 | { 21062, 0x0009 }, /* R21062 - VSS_XTD26_1 */ |
708 | { 21063, 0x5580 }, /* R21063 - VSS_XTD26_0 */ |
709 | { 21064, 0x00FE }, /* R21064 - VSS_XTD27_1 */ |
710 | { 21065, 0x7E80 }, /* R21065 - VSS_XTD27_0 */ |
711 | { 21066, 0x000E }, /* R21066 - VSS_XTD28_1 */ |
712 | { 21067, 0xAB40 }, /* R21067 - VSS_XTD28_0 */ |
713 | { 21068, 0x00F9 }, /* R21068 - VSS_XTD29_1 */ |
714 | { 21069, 0x9880 }, /* R21069 - VSS_XTD29_0 */ |
715 | { 21070, 0x0009 }, /* R21070 - VSS_XTD30_1 */ |
716 | { 21071, 0x87C0 }, /* R21071 - VSS_XTD30_0 */ |
717 | { 21072, 0x00FD }, /* R21072 - VSS_XTD31_1 */ |
718 | { 21073, 0x2C40 }, /* R21073 - VSS_XTD31_0 */ |
719 | { 21074, 0x0009 }, /* R21074 - VSS_XTD32_1 */ |
720 | { 21075, 0x4800 }, /* R21075 - VSS_XTD32_0 */ |
721 | { 21076, 0x0003 }, /* R21076 - VSS_XTS1_1 */ |
722 | { 21077, 0x5F40 }, /* R21077 - VSS_XTS1_0 */ |
723 | { 21078, 0x0000 }, /* R21078 - VSS_XTS2_1 */ |
724 | { 21079, 0x8700 }, /* R21079 - VSS_XTS2_0 */ |
725 | { 21080, 0x00FA }, /* R21080 - VSS_XTS3_1 */ |
726 | { 21081, 0xE4C0 }, /* R21081 - VSS_XTS3_0 */ |
727 | { 21082, 0x0000 }, /* R21082 - VSS_XTS4_1 */ |
728 | { 21083, 0x0B40 }, /* R21083 - VSS_XTS4_0 */ |
729 | { 21084, 0x0004 }, /* R21084 - VSS_XTS5_1 */ |
730 | { 21085, 0xE180 }, /* R21085 - VSS_XTS5_0 */ |
731 | { 21086, 0x0001 }, /* R21086 - VSS_XTS6_1 */ |
732 | { 21087, 0x1F40 }, /* R21087 - VSS_XTS6_0 */ |
733 | { 21088, 0x00F8 }, /* R21088 - VSS_XTS7_1 */ |
734 | { 21089, 0xB000 }, /* R21089 - VSS_XTS7_0 */ |
735 | { 21090, 0x00FB }, /* R21090 - VSS_XTS8_1 */ |
736 | { 21091, 0xCBC0 }, /* R21091 - VSS_XTS8_0 */ |
737 | { 21092, 0x0004 }, /* R21092 - VSS_XTS9_1 */ |
738 | { 21093, 0xF380 }, /* R21093 - VSS_XTS9_0 */ |
739 | { 21094, 0x0007 }, /* R21094 - VSS_XTS10_1 */ |
740 | { 21095, 0xDF40 }, /* R21095 - VSS_XTS10_0 */ |
741 | { 21096, 0x00FF }, /* R21096 - VSS_XTS11_1 */ |
742 | { 21097, 0x0700 }, /* R21097 - VSS_XTS11_0 */ |
743 | { 21098, 0x00EF }, /* R21098 - VSS_XTS12_1 */ |
744 | { 21099, 0xD700 }, /* R21099 - VSS_XTS12_0 */ |
745 | { 21100, 0x00FB }, /* R21100 - VSS_XTS13_1 */ |
746 | { 21101, 0xAF40 }, /* R21101 - VSS_XTS13_0 */ |
747 | { 21102, 0x0010 }, /* R21102 - VSS_XTS14_1 */ |
748 | { 21103, 0x8A80 }, /* R21103 - VSS_XTS14_0 */ |
749 | { 21104, 0x0011 }, /* R21104 - VSS_XTS15_1 */ |
750 | { 21105, 0x07C0 }, /* R21105 - VSS_XTS15_0 */ |
751 | { 21106, 0x00E0 }, /* R21106 - VSS_XTS16_1 */ |
752 | { 21107, 0x0800 }, /* R21107 - VSS_XTS16_0 */ |
753 | { 21108, 0x00D2 }, /* R21108 - VSS_XTS17_1 */ |
754 | { 21109, 0x7600 }, /* R21109 - VSS_XTS17_0 */ |
755 | { 21110, 0x0020 }, /* R21110 - VSS_XTS18_1 */ |
756 | { 21111, 0xCF40 }, /* R21111 - VSS_XTS18_0 */ |
757 | { 21112, 0x0030 }, /* R21112 - VSS_XTS19_1 */ |
758 | { 21113, 0x2340 }, /* R21113 - VSS_XTS19_0 */ |
759 | { 21114, 0x00FD }, /* R21114 - VSS_XTS20_1 */ |
760 | { 21115, 0x69C0 }, /* R21115 - VSS_XTS20_0 */ |
761 | { 21116, 0x0028 }, /* R21116 - VSS_XTS21_1 */ |
762 | { 21117, 0x3500 }, /* R21117 - VSS_XTS21_0 */ |
763 | { 21118, 0x0006 }, /* R21118 - VSS_XTS22_1 */ |
764 | { 21119, 0x3300 }, /* R21119 - VSS_XTS22_0 */ |
765 | { 21120, 0x00D9 }, /* R21120 - VSS_XTS23_1 */ |
766 | { 21121, 0xF6C0 }, /* R21121 - VSS_XTS23_0 */ |
767 | { 21122, 0x00F3 }, /* R21122 - VSS_XTS24_1 */ |
768 | { 21123, 0x3340 }, /* R21123 - VSS_XTS24_0 */ |
769 | { 21124, 0x000F }, /* R21124 - VSS_XTS25_1 */ |
770 | { 21125, 0x4200 }, /* R21125 - VSS_XTS25_0 */ |
771 | { 21126, 0x0004 }, /* R21126 - VSS_XTS26_1 */ |
772 | { 21127, 0x0C80 }, /* R21127 - VSS_XTS26_0 */ |
773 | { 21128, 0x00FB }, /* R21128 - VSS_XTS27_1 */ |
774 | { 21129, 0x3F80 }, /* R21129 - VSS_XTS27_0 */ |
775 | { 21130, 0x00F7 }, /* R21130 - VSS_XTS28_1 */ |
776 | { 21131, 0x57C0 }, /* R21131 - VSS_XTS28_0 */ |
777 | { 21132, 0x0003 }, /* R21132 - VSS_XTS29_1 */ |
778 | { 21133, 0x5400 }, /* R21133 - VSS_XTS29_0 */ |
779 | { 21134, 0x0000 }, /* R21134 - VSS_XTS30_1 */ |
780 | { 21135, 0xC6C0 }, /* R21135 - VSS_XTS30_0 */ |
781 | { 21136, 0x0003 }, /* R21136 - VSS_XTS31_1 */ |
782 | { 21137, 0x12C0 }, /* R21137 - VSS_XTS31_0 */ |
783 | { 21138, 0x00FD }, /* R21138 - VSS_XTS32_1 */ |
784 | { 21139, 0x8580 }, /* R21139 - VSS_XTS32_0 */ |
785 | }; |
786 | |
787 | static bool wm8962_volatile_register(struct device *dev, unsigned int reg) |
788 | { |
789 | switch (reg) { |
790 | case WM8962_CLOCKING1: |
791 | case WM8962_SOFTWARE_RESET: |
792 | case WM8962_THERMAL_SHUTDOWN_STATUS: |
793 | case WM8962_ADDITIONAL_CONTROL_4: |
794 | case WM8962_DC_SERVO_6: |
795 | case WM8962_INTERRUPT_STATUS_1: |
796 | case WM8962_INTERRUPT_STATUS_2: |
797 | case WM8962_DSP2_EXECCONTROL: |
798 | return true; |
799 | default: |
800 | return false; |
801 | } |
802 | } |
803 | |
804 | static bool wm8962_readable_register(struct device *dev, unsigned int reg) |
805 | { |
806 | switch (reg) { |
807 | case WM8962_LEFT_INPUT_VOLUME: |
808 | case WM8962_RIGHT_INPUT_VOLUME: |
809 | case WM8962_HPOUTL_VOLUME: |
810 | case WM8962_HPOUTR_VOLUME: |
811 | case WM8962_CLOCKING1: |
812 | case WM8962_ADC_DAC_CONTROL_1: |
813 | case WM8962_ADC_DAC_CONTROL_2: |
814 | case WM8962_AUDIO_INTERFACE_0: |
815 | case WM8962_CLOCKING2: |
816 | case WM8962_AUDIO_INTERFACE_1: |
817 | case WM8962_LEFT_DAC_VOLUME: |
818 | case WM8962_RIGHT_DAC_VOLUME: |
819 | case WM8962_AUDIO_INTERFACE_2: |
820 | case WM8962_SOFTWARE_RESET: |
821 | case WM8962_ALC1: |
822 | case WM8962_ALC2: |
823 | case WM8962_ALC3: |
824 | case WM8962_NOISE_GATE: |
825 | case WM8962_LEFT_ADC_VOLUME: |
826 | case WM8962_RIGHT_ADC_VOLUME: |
827 | case WM8962_ADDITIONAL_CONTROL_1: |
828 | case WM8962_ADDITIONAL_CONTROL_2: |
829 | case WM8962_PWR_MGMT_1: |
830 | case WM8962_PWR_MGMT_2: |
831 | case WM8962_ADDITIONAL_CONTROL_3: |
832 | case WM8962_ANTI_POP: |
833 | case WM8962_CLOCKING_3: |
834 | case WM8962_INPUT_MIXER_CONTROL_1: |
835 | case WM8962_LEFT_INPUT_MIXER_VOLUME: |
836 | case WM8962_RIGHT_INPUT_MIXER_VOLUME: |
837 | case WM8962_INPUT_MIXER_CONTROL_2: |
838 | case WM8962_INPUT_BIAS_CONTROL: |
839 | case WM8962_LEFT_INPUT_PGA_CONTROL: |
840 | case WM8962_RIGHT_INPUT_PGA_CONTROL: |
841 | case WM8962_SPKOUTL_VOLUME: |
842 | case WM8962_SPKOUTR_VOLUME: |
843 | case WM8962_THERMAL_SHUTDOWN_STATUS: |
844 | case WM8962_ADDITIONAL_CONTROL_4: |
845 | case WM8962_CLASS_D_CONTROL_1: |
846 | case WM8962_CLASS_D_CONTROL_2: |
847 | case WM8962_CLOCKING_4: |
848 | case WM8962_DAC_DSP_MIXING_1: |
849 | case WM8962_DAC_DSP_MIXING_2: |
850 | case WM8962_DC_SERVO_0: |
851 | case WM8962_DC_SERVO_1: |
852 | case WM8962_DC_SERVO_4: |
853 | case WM8962_DC_SERVO_6: |
854 | case WM8962_ANALOGUE_PGA_BIAS: |
855 | case WM8962_ANALOGUE_HP_0: |
856 | case WM8962_ANALOGUE_HP_2: |
857 | case WM8962_CHARGE_PUMP_1: |
858 | case WM8962_CHARGE_PUMP_B: |
859 | case WM8962_WRITE_SEQUENCER_CONTROL_1: |
860 | case WM8962_WRITE_SEQUENCER_CONTROL_2: |
861 | case WM8962_WRITE_SEQUENCER_CONTROL_3: |
862 | case WM8962_CONTROL_INTERFACE: |
863 | case WM8962_MIXER_ENABLES: |
864 | case WM8962_HEADPHONE_MIXER_1: |
865 | case WM8962_HEADPHONE_MIXER_2: |
866 | case WM8962_HEADPHONE_MIXER_3: |
867 | case WM8962_HEADPHONE_MIXER_4: |
868 | case WM8962_SPEAKER_MIXER_1: |
869 | case WM8962_SPEAKER_MIXER_2: |
870 | case WM8962_SPEAKER_MIXER_3: |
871 | case WM8962_SPEAKER_MIXER_4: |
872 | case WM8962_SPEAKER_MIXER_5: |
873 | case WM8962_BEEP_GENERATOR_1: |
874 | case WM8962_OSCILLATOR_TRIM_3: |
875 | case WM8962_OSCILLATOR_TRIM_4: |
876 | case WM8962_OSCILLATOR_TRIM_7: |
877 | case WM8962_ANALOGUE_CLOCKING1: |
878 | case WM8962_ANALOGUE_CLOCKING2: |
879 | case WM8962_ANALOGUE_CLOCKING3: |
880 | case WM8962_PLL_SOFTWARE_RESET: |
881 | case WM8962_PLL2: |
882 | case WM8962_PLL_4: |
883 | case WM8962_PLL_9: |
884 | case WM8962_PLL_10: |
885 | case WM8962_PLL_11: |
886 | case WM8962_PLL_12: |
887 | case WM8962_PLL_13: |
888 | case WM8962_PLL_14: |
889 | case WM8962_PLL_15: |
890 | case WM8962_PLL_16: |
891 | case WM8962_FLL_CONTROL_1: |
892 | case WM8962_FLL_CONTROL_2: |
893 | case WM8962_FLL_CONTROL_3: |
894 | case WM8962_FLL_CONTROL_5: |
895 | case WM8962_FLL_CONTROL_6: |
896 | case WM8962_FLL_CONTROL_7: |
897 | case WM8962_FLL_CONTROL_8: |
898 | case WM8962_GENERAL_TEST_1: |
899 | case WM8962_DF1: |
900 | case WM8962_DF2: |
901 | case WM8962_DF3: |
902 | case WM8962_DF4: |
903 | case WM8962_DF5: |
904 | case WM8962_DF6: |
905 | case WM8962_DF7: |
906 | case WM8962_LHPF1: |
907 | case WM8962_LHPF2: |
908 | case WM8962_THREED1: |
909 | case WM8962_THREED2: |
910 | case WM8962_THREED3: |
911 | case WM8962_THREED4: |
912 | case WM8962_DRC_1: |
913 | case WM8962_DRC_2: |
914 | case WM8962_DRC_3: |
915 | case WM8962_DRC_4: |
916 | case WM8962_DRC_5: |
917 | case WM8962_TLOOPBACK: |
918 | case WM8962_EQ1: |
919 | case WM8962_EQ2: |
920 | case WM8962_EQ3: |
921 | case WM8962_EQ4: |
922 | case WM8962_EQ5: |
923 | case WM8962_EQ6: |
924 | case WM8962_EQ7: |
925 | case WM8962_EQ8: |
926 | case WM8962_EQ9: |
927 | case WM8962_EQ10: |
928 | case WM8962_EQ11: |
929 | case WM8962_EQ12: |
930 | case WM8962_EQ13: |
931 | case WM8962_EQ14: |
932 | case WM8962_EQ15: |
933 | case WM8962_EQ16: |
934 | case WM8962_EQ17: |
935 | case WM8962_EQ18: |
936 | case WM8962_EQ19: |
937 | case WM8962_EQ20: |
938 | case WM8962_EQ21: |
939 | case WM8962_EQ22: |
940 | case WM8962_EQ23: |
941 | case WM8962_EQ24: |
942 | case WM8962_EQ25: |
943 | case WM8962_EQ26: |
944 | case WM8962_EQ27: |
945 | case WM8962_EQ28: |
946 | case WM8962_EQ29: |
947 | case WM8962_EQ30: |
948 | case WM8962_EQ31: |
949 | case WM8962_EQ32: |
950 | case WM8962_EQ33: |
951 | case WM8962_EQ34: |
952 | case WM8962_EQ35: |
953 | case WM8962_EQ36: |
954 | case WM8962_EQ37: |
955 | case WM8962_EQ38: |
956 | case WM8962_EQ39: |
957 | case WM8962_EQ40: |
958 | case WM8962_EQ41: |
959 | case WM8962_GPIO_2: |
960 | case WM8962_GPIO_3: |
961 | case WM8962_GPIO_5: |
962 | case WM8962_GPIO_6: |
963 | case WM8962_INTERRUPT_STATUS_1: |
964 | case WM8962_INTERRUPT_STATUS_2: |
965 | case WM8962_INTERRUPT_STATUS_1_MASK: |
966 | case WM8962_INTERRUPT_STATUS_2_MASK: |
967 | case WM8962_INTERRUPT_CONTROL: |
968 | case WM8962_IRQ_DEBOUNCE: |
969 | case WM8962_MICINT_SOURCE_POL: |
970 | case WM8962_DSP2_POWER_MANAGEMENT: |
971 | case WM8962_DSP2_EXECCONTROL: |
972 | case WM8962_DSP2_INSTRUCTION_RAM_0: |
973 | case WM8962_DSP2_ADDRESS_RAM_2: |
974 | case WM8962_DSP2_ADDRESS_RAM_1: |
975 | case WM8962_DSP2_ADDRESS_RAM_0: |
976 | case WM8962_DSP2_DATA1_RAM_1: |
977 | case WM8962_DSP2_DATA1_RAM_0: |
978 | case WM8962_DSP2_DATA2_RAM_1: |
979 | case WM8962_DSP2_DATA2_RAM_0: |
980 | case WM8962_DSP2_DATA3_RAM_1: |
981 | case WM8962_DSP2_DATA3_RAM_0: |
982 | case WM8962_DSP2_COEFF_RAM_0: |
983 | case WM8962_RETUNEADC_SHARED_COEFF_1: |
984 | case WM8962_RETUNEADC_SHARED_COEFF_0: |
985 | case WM8962_RETUNEDAC_SHARED_COEFF_1: |
986 | case WM8962_RETUNEDAC_SHARED_COEFF_0: |
987 | case WM8962_SOUNDSTAGE_ENABLES_1: |
988 | case WM8962_SOUNDSTAGE_ENABLES_0: |
989 | case WM8962_HDBASS_AI_1: |
990 | case WM8962_HDBASS_AI_0: |
991 | case WM8962_HDBASS_AR_1: |
992 | case WM8962_HDBASS_AR_0: |
993 | case WM8962_HDBASS_B_1: |
994 | case WM8962_HDBASS_B_0: |
995 | case WM8962_HDBASS_K_1: |
996 | case WM8962_HDBASS_K_0: |
997 | case WM8962_HDBASS_N1_1: |
998 | case WM8962_HDBASS_N1_0: |
999 | case WM8962_HDBASS_N2_1: |
1000 | case WM8962_HDBASS_N2_0: |
1001 | case WM8962_HDBASS_N3_1: |
1002 | case WM8962_HDBASS_N3_0: |
1003 | case WM8962_HDBASS_N4_1: |
1004 | case WM8962_HDBASS_N4_0: |
1005 | case WM8962_HDBASS_N5_1: |
1006 | case WM8962_HDBASS_N5_0: |
1007 | case WM8962_HDBASS_X1_1: |
1008 | case WM8962_HDBASS_X1_0: |
1009 | case WM8962_HDBASS_X2_1: |
1010 | case WM8962_HDBASS_X2_0: |
1011 | case WM8962_HDBASS_X3_1: |
1012 | case WM8962_HDBASS_X3_0: |
1013 | case WM8962_HDBASS_ATK_1: |
1014 | case WM8962_HDBASS_ATK_0: |
1015 | case WM8962_HDBASS_DCY_1: |
1016 | case WM8962_HDBASS_DCY_0: |
1017 | case WM8962_HDBASS_PG_1: |
1018 | case WM8962_HDBASS_PG_0: |
1019 | case WM8962_HPF_C_1: |
1020 | case WM8962_HPF_C_0: |
1021 | case WM8962_ADCL_RETUNE_C1_1: |
1022 | case WM8962_ADCL_RETUNE_C1_0: |
1023 | case WM8962_ADCL_RETUNE_C2_1: |
1024 | case WM8962_ADCL_RETUNE_C2_0: |
1025 | case WM8962_ADCL_RETUNE_C3_1: |
1026 | case WM8962_ADCL_RETUNE_C3_0: |
1027 | case WM8962_ADCL_RETUNE_C4_1: |
1028 | case WM8962_ADCL_RETUNE_C4_0: |
1029 | case WM8962_ADCL_RETUNE_C5_1: |
1030 | case WM8962_ADCL_RETUNE_C5_0: |
1031 | case WM8962_ADCL_RETUNE_C6_1: |
1032 | case WM8962_ADCL_RETUNE_C6_0: |
1033 | case WM8962_ADCL_RETUNE_C7_1: |
1034 | case WM8962_ADCL_RETUNE_C7_0: |
1035 | case WM8962_ADCL_RETUNE_C8_1: |
1036 | case WM8962_ADCL_RETUNE_C8_0: |
1037 | case WM8962_ADCL_RETUNE_C9_1: |
1038 | case WM8962_ADCL_RETUNE_C9_0: |
1039 | case WM8962_ADCL_RETUNE_C10_1: |
1040 | case WM8962_ADCL_RETUNE_C10_0: |
1041 | case WM8962_ADCL_RETUNE_C11_1: |
1042 | case WM8962_ADCL_RETUNE_C11_0: |
1043 | case WM8962_ADCL_RETUNE_C12_1: |
1044 | case WM8962_ADCL_RETUNE_C12_0: |
1045 | case WM8962_ADCL_RETUNE_C13_1: |
1046 | case WM8962_ADCL_RETUNE_C13_0: |
1047 | case WM8962_ADCL_RETUNE_C14_1: |
1048 | case WM8962_ADCL_RETUNE_C14_0: |
1049 | case WM8962_ADCL_RETUNE_C15_1: |
1050 | case WM8962_ADCL_RETUNE_C15_0: |
1051 | case WM8962_ADCL_RETUNE_C16_1: |
1052 | case WM8962_ADCL_RETUNE_C16_0: |
1053 | case WM8962_ADCL_RETUNE_C17_1: |
1054 | case WM8962_ADCL_RETUNE_C17_0: |
1055 | case WM8962_ADCL_RETUNE_C18_1: |
1056 | case WM8962_ADCL_RETUNE_C18_0: |
1057 | case WM8962_ADCL_RETUNE_C19_1: |
1058 | case WM8962_ADCL_RETUNE_C19_0: |
1059 | case WM8962_ADCL_RETUNE_C20_1: |
1060 | case WM8962_ADCL_RETUNE_C20_0: |
1061 | case WM8962_ADCL_RETUNE_C21_1: |
1062 | case WM8962_ADCL_RETUNE_C21_0: |
1063 | case WM8962_ADCL_RETUNE_C22_1: |
1064 | case WM8962_ADCL_RETUNE_C22_0: |
1065 | case WM8962_ADCL_RETUNE_C23_1: |
1066 | case WM8962_ADCL_RETUNE_C23_0: |
1067 | case WM8962_ADCL_RETUNE_C24_1: |
1068 | case WM8962_ADCL_RETUNE_C24_0: |
1069 | case WM8962_ADCL_RETUNE_C25_1: |
1070 | case WM8962_ADCL_RETUNE_C25_0: |
1071 | case WM8962_ADCL_RETUNE_C26_1: |
1072 | case WM8962_ADCL_RETUNE_C26_0: |
1073 | case WM8962_ADCL_RETUNE_C27_1: |
1074 | case WM8962_ADCL_RETUNE_C27_0: |
1075 | case WM8962_ADCL_RETUNE_C28_1: |
1076 | case WM8962_ADCL_RETUNE_C28_0: |
1077 | case WM8962_ADCL_RETUNE_C29_1: |
1078 | case WM8962_ADCL_RETUNE_C29_0: |
1079 | case WM8962_ADCL_RETUNE_C30_1: |
1080 | case WM8962_ADCL_RETUNE_C30_0: |
1081 | case WM8962_ADCL_RETUNE_C31_1: |
1082 | case WM8962_ADCL_RETUNE_C31_0: |
1083 | case WM8962_ADCL_RETUNE_C32_1: |
1084 | case WM8962_ADCL_RETUNE_C32_0: |
1085 | case WM8962_RETUNEADC_PG2_1: |
1086 | case WM8962_RETUNEADC_PG2_0: |
1087 | case WM8962_RETUNEADC_PG_1: |
1088 | case WM8962_RETUNEADC_PG_0: |
1089 | case WM8962_ADCR_RETUNE_C1_1: |
1090 | case WM8962_ADCR_RETUNE_C1_0: |
1091 | case WM8962_ADCR_RETUNE_C2_1: |
1092 | case WM8962_ADCR_RETUNE_C2_0: |
1093 | case WM8962_ADCR_RETUNE_C3_1: |
1094 | case WM8962_ADCR_RETUNE_C3_0: |
1095 | case WM8962_ADCR_RETUNE_C4_1: |
1096 | case WM8962_ADCR_RETUNE_C4_0: |
1097 | case WM8962_ADCR_RETUNE_C5_1: |
1098 | case WM8962_ADCR_RETUNE_C5_0: |
1099 | case WM8962_ADCR_RETUNE_C6_1: |
1100 | case WM8962_ADCR_RETUNE_C6_0: |
1101 | case WM8962_ADCR_RETUNE_C7_1: |
1102 | case WM8962_ADCR_RETUNE_C7_0: |
1103 | case WM8962_ADCR_RETUNE_C8_1: |
1104 | case WM8962_ADCR_RETUNE_C8_0: |
1105 | case WM8962_ADCR_RETUNE_C9_1: |
1106 | case WM8962_ADCR_RETUNE_C9_0: |
1107 | case WM8962_ADCR_RETUNE_C10_1: |
1108 | case WM8962_ADCR_RETUNE_C10_0: |
1109 | case WM8962_ADCR_RETUNE_C11_1: |
1110 | case WM8962_ADCR_RETUNE_C11_0: |
1111 | case WM8962_ADCR_RETUNE_C12_1: |
1112 | case WM8962_ADCR_RETUNE_C12_0: |
1113 | case WM8962_ADCR_RETUNE_C13_1: |
1114 | case WM8962_ADCR_RETUNE_C13_0: |
1115 | case WM8962_ADCR_RETUNE_C14_1: |
1116 | case WM8962_ADCR_RETUNE_C14_0: |
1117 | case WM8962_ADCR_RETUNE_C15_1: |
1118 | case WM8962_ADCR_RETUNE_C15_0: |
1119 | case WM8962_ADCR_RETUNE_C16_1: |
1120 | case WM8962_ADCR_RETUNE_C16_0: |
1121 | case WM8962_ADCR_RETUNE_C17_1: |
1122 | case WM8962_ADCR_RETUNE_C17_0: |
1123 | case WM8962_ADCR_RETUNE_C18_1: |
1124 | case WM8962_ADCR_RETUNE_C18_0: |
1125 | case WM8962_ADCR_RETUNE_C19_1: |
1126 | case WM8962_ADCR_RETUNE_C19_0: |
1127 | case WM8962_ADCR_RETUNE_C20_1: |
1128 | case WM8962_ADCR_RETUNE_C20_0: |
1129 | case WM8962_ADCR_RETUNE_C21_1: |
1130 | case WM8962_ADCR_RETUNE_C21_0: |
1131 | case WM8962_ADCR_RETUNE_C22_1: |
1132 | case WM8962_ADCR_RETUNE_C22_0: |
1133 | case WM8962_ADCR_RETUNE_C23_1: |
1134 | case WM8962_ADCR_RETUNE_C23_0: |
1135 | case WM8962_ADCR_RETUNE_C24_1: |
1136 | case WM8962_ADCR_RETUNE_C24_0: |
1137 | case WM8962_ADCR_RETUNE_C25_1: |
1138 | case WM8962_ADCR_RETUNE_C25_0: |
1139 | case WM8962_ADCR_RETUNE_C26_1: |
1140 | case WM8962_ADCR_RETUNE_C26_0: |
1141 | case WM8962_ADCR_RETUNE_C27_1: |
1142 | case WM8962_ADCR_RETUNE_C27_0: |
1143 | case WM8962_ADCR_RETUNE_C28_1: |
1144 | case WM8962_ADCR_RETUNE_C28_0: |
1145 | case WM8962_ADCR_RETUNE_C29_1: |
1146 | case WM8962_ADCR_RETUNE_C29_0: |
1147 | case WM8962_ADCR_RETUNE_C30_1: |
1148 | case WM8962_ADCR_RETUNE_C30_0: |
1149 | case WM8962_ADCR_RETUNE_C31_1: |
1150 | case WM8962_ADCR_RETUNE_C31_0: |
1151 | case WM8962_ADCR_RETUNE_C32_1: |
1152 | case WM8962_ADCR_RETUNE_C32_0: |
1153 | case WM8962_DACL_RETUNE_C1_1: |
1154 | case WM8962_DACL_RETUNE_C1_0: |
1155 | case WM8962_DACL_RETUNE_C2_1: |
1156 | case WM8962_DACL_RETUNE_C2_0: |
1157 | case WM8962_DACL_RETUNE_C3_1: |
1158 | case WM8962_DACL_RETUNE_C3_0: |
1159 | case WM8962_DACL_RETUNE_C4_1: |
1160 | case WM8962_DACL_RETUNE_C4_0: |
1161 | case WM8962_DACL_RETUNE_C5_1: |
1162 | case WM8962_DACL_RETUNE_C5_0: |
1163 | case WM8962_DACL_RETUNE_C6_1: |
1164 | case WM8962_DACL_RETUNE_C6_0: |
1165 | case WM8962_DACL_RETUNE_C7_1: |
1166 | case WM8962_DACL_RETUNE_C7_0: |
1167 | case WM8962_DACL_RETUNE_C8_1: |
1168 | case WM8962_DACL_RETUNE_C8_0: |
1169 | case WM8962_DACL_RETUNE_C9_1: |
1170 | case WM8962_DACL_RETUNE_C9_0: |
1171 | case WM8962_DACL_RETUNE_C10_1: |
1172 | case WM8962_DACL_RETUNE_C10_0: |
1173 | case WM8962_DACL_RETUNE_C11_1: |
1174 | case WM8962_DACL_RETUNE_C11_0: |
1175 | case WM8962_DACL_RETUNE_C12_1: |
1176 | case WM8962_DACL_RETUNE_C12_0: |
1177 | case WM8962_DACL_RETUNE_C13_1: |
1178 | case WM8962_DACL_RETUNE_C13_0: |
1179 | case WM8962_DACL_RETUNE_C14_1: |
1180 | case WM8962_DACL_RETUNE_C14_0: |
1181 | case WM8962_DACL_RETUNE_C15_1: |
1182 | case WM8962_DACL_RETUNE_C15_0: |
1183 | case WM8962_DACL_RETUNE_C16_1: |
1184 | case WM8962_DACL_RETUNE_C16_0: |
1185 | case WM8962_DACL_RETUNE_C17_1: |
1186 | case WM8962_DACL_RETUNE_C17_0: |
1187 | case WM8962_DACL_RETUNE_C18_1: |
1188 | case WM8962_DACL_RETUNE_C18_0: |
1189 | case WM8962_DACL_RETUNE_C19_1: |
1190 | case WM8962_DACL_RETUNE_C19_0: |
1191 | case WM8962_DACL_RETUNE_C20_1: |
1192 | case WM8962_DACL_RETUNE_C20_0: |
1193 | case WM8962_DACL_RETUNE_C21_1: |
1194 | case WM8962_DACL_RETUNE_C21_0: |
1195 | case WM8962_DACL_RETUNE_C22_1: |
1196 | case WM8962_DACL_RETUNE_C22_0: |
1197 | case WM8962_DACL_RETUNE_C23_1: |
1198 | case WM8962_DACL_RETUNE_C23_0: |
1199 | case WM8962_DACL_RETUNE_C24_1: |
1200 | case WM8962_DACL_RETUNE_C24_0: |
1201 | case WM8962_DACL_RETUNE_C25_1: |
1202 | case WM8962_DACL_RETUNE_C25_0: |
1203 | case WM8962_DACL_RETUNE_C26_1: |
1204 | case WM8962_DACL_RETUNE_C26_0: |
1205 | case WM8962_DACL_RETUNE_C27_1: |
1206 | case WM8962_DACL_RETUNE_C27_0: |
1207 | case WM8962_DACL_RETUNE_C28_1: |
1208 | case WM8962_DACL_RETUNE_C28_0: |
1209 | case WM8962_DACL_RETUNE_C29_1: |
1210 | case WM8962_DACL_RETUNE_C29_0: |
1211 | case WM8962_DACL_RETUNE_C30_1: |
1212 | case WM8962_DACL_RETUNE_C30_0: |
1213 | case WM8962_DACL_RETUNE_C31_1: |
1214 | case WM8962_DACL_RETUNE_C31_0: |
1215 | case WM8962_DACL_RETUNE_C32_1: |
1216 | case WM8962_DACL_RETUNE_C32_0: |
1217 | case WM8962_RETUNEDAC_PG2_1: |
1218 | case WM8962_RETUNEDAC_PG2_0: |
1219 | case WM8962_RETUNEDAC_PG_1: |
1220 | case WM8962_RETUNEDAC_PG_0: |
1221 | case WM8962_DACR_RETUNE_C1_1: |
1222 | case WM8962_DACR_RETUNE_C1_0: |
1223 | case WM8962_DACR_RETUNE_C2_1: |
1224 | case WM8962_DACR_RETUNE_C2_0: |
1225 | case WM8962_DACR_RETUNE_C3_1: |
1226 | case WM8962_DACR_RETUNE_C3_0: |
1227 | case WM8962_DACR_RETUNE_C4_1: |
1228 | case WM8962_DACR_RETUNE_C4_0: |
1229 | case WM8962_DACR_RETUNE_C5_1: |
1230 | case WM8962_DACR_RETUNE_C5_0: |
1231 | case WM8962_DACR_RETUNE_C6_1: |
1232 | case WM8962_DACR_RETUNE_C6_0: |
1233 | case WM8962_DACR_RETUNE_C7_1: |
1234 | case WM8962_DACR_RETUNE_C7_0: |
1235 | case WM8962_DACR_RETUNE_C8_1: |
1236 | case WM8962_DACR_RETUNE_C8_0: |
1237 | case WM8962_DACR_RETUNE_C9_1: |
1238 | case WM8962_DACR_RETUNE_C9_0: |
1239 | case WM8962_DACR_RETUNE_C10_1: |
1240 | case WM8962_DACR_RETUNE_C10_0: |
1241 | case WM8962_DACR_RETUNE_C11_1: |
1242 | case WM8962_DACR_RETUNE_C11_0: |
1243 | case WM8962_DACR_RETUNE_C12_1: |
1244 | case WM8962_DACR_RETUNE_C12_0: |
1245 | case WM8962_DACR_RETUNE_C13_1: |
1246 | case WM8962_DACR_RETUNE_C13_0: |
1247 | case WM8962_DACR_RETUNE_C14_1: |
1248 | case WM8962_DACR_RETUNE_C14_0: |
1249 | case WM8962_DACR_RETUNE_C15_1: |
1250 | case WM8962_DACR_RETUNE_C15_0: |
1251 | case WM8962_DACR_RETUNE_C16_1: |
1252 | case WM8962_DACR_RETUNE_C16_0: |
1253 | case WM8962_DACR_RETUNE_C17_1: |
1254 | case WM8962_DACR_RETUNE_C17_0: |
1255 | case WM8962_DACR_RETUNE_C18_1: |
1256 | case WM8962_DACR_RETUNE_C18_0: |
1257 | case WM8962_DACR_RETUNE_C19_1: |
1258 | case WM8962_DACR_RETUNE_C19_0: |
1259 | case WM8962_DACR_RETUNE_C20_1: |
1260 | case WM8962_DACR_RETUNE_C20_0: |
1261 | case WM8962_DACR_RETUNE_C21_1: |
1262 | case WM8962_DACR_RETUNE_C21_0: |
1263 | case WM8962_DACR_RETUNE_C22_1: |
1264 | case WM8962_DACR_RETUNE_C22_0: |
1265 | case WM8962_DACR_RETUNE_C23_1: |
1266 | case WM8962_DACR_RETUNE_C23_0: |
1267 | case WM8962_DACR_RETUNE_C24_1: |
1268 | case WM8962_DACR_RETUNE_C24_0: |
1269 | case WM8962_DACR_RETUNE_C25_1: |
1270 | case WM8962_DACR_RETUNE_C25_0: |
1271 | case WM8962_DACR_RETUNE_C26_1: |
1272 | case WM8962_DACR_RETUNE_C26_0: |
1273 | case WM8962_DACR_RETUNE_C27_1: |
1274 | case WM8962_DACR_RETUNE_C27_0: |
1275 | case WM8962_DACR_RETUNE_C28_1: |
1276 | case WM8962_DACR_RETUNE_C28_0: |
1277 | case WM8962_DACR_RETUNE_C29_1: |
1278 | case WM8962_DACR_RETUNE_C29_0: |
1279 | case WM8962_DACR_RETUNE_C30_1: |
1280 | case WM8962_DACR_RETUNE_C30_0: |
1281 | case WM8962_DACR_RETUNE_C31_1: |
1282 | case WM8962_DACR_RETUNE_C31_0: |
1283 | case WM8962_DACR_RETUNE_C32_1: |
1284 | case WM8962_DACR_RETUNE_C32_0: |
1285 | case WM8962_VSS_XHD2_1: |
1286 | case WM8962_VSS_XHD2_0: |
1287 | case WM8962_VSS_XHD3_1: |
1288 | case WM8962_VSS_XHD3_0: |
1289 | case WM8962_VSS_XHN1_1: |
1290 | case WM8962_VSS_XHN1_0: |
1291 | case WM8962_VSS_XHN2_1: |
1292 | case WM8962_VSS_XHN2_0: |
1293 | case WM8962_VSS_XHN3_1: |
1294 | case WM8962_VSS_XHN3_0: |
1295 | case WM8962_VSS_XLA_1: |
1296 | case WM8962_VSS_XLA_0: |
1297 | case WM8962_VSS_XLB_1: |
1298 | case WM8962_VSS_XLB_0: |
1299 | case WM8962_VSS_XLG_1: |
1300 | case WM8962_VSS_XLG_0: |
1301 | case WM8962_VSS_PG2_1: |
1302 | case WM8962_VSS_PG2_0: |
1303 | case WM8962_VSS_PG_1: |
1304 | case WM8962_VSS_PG_0: |
1305 | case WM8962_VSS_XTD1_1: |
1306 | case WM8962_VSS_XTD1_0: |
1307 | case WM8962_VSS_XTD2_1: |
1308 | case WM8962_VSS_XTD2_0: |
1309 | case WM8962_VSS_XTD3_1: |
1310 | case WM8962_VSS_XTD3_0: |
1311 | case WM8962_VSS_XTD4_1: |
1312 | case WM8962_VSS_XTD4_0: |
1313 | case WM8962_VSS_XTD5_1: |
1314 | case WM8962_VSS_XTD5_0: |
1315 | case WM8962_VSS_XTD6_1: |
1316 | case WM8962_VSS_XTD6_0: |
1317 | case WM8962_VSS_XTD7_1: |
1318 | case WM8962_VSS_XTD7_0: |
1319 | case WM8962_VSS_XTD8_1: |
1320 | case WM8962_VSS_XTD8_0: |
1321 | case WM8962_VSS_XTD9_1: |
1322 | case WM8962_VSS_XTD9_0: |
1323 | case WM8962_VSS_XTD10_1: |
1324 | case WM8962_VSS_XTD10_0: |
1325 | case WM8962_VSS_XTD11_1: |
1326 | case WM8962_VSS_XTD11_0: |
1327 | case WM8962_VSS_XTD12_1: |
1328 | case WM8962_VSS_XTD12_0: |
1329 | case WM8962_VSS_XTD13_1: |
1330 | case WM8962_VSS_XTD13_0: |
1331 | case WM8962_VSS_XTD14_1: |
1332 | case WM8962_VSS_XTD14_0: |
1333 | case WM8962_VSS_XTD15_1: |
1334 | case WM8962_VSS_XTD15_0: |
1335 | case WM8962_VSS_XTD16_1: |
1336 | case WM8962_VSS_XTD16_0: |
1337 | case WM8962_VSS_XTD17_1: |
1338 | case WM8962_VSS_XTD17_0: |
1339 | case WM8962_VSS_XTD18_1: |
1340 | case WM8962_VSS_XTD18_0: |
1341 | case WM8962_VSS_XTD19_1: |
1342 | case WM8962_VSS_XTD19_0: |
1343 | case WM8962_VSS_XTD20_1: |
1344 | case WM8962_VSS_XTD20_0: |
1345 | case WM8962_VSS_XTD21_1: |
1346 | case WM8962_VSS_XTD21_0: |
1347 | case WM8962_VSS_XTD22_1: |
1348 | case WM8962_VSS_XTD22_0: |
1349 | case WM8962_VSS_XTD23_1: |
1350 | case WM8962_VSS_XTD23_0: |
1351 | case WM8962_VSS_XTD24_1: |
1352 | case WM8962_VSS_XTD24_0: |
1353 | case WM8962_VSS_XTD25_1: |
1354 | case WM8962_VSS_XTD25_0: |
1355 | case WM8962_VSS_XTD26_1: |
1356 | case WM8962_VSS_XTD26_0: |
1357 | case WM8962_VSS_XTD27_1: |
1358 | case WM8962_VSS_XTD27_0: |
1359 | case WM8962_VSS_XTD28_1: |
1360 | case WM8962_VSS_XTD28_0: |
1361 | case WM8962_VSS_XTD29_1: |
1362 | case WM8962_VSS_XTD29_0: |
1363 | case WM8962_VSS_XTD30_1: |
1364 | case WM8962_VSS_XTD30_0: |
1365 | case WM8962_VSS_XTD31_1: |
1366 | case WM8962_VSS_XTD31_0: |
1367 | case WM8962_VSS_XTD32_1: |
1368 | case WM8962_VSS_XTD32_0: |
1369 | case WM8962_VSS_XTS1_1: |
1370 | case WM8962_VSS_XTS1_0: |
1371 | case WM8962_VSS_XTS2_1: |
1372 | case WM8962_VSS_XTS2_0: |
1373 | case WM8962_VSS_XTS3_1: |
1374 | case WM8962_VSS_XTS3_0: |
1375 | case WM8962_VSS_XTS4_1: |
1376 | case WM8962_VSS_XTS4_0: |
1377 | case WM8962_VSS_XTS5_1: |
1378 | case WM8962_VSS_XTS5_0: |
1379 | case WM8962_VSS_XTS6_1: |
1380 | case WM8962_VSS_XTS6_0: |
1381 | case WM8962_VSS_XTS7_1: |
1382 | case WM8962_VSS_XTS7_0: |
1383 | case WM8962_VSS_XTS8_1: |
1384 | case WM8962_VSS_XTS8_0: |
1385 | case WM8962_VSS_XTS9_1: |
1386 | case WM8962_VSS_XTS9_0: |
1387 | case WM8962_VSS_XTS10_1: |
1388 | case WM8962_VSS_XTS10_0: |
1389 | case WM8962_VSS_XTS11_1: |
1390 | case WM8962_VSS_XTS11_0: |
1391 | case WM8962_VSS_XTS12_1: |
1392 | case WM8962_VSS_XTS12_0: |
1393 | case WM8962_VSS_XTS13_1: |
1394 | case WM8962_VSS_XTS13_0: |
1395 | case WM8962_VSS_XTS14_1: |
1396 | case WM8962_VSS_XTS14_0: |
1397 | case WM8962_VSS_XTS15_1: |
1398 | case WM8962_VSS_XTS15_0: |
1399 | case WM8962_VSS_XTS16_1: |
1400 | case WM8962_VSS_XTS16_0: |
1401 | case WM8962_VSS_XTS17_1: |
1402 | case WM8962_VSS_XTS17_0: |
1403 | case WM8962_VSS_XTS18_1: |
1404 | case WM8962_VSS_XTS18_0: |
1405 | case WM8962_VSS_XTS19_1: |
1406 | case WM8962_VSS_XTS19_0: |
1407 | case WM8962_VSS_XTS20_1: |
1408 | case WM8962_VSS_XTS20_0: |
1409 | case WM8962_VSS_XTS21_1: |
1410 | case WM8962_VSS_XTS21_0: |
1411 | case WM8962_VSS_XTS22_1: |
1412 | case WM8962_VSS_XTS22_0: |
1413 | case WM8962_VSS_XTS23_1: |
1414 | case WM8962_VSS_XTS23_0: |
1415 | case WM8962_VSS_XTS24_1: |
1416 | case WM8962_VSS_XTS24_0: |
1417 | case WM8962_VSS_XTS25_1: |
1418 | case WM8962_VSS_XTS25_0: |
1419 | case WM8962_VSS_XTS26_1: |
1420 | case WM8962_VSS_XTS26_0: |
1421 | case WM8962_VSS_XTS27_1: |
1422 | case WM8962_VSS_XTS27_0: |
1423 | case WM8962_VSS_XTS28_1: |
1424 | case WM8962_VSS_XTS28_0: |
1425 | case WM8962_VSS_XTS29_1: |
1426 | case WM8962_VSS_XTS29_0: |
1427 | case WM8962_VSS_XTS30_1: |
1428 | case WM8962_VSS_XTS30_0: |
1429 | case WM8962_VSS_XTS31_1: |
1430 | case WM8962_VSS_XTS31_0: |
1431 | case WM8962_VSS_XTS32_1: |
1432 | case WM8962_VSS_XTS32_0: |
1433 | return true; |
1434 | default: |
1435 | return false; |
1436 | } |
1437 | } |
1438 | |
1439 | static int wm8962_reset(struct wm8962_priv *wm8962) |
1440 | { |
1441 | int ret; |
1442 | |
1443 | ret = regmap_write(map: wm8962->regmap, WM8962_SOFTWARE_RESET, val: 0x6243); |
1444 | if (ret != 0) |
1445 | return ret; |
1446 | |
1447 | return regmap_write(map: wm8962->regmap, WM8962_PLL_SOFTWARE_RESET, val: 0); |
1448 | } |
1449 | |
1450 | static const DECLARE_TLV_DB_SCALE(inpga_tlv, -2325, 75, 0); |
1451 | static const DECLARE_TLV_DB_SCALE(mixin_tlv, -1500, 300, 0); |
1452 | static const DECLARE_TLV_DB_RANGE(mixinpga_tlv, |
1453 | 0, 1, TLV_DB_SCALE_ITEM(0, 600, 0), |
1454 | 2, 2, TLV_DB_SCALE_ITEM(1300, 1300, 0), |
1455 | 3, 4, TLV_DB_SCALE_ITEM(1800, 200, 0), |
1456 | 5, 5, TLV_DB_SCALE_ITEM(2400, 0, 0), |
1457 | 6, 7, TLV_DB_SCALE_ITEM(2700, 300, 0) |
1458 | ); |
1459 | static const DECLARE_TLV_DB_SCALE(beep_tlv, -9600, 600, 1); |
1460 | static const DECLARE_TLV_DB_SCALE(digital_tlv, -7200, 75, 1); |
1461 | static const DECLARE_TLV_DB_SCALE(st_tlv, -3600, 300, 0); |
1462 | static const DECLARE_TLV_DB_SCALE(inmix_tlv, -600, 600, 0); |
1463 | static const DECLARE_TLV_DB_SCALE(bypass_tlv, -1500, 300, 0); |
1464 | static const DECLARE_TLV_DB_SCALE(out_tlv, -12100, 100, 1); |
1465 | static const DECLARE_TLV_DB_SCALE(hp_tlv, -700, 100, 0); |
1466 | static const DECLARE_TLV_DB_RANGE(classd_tlv, |
1467 | 0, 6, TLV_DB_SCALE_ITEM(0, 150, 0), |
1468 | 7, 7, TLV_DB_SCALE_ITEM(1200, 0, 0) |
1469 | ); |
1470 | static const DECLARE_TLV_DB_SCALE(eq_tlv, -1200, 100, 0); |
1471 | |
1472 | static int wm8962_dsp2_write_config(struct snd_soc_component *component) |
1473 | { |
1474 | struct wm8962_priv *wm8962 = snd_soc_component_get_drvdata(c: component); |
1475 | |
1476 | return regcache_sync_region(map: wm8962->regmap, |
1477 | WM8962_HDBASS_AI_1, WM8962_MAX_REGISTER); |
1478 | } |
1479 | |
1480 | static int wm8962_dsp2_set_enable(struct snd_soc_component *component, u16 val) |
1481 | { |
1482 | u16 adcl = snd_soc_component_read(component, WM8962_LEFT_ADC_VOLUME); |
1483 | u16 adcr = snd_soc_component_read(component, WM8962_RIGHT_ADC_VOLUME); |
1484 | u16 dac = snd_soc_component_read(component, WM8962_ADC_DAC_CONTROL_1); |
1485 | |
1486 | /* Mute the ADCs and DACs */ |
1487 | snd_soc_component_write(component, WM8962_LEFT_ADC_VOLUME, val: 0); |
1488 | snd_soc_component_write(component, WM8962_RIGHT_ADC_VOLUME, WM8962_ADC_VU); |
1489 | snd_soc_component_update_bits(component, WM8962_ADC_DAC_CONTROL_1, |
1490 | WM8962_DAC_MUTE, WM8962_DAC_MUTE); |
1491 | |
1492 | snd_soc_component_write(component, WM8962_SOUNDSTAGE_ENABLES_0, val); |
1493 | |
1494 | /* Restore the ADCs and DACs */ |
1495 | snd_soc_component_write(component, WM8962_LEFT_ADC_VOLUME, val: adcl); |
1496 | snd_soc_component_write(component, WM8962_RIGHT_ADC_VOLUME, val: adcr); |
1497 | snd_soc_component_update_bits(component, WM8962_ADC_DAC_CONTROL_1, |
1498 | WM8962_DAC_MUTE, val: dac); |
1499 | |
1500 | return 0; |
1501 | } |
1502 | |
1503 | static int wm8962_dsp2_start(struct snd_soc_component *component) |
1504 | { |
1505 | struct wm8962_priv *wm8962 = snd_soc_component_get_drvdata(c: component); |
1506 | |
1507 | wm8962_dsp2_write_config(component); |
1508 | |
1509 | snd_soc_component_write(component, WM8962_DSP2_EXECCONTROL, WM8962_DSP2_RUNR); |
1510 | |
1511 | wm8962_dsp2_set_enable(component, val: wm8962->dsp2_ena); |
1512 | |
1513 | return 0; |
1514 | } |
1515 | |
1516 | static int wm8962_dsp2_stop(struct snd_soc_component *component) |
1517 | { |
1518 | wm8962_dsp2_set_enable(component, val: 0); |
1519 | |
1520 | snd_soc_component_write(component, WM8962_DSP2_EXECCONTROL, WM8962_DSP2_STOP); |
1521 | |
1522 | return 0; |
1523 | } |
1524 | |
1525 | #define WM8962_DSP2_ENABLE(xname, xshift) \ |
1526 | { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \ |
1527 | .info = wm8962_dsp2_ena_info, \ |
1528 | .get = wm8962_dsp2_ena_get, .put = wm8962_dsp2_ena_put, \ |
1529 | .private_value = xshift } |
1530 | |
1531 | static int wm8962_dsp2_ena_info(struct snd_kcontrol *kcontrol, |
1532 | struct snd_ctl_elem_info *uinfo) |
1533 | { |
1534 | uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN; |
1535 | |
1536 | uinfo->count = 1; |
1537 | uinfo->value.integer.min = 0; |
1538 | uinfo->value.integer.max = 1; |
1539 | |
1540 | return 0; |
1541 | } |
1542 | |
1543 | static int wm8962_dsp2_ena_get(struct snd_kcontrol *kcontrol, |
1544 | struct snd_ctl_elem_value *ucontrol) |
1545 | { |
1546 | int shift = kcontrol->private_value; |
1547 | struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); |
1548 | struct wm8962_priv *wm8962 = snd_soc_component_get_drvdata(c: component); |
1549 | |
1550 | ucontrol->value.integer.value[0] = !!(wm8962->dsp2_ena & 1 << shift); |
1551 | |
1552 | return 0; |
1553 | } |
1554 | |
1555 | static int wm8962_dsp2_ena_put(struct snd_kcontrol *kcontrol, |
1556 | struct snd_ctl_elem_value *ucontrol) |
1557 | { |
1558 | int shift = kcontrol->private_value; |
1559 | struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); |
1560 | struct wm8962_priv *wm8962 = snd_soc_component_get_drvdata(c: component); |
1561 | int old = wm8962->dsp2_ena; |
1562 | int ret = 0; |
1563 | int dsp2_running = snd_soc_component_read(component, WM8962_DSP2_POWER_MANAGEMENT) & |
1564 | WM8962_DSP2_ENA; |
1565 | |
1566 | mutex_lock(&wm8962->dsp2_ena_lock); |
1567 | |
1568 | if (ucontrol->value.integer.value[0]) |
1569 | wm8962->dsp2_ena |= 1 << shift; |
1570 | else |
1571 | wm8962->dsp2_ena &= ~(1 << shift); |
1572 | |
1573 | if (wm8962->dsp2_ena == old) |
1574 | goto out; |
1575 | |
1576 | ret = 1; |
1577 | |
1578 | if (dsp2_running) { |
1579 | if (wm8962->dsp2_ena) |
1580 | wm8962_dsp2_set_enable(component, val: wm8962->dsp2_ena); |
1581 | else |
1582 | wm8962_dsp2_stop(component); |
1583 | } |
1584 | |
1585 | out: |
1586 | mutex_unlock(lock: &wm8962->dsp2_ena_lock); |
1587 | |
1588 | return ret; |
1589 | } |
1590 | |
1591 | /* The VU bits for the headphones are in a different register to the mute |
1592 | * bits and only take effect on the PGA if it is actually powered. |
1593 | */ |
1594 | static int wm8962_put_hp_sw(struct snd_kcontrol *kcontrol, |
1595 | struct snd_ctl_elem_value *ucontrol) |
1596 | { |
1597 | struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); |
1598 | int ret; |
1599 | |
1600 | /* Apply the update (if any) */ |
1601 | ret = snd_soc_put_volsw(kcontrol, ucontrol); |
1602 | if (ret == 0) |
1603 | return 0; |
1604 | |
1605 | /* If the left PGA is enabled hit that VU bit... */ |
1606 | ret = snd_soc_component_read(component, WM8962_PWR_MGMT_2); |
1607 | if (ret & WM8962_HPOUTL_PGA_ENA) { |
1608 | snd_soc_component_write(component, WM8962_HPOUTL_VOLUME, |
1609 | val: snd_soc_component_read(component, WM8962_HPOUTL_VOLUME)); |
1610 | return 1; |
1611 | } |
1612 | |
1613 | /* ...otherwise the right. The VU is stereo. */ |
1614 | if (ret & WM8962_HPOUTR_PGA_ENA) |
1615 | snd_soc_component_write(component, WM8962_HPOUTR_VOLUME, |
1616 | val: snd_soc_component_read(component, WM8962_HPOUTR_VOLUME)); |
1617 | |
1618 | return 1; |
1619 | } |
1620 | |
1621 | /* The VU bits for the speakers are in a different register to the mute |
1622 | * bits and only take effect on the PGA if it is actually powered. |
1623 | */ |
1624 | static int wm8962_put_spk_sw(struct snd_kcontrol *kcontrol, |
1625 | struct snd_ctl_elem_value *ucontrol) |
1626 | { |
1627 | struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); |
1628 | int ret; |
1629 | |
1630 | /* Apply the update (if any) */ |
1631 | ret = snd_soc_put_volsw(kcontrol, ucontrol); |
1632 | if (ret == 0) |
1633 | return 0; |
1634 | |
1635 | /* If the left PGA is enabled hit that VU bit... */ |
1636 | ret = snd_soc_component_read(component, WM8962_PWR_MGMT_2); |
1637 | if (ret & WM8962_SPKOUTL_PGA_ENA) { |
1638 | snd_soc_component_write(component, WM8962_SPKOUTL_VOLUME, |
1639 | val: snd_soc_component_read(component, WM8962_SPKOUTL_VOLUME)); |
1640 | return 1; |
1641 | } |
1642 | |
1643 | /* ...otherwise the right. The VU is stereo. */ |
1644 | if (ret & WM8962_SPKOUTR_PGA_ENA) |
1645 | snd_soc_component_write(component, WM8962_SPKOUTR_VOLUME, |
1646 | val: snd_soc_component_read(component, WM8962_SPKOUTR_VOLUME)); |
1647 | |
1648 | return 1; |
1649 | } |
1650 | |
1651 | static const char *cap_hpf_mode_text[] = { |
1652 | "Hi-fi" , "Application" |
1653 | }; |
1654 | |
1655 | static SOC_ENUM_SINGLE_DECL(cap_hpf_mode, |
1656 | WM8962_ADC_DAC_CONTROL_2, 10, cap_hpf_mode_text); |
1657 | |
1658 | |
1659 | static const char *cap_lhpf_mode_text[] = { |
1660 | "LPF" , "HPF" |
1661 | }; |
1662 | |
1663 | static SOC_ENUM_SINGLE_DECL(cap_lhpf_mode, |
1664 | WM8962_LHPF1, 1, cap_lhpf_mode_text); |
1665 | |
1666 | static const struct snd_kcontrol_new wm8962_snd_controls[] = { |
1667 | SOC_DOUBLE("Input Mixer Switch" , WM8962_INPUT_MIXER_CONTROL_1, 3, 2, 1, 1), |
1668 | |
1669 | SOC_SINGLE_TLV("MIXINL IN2L Volume" , WM8962_LEFT_INPUT_MIXER_VOLUME, 6, 7, 0, |
1670 | mixin_tlv), |
1671 | SOC_SINGLE_TLV("MIXINL PGA Volume" , WM8962_LEFT_INPUT_MIXER_VOLUME, 3, 7, 0, |
1672 | mixinpga_tlv), |
1673 | SOC_SINGLE_TLV("MIXINL IN3L Volume" , WM8962_LEFT_INPUT_MIXER_VOLUME, 0, 7, 0, |
1674 | mixin_tlv), |
1675 | |
1676 | SOC_SINGLE_TLV("MIXINR IN2R Volume" , WM8962_RIGHT_INPUT_MIXER_VOLUME, 6, 7, 0, |
1677 | mixin_tlv), |
1678 | SOC_SINGLE_TLV("MIXINR PGA Volume" , WM8962_RIGHT_INPUT_MIXER_VOLUME, 3, 7, 0, |
1679 | mixinpga_tlv), |
1680 | SOC_SINGLE_TLV("MIXINR IN3R Volume" , WM8962_RIGHT_INPUT_MIXER_VOLUME, 0, 7, 0, |
1681 | mixin_tlv), |
1682 | |
1683 | SOC_DOUBLE_R_TLV("Digital Capture Volume" , WM8962_LEFT_ADC_VOLUME, |
1684 | WM8962_RIGHT_ADC_VOLUME, 1, 127, 0, digital_tlv), |
1685 | SOC_DOUBLE_R_TLV("Capture Volume" , WM8962_LEFT_INPUT_VOLUME, |
1686 | WM8962_RIGHT_INPUT_VOLUME, 0, 63, 0, inpga_tlv), |
1687 | SOC_DOUBLE_R("Capture Switch" , WM8962_LEFT_INPUT_VOLUME, |
1688 | WM8962_RIGHT_INPUT_VOLUME, 7, 1, 1), |
1689 | SOC_DOUBLE_R("Capture ZC Switch" , WM8962_LEFT_INPUT_VOLUME, |
1690 | WM8962_RIGHT_INPUT_VOLUME, 6, 1, 1), |
1691 | SOC_SINGLE("Capture HPF Switch" , WM8962_ADC_DAC_CONTROL_1, 0, 1, 1), |
1692 | SOC_ENUM("Capture HPF Mode" , cap_hpf_mode), |
1693 | SOC_SINGLE("Capture HPF Cutoff" , WM8962_ADC_DAC_CONTROL_2, 7, 7, 0), |
1694 | SOC_SINGLE("Capture LHPF Switch" , WM8962_LHPF1, 0, 1, 0), |
1695 | SOC_ENUM("Capture LHPF Mode" , cap_lhpf_mode), |
1696 | |
1697 | SOC_DOUBLE_R_TLV("Sidetone Volume" , WM8962_DAC_DSP_MIXING_1, |
1698 | WM8962_DAC_DSP_MIXING_2, 4, 12, 0, st_tlv), |
1699 | |
1700 | SOC_DOUBLE_R_TLV("Digital Playback Volume" , WM8962_LEFT_DAC_VOLUME, |
1701 | WM8962_RIGHT_DAC_VOLUME, 1, 127, 0, digital_tlv), |
1702 | SOC_SINGLE("DAC High Performance Switch" , WM8962_ADC_DAC_CONTROL_2, 0, 1, 0), |
1703 | SOC_SINGLE("DAC L/R Swap Switch" , WM8962_AUDIO_INTERFACE_0, 5, 1, 0), |
1704 | SOC_SINGLE("ADC L/R Swap Switch" , WM8962_AUDIO_INTERFACE_0, 8, 1, 0), |
1705 | SOC_SINGLE("DAC Monomix Switch" , WM8962_DAC_DSP_MIXING_1, WM8962_DAC_MONOMIX_SHIFT, 1, 0), |
1706 | SOC_SINGLE("ADC Monomix Switch" , WM8962_THREED1, WM8962_ADC_MONOMIX_SHIFT, 1, 0), |
1707 | |
1708 | SOC_SINGLE("ADC High Performance Switch" , WM8962_ADDITIONAL_CONTROL_1, |
1709 | 5, 1, 0), |
1710 | |
1711 | SOC_SINGLE_TLV("Beep Volume" , WM8962_BEEP_GENERATOR_1, 4, 15, 0, beep_tlv), |
1712 | |
1713 | SOC_DOUBLE_R_TLV("Headphone Volume" , WM8962_HPOUTL_VOLUME, |
1714 | WM8962_HPOUTR_VOLUME, 0, 127, 0, out_tlv), |
1715 | SOC_DOUBLE_EXT("Headphone Switch" , WM8962_PWR_MGMT_2, 1, 0, 1, 1, |
1716 | snd_soc_get_volsw, wm8962_put_hp_sw), |
1717 | SOC_DOUBLE_R("Headphone ZC Switch" , WM8962_HPOUTL_VOLUME, WM8962_HPOUTR_VOLUME, |
1718 | 7, 1, 0), |
1719 | SOC_DOUBLE_TLV("Headphone Aux Volume" , WM8962_ANALOGUE_HP_2, 3, 6, 7, 0, |
1720 | hp_tlv), |
1721 | |
1722 | SOC_DOUBLE_R("Headphone Mixer Switch" , WM8962_HEADPHONE_MIXER_3, |
1723 | WM8962_HEADPHONE_MIXER_4, 8, 1, 1), |
1724 | |
1725 | SOC_SINGLE_TLV("HPMIXL IN4L Volume" , WM8962_HEADPHONE_MIXER_3, |
1726 | 3, 7, 0, bypass_tlv), |
1727 | SOC_SINGLE_TLV("HPMIXL IN4R Volume" , WM8962_HEADPHONE_MIXER_3, |
1728 | 0, 7, 0, bypass_tlv), |
1729 | SOC_SINGLE_TLV("HPMIXL MIXINL Volume" , WM8962_HEADPHONE_MIXER_3, |
1730 | 7, 1, 1, inmix_tlv), |
1731 | SOC_SINGLE_TLV("HPMIXL MIXINR Volume" , WM8962_HEADPHONE_MIXER_3, |
1732 | 6, 1, 1, inmix_tlv), |
1733 | |
1734 | SOC_SINGLE_TLV("HPMIXR IN4L Volume" , WM8962_HEADPHONE_MIXER_4, |
1735 | 3, 7, 0, bypass_tlv), |
1736 | SOC_SINGLE_TLV("HPMIXR IN4R Volume" , WM8962_HEADPHONE_MIXER_4, |
1737 | 0, 7, 0, bypass_tlv), |
1738 | SOC_SINGLE_TLV("HPMIXR MIXINL Volume" , WM8962_HEADPHONE_MIXER_4, |
1739 | 7, 1, 1, inmix_tlv), |
1740 | SOC_SINGLE_TLV("HPMIXR MIXINR Volume" , WM8962_HEADPHONE_MIXER_4, |
1741 | 6, 1, 1, inmix_tlv), |
1742 | |
1743 | SOC_SINGLE_TLV("Speaker Boost Volume" , WM8962_CLASS_D_CONTROL_2, 0, 7, 0, |
1744 | classd_tlv), |
1745 | |
1746 | SOC_SINGLE("EQ Switch" , WM8962_EQ1, WM8962_EQ_ENA_SHIFT, 1, 0), |
1747 | SOC_DOUBLE_R_TLV("EQ1 Volume" , WM8962_EQ2, WM8962_EQ22, |
1748 | WM8962_EQL_B1_GAIN_SHIFT, 31, 0, eq_tlv), |
1749 | SOC_DOUBLE_R_TLV("EQ2 Volume" , WM8962_EQ2, WM8962_EQ22, |
1750 | WM8962_EQL_B2_GAIN_SHIFT, 31, 0, eq_tlv), |
1751 | SOC_DOUBLE_R_TLV("EQ3 Volume" , WM8962_EQ2, WM8962_EQ22, |
1752 | WM8962_EQL_B3_GAIN_SHIFT, 31, 0, eq_tlv), |
1753 | SOC_DOUBLE_R_TLV("EQ4 Volume" , WM8962_EQ3, WM8962_EQ23, |
1754 | WM8962_EQL_B4_GAIN_SHIFT, 31, 0, eq_tlv), |
1755 | SOC_DOUBLE_R_TLV("EQ5 Volume" , WM8962_EQ3, WM8962_EQ23, |
1756 | WM8962_EQL_B5_GAIN_SHIFT, 31, 0, eq_tlv), |
1757 | SND_SOC_BYTES("EQL Coefficients" , WM8962_EQ4, 18), |
1758 | SND_SOC_BYTES("EQR Coefficients" , WM8962_EQ24, 18), |
1759 | |
1760 | |
1761 | SOC_SINGLE("3D Switch" , WM8962_THREED1, 0, 1, 0), |
1762 | SND_SOC_BYTES_MASK("3D Coefficients" , WM8962_THREED1, 4, WM8962_THREED_ENA), |
1763 | |
1764 | SOC_SINGLE("DF1 Switch" , WM8962_DF1, 0, 1, 0), |
1765 | SND_SOC_BYTES_MASK("DF1 Coefficients" , WM8962_DF1, 7, WM8962_DF1_ENA), |
1766 | |
1767 | SOC_SINGLE("DRC Switch" , WM8962_DRC_1, 0, 1, 0), |
1768 | SND_SOC_BYTES_MASK("DRC Coefficients" , WM8962_DRC_1, 5, WM8962_DRC_ENA), |
1769 | |
1770 | WM8962_DSP2_ENABLE("VSS Switch" , WM8962_VSS_ENA_SHIFT), |
1771 | SND_SOC_BYTES("VSS Coefficients" , WM8962_VSS_XHD2_1, 148), |
1772 | WM8962_DSP2_ENABLE("HPF1 Switch" , WM8962_HPF1_ENA_SHIFT), |
1773 | WM8962_DSP2_ENABLE("HPF2 Switch" , WM8962_HPF2_ENA_SHIFT), |
1774 | SND_SOC_BYTES("HPF Coefficients" , WM8962_LHPF2, 1), |
1775 | WM8962_DSP2_ENABLE("HD Bass Switch" , WM8962_HDBASS_ENA_SHIFT), |
1776 | SND_SOC_BYTES("HD Bass Coefficients" , WM8962_HDBASS_AI_1, 30), |
1777 | |
1778 | SOC_DOUBLE("ALC Switch" , WM8962_ALC1, WM8962_ALCL_ENA_SHIFT, |
1779 | WM8962_ALCR_ENA_SHIFT, 1, 0), |
1780 | SND_SOC_BYTES_MASK("ALC Coefficients" , WM8962_ALC1, 4, |
1781 | WM8962_ALCL_ENA_MASK | WM8962_ALCR_ENA_MASK), |
1782 | }; |
1783 | |
1784 | static const struct snd_kcontrol_new wm8962_spk_mono_controls[] = { |
1785 | SOC_SINGLE_TLV("Speaker Volume" , WM8962_SPKOUTL_VOLUME, 0, 127, 0, out_tlv), |
1786 | SOC_SINGLE_EXT("Speaker Switch" , WM8962_CLASS_D_CONTROL_1, 1, 1, 1, |
1787 | snd_soc_get_volsw, wm8962_put_spk_sw), |
1788 | SOC_SINGLE("Speaker ZC Switch" , WM8962_SPKOUTL_VOLUME, 7, 1, 0), |
1789 | |
1790 | SOC_SINGLE("Speaker Mixer Switch" , WM8962_SPEAKER_MIXER_3, 8, 1, 1), |
1791 | SOC_SINGLE_TLV("Speaker Mixer IN4L Volume" , WM8962_SPEAKER_MIXER_3, |
1792 | 3, 7, 0, bypass_tlv), |
1793 | SOC_SINGLE_TLV("Speaker Mixer IN4R Volume" , WM8962_SPEAKER_MIXER_3, |
1794 | 0, 7, 0, bypass_tlv), |
1795 | SOC_SINGLE_TLV("Speaker Mixer MIXINL Volume" , WM8962_SPEAKER_MIXER_3, |
1796 | 7, 1, 1, inmix_tlv), |
1797 | SOC_SINGLE_TLV("Speaker Mixer MIXINR Volume" , WM8962_SPEAKER_MIXER_3, |
1798 | 6, 1, 1, inmix_tlv), |
1799 | SOC_SINGLE_TLV("Speaker Mixer DACL Volume" , WM8962_SPEAKER_MIXER_5, |
1800 | 7, 1, 0, inmix_tlv), |
1801 | SOC_SINGLE_TLV("Speaker Mixer DACR Volume" , WM8962_SPEAKER_MIXER_5, |
1802 | 6, 1, 0, inmix_tlv), |
1803 | }; |
1804 | |
1805 | static const struct snd_kcontrol_new wm8962_spk_stereo_controls[] = { |
1806 | SOC_DOUBLE_R_TLV("Speaker Volume" , WM8962_SPKOUTL_VOLUME, |
1807 | WM8962_SPKOUTR_VOLUME, 0, 127, 0, out_tlv), |
1808 | SOC_DOUBLE_EXT("Speaker Switch" , WM8962_CLASS_D_CONTROL_1, 1, 0, 1, 1, |
1809 | snd_soc_get_volsw, wm8962_put_spk_sw), |
1810 | SOC_DOUBLE_R("Speaker ZC Switch" , WM8962_SPKOUTL_VOLUME, WM8962_SPKOUTR_VOLUME, |
1811 | 7, 1, 0), |
1812 | |
1813 | SOC_DOUBLE_R("Speaker Mixer Switch" , WM8962_SPEAKER_MIXER_3, |
1814 | WM8962_SPEAKER_MIXER_4, 8, 1, 1), |
1815 | |
1816 | SOC_SINGLE_TLV("SPKOUTL Mixer IN4L Volume" , WM8962_SPEAKER_MIXER_3, |
1817 | 3, 7, 0, bypass_tlv), |
1818 | SOC_SINGLE_TLV("SPKOUTL Mixer IN4R Volume" , WM8962_SPEAKER_MIXER_3, |
1819 | 0, 7, 0, bypass_tlv), |
1820 | SOC_SINGLE_TLV("SPKOUTL Mixer MIXINL Volume" , WM8962_SPEAKER_MIXER_3, |
1821 | 7, 1, 1, inmix_tlv), |
1822 | SOC_SINGLE_TLV("SPKOUTL Mixer MIXINR Volume" , WM8962_SPEAKER_MIXER_3, |
1823 | 6, 1, 1, inmix_tlv), |
1824 | SOC_SINGLE_TLV("SPKOUTL Mixer DACL Volume" , WM8962_SPEAKER_MIXER_5, |
1825 | 7, 1, 0, inmix_tlv), |
1826 | SOC_SINGLE_TLV("SPKOUTL Mixer DACR Volume" , WM8962_SPEAKER_MIXER_5, |
1827 | 6, 1, 0, inmix_tlv), |
1828 | |
1829 | SOC_SINGLE_TLV("SPKOUTR Mixer IN4L Volume" , WM8962_SPEAKER_MIXER_4, |
1830 | 3, 7, 0, bypass_tlv), |
1831 | SOC_SINGLE_TLV("SPKOUTR Mixer IN4R Volume" , WM8962_SPEAKER_MIXER_4, |
1832 | 0, 7, 0, bypass_tlv), |
1833 | SOC_SINGLE_TLV("SPKOUTR Mixer MIXINL Volume" , WM8962_SPEAKER_MIXER_4, |
1834 | 7, 1, 1, inmix_tlv), |
1835 | SOC_SINGLE_TLV("SPKOUTR Mixer MIXINR Volume" , WM8962_SPEAKER_MIXER_4, |
1836 | 6, 1, 1, inmix_tlv), |
1837 | SOC_SINGLE_TLV("SPKOUTR Mixer DACL Volume" , WM8962_SPEAKER_MIXER_5, |
1838 | 5, 1, 0, inmix_tlv), |
1839 | SOC_SINGLE_TLV("SPKOUTR Mixer DACR Volume" , WM8962_SPEAKER_MIXER_5, |
1840 | 4, 1, 0, inmix_tlv), |
1841 | }; |
1842 | |
1843 | static int tp_event(struct snd_soc_dapm_widget *w, |
1844 | struct snd_kcontrol *kcontrol, int event) |
1845 | { |
1846 | int ret, reg, val, mask; |
1847 | struct snd_soc_component *component = snd_soc_dapm_to_component(dapm: w->dapm); |
1848 | |
1849 | ret = pm_runtime_resume_and_get(dev: component->dev); |
1850 | if (ret < 0) { |
1851 | dev_err(component->dev, "Failed to resume device: %d\n" , ret); |
1852 | return ret; |
1853 | } |
1854 | |
1855 | reg = WM8962_ADDITIONAL_CONTROL_4; |
1856 | |
1857 | if (!snd_soc_dapm_widget_name_cmp(widget: w, s: "TEMP_HP" )) { |
1858 | mask = WM8962_TEMP_ENA_HP_MASK; |
1859 | val = WM8962_TEMP_ENA_HP; |
1860 | } else if (!snd_soc_dapm_widget_name_cmp(widget: w, s: "TEMP_SPK" )) { |
1861 | mask = WM8962_TEMP_ENA_SPK_MASK; |
1862 | val = WM8962_TEMP_ENA_SPK; |
1863 | } else { |
1864 | pm_runtime_put(dev: component->dev); |
1865 | return -EINVAL; |
1866 | } |
1867 | |
1868 | switch (event) { |
1869 | case SND_SOC_DAPM_POST_PMD: |
1870 | val = 0; |
1871 | fallthrough; |
1872 | case SND_SOC_DAPM_POST_PMU: |
1873 | ret = snd_soc_component_update_bits(component, reg, mask, val); |
1874 | break; |
1875 | default: |
1876 | WARN(1, "Invalid event %d\n" , event); |
1877 | pm_runtime_put(dev: component->dev); |
1878 | return -EINVAL; |
1879 | } |
1880 | |
1881 | pm_runtime_put(dev: component->dev); |
1882 | |
1883 | return 0; |
1884 | } |
1885 | |
1886 | static int cp_event(struct snd_soc_dapm_widget *w, |
1887 | struct snd_kcontrol *kcontrol, int event) |
1888 | { |
1889 | switch (event) { |
1890 | case SND_SOC_DAPM_POST_PMU: |
1891 | msleep(msecs: 5); |
1892 | break; |
1893 | |
1894 | default: |
1895 | WARN(1, "Invalid event %d\n" , event); |
1896 | return -EINVAL; |
1897 | } |
1898 | |
1899 | return 0; |
1900 | } |
1901 | |
1902 | static int hp_event(struct snd_soc_dapm_widget *w, |
1903 | struct snd_kcontrol *kcontrol, int event) |
1904 | { |
1905 | struct snd_soc_component *component = snd_soc_dapm_to_component(dapm: w->dapm); |
1906 | int timeout; |
1907 | int reg; |
1908 | int expected = (WM8962_DCS_STARTUP_DONE_HP1L | |
1909 | WM8962_DCS_STARTUP_DONE_HP1R); |
1910 | |
1911 | switch (event) { |
1912 | case SND_SOC_DAPM_POST_PMU: |
1913 | snd_soc_component_update_bits(component, WM8962_ANALOGUE_HP_0, |
1914 | WM8962_HP1L_ENA | WM8962_HP1R_ENA, |
1915 | WM8962_HP1L_ENA | WM8962_HP1R_ENA); |
1916 | udelay(20); |
1917 | |
1918 | snd_soc_component_update_bits(component, WM8962_ANALOGUE_HP_0, |
1919 | WM8962_HP1L_ENA_DLY | WM8962_HP1R_ENA_DLY, |
1920 | WM8962_HP1L_ENA_DLY | WM8962_HP1R_ENA_DLY); |
1921 | |
1922 | /* Start the DC servo */ |
1923 | snd_soc_component_update_bits(component, WM8962_DC_SERVO_1, |
1924 | WM8962_HP1L_DCS_ENA | WM8962_HP1R_DCS_ENA | |
1925 | WM8962_HP1L_DCS_STARTUP | |
1926 | WM8962_HP1R_DCS_STARTUP, |
1927 | WM8962_HP1L_DCS_ENA | WM8962_HP1R_DCS_ENA | |
1928 | WM8962_HP1L_DCS_STARTUP | |
1929 | WM8962_HP1R_DCS_STARTUP); |
1930 | |
1931 | /* Wait for it to complete, should be well under 100ms */ |
1932 | timeout = 0; |
1933 | do { |
1934 | msleep(msecs: 1); |
1935 | reg = snd_soc_component_read(component, WM8962_DC_SERVO_6); |
1936 | if (reg < 0) { |
1937 | dev_err(component->dev, |
1938 | "Failed to read DCS status: %d\n" , |
1939 | reg); |
1940 | continue; |
1941 | } |
1942 | dev_dbg(component->dev, "DCS status: %x\n" , reg); |
1943 | } while (++timeout < 200 && (reg & expected) != expected); |
1944 | |
1945 | if ((reg & expected) != expected) |
1946 | dev_err(component->dev, "DC servo timed out\n" ); |
1947 | else |
1948 | dev_dbg(component->dev, "DC servo complete after %dms\n" , |
1949 | timeout); |
1950 | |
1951 | snd_soc_component_update_bits(component, WM8962_ANALOGUE_HP_0, |
1952 | WM8962_HP1L_ENA_OUTP | |
1953 | WM8962_HP1R_ENA_OUTP, |
1954 | WM8962_HP1L_ENA_OUTP | |
1955 | WM8962_HP1R_ENA_OUTP); |
1956 | udelay(20); |
1957 | |
1958 | snd_soc_component_update_bits(component, WM8962_ANALOGUE_HP_0, |
1959 | WM8962_HP1L_RMV_SHORT | |
1960 | WM8962_HP1R_RMV_SHORT, |
1961 | WM8962_HP1L_RMV_SHORT | |
1962 | WM8962_HP1R_RMV_SHORT); |
1963 | break; |
1964 | |
1965 | case SND_SOC_DAPM_PRE_PMD: |
1966 | snd_soc_component_update_bits(component, WM8962_ANALOGUE_HP_0, |
1967 | WM8962_HP1L_RMV_SHORT | |
1968 | WM8962_HP1R_RMV_SHORT, val: 0); |
1969 | |
1970 | udelay(20); |
1971 | |
1972 | snd_soc_component_update_bits(component, WM8962_DC_SERVO_1, |
1973 | WM8962_HP1L_DCS_ENA | WM8962_HP1R_DCS_ENA | |
1974 | WM8962_HP1L_DCS_STARTUP | |
1975 | WM8962_HP1R_DCS_STARTUP, |
1976 | val: 0); |
1977 | |
1978 | snd_soc_component_update_bits(component, WM8962_ANALOGUE_HP_0, |
1979 | WM8962_HP1L_ENA | WM8962_HP1R_ENA | |
1980 | WM8962_HP1L_ENA_DLY | WM8962_HP1R_ENA_DLY | |
1981 | WM8962_HP1L_ENA_OUTP | |
1982 | WM8962_HP1R_ENA_OUTP, val: 0); |
1983 | |
1984 | break; |
1985 | |
1986 | default: |
1987 | WARN(1, "Invalid event %d\n" , event); |
1988 | return -EINVAL; |
1989 | |
1990 | } |
1991 | |
1992 | return 0; |
1993 | } |
1994 | |
1995 | /* VU bits for the output PGAs only take effect while the PGA is powered */ |
1996 | static int out_pga_event(struct snd_soc_dapm_widget *w, |
1997 | struct snd_kcontrol *kcontrol, int event) |
1998 | { |
1999 | struct snd_soc_component *component = snd_soc_dapm_to_component(dapm: w->dapm); |
2000 | int reg; |
2001 | |
2002 | switch (w->shift) { |
2003 | case WM8962_HPOUTR_PGA_ENA_SHIFT: |
2004 | reg = WM8962_HPOUTR_VOLUME; |
2005 | break; |
2006 | case WM8962_HPOUTL_PGA_ENA_SHIFT: |
2007 | reg = WM8962_HPOUTL_VOLUME; |
2008 | break; |
2009 | case WM8962_SPKOUTR_PGA_ENA_SHIFT: |
2010 | reg = WM8962_SPKOUTR_VOLUME; |
2011 | break; |
2012 | case WM8962_SPKOUTL_PGA_ENA_SHIFT: |
2013 | reg = WM8962_SPKOUTL_VOLUME; |
2014 | break; |
2015 | default: |
2016 | WARN(1, "Invalid shift %d\n" , w->shift); |
2017 | return -EINVAL; |
2018 | } |
2019 | |
2020 | switch (event) { |
2021 | case SND_SOC_DAPM_POST_PMU: |
2022 | return snd_soc_component_write(component, reg, |
2023 | val: snd_soc_component_read(component, reg)); |
2024 | default: |
2025 | WARN(1, "Invalid event %d\n" , event); |
2026 | return -EINVAL; |
2027 | } |
2028 | } |
2029 | |
2030 | static int dsp2_event(struct snd_soc_dapm_widget *w, |
2031 | struct snd_kcontrol *kcontrol, int event) |
2032 | { |
2033 | struct snd_soc_component *component = snd_soc_dapm_to_component(dapm: w->dapm); |
2034 | struct wm8962_priv *wm8962 = snd_soc_component_get_drvdata(c: component); |
2035 | |
2036 | switch (event) { |
2037 | case SND_SOC_DAPM_POST_PMU: |
2038 | if (wm8962->dsp2_ena) |
2039 | wm8962_dsp2_start(component); |
2040 | break; |
2041 | |
2042 | case SND_SOC_DAPM_PRE_PMD: |
2043 | if (wm8962->dsp2_ena) |
2044 | wm8962_dsp2_stop(component); |
2045 | break; |
2046 | |
2047 | default: |
2048 | WARN(1, "Invalid event %d\n" , event); |
2049 | return -EINVAL; |
2050 | } |
2051 | |
2052 | return 0; |
2053 | } |
2054 | |
2055 | static const char *st_text[] = { "None" , "Left" , "Right" }; |
2056 | |
2057 | static SOC_ENUM_SINGLE_DECL(str_enum, |
2058 | WM8962_DAC_DSP_MIXING_1, 2, st_text); |
2059 | |
2060 | static const struct snd_kcontrol_new str_mux = |
2061 | SOC_DAPM_ENUM("Right Sidetone" , str_enum); |
2062 | |
2063 | static SOC_ENUM_SINGLE_DECL(stl_enum, |
2064 | WM8962_DAC_DSP_MIXING_2, 2, st_text); |
2065 | |
2066 | static const struct snd_kcontrol_new stl_mux = |
2067 | SOC_DAPM_ENUM("Left Sidetone" , stl_enum); |
2068 | |
2069 | static const char *outmux_text[] = { "DAC" , "Mixer" }; |
2070 | |
2071 | static SOC_ENUM_SINGLE_DECL(spkoutr_enum, |
2072 | WM8962_SPEAKER_MIXER_2, 7, outmux_text); |
2073 | |
2074 | static const struct snd_kcontrol_new spkoutr_mux = |
2075 | SOC_DAPM_ENUM("SPKOUTR Mux" , spkoutr_enum); |
2076 | |
2077 | static SOC_ENUM_SINGLE_DECL(spkoutl_enum, |
2078 | WM8962_SPEAKER_MIXER_1, 7, outmux_text); |
2079 | |
2080 | static const struct snd_kcontrol_new spkoutl_mux = |
2081 | SOC_DAPM_ENUM("SPKOUTL Mux" , spkoutl_enum); |
2082 | |
2083 | static SOC_ENUM_SINGLE_DECL(hpoutr_enum, |
2084 | WM8962_HEADPHONE_MIXER_2, 7, outmux_text); |
2085 | |
2086 | static const struct snd_kcontrol_new hpoutr_mux = |
2087 | SOC_DAPM_ENUM("HPOUTR Mux" , hpoutr_enum); |
2088 | |
2089 | static SOC_ENUM_SINGLE_DECL(hpoutl_enum, |
2090 | WM8962_HEADPHONE_MIXER_1, 7, outmux_text); |
2091 | |
2092 | static const struct snd_kcontrol_new hpoutl_mux = |
2093 | SOC_DAPM_ENUM("HPOUTL Mux" , hpoutl_enum); |
2094 | |
2095 | static const char * const input_mode_text[] = { "Analog" , "Digital" }; |
2096 | |
2097 | static SOC_ENUM_SINGLE_VIRT_DECL(input_mode_enum, input_mode_text); |
2098 | |
2099 | static const struct snd_kcontrol_new input_mode_mux = |
2100 | SOC_DAPM_ENUM("Input Mode" , input_mode_enum); |
2101 | |
2102 | static const struct snd_kcontrol_new inpgal[] = { |
2103 | SOC_DAPM_SINGLE("IN1L Switch" , WM8962_LEFT_INPUT_PGA_CONTROL, 3, 1, 0), |
2104 | SOC_DAPM_SINGLE("IN2L Switch" , WM8962_LEFT_INPUT_PGA_CONTROL, 2, 1, 0), |
2105 | SOC_DAPM_SINGLE("IN3L Switch" , WM8962_LEFT_INPUT_PGA_CONTROL, 1, 1, 0), |
2106 | SOC_DAPM_SINGLE("IN4L Switch" , WM8962_LEFT_INPUT_PGA_CONTROL, 0, 1, 0), |
2107 | }; |
2108 | |
2109 | static const struct snd_kcontrol_new inpgar[] = { |
2110 | SOC_DAPM_SINGLE("IN1R Switch" , WM8962_RIGHT_INPUT_PGA_CONTROL, 3, 1, 0), |
2111 | SOC_DAPM_SINGLE("IN2R Switch" , WM8962_RIGHT_INPUT_PGA_CONTROL, 2, 1, 0), |
2112 | SOC_DAPM_SINGLE("IN3R Switch" , WM8962_RIGHT_INPUT_PGA_CONTROL, 1, 1, 0), |
2113 | SOC_DAPM_SINGLE("IN4R Switch" , WM8962_RIGHT_INPUT_PGA_CONTROL, 0, 1, 0), |
2114 | }; |
2115 | |
2116 | static const struct snd_kcontrol_new mixinl[] = { |
2117 | SOC_DAPM_SINGLE("IN2L Switch" , WM8962_INPUT_MIXER_CONTROL_2, 5, 1, 0), |
2118 | SOC_DAPM_SINGLE("IN3L Switch" , WM8962_INPUT_MIXER_CONTROL_2, 4, 1, 0), |
2119 | SOC_DAPM_SINGLE("PGA Switch" , WM8962_INPUT_MIXER_CONTROL_2, 3, 1, 0), |
2120 | }; |
2121 | |
2122 | static const struct snd_kcontrol_new mixinr[] = { |
2123 | SOC_DAPM_SINGLE("IN2R Switch" , WM8962_INPUT_MIXER_CONTROL_2, 2, 1, 0), |
2124 | SOC_DAPM_SINGLE("IN3R Switch" , WM8962_INPUT_MIXER_CONTROL_2, 1, 1, 0), |
2125 | SOC_DAPM_SINGLE("PGA Switch" , WM8962_INPUT_MIXER_CONTROL_2, 0, 1, 0), |
2126 | }; |
2127 | |
2128 | static const struct snd_kcontrol_new hpmixl[] = { |
2129 | SOC_DAPM_SINGLE("DACL Switch" , WM8962_HEADPHONE_MIXER_1, 5, 1, 0), |
2130 | SOC_DAPM_SINGLE("DACR Switch" , WM8962_HEADPHONE_MIXER_1, 4, 1, 0), |
2131 | SOC_DAPM_SINGLE("MIXINL Switch" , WM8962_HEADPHONE_MIXER_1, 3, 1, 0), |
2132 | SOC_DAPM_SINGLE("MIXINR Switch" , WM8962_HEADPHONE_MIXER_1, 2, 1, 0), |
2133 | SOC_DAPM_SINGLE("IN4L Switch" , WM8962_HEADPHONE_MIXER_1, 1, 1, 0), |
2134 | SOC_DAPM_SINGLE("IN4R Switch" , WM8962_HEADPHONE_MIXER_1, 0, 1, 0), |
2135 | }; |
2136 | |
2137 | static const struct snd_kcontrol_new hpmixr[] = { |
2138 | SOC_DAPM_SINGLE("DACL Switch" , WM8962_HEADPHONE_MIXER_2, 5, 1, 0), |
2139 | SOC_DAPM_SINGLE("DACR Switch" , WM8962_HEADPHONE_MIXER_2, 4, 1, 0), |
2140 | SOC_DAPM_SINGLE("MIXINL Switch" , WM8962_HEADPHONE_MIXER_2, 3, 1, 0), |
2141 | SOC_DAPM_SINGLE("MIXINR Switch" , WM8962_HEADPHONE_MIXER_2, 2, 1, 0), |
2142 | SOC_DAPM_SINGLE("IN4L Switch" , WM8962_HEADPHONE_MIXER_2, 1, 1, 0), |
2143 | SOC_DAPM_SINGLE("IN4R Switch" , WM8962_HEADPHONE_MIXER_2, 0, 1, 0), |
2144 | }; |
2145 | |
2146 | static const struct snd_kcontrol_new spkmixl[] = { |
2147 | SOC_DAPM_SINGLE("DACL Switch" , WM8962_SPEAKER_MIXER_1, 5, 1, 0), |
2148 | SOC_DAPM_SINGLE("DACR Switch" , WM8962_SPEAKER_MIXER_1, 4, 1, 0), |
2149 | SOC_DAPM_SINGLE("MIXINL Switch" , WM8962_SPEAKER_MIXER_1, 3, 1, 0), |
2150 | SOC_DAPM_SINGLE("MIXINR Switch" , WM8962_SPEAKER_MIXER_1, 2, 1, 0), |
2151 | SOC_DAPM_SINGLE("IN4L Switch" , WM8962_SPEAKER_MIXER_1, 1, 1, 0), |
2152 | SOC_DAPM_SINGLE("IN4R Switch" , WM8962_SPEAKER_MIXER_1, 0, 1, 0), |
2153 | }; |
2154 | |
2155 | static const struct snd_kcontrol_new spkmixr[] = { |
2156 | SOC_DAPM_SINGLE("DACL Switch" , WM8962_SPEAKER_MIXER_2, 5, 1, 0), |
2157 | SOC_DAPM_SINGLE("DACR Switch" , WM8962_SPEAKER_MIXER_2, 4, 1, 0), |
2158 | SOC_DAPM_SINGLE("MIXINL Switch" , WM8962_SPEAKER_MIXER_2, 3, 1, 0), |
2159 | SOC_DAPM_SINGLE("MIXINR Switch" , WM8962_SPEAKER_MIXER_2, 2, 1, 0), |
2160 | SOC_DAPM_SINGLE("IN4L Switch" , WM8962_SPEAKER_MIXER_2, 1, 1, 0), |
2161 | SOC_DAPM_SINGLE("IN4R Switch" , WM8962_SPEAKER_MIXER_2, 0, 1, 0), |
2162 | }; |
2163 | |
2164 | static const struct snd_soc_dapm_widget wm8962_dapm_widgets[] = { |
2165 | SND_SOC_DAPM_INPUT("IN1L" ), |
2166 | SND_SOC_DAPM_INPUT("IN1R" ), |
2167 | SND_SOC_DAPM_INPUT("IN2L" ), |
2168 | SND_SOC_DAPM_INPUT("IN2R" ), |
2169 | SND_SOC_DAPM_INPUT("IN3L" ), |
2170 | SND_SOC_DAPM_INPUT("IN3R" ), |
2171 | SND_SOC_DAPM_INPUT("IN4L" ), |
2172 | SND_SOC_DAPM_INPUT("IN4R" ), |
2173 | SND_SOC_DAPM_SIGGEN("Beep" ), |
2174 | SND_SOC_DAPM_INPUT("DMICDAT" ), |
2175 | |
2176 | SND_SOC_DAPM_SUPPLY("MICBIAS" , WM8962_PWR_MGMT_1, 1, 0, NULL, 0), |
2177 | |
2178 | SND_SOC_DAPM_SUPPLY("Class G" , WM8962_CHARGE_PUMP_B, 0, 1, NULL, 0), |
2179 | SND_SOC_DAPM_SUPPLY("SYSCLK" , WM8962_CLOCKING2, 5, 0, NULL, 0), |
2180 | SND_SOC_DAPM_SUPPLY("Charge Pump" , WM8962_CHARGE_PUMP_1, 0, 0, cp_event, |
2181 | SND_SOC_DAPM_POST_PMU), |
2182 | SND_SOC_DAPM_SUPPLY("TOCLK" , WM8962_ADDITIONAL_CONTROL_1, 0, 0, NULL, 0), |
2183 | SND_SOC_DAPM_SUPPLY_S("DSP2" , 1, WM8962_DSP2_POWER_MANAGEMENT, |
2184 | WM8962_DSP2_ENA_SHIFT, 0, dsp2_event, |
2185 | SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), |
2186 | SND_SOC_DAPM_SUPPLY("TEMP_HP" , SND_SOC_NOPM, 0, 0, tp_event, |
2187 | SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD), |
2188 | SND_SOC_DAPM_SUPPLY("TEMP_SPK" , SND_SOC_NOPM, 0, 0, tp_event, |
2189 | SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD), |
2190 | |
2191 | SND_SOC_DAPM_MIXER("INPGAL" , WM8962_LEFT_INPUT_PGA_CONTROL, 4, 0, |
2192 | inpgal, ARRAY_SIZE(inpgal)), |
2193 | SND_SOC_DAPM_MIXER("INPGAR" , WM8962_RIGHT_INPUT_PGA_CONTROL, 4, 0, |
2194 | inpgar, ARRAY_SIZE(inpgar)), |
2195 | SND_SOC_DAPM_MIXER("MIXINL" , WM8962_PWR_MGMT_1, 5, 0, |
2196 | mixinl, ARRAY_SIZE(mixinl)), |
2197 | SND_SOC_DAPM_MIXER("MIXINR" , WM8962_PWR_MGMT_1, 4, 0, |
2198 | mixinr, ARRAY_SIZE(mixinr)), |
2199 | |
2200 | SND_SOC_DAPM_AIF_IN("DMIC_ENA" , NULL, 0, WM8962_PWR_MGMT_1, 10, 0), |
2201 | |
2202 | SND_SOC_DAPM_MUX("Input Mode L" , SND_SOC_NOPM, 0, 0, &input_mode_mux), |
2203 | SND_SOC_DAPM_MUX("Input Mode R" , SND_SOC_NOPM, 0, 0, &input_mode_mux), |
2204 | |
2205 | SND_SOC_DAPM_ADC("ADCL" , "Capture" , WM8962_PWR_MGMT_1, 3, 0), |
2206 | SND_SOC_DAPM_ADC("ADCR" , "Capture" , WM8962_PWR_MGMT_1, 2, 0), |
2207 | |
2208 | SND_SOC_DAPM_MUX("STL" , SND_SOC_NOPM, 0, 0, &stl_mux), |
2209 | SND_SOC_DAPM_MUX("STR" , SND_SOC_NOPM, 0, 0, &str_mux), |
2210 | |
2211 | SND_SOC_DAPM_DAC("DACL" , "Playback" , WM8962_PWR_MGMT_2, 8, 0), |
2212 | SND_SOC_DAPM_DAC("DACR" , "Playback" , WM8962_PWR_MGMT_2, 7, 0), |
2213 | |
2214 | SND_SOC_DAPM_PGA("Left Bypass" , SND_SOC_NOPM, 0, 0, NULL, 0), |
2215 | SND_SOC_DAPM_PGA("Right Bypass" , SND_SOC_NOPM, 0, 0, NULL, 0), |
2216 | |
2217 | SND_SOC_DAPM_MIXER("HPMIXL" , WM8962_MIXER_ENABLES, 3, 0, |
2218 | hpmixl, ARRAY_SIZE(hpmixl)), |
2219 | SND_SOC_DAPM_MIXER("HPMIXR" , WM8962_MIXER_ENABLES, 2, 0, |
2220 | hpmixr, ARRAY_SIZE(hpmixr)), |
2221 | |
2222 | SND_SOC_DAPM_MUX_E("HPOUTL PGA" , WM8962_PWR_MGMT_2, 6, 0, &hpoutl_mux, |
2223 | out_pga_event, SND_SOC_DAPM_POST_PMU), |
2224 | SND_SOC_DAPM_MUX_E("HPOUTR PGA" , WM8962_PWR_MGMT_2, 5, 0, &hpoutr_mux, |
2225 | out_pga_event, SND_SOC_DAPM_POST_PMU), |
2226 | |
2227 | SND_SOC_DAPM_PGA_E("HPOUT" , SND_SOC_NOPM, 0, 0, NULL, 0, hp_event, |
2228 | SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), |
2229 | |
2230 | SND_SOC_DAPM_OUTPUT("HPOUTL" ), |
2231 | SND_SOC_DAPM_OUTPUT("HPOUTR" ), |
2232 | |
2233 | SND_SOC_DAPM_PGA("SPKOUTL Output" , WM8962_CLASS_D_CONTROL_1, 6, 0, NULL, 0), |
2234 | SND_SOC_DAPM_PGA("SPKOUTR Output" , WM8962_CLASS_D_CONTROL_1, 7, 0, NULL, 0), |
2235 | }; |
2236 | |
2237 | static const struct snd_soc_dapm_widget wm8962_dapm_spk_mono_widgets[] = { |
2238 | SND_SOC_DAPM_MIXER("Speaker Mixer" , WM8962_MIXER_ENABLES, 1, 0, |
2239 | spkmixl, ARRAY_SIZE(spkmixl)), |
2240 | SND_SOC_DAPM_MUX_E("Speaker PGA" , WM8962_PWR_MGMT_2, 4, 0, &spkoutl_mux, |
2241 | out_pga_event, SND_SOC_DAPM_POST_PMU), |
2242 | SND_SOC_DAPM_OUTPUT("SPKOUT" ), |
2243 | }; |
2244 | |
2245 | static const struct snd_soc_dapm_widget wm8962_dapm_spk_stereo_widgets[] = { |
2246 | SND_SOC_DAPM_MIXER("SPKOUTL Mixer" , WM8962_MIXER_ENABLES, 1, 0, |
2247 | spkmixl, ARRAY_SIZE(spkmixl)), |
2248 | SND_SOC_DAPM_MIXER("SPKOUTR Mixer" , WM8962_MIXER_ENABLES, 0, 0, |
2249 | spkmixr, ARRAY_SIZE(spkmixr)), |
2250 | |
2251 | SND_SOC_DAPM_MUX_E("SPKOUTL PGA" , WM8962_PWR_MGMT_2, 4, 0, &spkoutl_mux, |
2252 | out_pga_event, SND_SOC_DAPM_POST_PMU), |
2253 | SND_SOC_DAPM_MUX_E("SPKOUTR PGA" , WM8962_PWR_MGMT_2, 3, 0, &spkoutr_mux, |
2254 | out_pga_event, SND_SOC_DAPM_POST_PMU), |
2255 | |
2256 | SND_SOC_DAPM_OUTPUT("SPKOUTL" ), |
2257 | SND_SOC_DAPM_OUTPUT("SPKOUTR" ), |
2258 | }; |
2259 | |
2260 | static const struct snd_soc_dapm_route wm8962_intercon[] = { |
2261 | { "INPGAL" , "IN1L Switch" , "IN1L" }, |
2262 | { "INPGAL" , "IN2L Switch" , "IN2L" }, |
2263 | { "INPGAL" , "IN3L Switch" , "IN3L" }, |
2264 | { "INPGAL" , "IN4L Switch" , "IN4L" }, |
2265 | |
2266 | { "INPGAR" , "IN1R Switch" , "IN1R" }, |
2267 | { "INPGAR" , "IN2R Switch" , "IN2R" }, |
2268 | { "INPGAR" , "IN3R Switch" , "IN3R" }, |
2269 | { "INPGAR" , "IN4R Switch" , "IN4R" }, |
2270 | |
2271 | { "MIXINL" , "IN2L Switch" , "IN2L" }, |
2272 | { "MIXINL" , "IN3L Switch" , "IN3L" }, |
2273 | { "MIXINL" , "PGA Switch" , "INPGAL" }, |
2274 | |
2275 | { "MIXINR" , "IN2R Switch" , "IN2R" }, |
2276 | { "MIXINR" , "IN3R Switch" , "IN3R" }, |
2277 | { "MIXINR" , "PGA Switch" , "INPGAR" }, |
2278 | |
2279 | { "MICBIAS" , NULL, "SYSCLK" }, |
2280 | |
2281 | { "DMIC_ENA" , NULL, "DMICDAT" }, |
2282 | |
2283 | { "Input Mode L" , "Analog" , "MIXINL" }, |
2284 | { "Input Mode L" , "Digital" , "DMIC_ENA" }, |
2285 | { "Input Mode R" , "Analog" , "MIXINR" }, |
2286 | { "Input Mode R" , "Digital" , "DMIC_ENA" }, |
2287 | |
2288 | { "ADCL" , NULL, "SYSCLK" }, |
2289 | { "ADCL" , NULL, "TOCLK" }, |
2290 | { "ADCL" , NULL, "Input Mode L" }, |
2291 | { "ADCL" , NULL, "DSP2" }, |
2292 | |
2293 | { "ADCR" , NULL, "SYSCLK" }, |
2294 | { "ADCR" , NULL, "TOCLK" }, |
2295 | { "ADCR" , NULL, "Input Mode R" }, |
2296 | { "ADCR" , NULL, "DSP2" }, |
2297 | |
2298 | { "STL" , "Left" , "ADCL" }, |
2299 | { "STL" , "Right" , "ADCR" }, |
2300 | { "STL" , NULL, "Class G" }, |
2301 | |
2302 | { "STR" , "Left" , "ADCL" }, |
2303 | { "STR" , "Right" , "ADCR" }, |
2304 | { "STR" , NULL, "Class G" }, |
2305 | |
2306 | { "DACL" , NULL, "SYSCLK" }, |
2307 | { "DACL" , NULL, "TOCLK" }, |
2308 | { "DACL" , NULL, "Beep" }, |
2309 | { "DACL" , NULL, "STL" }, |
2310 | { "DACL" , NULL, "DSP2" }, |
2311 | |
2312 | { "DACR" , NULL, "SYSCLK" }, |
2313 | { "DACR" , NULL, "TOCLK" }, |
2314 | { "DACR" , NULL, "Beep" }, |
2315 | { "DACR" , NULL, "STR" }, |
2316 | { "DACR" , NULL, "DSP2" }, |
2317 | |
2318 | { "HPMIXL" , "IN4L Switch" , "IN4L" }, |
2319 | { "HPMIXL" , "IN4R Switch" , "IN4R" }, |
2320 | { "HPMIXL" , "DACL Switch" , "DACL" }, |
2321 | { "HPMIXL" , "DACR Switch" , "DACR" }, |
2322 | { "HPMIXL" , "MIXINL Switch" , "MIXINL" }, |
2323 | { "HPMIXL" , "MIXINR Switch" , "MIXINR" }, |
2324 | |
2325 | { "HPMIXR" , "IN4L Switch" , "IN4L" }, |
2326 | { "HPMIXR" , "IN4R Switch" , "IN4R" }, |
2327 | { "HPMIXR" , "DACL Switch" , "DACL" }, |
2328 | { "HPMIXR" , "DACR Switch" , "DACR" }, |
2329 | { "HPMIXR" , "MIXINL Switch" , "MIXINL" }, |
2330 | { "HPMIXR" , "MIXINR Switch" , "MIXINR" }, |
2331 | |
2332 | { "Left Bypass" , NULL, "HPMIXL" }, |
2333 | { "Left Bypass" , NULL, "Class G" }, |
2334 | |
2335 | { "Right Bypass" , NULL, "HPMIXR" }, |
2336 | { "Right Bypass" , NULL, "Class G" }, |
2337 | |
2338 | { "HPOUTL PGA" , "Mixer" , "Left Bypass" }, |
2339 | { "HPOUTL PGA" , "DAC" , "DACL" }, |
2340 | |
2341 | { "HPOUTR PGA" , "Mixer" , "Right Bypass" }, |
2342 | { "HPOUTR PGA" , "DAC" , "DACR" }, |
2343 | |
2344 | { "HPOUT" , NULL, "HPOUTL PGA" }, |
2345 | { "HPOUT" , NULL, "HPOUTR PGA" }, |
2346 | { "HPOUT" , NULL, "Charge Pump" }, |
2347 | { "HPOUT" , NULL, "SYSCLK" }, |
2348 | { "HPOUT" , NULL, "TOCLK" }, |
2349 | |
2350 | { "HPOUTL" , NULL, "HPOUT" }, |
2351 | { "HPOUTR" , NULL, "HPOUT" }, |
2352 | |
2353 | { "HPOUTL" , NULL, "TEMP_HP" }, |
2354 | { "HPOUTR" , NULL, "TEMP_HP" }, |
2355 | }; |
2356 | |
2357 | static const struct snd_soc_dapm_route wm8962_spk_mono_intercon[] = { |
2358 | { "Speaker Mixer" , "IN4L Switch" , "IN4L" }, |
2359 | { "Speaker Mixer" , "IN4R Switch" , "IN4R" }, |
2360 | { "Speaker Mixer" , "DACL Switch" , "DACL" }, |
2361 | { "Speaker Mixer" , "DACR Switch" , "DACR" }, |
2362 | { "Speaker Mixer" , "MIXINL Switch" , "MIXINL" }, |
2363 | { "Speaker Mixer" , "MIXINR Switch" , "MIXINR" }, |
2364 | |
2365 | { "Speaker PGA" , "Mixer" , "Speaker Mixer" }, |
2366 | { "Speaker PGA" , "DAC" , "DACL" }, |
2367 | |
2368 | { "SPKOUTL Output" , NULL, "Speaker PGA" }, |
2369 | { "SPKOUTL Output" , NULL, "SYSCLK" }, |
2370 | { "SPKOUTL Output" , NULL, "TOCLK" }, |
2371 | { "SPKOUTL Output" , NULL, "TEMP_SPK" }, |
2372 | |
2373 | { "SPKOUTR Output" , NULL, "Speaker PGA" }, |
2374 | { "SPKOUTR Output" , NULL, "SYSCLK" }, |
2375 | { "SPKOUTR Output" , NULL, "TOCLK" }, |
2376 | { "SPKOUTR Output" , NULL, "TEMP_SPK" }, |
2377 | |
2378 | { "SPKOUT" , NULL, "SPKOUTL Output" }, |
2379 | { "SPKOUT" , NULL, "SPKOUTR Output" }, |
2380 | }; |
2381 | |
2382 | static const struct snd_soc_dapm_route wm8962_spk_stereo_intercon[] = { |
2383 | { "SPKOUTL Mixer" , "IN4L Switch" , "IN4L" }, |
2384 | { "SPKOUTL Mixer" , "IN4R Switch" , "IN4R" }, |
2385 | { "SPKOUTL Mixer" , "DACL Switch" , "DACL" }, |
2386 | { "SPKOUTL Mixer" , "DACR Switch" , "DACR" }, |
2387 | { "SPKOUTL Mixer" , "MIXINL Switch" , "MIXINL" }, |
2388 | { "SPKOUTL Mixer" , "MIXINR Switch" , "MIXINR" }, |
2389 | |
2390 | { "SPKOUTR Mixer" , "IN4L Switch" , "IN4L" }, |
2391 | { "SPKOUTR Mixer" , "IN4R Switch" , "IN4R" }, |
2392 | { "SPKOUTR Mixer" , "DACL Switch" , "DACL" }, |
2393 | { "SPKOUTR Mixer" , "DACR Switch" , "DACR" }, |
2394 | { "SPKOUTR Mixer" , "MIXINL Switch" , "MIXINL" }, |
2395 | { "SPKOUTR Mixer" , "MIXINR Switch" , "MIXINR" }, |
2396 | |
2397 | { "SPKOUTL PGA" , "Mixer" , "SPKOUTL Mixer" }, |
2398 | { "SPKOUTL PGA" , "DAC" , "DACL" }, |
2399 | |
2400 | { "SPKOUTR PGA" , "Mixer" , "SPKOUTR Mixer" }, |
2401 | { "SPKOUTR PGA" , "DAC" , "DACR" }, |
2402 | |
2403 | { "SPKOUTL Output" , NULL, "SPKOUTL PGA" }, |
2404 | { "SPKOUTL Output" , NULL, "SYSCLK" }, |
2405 | { "SPKOUTL Output" , NULL, "TOCLK" }, |
2406 | { "SPKOUTL Output" , NULL, "TEMP_SPK" }, |
2407 | |
2408 | { "SPKOUTR Output" , NULL, "SPKOUTR PGA" }, |
2409 | { "SPKOUTR Output" , NULL, "SYSCLK" }, |
2410 | { "SPKOUTR Output" , NULL, "TOCLK" }, |
2411 | { "SPKOUTR Output" , NULL, "TEMP_SPK" }, |
2412 | |
2413 | { "SPKOUTL" , NULL, "SPKOUTL Output" }, |
2414 | { "SPKOUTR" , NULL, "SPKOUTR Output" }, |
2415 | }; |
2416 | |
2417 | static int wm8962_add_widgets(struct snd_soc_component *component) |
2418 | { |
2419 | struct wm8962_priv *wm8962 = snd_soc_component_get_drvdata(c: component); |
2420 | struct wm8962_pdata *pdata = &wm8962->pdata; |
2421 | struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component); |
2422 | |
2423 | snd_soc_add_component_controls(component, controls: wm8962_snd_controls, |
2424 | ARRAY_SIZE(wm8962_snd_controls)); |
2425 | if (pdata->spk_mono) |
2426 | snd_soc_add_component_controls(component, controls: wm8962_spk_mono_controls, |
2427 | ARRAY_SIZE(wm8962_spk_mono_controls)); |
2428 | else |
2429 | snd_soc_add_component_controls(component, controls: wm8962_spk_stereo_controls, |
2430 | ARRAY_SIZE(wm8962_spk_stereo_controls)); |
2431 | |
2432 | |
2433 | snd_soc_dapm_new_controls(dapm, widget: wm8962_dapm_widgets, |
2434 | ARRAY_SIZE(wm8962_dapm_widgets)); |
2435 | if (pdata->spk_mono) |
2436 | snd_soc_dapm_new_controls(dapm, widget: wm8962_dapm_spk_mono_widgets, |
2437 | ARRAY_SIZE(wm8962_dapm_spk_mono_widgets)); |
2438 | else |
2439 | snd_soc_dapm_new_controls(dapm, widget: wm8962_dapm_spk_stereo_widgets, |
2440 | ARRAY_SIZE(wm8962_dapm_spk_stereo_widgets)); |
2441 | |
2442 | snd_soc_dapm_add_routes(dapm, route: wm8962_intercon, |
2443 | ARRAY_SIZE(wm8962_intercon)); |
2444 | if (pdata->spk_mono) |
2445 | snd_soc_dapm_add_routes(dapm, route: wm8962_spk_mono_intercon, |
2446 | ARRAY_SIZE(wm8962_spk_mono_intercon)); |
2447 | else |
2448 | snd_soc_dapm_add_routes(dapm, route: wm8962_spk_stereo_intercon, |
2449 | ARRAY_SIZE(wm8962_spk_stereo_intercon)); |
2450 | |
2451 | |
2452 | snd_soc_dapm_disable_pin(dapm, pin: "Beep" ); |
2453 | |
2454 | return 0; |
2455 | } |
2456 | |
2457 | /* -1 for reserved values */ |
2458 | static const int bclk_divs[] = { |
2459 | 1, -1, 2, 3, 4, -1, 6, 8, -1, 12, 16, 24, -1, 32, 32, 32 |
2460 | }; |
2461 | |
2462 | static const int sysclk_rates[] = { |
2463 | 64, 128, 192, 256, 384, 512, 768, 1024, 1408, 1536, 3072, 6144 |
2464 | }; |
2465 | |
2466 | static void wm8962_configure_bclk(struct snd_soc_component *component) |
2467 | { |
2468 | struct wm8962_priv *wm8962 = snd_soc_component_get_drvdata(c: component); |
2469 | int best, min_diff, diff; |
2470 | int dspclk, i; |
2471 | int clocking2 = 0; |
2472 | int clocking4 = 0; |
2473 | int aif2 = 0; |
2474 | |
2475 | if (!wm8962->sysclk_rate) { |
2476 | dev_dbg(component->dev, "No SYSCLK configured\n" ); |
2477 | return; |
2478 | } |
2479 | |
2480 | if (!wm8962->bclk || !wm8962->lrclk) { |
2481 | dev_dbg(component->dev, "No audio clocks configured\n" ); |
2482 | return; |
2483 | } |
2484 | |
2485 | for (i = 0; i < ARRAY_SIZE(sysclk_rates); i++) { |
2486 | if (sysclk_rates[i] == wm8962->sysclk_rate / wm8962->lrclk) { |
2487 | clocking4 |= i << WM8962_SYSCLK_RATE_SHIFT; |
2488 | break; |
2489 | } |
2490 | } |
2491 | |
2492 | if (i == ARRAY_SIZE(sysclk_rates)) { |
2493 | dev_err(component->dev, "Unsupported sysclk ratio %d\n" , |
2494 | wm8962->sysclk_rate / wm8962->lrclk); |
2495 | return; |
2496 | } |
2497 | |
2498 | dev_dbg(component->dev, "Selected sysclk ratio %d\n" , sysclk_rates[i]); |
2499 | |
2500 | snd_soc_component_update_bits(component, WM8962_CLOCKING_4, |
2501 | WM8962_SYSCLK_RATE_MASK, val: clocking4); |
2502 | |
2503 | /* DSPCLK_DIV can be only generated correctly after enabling SYSCLK. |
2504 | * So we here provisionally enable it and then disable it afterward |
2505 | * if current bias_level hasn't reached SND_SOC_BIAS_ON. |
2506 | */ |
2507 | if (snd_soc_component_get_bias_level(component) != SND_SOC_BIAS_ON) |
2508 | snd_soc_component_update_bits(component, WM8962_CLOCKING2, |
2509 | WM8962_SYSCLK_ENA_MASK, WM8962_SYSCLK_ENA); |
2510 | |
2511 | /* DSPCLK_DIV field in WM8962_CLOCKING1 register is used to generate |
2512 | * correct frequency of LRCLK and BCLK. Sometimes the read-only value |
2513 | * can't be updated timely after enabling SYSCLK. This results in wrong |
2514 | * calculation values. Delay is introduced here to wait for newest |
2515 | * value from register. The time of the delay should be at least |
2516 | * 500~1000us according to test. |
2517 | */ |
2518 | usleep_range(min: 500, max: 1000); |
2519 | dspclk = snd_soc_component_read(component, WM8962_CLOCKING1); |
2520 | |
2521 | if (snd_soc_component_get_bias_level(component) != SND_SOC_BIAS_ON) |
2522 | snd_soc_component_update_bits(component, WM8962_CLOCKING2, |
2523 | WM8962_SYSCLK_ENA_MASK, val: 0); |
2524 | |
2525 | if (dspclk < 0) { |
2526 | dev_err(component->dev, "Failed to read DSPCLK: %d\n" , dspclk); |
2527 | return; |
2528 | } |
2529 | |
2530 | dspclk = (dspclk & WM8962_DSPCLK_DIV_MASK) >> WM8962_DSPCLK_DIV_SHIFT; |
2531 | switch (dspclk) { |
2532 | case 0: |
2533 | dspclk = wm8962->sysclk_rate; |
2534 | break; |
2535 | case 1: |
2536 | dspclk = wm8962->sysclk_rate / 2; |
2537 | break; |
2538 | case 2: |
2539 | dspclk = wm8962->sysclk_rate / 4; |
2540 | break; |
2541 | default: |
2542 | dev_warn(component->dev, "Unknown DSPCLK divisor read back\n" ); |
2543 | dspclk = wm8962->sysclk_rate; |
2544 | } |
2545 | |
2546 | dev_dbg(component->dev, "DSPCLK is %dHz, BCLK %d\n" , dspclk, wm8962->bclk); |
2547 | |
2548 | /* Search a proper bclk, not exact match. */ |
2549 | best = 0; |
2550 | min_diff = INT_MAX; |
2551 | for (i = 0; i < ARRAY_SIZE(bclk_divs); i++) { |
2552 | if (bclk_divs[i] < 0) |
2553 | continue; |
2554 | |
2555 | diff = (dspclk / bclk_divs[i]) - wm8962->bclk; |
2556 | if (diff < 0) /* Table is sorted */ |
2557 | break; |
2558 | if (diff < min_diff) { |
2559 | best = i; |
2560 | min_diff = diff; |
2561 | } |
2562 | } |
2563 | wm8962->bclk = dspclk / bclk_divs[best]; |
2564 | clocking2 |= best; |
2565 | dev_dbg(component->dev, "Selected BCLK_DIV %d for %dHz\n" , |
2566 | bclk_divs[best], wm8962->bclk); |
2567 | |
2568 | aif2 |= wm8962->bclk / wm8962->lrclk; |
2569 | dev_dbg(component->dev, "Selected LRCLK divisor %d for %dHz\n" , |
2570 | wm8962->bclk / wm8962->lrclk, wm8962->lrclk); |
2571 | |
2572 | snd_soc_component_update_bits(component, WM8962_CLOCKING2, |
2573 | WM8962_BCLK_DIV_MASK, val: clocking2); |
2574 | snd_soc_component_update_bits(component, WM8962_AUDIO_INTERFACE_2, |
2575 | WM8962_AIF_RATE_MASK, val: aif2); |
2576 | } |
2577 | |
2578 | static int wm8962_set_bias_level(struct snd_soc_component *component, |
2579 | enum snd_soc_bias_level level) |
2580 | { |
2581 | switch (level) { |
2582 | case SND_SOC_BIAS_ON: |
2583 | break; |
2584 | |
2585 | case SND_SOC_BIAS_PREPARE: |
2586 | /* VMID 2*50k */ |
2587 | snd_soc_component_update_bits(component, WM8962_PWR_MGMT_1, |
2588 | WM8962_VMID_SEL_MASK, val: 0x80); |
2589 | |
2590 | wm8962_configure_bclk(component); |
2591 | break; |
2592 | |
2593 | case SND_SOC_BIAS_STANDBY: |
2594 | /* VMID 2*250k */ |
2595 | snd_soc_component_update_bits(component, WM8962_PWR_MGMT_1, |
2596 | WM8962_VMID_SEL_MASK, val: 0x100); |
2597 | |
2598 | if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF) |
2599 | msleep(msecs: 100); |
2600 | break; |
2601 | |
2602 | case SND_SOC_BIAS_OFF: |
2603 | break; |
2604 | } |
2605 | |
2606 | return 0; |
2607 | } |
2608 | |
2609 | static const struct { |
2610 | int rate; |
2611 | int reg; |
2612 | } sr_vals[] = { |
2613 | { 48000, 0 }, |
2614 | { 44100, 0 }, |
2615 | { 32000, 1 }, |
2616 | { 22050, 2 }, |
2617 | { 24000, 2 }, |
2618 | { 16000, 3 }, |
2619 | { 11025, 4 }, |
2620 | { 12000, 4 }, |
2621 | { 8000, 5 }, |
2622 | { 88200, 6 }, |
2623 | { 96000, 6 }, |
2624 | }; |
2625 | |
2626 | static int wm8962_hw_params(struct snd_pcm_substream *substream, |
2627 | struct snd_pcm_hw_params *params, |
2628 | struct snd_soc_dai *dai) |
2629 | { |
2630 | struct snd_soc_component *component = dai->component; |
2631 | struct wm8962_priv *wm8962 = snd_soc_component_get_drvdata(c: component); |
2632 | int i; |
2633 | int aif0 = 0; |
2634 | int adctl3 = 0; |
2635 | |
2636 | wm8962->bclk = snd_soc_params_to_bclk(parms: params); |
2637 | if (params_channels(p: params) == 1) |
2638 | wm8962->bclk *= 2; |
2639 | |
2640 | wm8962->lrclk = params_rate(p: params); |
2641 | |
2642 | for (i = 0; i < ARRAY_SIZE(sr_vals); i++) { |
2643 | if (sr_vals[i].rate == wm8962->lrclk) { |
2644 | adctl3 |= sr_vals[i].reg; |
2645 | break; |
2646 | } |
2647 | } |
2648 | if (i == ARRAY_SIZE(sr_vals)) { |
2649 | dev_err(component->dev, "Unsupported rate %dHz\n" , wm8962->lrclk); |
2650 | return -EINVAL; |
2651 | } |
2652 | |
2653 | if (wm8962->lrclk % 8000 == 0) |
2654 | adctl3 |= WM8962_SAMPLE_RATE_INT_MODE; |
2655 | |
2656 | switch (params_width(p: params)) { |
2657 | case 16: |
2658 | break; |
2659 | case 20: |
2660 | aif0 |= 0x4; |
2661 | break; |
2662 | case 24: |
2663 | aif0 |= 0x8; |
2664 | break; |
2665 | case 32: |
2666 | aif0 |= 0xc; |
2667 | break; |
2668 | default: |
2669 | return -EINVAL; |
2670 | } |
2671 | |
2672 | snd_soc_component_update_bits(component, WM8962_AUDIO_INTERFACE_0, |
2673 | WM8962_WL_MASK, val: aif0); |
2674 | snd_soc_component_update_bits(component, WM8962_ADDITIONAL_CONTROL_3, |
2675 | WM8962_SAMPLE_RATE_INT_MODE | |
2676 | WM8962_SAMPLE_RATE_MASK, val: adctl3); |
2677 | |
2678 | dev_dbg(component->dev, "hw_params set BCLK %dHz LRCLK %dHz\n" , |
2679 | wm8962->bclk, wm8962->lrclk); |
2680 | |
2681 | if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_ON) |
2682 | wm8962_configure_bclk(component); |
2683 | |
2684 | return 0; |
2685 | } |
2686 | |
2687 | static int wm8962_set_dai_sysclk(struct snd_soc_dai *dai, int clk_id, |
2688 | unsigned int freq, int dir) |
2689 | { |
2690 | struct snd_soc_component *component = dai->component; |
2691 | struct wm8962_priv *wm8962 = snd_soc_component_get_drvdata(c: component); |
2692 | int src; |
2693 | |
2694 | switch (clk_id) { |
2695 | case WM8962_SYSCLK_MCLK: |
2696 | wm8962->sysclk = WM8962_SYSCLK_MCLK; |
2697 | src = 0; |
2698 | break; |
2699 | case WM8962_SYSCLK_FLL: |
2700 | wm8962->sysclk = WM8962_SYSCLK_FLL; |
2701 | src = 1 << WM8962_SYSCLK_SRC_SHIFT; |
2702 | break; |
2703 | default: |
2704 | return -EINVAL; |
2705 | } |
2706 | |
2707 | snd_soc_component_update_bits(component, WM8962_CLOCKING2, WM8962_SYSCLK_SRC_MASK, |
2708 | val: src); |
2709 | |
2710 | wm8962->sysclk_rate = freq; |
2711 | |
2712 | return 0; |
2713 | } |
2714 | |
2715 | static int wm8962_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt) |
2716 | { |
2717 | struct snd_soc_component *component = dai->component; |
2718 | int aif0 = 0; |
2719 | |
2720 | switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { |
2721 | case SND_SOC_DAIFMT_DSP_B: |
2722 | aif0 |= WM8962_LRCLK_INV | 3; |
2723 | fallthrough; |
2724 | case SND_SOC_DAIFMT_DSP_A: |
2725 | aif0 |= 3; |
2726 | |
2727 | switch (fmt & SND_SOC_DAIFMT_INV_MASK) { |
2728 | case SND_SOC_DAIFMT_NB_NF: |
2729 | case SND_SOC_DAIFMT_IB_NF: |
2730 | break; |
2731 | default: |
2732 | return -EINVAL; |
2733 | } |
2734 | break; |
2735 | |
2736 | case SND_SOC_DAIFMT_RIGHT_J: |
2737 | break; |
2738 | case SND_SOC_DAIFMT_LEFT_J: |
2739 | aif0 |= 1; |
2740 | break; |
2741 | case SND_SOC_DAIFMT_I2S: |
2742 | aif0 |= 2; |
2743 | break; |
2744 | default: |
2745 | return -EINVAL; |
2746 | } |
2747 | |
2748 | switch (fmt & SND_SOC_DAIFMT_INV_MASK) { |
2749 | case SND_SOC_DAIFMT_NB_NF: |
2750 | break; |
2751 | case SND_SOC_DAIFMT_IB_NF: |
2752 | aif0 |= WM8962_BCLK_INV; |
2753 | break; |
2754 | case SND_SOC_DAIFMT_NB_IF: |
2755 | aif0 |= WM8962_LRCLK_INV; |
2756 | break; |
2757 | case SND_SOC_DAIFMT_IB_IF: |
2758 | aif0 |= WM8962_BCLK_INV | WM8962_LRCLK_INV; |
2759 | break; |
2760 | default: |
2761 | return -EINVAL; |
2762 | } |
2763 | |
2764 | switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { |
2765 | case SND_SOC_DAIFMT_CBM_CFM: |
2766 | aif0 |= WM8962_MSTR; |
2767 | break; |
2768 | case SND_SOC_DAIFMT_CBS_CFS: |
2769 | break; |
2770 | default: |
2771 | return -EINVAL; |
2772 | } |
2773 | |
2774 | snd_soc_component_update_bits(component, WM8962_AUDIO_INTERFACE_0, |
2775 | WM8962_FMT_MASK | WM8962_BCLK_INV | WM8962_MSTR | |
2776 | WM8962_LRCLK_INV, val: aif0); |
2777 | |
2778 | return 0; |
2779 | } |
2780 | |
2781 | struct _fll_div { |
2782 | u16 fll_fratio; |
2783 | u16 fll_outdiv; |
2784 | u16 fll_refclk_div; |
2785 | u16 n; |
2786 | u16 theta; |
2787 | u16 lambda; |
2788 | }; |
2789 | |
2790 | /* The size in bits of the FLL divide multiplied by 10 |
2791 | * to allow rounding later */ |
2792 | #define FIXED_FLL_SIZE ((1 << 16) * 10) |
2793 | |
2794 | static struct { |
2795 | unsigned int min; |
2796 | unsigned int max; |
2797 | u16 fll_fratio; |
2798 | int ratio; |
2799 | } fll_fratios[] = { |
2800 | { 0, 64000, 4, 16 }, |
2801 | { 64000, 128000, 3, 8 }, |
2802 | { 128000, 256000, 2, 4 }, |
2803 | { 256000, 1000000, 1, 2 }, |
2804 | { 1000000, 13500000, 0, 1 }, |
2805 | }; |
2806 | |
2807 | static int fll_factors(struct _fll_div *fll_div, unsigned int Fref, |
2808 | unsigned int Fout) |
2809 | { |
2810 | unsigned int target; |
2811 | unsigned int div; |
2812 | unsigned int fratio, gcd_fll; |
2813 | int i; |
2814 | |
2815 | /* Fref must be <=13.5MHz */ |
2816 | div = 1; |
2817 | fll_div->fll_refclk_div = 0; |
2818 | while ((Fref / div) > 13500000) { |
2819 | div *= 2; |
2820 | fll_div->fll_refclk_div++; |
2821 | |
2822 | if (div > 4) { |
2823 | pr_err("Can't scale %dMHz input down to <=13.5MHz\n" , |
2824 | Fref); |
2825 | return -EINVAL; |
2826 | } |
2827 | } |
2828 | |
2829 | pr_debug("FLL Fref=%u Fout=%u\n" , Fref, Fout); |
2830 | |
2831 | /* Apply the division for our remaining calculations */ |
2832 | Fref /= div; |
2833 | |
2834 | /* Fvco should be 90-100MHz; don't check the upper bound */ |
2835 | div = 2; |
2836 | while (Fout * div < 90000000) { |
2837 | div++; |
2838 | if (div > 64) { |
2839 | pr_err("Unable to find FLL_OUTDIV for Fout=%uHz\n" , |
2840 | Fout); |
2841 | return -EINVAL; |
2842 | } |
2843 | } |
2844 | target = Fout * div; |
2845 | fll_div->fll_outdiv = div - 1; |
2846 | |
2847 | pr_debug("FLL Fvco=%dHz\n" , target); |
2848 | |
2849 | /* Find an appropriate FLL_FRATIO and factor it out of the target */ |
2850 | for (i = 0; i < ARRAY_SIZE(fll_fratios); i++) { |
2851 | if (fll_fratios[i].min <= Fref && Fref <= fll_fratios[i].max) { |
2852 | fll_div->fll_fratio = fll_fratios[i].fll_fratio; |
2853 | fratio = fll_fratios[i].ratio; |
2854 | break; |
2855 | } |
2856 | } |
2857 | if (i == ARRAY_SIZE(fll_fratios)) { |
2858 | pr_err("Unable to find FLL_FRATIO for Fref=%uHz\n" , Fref); |
2859 | return -EINVAL; |
2860 | } |
2861 | |
2862 | fll_div->n = target / (fratio * Fref); |
2863 | |
2864 | if (target % Fref == 0) { |
2865 | fll_div->theta = 0; |
2866 | fll_div->lambda = 1; |
2867 | } else { |
2868 | gcd_fll = gcd(a: target, b: fratio * Fref); |
2869 | |
2870 | fll_div->theta = (target - (fll_div->n * fratio * Fref)) |
2871 | / gcd_fll; |
2872 | fll_div->lambda = (fratio * Fref) / gcd_fll; |
2873 | } |
2874 | |
2875 | pr_debug("FLL N=%x THETA=%x LAMBDA=%x\n" , |
2876 | fll_div->n, fll_div->theta, fll_div->lambda); |
2877 | pr_debug("FLL_FRATIO=%x FLL_OUTDIV=%x FLL_REFCLK_DIV=%x\n" , |
2878 | fll_div->fll_fratio, fll_div->fll_outdiv, |
2879 | fll_div->fll_refclk_div); |
2880 | |
2881 | return 0; |
2882 | } |
2883 | |
2884 | static int wm8962_set_fll(struct snd_soc_component *component, int fll_id, int source, |
2885 | unsigned int Fref, unsigned int Fout) |
2886 | { |
2887 | struct wm8962_priv *wm8962 = snd_soc_component_get_drvdata(c: component); |
2888 | struct _fll_div fll_div; |
2889 | unsigned long timeout; |
2890 | int ret; |
2891 | int fll1 = 0; |
2892 | |
2893 | /* Any change? */ |
2894 | if (source == wm8962->fll_src && Fref == wm8962->fll_fref && |
2895 | Fout == wm8962->fll_fout) |
2896 | return 0; |
2897 | |
2898 | if (Fout == 0) { |
2899 | dev_dbg(component->dev, "FLL disabled\n" ); |
2900 | |
2901 | wm8962->fll_fref = 0; |
2902 | wm8962->fll_fout = 0; |
2903 | |
2904 | snd_soc_component_update_bits(component, WM8962_FLL_CONTROL_1, |
2905 | WM8962_FLL_ENA, val: 0); |
2906 | |
2907 | pm_runtime_put(dev: component->dev); |
2908 | |
2909 | return 0; |
2910 | } |
2911 | |
2912 | ret = fll_factors(fll_div: &fll_div, Fref, Fout); |
2913 | if (ret != 0) |
2914 | return ret; |
2915 | |
2916 | /* Parameters good, disable so we can reprogram */ |
2917 | snd_soc_component_update_bits(component, WM8962_FLL_CONTROL_1, WM8962_FLL_ENA, val: 0); |
2918 | |
2919 | switch (fll_id) { |
2920 | case WM8962_FLL_MCLK: |
2921 | case WM8962_FLL_BCLK: |
2922 | fll1 |= (fll_id - 1) << WM8962_FLL_REFCLK_SRC_SHIFT; |
2923 | break; |
2924 | case WM8962_FLL_OSC: |
2925 | fll1 |= (fll_id - 1) << WM8962_FLL_REFCLK_SRC_SHIFT; |
2926 | snd_soc_component_update_bits(component, WM8962_PLL2, |
2927 | WM8962_OSC_ENA, WM8962_OSC_ENA); |
2928 | break; |
2929 | case WM8962_FLL_INT: |
2930 | snd_soc_component_update_bits(component, WM8962_FLL_CONTROL_1, |
2931 | WM8962_FLL_OSC_ENA, WM8962_FLL_OSC_ENA); |
2932 | snd_soc_component_update_bits(component, WM8962_FLL_CONTROL_5, |
2933 | WM8962_FLL_FRC_NCO, WM8962_FLL_FRC_NCO); |
2934 | break; |
2935 | default: |
2936 | dev_err(component->dev, "Unknown FLL source %d\n" , source); |
2937 | return -EINVAL; |
2938 | } |
2939 | |
2940 | if (fll_div.theta) |
2941 | fll1 |= WM8962_FLL_FRAC; |
2942 | |
2943 | /* Stop the FLL while we reconfigure */ |
2944 | snd_soc_component_update_bits(component, WM8962_FLL_CONTROL_1, WM8962_FLL_ENA, val: 0); |
2945 | |
2946 | snd_soc_component_update_bits(component, WM8962_FLL_CONTROL_2, |
2947 | WM8962_FLL_OUTDIV_MASK | |
2948 | WM8962_FLL_REFCLK_DIV_MASK, |
2949 | val: (fll_div.fll_outdiv << WM8962_FLL_OUTDIV_SHIFT) | |
2950 | (fll_div.fll_refclk_div)); |
2951 | |
2952 | snd_soc_component_update_bits(component, WM8962_FLL_CONTROL_3, |
2953 | WM8962_FLL_FRATIO_MASK, val: fll_div.fll_fratio); |
2954 | |
2955 | snd_soc_component_write(component, WM8962_FLL_CONTROL_6, val: fll_div.theta); |
2956 | snd_soc_component_write(component, WM8962_FLL_CONTROL_7, val: fll_div.lambda); |
2957 | snd_soc_component_write(component, WM8962_FLL_CONTROL_8, val: fll_div.n); |
2958 | |
2959 | reinit_completion(x: &wm8962->fll_lock); |
2960 | |
2961 | ret = pm_runtime_resume_and_get(dev: component->dev); |
2962 | if (ret < 0) { |
2963 | dev_err(component->dev, "Failed to resume device: %d\n" , ret); |
2964 | return ret; |
2965 | } |
2966 | |
2967 | snd_soc_component_update_bits(component, WM8962_FLL_CONTROL_1, |
2968 | WM8962_FLL_FRAC | WM8962_FLL_REFCLK_SRC_MASK | |
2969 | WM8962_FLL_ENA, val: fll1 | WM8962_FLL_ENA); |
2970 | |
2971 | dev_dbg(component->dev, "FLL configured for %dHz->%dHz\n" , Fref, Fout); |
2972 | |
2973 | /* This should be a massive overestimate but go even |
2974 | * higher if we'll error out |
2975 | */ |
2976 | if (wm8962->irq) |
2977 | timeout = msecs_to_jiffies(m: 5); |
2978 | else |
2979 | timeout = msecs_to_jiffies(m: 1); |
2980 | |
2981 | timeout = wait_for_completion_timeout(x: &wm8962->fll_lock, |
2982 | timeout); |
2983 | |
2984 | if (timeout == 0 && wm8962->irq) { |
2985 | dev_err(component->dev, "FLL lock timed out" ); |
2986 | snd_soc_component_update_bits(component, WM8962_FLL_CONTROL_1, |
2987 | WM8962_FLL_ENA, val: 0); |
2988 | pm_runtime_put(dev: component->dev); |
2989 | return -ETIMEDOUT; |
2990 | } |
2991 | |
2992 | wm8962->fll_fref = Fref; |
2993 | wm8962->fll_fout = Fout; |
2994 | wm8962->fll_src = source; |
2995 | |
2996 | return 0; |
2997 | } |
2998 | |
2999 | static int wm8962_mute(struct snd_soc_dai *dai, int mute, int direction) |
3000 | { |
3001 | struct snd_soc_component *component = dai->component; |
3002 | int val, ret; |
3003 | |
3004 | if (mute) |
3005 | val = WM8962_DAC_MUTE | WM8962_DAC_MUTE_ALT; |
3006 | else |
3007 | val = 0; |
3008 | |
3009 | /** |
3010 | * The DAC mute bit is mirrored in two registers, update both to keep |
3011 | * the register cache consistent. |
3012 | */ |
3013 | ret = snd_soc_component_update_bits(component, WM8962_CLASS_D_CONTROL_1, |
3014 | WM8962_DAC_MUTE_ALT, val); |
3015 | if (ret < 0) |
3016 | return ret; |
3017 | |
3018 | return snd_soc_component_update_bits(component, WM8962_ADC_DAC_CONTROL_1, |
3019 | WM8962_DAC_MUTE, val); |
3020 | } |
3021 | |
3022 | #define WM8962_RATES (SNDRV_PCM_RATE_8000_48000 |\ |
3023 | SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000) |
3024 | |
3025 | #define WM8962_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\ |
3026 | SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE) |
3027 | |
3028 | static const struct snd_soc_dai_ops wm8962_dai_ops = { |
3029 | .hw_params = wm8962_hw_params, |
3030 | .set_sysclk = wm8962_set_dai_sysclk, |
3031 | .set_fmt = wm8962_set_dai_fmt, |
3032 | .mute_stream = wm8962_mute, |
3033 | .no_capture_mute = 1, |
3034 | }; |
3035 | |
3036 | static struct snd_soc_dai_driver wm8962_dai = { |
3037 | .name = "wm8962" , |
3038 | .playback = { |
3039 | .stream_name = "Playback" , |
3040 | .channels_min = 1, |
3041 | .channels_max = 2, |
3042 | .rates = WM8962_RATES, |
3043 | .formats = WM8962_FORMATS, |
3044 | }, |
3045 | .capture = { |
3046 | .stream_name = "Capture" , |
3047 | .channels_min = 1, |
3048 | .channels_max = 2, |
3049 | .rates = WM8962_RATES, |
3050 | .formats = WM8962_FORMATS, |
3051 | }, |
3052 | .ops = &wm8962_dai_ops, |
3053 | .symmetric_rate = 1, |
3054 | }; |
3055 | |
3056 | static void wm8962_mic_work(struct work_struct *work) |
3057 | { |
3058 | struct wm8962_priv *wm8962 = container_of(work, |
3059 | struct wm8962_priv, |
3060 | mic_work.work); |
3061 | struct snd_soc_component *component = wm8962->component; |
3062 | int status = 0; |
3063 | int irq_pol = 0; |
3064 | int reg; |
3065 | |
3066 | reg = snd_soc_component_read(component, WM8962_ADDITIONAL_CONTROL_4); |
3067 | |
3068 | if (reg & WM8962_MICDET_STS) { |
3069 | status |= SND_JACK_MICROPHONE; |
3070 | irq_pol |= WM8962_MICD_IRQ_POL; |
3071 | } |
3072 | |
3073 | if (reg & WM8962_MICSHORT_STS) { |
3074 | status |= SND_JACK_BTN_0; |
3075 | irq_pol |= WM8962_MICSCD_IRQ_POL; |
3076 | } |
3077 | |
3078 | snd_soc_jack_report(jack: wm8962->jack, status, |
3079 | mask: SND_JACK_MICROPHONE | SND_JACK_BTN_0); |
3080 | |
3081 | snd_soc_component_update_bits(component, WM8962_MICINT_SOURCE_POL, |
3082 | WM8962_MICSCD_IRQ_POL | |
3083 | WM8962_MICD_IRQ_POL, val: irq_pol); |
3084 | } |
3085 | |
3086 | static irqreturn_t wm8962_irq(int irq, void *data) |
3087 | { |
3088 | struct device *dev = data; |
3089 | struct wm8962_priv *wm8962 = dev_get_drvdata(dev); |
3090 | unsigned int mask; |
3091 | unsigned int active; |
3092 | int reg, ret; |
3093 | |
3094 | ret = pm_runtime_resume_and_get(dev); |
3095 | if (ret < 0) { |
3096 | dev_err(dev, "Failed to resume: %d\n" , ret); |
3097 | return IRQ_NONE; |
3098 | } |
3099 | |
3100 | ret = regmap_read(map: wm8962->regmap, WM8962_INTERRUPT_STATUS_2_MASK, |
3101 | val: &mask); |
3102 | if (ret != 0) { |
3103 | pm_runtime_put(dev); |
3104 | dev_err(dev, "Failed to read interrupt mask: %d\n" , |
3105 | ret); |
3106 | return IRQ_NONE; |
3107 | } |
3108 | |
3109 | ret = regmap_read(map: wm8962->regmap, WM8962_INTERRUPT_STATUS_2, val: &active); |
3110 | if (ret != 0) { |
3111 | pm_runtime_put(dev); |
3112 | dev_err(dev, "Failed to read interrupt: %d\n" , ret); |
3113 | return IRQ_NONE; |
3114 | } |
3115 | |
3116 | active &= ~mask; |
3117 | |
3118 | if (!active) { |
3119 | pm_runtime_put(dev); |
3120 | return IRQ_NONE; |
3121 | } |
3122 | |
3123 | /* Acknowledge the interrupts */ |
3124 | ret = regmap_write(map: wm8962->regmap, WM8962_INTERRUPT_STATUS_2, val: active); |
3125 | if (ret != 0) |
3126 | dev_warn(dev, "Failed to ack interrupt: %d\n" , ret); |
3127 | |
3128 | if (active & WM8962_FLL_LOCK_EINT) { |
3129 | dev_dbg(dev, "FLL locked\n" ); |
3130 | complete(&wm8962->fll_lock); |
3131 | } |
3132 | |
3133 | if (active & WM8962_FIFOS_ERR_EINT) |
3134 | dev_err(dev, "FIFO error\n" ); |
3135 | |
3136 | if (active & WM8962_TEMP_SHUT_EINT) { |
3137 | dev_crit(dev, "Thermal shutdown\n" ); |
3138 | |
3139 | ret = regmap_read(map: wm8962->regmap, |
3140 | WM8962_THERMAL_SHUTDOWN_STATUS, val: ®); |
3141 | if (ret != 0) { |
3142 | dev_warn(dev, "Failed to read thermal status: %d\n" , |
3143 | ret); |
3144 | reg = 0; |
3145 | } |
3146 | |
3147 | if (reg & WM8962_TEMP_ERR_HP) |
3148 | dev_crit(dev, "Headphone thermal error\n" ); |
3149 | if (reg & WM8962_TEMP_WARN_HP) |
3150 | dev_crit(dev, "Headphone thermal warning\n" ); |
3151 | if (reg & WM8962_TEMP_ERR_SPK) |
3152 | dev_crit(dev, "Speaker thermal error\n" ); |
3153 | if (reg & WM8962_TEMP_WARN_SPK) |
3154 | dev_crit(dev, "Speaker thermal warning\n" ); |
3155 | } |
3156 | |
3157 | if (active & (WM8962_MICSCD_EINT | WM8962_MICD_EINT)) { |
3158 | dev_dbg(dev, "Microphone event detected\n" ); |
3159 | |
3160 | #ifndef CONFIG_SND_SOC_WM8962_MODULE |
3161 | trace_snd_soc_jack_irq(name: dev_name(dev)); |
3162 | #endif |
3163 | |
3164 | pm_wakeup_event(dev, msec: 300); |
3165 | |
3166 | queue_delayed_work(wq: system_power_efficient_wq, |
3167 | dwork: &wm8962->mic_work, |
3168 | delay: msecs_to_jiffies(m: 250)); |
3169 | } |
3170 | |
3171 | pm_runtime_put(dev); |
3172 | |
3173 | return IRQ_HANDLED; |
3174 | } |
3175 | |
3176 | /** |
3177 | * wm8962_mic_detect - Enable microphone detection via the WM8962 IRQ |
3178 | * |
3179 | * @component: WM8962 component |
3180 | * @jack: jack to report detection events on |
3181 | * |
3182 | * Enable microphone detection via IRQ on the WM8962. If GPIOs are |
3183 | * being used to bring out signals to the processor then only platform |
3184 | * data configuration is needed for WM8962 and processor GPIOs should |
3185 | * be configured using snd_soc_jack_add_gpios() instead. |
3186 | * |
3187 | * If no jack is supplied detection will be disabled. |
3188 | */ |
3189 | int wm8962_mic_detect(struct snd_soc_component *component, struct snd_soc_jack *jack) |
3190 | { |
3191 | struct wm8962_priv *wm8962 = snd_soc_component_get_drvdata(c: component); |
3192 | struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component); |
3193 | int irq_mask, enable; |
3194 | |
3195 | wm8962->jack = jack; |
3196 | if (jack) { |
3197 | irq_mask = 0; |
3198 | enable = WM8962_MICDET_ENA; |
3199 | } else { |
3200 | irq_mask = WM8962_MICD_EINT | WM8962_MICSCD_EINT; |
3201 | enable = 0; |
3202 | } |
3203 | |
3204 | snd_soc_component_update_bits(component, WM8962_INTERRUPT_STATUS_2_MASK, |
3205 | WM8962_MICD_EINT | WM8962_MICSCD_EINT, val: irq_mask); |
3206 | snd_soc_component_update_bits(component, WM8962_ADDITIONAL_CONTROL_4, |
3207 | WM8962_MICDET_ENA, val: enable); |
3208 | |
3209 | /* Send an initial empty report */ |
3210 | snd_soc_jack_report(jack: wm8962->jack, status: 0, |
3211 | mask: SND_JACK_MICROPHONE | SND_JACK_BTN_0); |
3212 | |
3213 | snd_soc_dapm_mutex_lock(dapm); |
3214 | |
3215 | if (jack) { |
3216 | snd_soc_dapm_force_enable_pin_unlocked(dapm, pin: "SYSCLK" ); |
3217 | snd_soc_dapm_force_enable_pin_unlocked(dapm, pin: "MICBIAS" ); |
3218 | } else { |
3219 | snd_soc_dapm_disable_pin_unlocked(dapm, pin: "SYSCLK" ); |
3220 | snd_soc_dapm_disable_pin_unlocked(dapm, pin: "MICBIAS" ); |
3221 | } |
3222 | |
3223 | snd_soc_dapm_mutex_unlock(dapm); |
3224 | |
3225 | return 0; |
3226 | } |
3227 | EXPORT_SYMBOL_GPL(wm8962_mic_detect); |
3228 | |
3229 | static int beep_rates[] = { |
3230 | 500, 1000, 2000, 4000, |
3231 | }; |
3232 | |
3233 | static void wm8962_beep_work(struct work_struct *work) |
3234 | { |
3235 | struct wm8962_priv *wm8962 = |
3236 | container_of(work, struct wm8962_priv, beep_work); |
3237 | struct snd_soc_component *component = wm8962->component; |
3238 | struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component); |
3239 | int i; |
3240 | int reg = 0; |
3241 | int best = 0; |
3242 | |
3243 | if (wm8962->beep_rate) { |
3244 | for (i = 0; i < ARRAY_SIZE(beep_rates); i++) { |
3245 | if (abs(wm8962->beep_rate - beep_rates[i]) < |
3246 | abs(wm8962->beep_rate - beep_rates[best])) |
3247 | best = i; |
3248 | } |
3249 | |
3250 | dev_dbg(component->dev, "Set beep rate %dHz for requested %dHz\n" , |
3251 | beep_rates[best], wm8962->beep_rate); |
3252 | |
3253 | reg = WM8962_BEEP_ENA | (best << WM8962_BEEP_RATE_SHIFT); |
3254 | |
3255 | snd_soc_dapm_enable_pin(dapm, pin: "Beep" ); |
3256 | } else { |
3257 | dev_dbg(component->dev, "Disabling beep\n" ); |
3258 | snd_soc_dapm_disable_pin(dapm, pin: "Beep" ); |
3259 | } |
3260 | |
3261 | snd_soc_component_update_bits(component, WM8962_BEEP_GENERATOR_1, |
3262 | WM8962_BEEP_ENA | WM8962_BEEP_RATE_MASK, val: reg); |
3263 | |
3264 | snd_soc_dapm_sync(dapm); |
3265 | } |
3266 | |
3267 | /* For usability define a way of injecting beep events for the device - |
3268 | * many systems will not have a keyboard. |
3269 | */ |
3270 | static int wm8962_beep_event(struct input_dev *dev, unsigned int type, |
3271 | unsigned int code, int hz) |
3272 | { |
3273 | struct snd_soc_component *component = input_get_drvdata(dev); |
3274 | struct wm8962_priv *wm8962 = snd_soc_component_get_drvdata(c: component); |
3275 | |
3276 | dev_dbg(component->dev, "Beep event %x %x\n" , code, hz); |
3277 | |
3278 | switch (code) { |
3279 | case SND_BELL: |
3280 | if (hz) |
3281 | hz = 1000; |
3282 | fallthrough; |
3283 | case SND_TONE: |
3284 | break; |
3285 | default: |
3286 | return -1; |
3287 | } |
3288 | |
3289 | /* Kick the beep from a workqueue */ |
3290 | wm8962->beep_rate = hz; |
3291 | schedule_work(work: &wm8962->beep_work); |
3292 | return 0; |
3293 | } |
3294 | |
3295 | static ssize_t beep_store(struct device *dev, struct device_attribute *attr, |
3296 | const char *buf, size_t count) |
3297 | { |
3298 | struct wm8962_priv *wm8962 = dev_get_drvdata(dev); |
3299 | long int time; |
3300 | int ret; |
3301 | |
3302 | ret = kstrtol(s: buf, base: 10, res: &time); |
3303 | if (ret != 0) |
3304 | return ret; |
3305 | |
3306 | input_event(dev: wm8962->beep, EV_SND, SND_TONE, value: time); |
3307 | |
3308 | return count; |
3309 | } |
3310 | |
3311 | static DEVICE_ATTR_WO(beep); |
3312 | |
3313 | static void wm8962_init_beep(struct snd_soc_component *component) |
3314 | { |
3315 | struct wm8962_priv *wm8962 = snd_soc_component_get_drvdata(c: component); |
3316 | int ret; |
3317 | |
3318 | wm8962->beep = devm_input_allocate_device(component->dev); |
3319 | if (!wm8962->beep) { |
3320 | dev_err(component->dev, "Failed to allocate beep device\n" ); |
3321 | return; |
3322 | } |
3323 | |
3324 | INIT_WORK(&wm8962->beep_work, wm8962_beep_work); |
3325 | wm8962->beep_rate = 0; |
3326 | |
3327 | wm8962->beep->name = "WM8962 Beep Generator" ; |
3328 | wm8962->beep->phys = dev_name(dev: component->dev); |
3329 | wm8962->beep->id.bustype = BUS_I2C; |
3330 | |
3331 | wm8962->beep->evbit[0] = BIT_MASK(EV_SND); |
3332 | wm8962->beep->sndbit[0] = BIT_MASK(SND_BELL) | BIT_MASK(SND_TONE); |
3333 | wm8962->beep->event = wm8962_beep_event; |
3334 | wm8962->beep->dev.parent = component->dev; |
3335 | input_set_drvdata(dev: wm8962->beep, data: component); |
3336 | |
3337 | ret = input_register_device(wm8962->beep); |
3338 | if (ret != 0) { |
3339 | wm8962->beep = NULL; |
3340 | dev_err(component->dev, "Failed to register beep device\n" ); |
3341 | } |
3342 | |
3343 | ret = device_create_file(device: component->dev, entry: &dev_attr_beep); |
3344 | if (ret != 0) { |
3345 | dev_err(component->dev, "Failed to create keyclick file: %d\n" , |
3346 | ret); |
3347 | } |
3348 | } |
3349 | |
3350 | static void wm8962_free_beep(struct snd_soc_component *component) |
3351 | { |
3352 | struct wm8962_priv *wm8962 = snd_soc_component_get_drvdata(c: component); |
3353 | |
3354 | device_remove_file(dev: component->dev, attr: &dev_attr_beep); |
3355 | cancel_work_sync(work: &wm8962->beep_work); |
3356 | wm8962->beep = NULL; |
3357 | |
3358 | snd_soc_component_update_bits(component, WM8962_BEEP_GENERATOR_1, WM8962_BEEP_ENA,val: 0); |
3359 | } |
3360 | |
3361 | static void wm8962_set_gpio_mode(struct wm8962_priv *wm8962, int gpio) |
3362 | { |
3363 | int mask = 0; |
3364 | int val = 0; |
3365 | |
3366 | /* Some of the GPIOs are behind MFP configuration and need to |
3367 | * be put into GPIO mode. */ |
3368 | switch (gpio) { |
3369 | case 2: |
3370 | mask = WM8962_CLKOUT2_SEL_MASK; |
3371 | val = 1 << WM8962_CLKOUT2_SEL_SHIFT; |
3372 | break; |
3373 | case 3: |
3374 | mask = WM8962_CLKOUT3_SEL_MASK; |
3375 | val = 1 << WM8962_CLKOUT3_SEL_SHIFT; |
3376 | break; |
3377 | default: |
3378 | break; |
3379 | } |
3380 | |
3381 | if (mask) |
3382 | regmap_update_bits(map: wm8962->regmap, WM8962_ANALOGUE_CLOCKING1, |
3383 | mask, val); |
3384 | } |
3385 | |
3386 | #ifdef CONFIG_GPIOLIB |
3387 | static int wm8962_gpio_request(struct gpio_chip *chip, unsigned offset) |
3388 | { |
3389 | struct wm8962_priv *wm8962 = gpiochip_get_data(gc: chip); |
3390 | |
3391 | /* The WM8962 GPIOs aren't linearly numbered. For simplicity |
3392 | * we export linear numbers and error out if the unsupported |
3393 | * ones are requsted. |
3394 | */ |
3395 | switch (offset + 1) { |
3396 | case 2: |
3397 | case 3: |
3398 | case 5: |
3399 | case 6: |
3400 | break; |
3401 | default: |
3402 | return -EINVAL; |
3403 | } |
3404 | |
3405 | wm8962_set_gpio_mode(wm8962, gpio: offset + 1); |
3406 | |
3407 | return 0; |
3408 | } |
3409 | |
3410 | static void wm8962_gpio_set(struct gpio_chip *chip, unsigned offset, int value) |
3411 | { |
3412 | struct wm8962_priv *wm8962 = gpiochip_get_data(gc: chip); |
3413 | struct snd_soc_component *component = wm8962->component; |
3414 | |
3415 | snd_soc_component_update_bits(component, WM8962_GPIO_BASE + offset, |
3416 | WM8962_GP2_LVL, val: !!value << WM8962_GP2_LVL_SHIFT); |
3417 | } |
3418 | |
3419 | static int wm8962_gpio_direction_out(struct gpio_chip *chip, |
3420 | unsigned offset, int value) |
3421 | { |
3422 | struct wm8962_priv *wm8962 = gpiochip_get_data(gc: chip); |
3423 | struct snd_soc_component *component = wm8962->component; |
3424 | int ret, val; |
3425 | |
3426 | /* Force function 1 (logic output) */ |
3427 | val = (1 << WM8962_GP2_FN_SHIFT) | (value << WM8962_GP2_LVL_SHIFT); |
3428 | |
3429 | ret = snd_soc_component_update_bits(component, WM8962_GPIO_BASE + offset, |
3430 | WM8962_GP2_FN_MASK | WM8962_GP2_LVL, val); |
3431 | if (ret < 0) |
3432 | return ret; |
3433 | |
3434 | return 0; |
3435 | } |
3436 | |
3437 | static const struct gpio_chip wm8962_template_chip = { |
3438 | .label = "wm8962" , |
3439 | .owner = THIS_MODULE, |
3440 | .request = wm8962_gpio_request, |
3441 | .direction_output = wm8962_gpio_direction_out, |
3442 | .set = wm8962_gpio_set, |
3443 | .can_sleep = 1, |
3444 | }; |
3445 | |
3446 | static void wm8962_init_gpio(struct snd_soc_component *component) |
3447 | { |
3448 | struct wm8962_priv *wm8962 = snd_soc_component_get_drvdata(c: component); |
3449 | struct wm8962_pdata *pdata = &wm8962->pdata; |
3450 | int ret; |
3451 | |
3452 | wm8962->gpio_chip = wm8962_template_chip; |
3453 | wm8962->gpio_chip.ngpio = WM8962_MAX_GPIO; |
3454 | wm8962->gpio_chip.parent = component->dev; |
3455 | |
3456 | if (pdata->gpio_base) |
3457 | wm8962->gpio_chip.base = pdata->gpio_base; |
3458 | else |
3459 | wm8962->gpio_chip.base = -1; |
3460 | |
3461 | ret = gpiochip_add_data(&wm8962->gpio_chip, wm8962); |
3462 | if (ret != 0) |
3463 | dev_err(component->dev, "Failed to add GPIOs: %d\n" , ret); |
3464 | } |
3465 | |
3466 | static void wm8962_free_gpio(struct snd_soc_component *component) |
3467 | { |
3468 | struct wm8962_priv *wm8962 = snd_soc_component_get_drvdata(c: component); |
3469 | |
3470 | gpiochip_remove(gc: &wm8962->gpio_chip); |
3471 | } |
3472 | #else |
3473 | static void wm8962_init_gpio(struct snd_soc_component *component) |
3474 | { |
3475 | } |
3476 | |
3477 | static void wm8962_free_gpio(struct snd_soc_component *component) |
3478 | { |
3479 | } |
3480 | #endif |
3481 | |
3482 | static int wm8962_probe(struct snd_soc_component *component) |
3483 | { |
3484 | struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component); |
3485 | int ret; |
3486 | struct wm8962_priv *wm8962 = snd_soc_component_get_drvdata(c: component); |
3487 | int i; |
3488 | bool dmicclk, dmicdat; |
3489 | |
3490 | wm8962->component = component; |
3491 | |
3492 | wm8962->disable_nb[0].notifier_call = wm8962_regulator_event_0; |
3493 | wm8962->disable_nb[1].notifier_call = wm8962_regulator_event_1; |
3494 | wm8962->disable_nb[2].notifier_call = wm8962_regulator_event_2; |
3495 | wm8962->disable_nb[3].notifier_call = wm8962_regulator_event_3; |
3496 | wm8962->disable_nb[4].notifier_call = wm8962_regulator_event_4; |
3497 | wm8962->disable_nb[5].notifier_call = wm8962_regulator_event_5; |
3498 | wm8962->disable_nb[6].notifier_call = wm8962_regulator_event_6; |
3499 | wm8962->disable_nb[7].notifier_call = wm8962_regulator_event_7; |
3500 | |
3501 | /* This should really be moved into the regulator core */ |
3502 | for (i = 0; i < ARRAY_SIZE(wm8962->supplies); i++) { |
3503 | ret = devm_regulator_register_notifier( |
3504 | regulator: wm8962->supplies[i].consumer, |
3505 | nb: &wm8962->disable_nb[i]); |
3506 | if (ret != 0) { |
3507 | dev_err(component->dev, |
3508 | "Failed to register regulator notifier: %d\n" , |
3509 | ret); |
3510 | } |
3511 | } |
3512 | |
3513 | wm8962_add_widgets(component); |
3514 | |
3515 | /* Save boards having to disable DMIC when not in use */ |
3516 | dmicclk = false; |
3517 | dmicdat = false; |
3518 | for (i = 1; i < WM8962_MAX_GPIO; i++) { |
3519 | /* |
3520 | * Register 515 (WM8962_GPIO_BASE + 3) does not exist, |
3521 | * so skip its access |
3522 | */ |
3523 | if (i == 3) |
3524 | continue; |
3525 | switch (snd_soc_component_read(component, WM8962_GPIO_BASE + i) |
3526 | & WM8962_GP2_FN_MASK) { |
3527 | case WM8962_GPIO_FN_DMICCLK: |
3528 | dmicclk = true; |
3529 | break; |
3530 | case WM8962_GPIO_FN_DMICDAT: |
3531 | dmicdat = true; |
3532 | break; |
3533 | default: |
3534 | break; |
3535 | } |
3536 | } |
3537 | if (!dmicclk || !dmicdat) { |
3538 | dev_dbg(component->dev, "DMIC not in use, disabling\n" ); |
3539 | snd_soc_dapm_nc_pin(dapm, pin: "DMICDAT" ); |
3540 | } |
3541 | if (dmicclk != dmicdat) |
3542 | dev_warn(component->dev, "DMIC GPIOs partially configured\n" ); |
3543 | |
3544 | wm8962_init_beep(component); |
3545 | wm8962_init_gpio(component); |
3546 | |
3547 | return 0; |
3548 | } |
3549 | |
3550 | static void wm8962_remove(struct snd_soc_component *component) |
3551 | { |
3552 | struct wm8962_priv *wm8962 = snd_soc_component_get_drvdata(c: component); |
3553 | |
3554 | cancel_delayed_work_sync(dwork: &wm8962->mic_work); |
3555 | |
3556 | wm8962_free_gpio(component); |
3557 | wm8962_free_beep(component); |
3558 | } |
3559 | |
3560 | static const struct snd_soc_component_driver soc_component_dev_wm8962 = { |
3561 | .probe = wm8962_probe, |
3562 | .remove = wm8962_remove, |
3563 | .set_bias_level = wm8962_set_bias_level, |
3564 | .set_pll = wm8962_set_fll, |
3565 | .use_pmdown_time = 1, |
3566 | .endianness = 1, |
3567 | }; |
3568 | |
3569 | /* Improve power consumption for IN4 DC measurement mode */ |
3570 | static const struct reg_sequence wm8962_dc_measure[] = { |
3571 | { 0xfd, 0x1 }, |
3572 | { 0xcc, 0x40 }, |
3573 | { 0xfd, 0 }, |
3574 | }; |
3575 | |
3576 | static const struct regmap_config wm8962_regmap = { |
3577 | .reg_bits = 16, |
3578 | .val_bits = 16, |
3579 | |
3580 | .max_register = WM8962_MAX_REGISTER, |
3581 | .reg_defaults = wm8962_reg, |
3582 | .num_reg_defaults = ARRAY_SIZE(wm8962_reg), |
3583 | .volatile_reg = wm8962_volatile_register, |
3584 | .readable_reg = wm8962_readable_register, |
3585 | .cache_type = REGCACHE_MAPLE, |
3586 | }; |
3587 | |
3588 | static int wm8962_set_pdata_from_of(struct i2c_client *i2c, |
3589 | struct wm8962_pdata *pdata) |
3590 | { |
3591 | const struct device_node *np = i2c->dev.of_node; |
3592 | u32 val32; |
3593 | int i; |
3594 | |
3595 | if (of_property_read_bool(np, propname: "spk-mono" )) |
3596 | pdata->spk_mono = true; |
3597 | |
3598 | if (of_property_read_u32(np, propname: "mic-cfg" , out_value: &val32) >= 0) |
3599 | pdata->mic_cfg = val32; |
3600 | |
3601 | if (of_property_read_u32_array(np, propname: "gpio-cfg" , out_values: pdata->gpio_init, |
3602 | ARRAY_SIZE(pdata->gpio_init)) >= 0) |
3603 | for (i = 0; i < ARRAY_SIZE(pdata->gpio_init); i++) { |
3604 | /* |
3605 | * The range of GPIO register value is [0x0, 0xffff] |
3606 | * While the default value of each register is 0x0 |
3607 | * Any other value will be regarded as default value |
3608 | */ |
3609 | if (pdata->gpio_init[i] > 0xffff) |
3610 | pdata->gpio_init[i] = 0x0; |
3611 | } |
3612 | |
3613 | pdata->mclk = devm_clk_get_optional(dev: &i2c->dev, NULL); |
3614 | return PTR_ERR_OR_ZERO(ptr: pdata->mclk); |
3615 | } |
3616 | |
3617 | static int wm8962_i2c_probe(struct i2c_client *i2c) |
3618 | { |
3619 | struct wm8962_pdata *pdata = dev_get_platdata(dev: &i2c->dev); |
3620 | struct wm8962_priv *wm8962; |
3621 | unsigned int reg; |
3622 | int ret, i, irq_pol, trigger; |
3623 | |
3624 | wm8962 = devm_kzalloc(dev: &i2c->dev, size: sizeof(*wm8962), GFP_KERNEL); |
3625 | if (wm8962 == NULL) |
3626 | return -ENOMEM; |
3627 | |
3628 | mutex_init(&wm8962->dsp2_ena_lock); |
3629 | |
3630 | i2c_set_clientdata(client: i2c, data: wm8962); |
3631 | |
3632 | INIT_DELAYED_WORK(&wm8962->mic_work, wm8962_mic_work); |
3633 | init_completion(x: &wm8962->fll_lock); |
3634 | wm8962->irq = i2c->irq; |
3635 | |
3636 | /* If platform data was supplied, update the default data in priv */ |
3637 | if (pdata) { |
3638 | memcpy(&wm8962->pdata, pdata, sizeof(struct wm8962_pdata)); |
3639 | } else if (i2c->dev.of_node) { |
3640 | ret = wm8962_set_pdata_from_of(i2c, pdata: &wm8962->pdata); |
3641 | if (ret != 0) |
3642 | return ret; |
3643 | } |
3644 | |
3645 | for (i = 0; i < ARRAY_SIZE(wm8962->supplies); i++) |
3646 | wm8962->supplies[i].supply = wm8962_supply_names[i]; |
3647 | |
3648 | ret = devm_regulator_bulk_get(dev: &i2c->dev, ARRAY_SIZE(wm8962->supplies), |
3649 | consumers: wm8962->supplies); |
3650 | if (ret != 0) { |
3651 | dev_err(&i2c->dev, "Failed to request supplies: %d\n" , ret); |
3652 | goto err; |
3653 | } |
3654 | |
3655 | ret = regulator_bulk_enable(ARRAY_SIZE(wm8962->supplies), |
3656 | consumers: wm8962->supplies); |
3657 | if (ret != 0) { |
3658 | dev_err(&i2c->dev, "Failed to enable supplies: %d\n" , ret); |
3659 | return ret; |
3660 | } |
3661 | |
3662 | wm8962->regmap = devm_regmap_init_i2c(i2c, &wm8962_regmap); |
3663 | if (IS_ERR(ptr: wm8962->regmap)) { |
3664 | ret = PTR_ERR(ptr: wm8962->regmap); |
3665 | dev_err(&i2c->dev, "Failed to allocate regmap: %d\n" , ret); |
3666 | goto err_enable; |
3667 | } |
3668 | |
3669 | /* |
3670 | * We haven't marked the chip revision as volatile due to |
3671 | * sharing a register with the right input volume; explicitly |
3672 | * bypass the cache to read it. |
3673 | */ |
3674 | regcache_cache_bypass(map: wm8962->regmap, enable: true); |
3675 | |
3676 | ret = regmap_read(map: wm8962->regmap, WM8962_SOFTWARE_RESET, val: ®); |
3677 | if (ret < 0) { |
3678 | dev_err(&i2c->dev, "Failed to read ID register\n" ); |
3679 | goto err_enable; |
3680 | } |
3681 | if (reg != 0x6243) { |
3682 | dev_err(&i2c->dev, |
3683 | "Device is not a WM8962, ID %x != 0x6243\n" , reg); |
3684 | ret = -EINVAL; |
3685 | goto err_enable; |
3686 | } |
3687 | |
3688 | ret = regmap_read(map: wm8962->regmap, WM8962_RIGHT_INPUT_VOLUME, val: ®); |
3689 | if (ret < 0) { |
3690 | dev_err(&i2c->dev, "Failed to read device revision: %d\n" , |
3691 | ret); |
3692 | goto err_enable; |
3693 | } |
3694 | |
3695 | dev_info(&i2c->dev, "customer id %x revision %c\n" , |
3696 | (reg & WM8962_CUST_ID_MASK) >> WM8962_CUST_ID_SHIFT, |
3697 | ((reg & WM8962_CHIP_REV_MASK) >> WM8962_CHIP_REV_SHIFT) |
3698 | + 'A'); |
3699 | |
3700 | regcache_cache_bypass(map: wm8962->regmap, enable: false); |
3701 | |
3702 | ret = wm8962_reset(wm8962); |
3703 | if (ret < 0) { |
3704 | dev_err(&i2c->dev, "Failed to issue reset\n" ); |
3705 | goto err_enable; |
3706 | } |
3707 | |
3708 | /* SYSCLK defaults to on; make sure it is off so we can safely |
3709 | * write to registers if the device is declocked. |
3710 | */ |
3711 | regmap_update_bits(map: wm8962->regmap, WM8962_CLOCKING2, |
3712 | WM8962_SYSCLK_ENA, val: 0); |
3713 | |
3714 | /* Ensure we have soft control over all registers */ |
3715 | regmap_update_bits(map: wm8962->regmap, WM8962_CLOCKING2, |
3716 | WM8962_CLKREG_OVD, WM8962_CLKREG_OVD); |
3717 | |
3718 | /* Ensure that the oscillator and PLLs are disabled */ |
3719 | regmap_update_bits(map: wm8962->regmap, WM8962_PLL2, |
3720 | WM8962_OSC_ENA | WM8962_PLL2_ENA | WM8962_PLL3_ENA, |
3721 | val: 0); |
3722 | |
3723 | /* Apply static configuration for GPIOs */ |
3724 | for (i = 0; i < ARRAY_SIZE(wm8962->pdata.gpio_init); i++) |
3725 | if (wm8962->pdata.gpio_init[i]) { |
3726 | wm8962_set_gpio_mode(wm8962, gpio: i + 1); |
3727 | regmap_write(map: wm8962->regmap, reg: 0x200 + i, |
3728 | val: wm8962->pdata.gpio_init[i] & 0xffff); |
3729 | } |
3730 | |
3731 | |
3732 | /* Put the speakers into mono mode? */ |
3733 | if (wm8962->pdata.spk_mono) |
3734 | regmap_update_bits(map: wm8962->regmap, WM8962_CLASS_D_CONTROL_2, |
3735 | WM8962_SPK_MONO_MASK, WM8962_SPK_MONO); |
3736 | |
3737 | /* Micbias setup, detection enable and detection |
3738 | * threasholds. */ |
3739 | if (wm8962->pdata.mic_cfg) |
3740 | regmap_update_bits(map: wm8962->regmap, WM8962_ADDITIONAL_CONTROL_4, |
3741 | WM8962_MICDET_ENA | |
3742 | WM8962_MICDET_THR_MASK | |
3743 | WM8962_MICSHORT_THR_MASK | |
3744 | WM8962_MICBIAS_LVL, |
3745 | val: wm8962->pdata.mic_cfg); |
3746 | |
3747 | /* Latch volume update bits */ |
3748 | regmap_update_bits(map: wm8962->regmap, WM8962_LEFT_INPUT_VOLUME, |
3749 | WM8962_IN_VU, WM8962_IN_VU); |
3750 | regmap_update_bits(map: wm8962->regmap, WM8962_RIGHT_INPUT_VOLUME, |
3751 | WM8962_IN_VU, WM8962_IN_VU); |
3752 | regmap_update_bits(map: wm8962->regmap, WM8962_LEFT_ADC_VOLUME, |
3753 | WM8962_ADC_VU, WM8962_ADC_VU); |
3754 | regmap_update_bits(map: wm8962->regmap, WM8962_RIGHT_ADC_VOLUME, |
3755 | WM8962_ADC_VU, WM8962_ADC_VU); |
3756 | regmap_update_bits(map: wm8962->regmap, WM8962_LEFT_DAC_VOLUME, |
3757 | WM8962_DAC_VU, WM8962_DAC_VU); |
3758 | regmap_update_bits(map: wm8962->regmap, WM8962_RIGHT_DAC_VOLUME, |
3759 | WM8962_DAC_VU, WM8962_DAC_VU); |
3760 | regmap_update_bits(map: wm8962->regmap, WM8962_SPKOUTL_VOLUME, |
3761 | WM8962_SPKOUT_VU, WM8962_SPKOUT_VU); |
3762 | regmap_update_bits(map: wm8962->regmap, WM8962_SPKOUTR_VOLUME, |
3763 | WM8962_SPKOUT_VU, WM8962_SPKOUT_VU); |
3764 | regmap_update_bits(map: wm8962->regmap, WM8962_HPOUTL_VOLUME, |
3765 | WM8962_HPOUT_VU, WM8962_HPOUT_VU); |
3766 | regmap_update_bits(map: wm8962->regmap, WM8962_HPOUTR_VOLUME, |
3767 | WM8962_HPOUT_VU, WM8962_HPOUT_VU); |
3768 | |
3769 | /* Stereo control for EQ */ |
3770 | regmap_update_bits(map: wm8962->regmap, WM8962_EQ1, |
3771 | WM8962_EQ_SHARED_COEFF, val: 0); |
3772 | |
3773 | /* Don't debouce interrupts so we don't need SYSCLK */ |
3774 | regmap_update_bits(map: wm8962->regmap, WM8962_IRQ_DEBOUNCE, |
3775 | WM8962_FLL_LOCK_DB | WM8962_PLL3_LOCK_DB | |
3776 | WM8962_PLL2_LOCK_DB | WM8962_TEMP_SHUT_DB, |
3777 | val: 0); |
3778 | |
3779 | if (wm8962->pdata.in4_dc_measure) { |
3780 | ret = regmap_register_patch(map: wm8962->regmap, |
3781 | regs: wm8962_dc_measure, |
3782 | ARRAY_SIZE(wm8962_dc_measure)); |
3783 | if (ret != 0) |
3784 | dev_err(&i2c->dev, |
3785 | "Failed to configure for DC measurement: %d\n" , |
3786 | ret); |
3787 | } |
3788 | |
3789 | if (wm8962->irq) { |
3790 | if (wm8962->pdata.irq_active_low) { |
3791 | trigger = IRQF_TRIGGER_LOW; |
3792 | irq_pol = WM8962_IRQ_POL; |
3793 | } else { |
3794 | trigger = IRQF_TRIGGER_HIGH; |
3795 | irq_pol = 0; |
3796 | } |
3797 | |
3798 | regmap_update_bits(map: wm8962->regmap, WM8962_INTERRUPT_CONTROL, |
3799 | WM8962_IRQ_POL, val: irq_pol); |
3800 | |
3801 | ret = devm_request_threaded_irq(dev: &i2c->dev, irq: wm8962->irq, NULL, |
3802 | thread_fn: wm8962_irq, |
3803 | irqflags: trigger | IRQF_ONESHOT, |
3804 | devname: "wm8962" , dev_id: &i2c->dev); |
3805 | if (ret != 0) { |
3806 | dev_err(&i2c->dev, "Failed to request IRQ %d: %d\n" , |
3807 | wm8962->irq, ret); |
3808 | wm8962->irq = 0; |
3809 | /* Non-fatal */ |
3810 | } else { |
3811 | /* Enable some IRQs by default */ |
3812 | regmap_update_bits(map: wm8962->regmap, |
3813 | WM8962_INTERRUPT_STATUS_2_MASK, |
3814 | WM8962_FLL_LOCK_EINT | |
3815 | WM8962_TEMP_SHUT_EINT | |
3816 | WM8962_FIFOS_ERR_EINT, val: 0); |
3817 | } |
3818 | } |
3819 | |
3820 | pm_runtime_enable(dev: &i2c->dev); |
3821 | pm_request_idle(dev: &i2c->dev); |
3822 | |
3823 | ret = devm_snd_soc_register_component(dev: &i2c->dev, |
3824 | component_driver: &soc_component_dev_wm8962, dai_drv: &wm8962_dai, num_dai: 1); |
3825 | if (ret < 0) |
3826 | goto err_pm_runtime; |
3827 | |
3828 | regmap_update_bits(map: wm8962->regmap, WM8962_ADDITIONAL_CONTROL_4, |
3829 | WM8962_TEMP_ENA_HP_MASK, val: 0); |
3830 | regmap_update_bits(map: wm8962->regmap, WM8962_ADDITIONAL_CONTROL_4, |
3831 | WM8962_TEMP_ENA_SPK_MASK, val: 0); |
3832 | |
3833 | regcache_cache_only(map: wm8962->regmap, enable: true); |
3834 | |
3835 | /* The drivers should power up as needed */ |
3836 | regulator_bulk_disable(ARRAY_SIZE(wm8962->supplies), consumers: wm8962->supplies); |
3837 | |
3838 | return 0; |
3839 | |
3840 | err_pm_runtime: |
3841 | pm_runtime_disable(dev: &i2c->dev); |
3842 | err_enable: |
3843 | regulator_bulk_disable(ARRAY_SIZE(wm8962->supplies), consumers: wm8962->supplies); |
3844 | err: |
3845 | return ret; |
3846 | } |
3847 | |
3848 | static void wm8962_i2c_remove(struct i2c_client *client) |
3849 | { |
3850 | pm_runtime_disable(dev: &client->dev); |
3851 | } |
3852 | |
3853 | #ifdef CONFIG_PM |
3854 | static int wm8962_runtime_resume(struct device *dev) |
3855 | { |
3856 | struct wm8962_priv *wm8962 = dev_get_drvdata(dev); |
3857 | int ret; |
3858 | |
3859 | ret = clk_prepare_enable(clk: wm8962->pdata.mclk); |
3860 | if (ret) { |
3861 | dev_err(dev, "Failed to enable MCLK: %d\n" , ret); |
3862 | return ret; |
3863 | } |
3864 | |
3865 | ret = regulator_bulk_enable(ARRAY_SIZE(wm8962->supplies), |
3866 | consumers: wm8962->supplies); |
3867 | if (ret != 0) { |
3868 | dev_err(dev, "Failed to enable supplies: %d\n" , ret); |
3869 | goto disable_clock; |
3870 | } |
3871 | |
3872 | regcache_cache_only(map: wm8962->regmap, enable: false); |
3873 | |
3874 | wm8962_reset(wm8962); |
3875 | |
3876 | regcache_mark_dirty(map: wm8962->regmap); |
3877 | |
3878 | /* SYSCLK defaults to on; make sure it is off so we can safely |
3879 | * write to registers if the device is declocked. |
3880 | */ |
3881 | regmap_write_bits(map: wm8962->regmap, WM8962_CLOCKING2, |
3882 | WM8962_SYSCLK_ENA, val: 0); |
3883 | |
3884 | /* Ensure we have soft control over all registers */ |
3885 | regmap_update_bits(map: wm8962->regmap, WM8962_CLOCKING2, |
3886 | WM8962_CLKREG_OVD, WM8962_CLKREG_OVD); |
3887 | |
3888 | /* Ensure that the oscillator and PLLs are disabled */ |
3889 | regmap_update_bits(map: wm8962->regmap, WM8962_PLL2, |
3890 | WM8962_OSC_ENA | WM8962_PLL2_ENA | WM8962_PLL3_ENA, |
3891 | val: 0); |
3892 | |
3893 | regcache_sync(map: wm8962->regmap); |
3894 | |
3895 | regmap_update_bits(map: wm8962->regmap, WM8962_ANTI_POP, |
3896 | WM8962_STARTUP_BIAS_ENA | WM8962_VMID_BUF_ENA, |
3897 | WM8962_STARTUP_BIAS_ENA | WM8962_VMID_BUF_ENA); |
3898 | |
3899 | /* Bias enable at 2*5k (fast start-up) */ |
3900 | regmap_update_bits(map: wm8962->regmap, WM8962_PWR_MGMT_1, |
3901 | WM8962_BIAS_ENA | WM8962_VMID_SEL_MASK, |
3902 | WM8962_BIAS_ENA | 0x180); |
3903 | |
3904 | msleep(msecs: 5); |
3905 | |
3906 | return 0; |
3907 | |
3908 | disable_clock: |
3909 | clk_disable_unprepare(clk: wm8962->pdata.mclk); |
3910 | return ret; |
3911 | } |
3912 | |
3913 | static int wm8962_runtime_suspend(struct device *dev) |
3914 | { |
3915 | struct wm8962_priv *wm8962 = dev_get_drvdata(dev); |
3916 | |
3917 | regmap_update_bits(map: wm8962->regmap, WM8962_PWR_MGMT_1, |
3918 | WM8962_VMID_SEL_MASK | WM8962_BIAS_ENA, val: 0); |
3919 | |
3920 | regmap_update_bits(map: wm8962->regmap, WM8962_ANTI_POP, |
3921 | WM8962_STARTUP_BIAS_ENA | |
3922 | WM8962_VMID_BUF_ENA, val: 0); |
3923 | |
3924 | regcache_cache_only(map: wm8962->regmap, enable: true); |
3925 | |
3926 | regulator_bulk_disable(ARRAY_SIZE(wm8962->supplies), |
3927 | consumers: wm8962->supplies); |
3928 | |
3929 | clk_disable_unprepare(clk: wm8962->pdata.mclk); |
3930 | |
3931 | return 0; |
3932 | } |
3933 | #endif |
3934 | |
3935 | static const struct dev_pm_ops wm8962_pm = { |
3936 | SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, pm_runtime_force_resume) |
3937 | SET_RUNTIME_PM_OPS(wm8962_runtime_suspend, wm8962_runtime_resume, NULL) |
3938 | }; |
3939 | |
3940 | static const struct i2c_device_id wm8962_i2c_id[] = { |
3941 | { "wm8962" , 0 }, |
3942 | { } |
3943 | }; |
3944 | MODULE_DEVICE_TABLE(i2c, wm8962_i2c_id); |
3945 | |
3946 | static const struct of_device_id wm8962_of_match[] = { |
3947 | { .compatible = "wlf,wm8962" , }, |
3948 | { } |
3949 | }; |
3950 | MODULE_DEVICE_TABLE(of, wm8962_of_match); |
3951 | |
3952 | static struct i2c_driver wm8962_i2c_driver = { |
3953 | .driver = { |
3954 | .name = "wm8962" , |
3955 | .of_match_table = wm8962_of_match, |
3956 | .pm = &wm8962_pm, |
3957 | }, |
3958 | .probe = wm8962_i2c_probe, |
3959 | .remove = wm8962_i2c_remove, |
3960 | .id_table = wm8962_i2c_id, |
3961 | }; |
3962 | |
3963 | module_i2c_driver(wm8962_i2c_driver); |
3964 | |
3965 | MODULE_DESCRIPTION("ASoC WM8962 driver" ); |
3966 | MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>" ); |
3967 | MODULE_LICENSE("GPL" ); |
3968 | |