| 1 | // SPDX-License-Identifier: GPL-2.0-only |
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| 2 | /* |
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| 3 | * Copyright (c) 2015-2021, The Linux Foundation. All rights reserved. |
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| 4 | */ |
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| 5 | |
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| 6 | #include <linux/bitops.h> |
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| 7 | #include <linux/device.h> |
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| 8 | #include <linux/gpio/consumer.h> |
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| 9 | #include <linux/init.h> |
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| 10 | #include <linux/kernel.h> |
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| 11 | #include <linux/module.h> |
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| 12 | #include <linux/of_gpio.h> |
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| 13 | #include <linux/pm_runtime.h> |
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| 14 | #include <linux/printk.h> |
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| 15 | #include <linux/regmap.h> |
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| 16 | #include <linux/regulator/consumer.h> |
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| 17 | #include <linux/slab.h> |
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| 18 | #include <linux/soundwire/sdw.h> |
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| 19 | #include <linux/soundwire/sdw_registers.h> |
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| 20 | #include <linux/soundwire/sdw_type.h> |
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| 21 | #include <sound/pcm.h> |
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| 22 | #include <sound/pcm_params.h> |
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| 23 | #include <sound/soc-dapm.h> |
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| 24 | #include <sound/soc.h> |
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| 25 | #include <sound/tlv.h> |
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| 26 | |
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| 27 | #define WSA883X_BASE 0x3000 |
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| 28 | #define WSA883X_ANA_BG_TSADC_BASE (WSA883X_BASE + 0x00000001) |
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| 29 | #define WSA883X_REF_CTRL (WSA883X_ANA_BG_TSADC_BASE + 0x0000) |
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| 30 | #define WSA883X_TEST_CTL_0 (WSA883X_ANA_BG_TSADC_BASE + 0x0001) |
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| 31 | #define WSA883X_BIAS_0 (WSA883X_ANA_BG_TSADC_BASE + 0x0002) |
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| 32 | #define WSA883X_OP_CTL (WSA883X_ANA_BG_TSADC_BASE + 0x0003) |
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| 33 | #define WSA883X_IREF_CTL (WSA883X_ANA_BG_TSADC_BASE + 0x0004) |
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| 34 | #define WSA883X_ISENS_CTL (WSA883X_ANA_BG_TSADC_BASE + 0x0005) |
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| 35 | #define WSA883X_CLK_CTL (WSA883X_ANA_BG_TSADC_BASE + 0x0006) |
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| 36 | #define WSA883X_TEST_CTL_1 (WSA883X_ANA_BG_TSADC_BASE + 0x0007) |
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| 37 | #define WSA883X_BIAS_1 (WSA883X_ANA_BG_TSADC_BASE + 0x0008) |
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| 38 | #define WSA883X_ADC_CTL (WSA883X_ANA_BG_TSADC_BASE + 0x0009) |
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| 39 | #define WSA883X_DOUT_MSB (WSA883X_ANA_BG_TSADC_BASE + 0x000A) |
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| 40 | #define WSA883X_DOUT_LSB (WSA883X_ANA_BG_TSADC_BASE + 0x000B) |
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| 41 | #define WSA883X_VBAT_SNS (WSA883X_ANA_BG_TSADC_BASE + 0x000C) |
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| 42 | #define WSA883X_ITRIM_CODE (WSA883X_ANA_BG_TSADC_BASE + 0x000D) |
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| 43 | |
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| 44 | #define WSA883X_ANA_IVSENSE_BASE (WSA883X_BASE + 0x0000000F) |
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| 45 | #define WSA883X_EN (WSA883X_ANA_IVSENSE_BASE + 0x0000) |
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| 46 | #define WSA883X_OVERRIDE1 (WSA883X_ANA_IVSENSE_BASE + 0x0001) |
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| 47 | #define WSA883X_OVERRIDE2 (WSA883X_ANA_IVSENSE_BASE + 0x0002) |
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| 48 | #define WSA883X_VSENSE1 (WSA883X_ANA_IVSENSE_BASE + 0x0003) |
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| 49 | #define WSA883X_ISENSE1 (WSA883X_ANA_IVSENSE_BASE + 0x0004) |
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| 50 | #define WSA883X_ISENSE2 (WSA883X_ANA_IVSENSE_BASE + 0x0005) |
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| 51 | #define WSA883X_ISENSE_CAL (WSA883X_ANA_IVSENSE_BASE + 0x0006) |
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| 52 | #define WSA883X_MISC (WSA883X_ANA_IVSENSE_BASE + 0x0007) |
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| 53 | #define WSA883X_ADC_0 (WSA883X_ANA_IVSENSE_BASE + 0x0008) |
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| 54 | #define WSA883X_ADC_1 (WSA883X_ANA_IVSENSE_BASE + 0x0009) |
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| 55 | #define WSA883X_ADC_2 (WSA883X_ANA_IVSENSE_BASE + 0x000A) |
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| 56 | #define WSA883X_ADC_3 (WSA883X_ANA_IVSENSE_BASE + 0x000B) |
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| 57 | #define WSA883X_ADC_4 (WSA883X_ANA_IVSENSE_BASE + 0x000C) |
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| 58 | #define WSA883X_ADC_5 (WSA883X_ANA_IVSENSE_BASE + 0x000D) |
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| 59 | #define WSA883X_ADC_6 (WSA883X_ANA_IVSENSE_BASE + 0x000E) |
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| 60 | #define WSA883X_ADC_7 (WSA883X_ANA_IVSENSE_BASE + 0x000F) |
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| 61 | #define WSA883X_STATUS (WSA883X_ANA_IVSENSE_BASE + 0x0010) |
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| 62 | |
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| 63 | #define WSA883X_ANA_SPK_TOP_BASE (WSA883X_BASE + 0x00000025) |
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| 64 | #define WSA883X_DAC_CTRL_REG (WSA883X_ANA_SPK_TOP_BASE + 0x0000) |
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| 65 | #define WSA883X_DAC_EN_DEBUG_REG (WSA883X_ANA_SPK_TOP_BASE + 0x0001) |
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| 66 | #define WSA883X_DAC_OPAMP_BIAS1_REG (WSA883X_ANA_SPK_TOP_BASE + 0x0002) |
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| 67 | #define WSA883X_DAC_OPAMP_BIAS2_REG (WSA883X_ANA_SPK_TOP_BASE + 0x0003) |
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| 68 | #define WSA883X_DAC_VCM_CTRL_REG (WSA883X_ANA_SPK_TOP_BASE + 0x0004) |
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| 69 | #define WSA883X_DAC_VOLTAGE_CTRL_REG (WSA883X_ANA_SPK_TOP_BASE + 0x0005) |
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| 70 | #define WSA883X_ATEST1_REG (WSA883X_ANA_SPK_TOP_BASE + 0x0006) |
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| 71 | #define WSA883X_ATEST2_REG (WSA883X_ANA_SPK_TOP_BASE + 0x0007) |
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| 72 | #define WSA883X_SPKR_TOP_BIAS_REG1 (WSA883X_ANA_SPK_TOP_BASE + 0x0008) |
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| 73 | #define WSA883X_SPKR_TOP_BIAS_REG2 (WSA883X_ANA_SPK_TOP_BASE + 0x0009) |
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| 74 | #define WSA883X_SPKR_TOP_BIAS_REG3 (WSA883X_ANA_SPK_TOP_BASE + 0x000A) |
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| 75 | #define WSA883X_SPKR_TOP_BIAS_REG4 (WSA883X_ANA_SPK_TOP_BASE + 0x000B) |
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| 76 | #define WSA883X_SPKR_CLIP_DET_REG (WSA883X_ANA_SPK_TOP_BASE + 0x000C) |
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| 77 | #define WSA883X_SPKR_DRV_LF_BLK_EN (WSA883X_ANA_SPK_TOP_BASE + 0x000D) |
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| 78 | #define WSA883X_SPKR_DRV_LF_EN (WSA883X_ANA_SPK_TOP_BASE + 0x000E) |
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| 79 | #define WSA883X_SPKR_DRV_LF_MASK_DCC_CTL (WSA883X_ANA_SPK_TOP_BASE + 0x000F) |
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| 80 | #define WSA883X_SPKR_DRV_LF_MISC_CTL (WSA883X_ANA_SPK_TOP_BASE + 0x0010) |
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| 81 | #define WSA883X_SPKR_DRV_LF_REG_GAIN (WSA883X_ANA_SPK_TOP_BASE + 0x0011) |
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| 82 | #define WSA883X_SPKR_DRV_OS_CAL_CTL (WSA883X_ANA_SPK_TOP_BASE + 0x0012) |
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| 83 | #define WSA883X_SPKR_DRV_OS_CAL_CTL1 (WSA883X_ANA_SPK_TOP_BASE + 0x0013) |
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| 84 | #define WSA883X_SPKR_PWM_CLK_CTL (WSA883X_ANA_SPK_TOP_BASE + 0x0014) |
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| 85 | #define WSA883X_SPKR_PWM_FREQ_SEL_MASK BIT(3) |
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| 86 | #define WSA883X_SPKR_PWM_FREQ_F300KHZ 0 |
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| 87 | #define WSA883X_SPKR_PWM_FREQ_F600KHZ 1 |
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| 88 | #define WSA883X_SPKR_PDRV_HS_CTL (WSA883X_ANA_SPK_TOP_BASE + 0x0015) |
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| 89 | #define WSA883X_SPKR_PDRV_LS_CTL (WSA883X_ANA_SPK_TOP_BASE + 0x0016) |
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| 90 | #define WSA883X_SPKR_PWRSTG_DBG (WSA883X_ANA_SPK_TOP_BASE + 0x0017) |
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| 91 | #define WSA883X_SPKR_OCP_CTL (WSA883X_ANA_SPK_TOP_BASE + 0x0018) |
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| 92 | #define WSA883X_SPKR_BBM_CTL (WSA883X_ANA_SPK_TOP_BASE + 0x0019) |
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| 93 | #define WSA883X_PA_STATUS0 (WSA883X_ANA_SPK_TOP_BASE + 0x001A) |
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| 94 | #define WSA883X_PA_STATUS1 (WSA883X_ANA_SPK_TOP_BASE + 0x001B) |
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| 95 | #define WSA883X_PA_STATUS2 (WSA883X_ANA_SPK_TOP_BASE + 0x001C) |
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| 96 | |
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| 97 | #define WSA883X_ANA_BOOST_BASE (WSA883X_BASE + 0x00000043) |
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| 98 | #define WSA883X_EN_CTRL (WSA883X_ANA_BOOST_BASE + 0x0000) |
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| 99 | #define WSA883X_CURRENT_LIMIT (WSA883X_ANA_BOOST_BASE + 0x0001) |
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| 100 | #define WSA883X_IBIAS1 (WSA883X_ANA_BOOST_BASE + 0x0002) |
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| 101 | #define WSA883X_IBIAS2 (WSA883X_ANA_BOOST_BASE + 0x0003) |
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| 102 | #define WSA883X_IBIAS3 (WSA883X_ANA_BOOST_BASE + 0x0004) |
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| 103 | #define WSA883X_LDO_PROG (WSA883X_ANA_BOOST_BASE + 0x0005) |
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| 104 | #define WSA883X_STABILITY_CTRL1 (WSA883X_ANA_BOOST_BASE + 0x0006) |
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| 105 | #define WSA883X_STABILITY_CTRL2 (WSA883X_ANA_BOOST_BASE + 0x0007) |
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| 106 | #define WSA883X_PWRSTAGE_CTRL1 (WSA883X_ANA_BOOST_BASE + 0x0008) |
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| 107 | #define WSA883X_PWRSTAGE_CTRL2 (WSA883X_ANA_BOOST_BASE + 0x0009) |
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| 108 | #define WSA883X_BYPASS_1 (WSA883X_ANA_BOOST_BASE + 0x000A) |
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| 109 | #define WSA883X_BYPASS_2 (WSA883X_ANA_BOOST_BASE + 0x000B) |
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| 110 | #define WSA883X_ZX_CTRL_1 (WSA883X_ANA_BOOST_BASE + 0x000C) |
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| 111 | #define WSA883X_ZX_CTRL_2 (WSA883X_ANA_BOOST_BASE + 0x000D) |
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| 112 | #define WSA883X_MISC1 (WSA883X_ANA_BOOST_BASE + 0x000E) |
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| 113 | #define WSA883X_MISC2 (WSA883X_ANA_BOOST_BASE + 0x000F) |
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| 114 | #define WSA883X_GMAMP_SUP1 (WSA883X_ANA_BOOST_BASE + 0x0010) |
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| 115 | #define WSA883X_PWRSTAGE_CTRL3 (WSA883X_ANA_BOOST_BASE + 0x0011) |
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| 116 | #define WSA883X_PWRSTAGE_CTRL4 (WSA883X_ANA_BOOST_BASE + 0x0012) |
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| 117 | #define WSA883X_TEST1 (WSA883X_ANA_BOOST_BASE + 0x0013) |
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| 118 | #define WSA883X_SPARE1 (WSA883X_ANA_BOOST_BASE + 0x0014) |
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| 119 | #define WSA883X_SPARE2 (WSA883X_ANA_BOOST_BASE + 0x0015) |
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| 120 | |
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| 121 | #define WSA883X_ANA_PON_LDOL_BASE (WSA883X_BASE + 0x00000059) |
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| 122 | #define WSA883X_PON_CTL_0 (WSA883X_ANA_PON_LDOL_BASE + 0x0000) |
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| 123 | #define WSA883X_PON_CLT_1 (WSA883X_ANA_PON_LDOL_BASE + 0x0001) |
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| 124 | #define WSA883X_PON_CTL_2 (WSA883X_ANA_PON_LDOL_BASE + 0x0002) |
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| 125 | #define WSA883X_PON_CTL_3 (WSA883X_ANA_PON_LDOL_BASE + 0x0003) |
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| 126 | #define WSA883X_CKWD_CTL_0 (WSA883X_ANA_PON_LDOL_BASE + 0x0004) |
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| 127 | #define WSA883X_CKWD_CTL_1 (WSA883X_ANA_PON_LDOL_BASE + 0x0005) |
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| 128 | #define WSA883X_CKWD_CTL_2 (WSA883X_ANA_PON_LDOL_BASE + 0x0006) |
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| 129 | #define WSA883X_CKSK_CTL_0 (WSA883X_ANA_PON_LDOL_BASE + 0x0007) |
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| 130 | #define WSA883X_PADSW_CTL_0 (WSA883X_ANA_PON_LDOL_BASE + 0x0008) |
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| 131 | #define WSA883X_TEST_0 (WSA883X_ANA_PON_LDOL_BASE + 0x0009) |
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| 132 | #define WSA883X_TEST_1 (WSA883X_ANA_PON_LDOL_BASE + 0x000A) |
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| 133 | #define WSA883X_STATUS_0 (WSA883X_ANA_PON_LDOL_BASE + 0x000B) |
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| 134 | #define WSA883X_STATUS_1 (WSA883X_ANA_PON_LDOL_BASE + 0x000C) |
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| 135 | |
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| 136 | #define WSA883X_DIG_CTRL_BASE (WSA883X_BASE + 0x00000400) |
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| 137 | #define WSA883X_CHIP_ID0 (WSA883X_DIG_CTRL_BASE + 0x0001) |
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| 138 | #define WSA883X_CHIP_ID1 (WSA883X_DIG_CTRL_BASE + 0x0002) |
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| 139 | #define WSA883X_CHIP_ID2 (WSA883X_DIG_CTRL_BASE + 0x0003) |
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| 140 | #define WSA883X_CHIP_ID3 (WSA883X_DIG_CTRL_BASE + 0x0004) |
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| 141 | #define WSA883X_BUS_ID (WSA883X_DIG_CTRL_BASE + 0x0005) |
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| 142 | #define WSA883X_CDC_RST_CTL (WSA883X_DIG_CTRL_BASE + 0x0006) |
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| 143 | #define WSA883X_TOP_CLK_CFG (WSA883X_DIG_CTRL_BASE + 0x0007) |
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| 144 | #define WSA883X_CDC_PATH_MODE (WSA883X_DIG_CTRL_BASE + 0x0008) |
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| 145 | #define WSA883X_RXD_MODE_MASK BIT(1) |
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| 146 | #define WSA883X_RXD_MODE_NORMAL 0 |
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| 147 | #define WSA883X_RXD_MODE_HIFI 1 |
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| 148 | #define WSA883X_CDC_CLK_CTL (WSA883X_DIG_CTRL_BASE + 0x0009) |
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| 149 | #define WSA883X_SWR_RESET_EN (WSA883X_DIG_CTRL_BASE + 0x000A) |
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| 150 | #define WSA883X_RESET_CTL (WSA883X_DIG_CTRL_BASE + 0x000B) |
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| 151 | #define WSA883X_PA_FSM_CTL (WSA883X_DIG_CTRL_BASE + 0x0010) |
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| 152 | #define WSA883X_GLOBAL_PA_EN_MASK BIT(0) |
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| 153 | #define WSA883X_GLOBAL_PA_ENABLE 1 |
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| 154 | #define WSA883X_PA_FSM_TIMER0 (WSA883X_DIG_CTRL_BASE + 0x0011) |
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| 155 | #define WSA883X_PA_FSM_TIMER1 (WSA883X_DIG_CTRL_BASE + 0x0012) |
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| 156 | #define WSA883X_PA_FSM_STA (WSA883X_DIG_CTRL_BASE + 0x0013) |
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| 157 | #define WSA883X_PA_FSM_ERR_COND (WSA883X_DIG_CTRL_BASE + 0x0014) |
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| 158 | #define WSA883X_PA_FSM_MSK (WSA883X_DIG_CTRL_BASE + 0x0015) |
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| 159 | #define WSA883X_PA_FSM_BYP (WSA883X_DIG_CTRL_BASE + 0x0016) |
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| 160 | #define WSA883X_PA_FSM_DBG (WSA883X_DIG_CTRL_BASE + 0x0017) |
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| 161 | #define WSA883X_TADC_VALUE_CTL (WSA883X_DIG_CTRL_BASE + 0x0020) |
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| 162 | #define WSA883X_TEMP_DETECT_CTL (WSA883X_DIG_CTRL_BASE + 0x0021) |
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| 163 | #define WSA883X_TEMP_MSB (WSA883X_DIG_CTRL_BASE + 0x0022) |
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| 164 | #define WSA883X_TEMP_LSB (WSA883X_DIG_CTRL_BASE + 0x0023) |
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| 165 | #define WSA883X_TEMP_CONFIG0 (WSA883X_DIG_CTRL_BASE + 0x0024) |
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| 166 | #define WSA883X_TEMP_CONFIG1 (WSA883X_DIG_CTRL_BASE + 0x0025) |
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| 167 | #define WSA883X_VBAT_ADC_FLT_CTL (WSA883X_DIG_CTRL_BASE + 0x0026) |
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| 168 | #define WSA883X_VBAT_ADC_FLT_EN_MASK BIT(0) |
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| 169 | #define WSA883X_VBAT_ADC_COEF_SEL_MASK GENMASK(3, 1) |
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| 170 | #define WSA883X_VBAT_ADC_COEF_F_1DIV2 0x0 |
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| 171 | #define WSA883X_VBAT_ADC_COEF_F_1DIV16 0x3 |
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| 172 | #define WSA883X_VBAT_DIN_MSB (WSA883X_DIG_CTRL_BASE + 0x0027) |
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| 173 | #define WSA883X_VBAT_DIN_LSB (WSA883X_DIG_CTRL_BASE + 0x0028) |
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| 174 | #define WSA883X_VBAT_DOUT (WSA883X_DIG_CTRL_BASE + 0x0029) |
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| 175 | #define WSA883X_SDM_PDM9_LSB (WSA883X_DIG_CTRL_BASE + 0x002A) |
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| 176 | #define WSA883X_SDM_PDM9_MSB (WSA883X_DIG_CTRL_BASE + 0x002B) |
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| 177 | #define WSA883X_CDC_RX_CTL (WSA883X_DIG_CTRL_BASE + 0x0030) |
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| 178 | #define WSA883X_CDC_SPK_DSM_A1_0 (WSA883X_DIG_CTRL_BASE + 0x0031) |
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| 179 | #define WSA883X_CDC_SPK_DSM_A1_1 (WSA883X_DIG_CTRL_BASE + 0x0032) |
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| 180 | #define WSA883X_CDC_SPK_DSM_A2_0 (WSA883X_DIG_CTRL_BASE + 0x0033) |
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| 181 | #define WSA883X_CDC_SPK_DSM_A2_1 (WSA883X_DIG_CTRL_BASE + 0x0034) |
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| 182 | #define WSA883X_CDC_SPK_DSM_A3_0 (WSA883X_DIG_CTRL_BASE + 0x0035) |
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| 183 | #define WSA883X_CDC_SPK_DSM_A3_1 (WSA883X_DIG_CTRL_BASE + 0x0036) |
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| 184 | #define WSA883X_CDC_SPK_DSM_A4_0 (WSA883X_DIG_CTRL_BASE + 0x0037) |
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| 185 | #define WSA883X_CDC_SPK_DSM_A4_1 (WSA883X_DIG_CTRL_BASE + 0x0038) |
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| 186 | #define WSA883X_CDC_SPK_DSM_A5_0 (WSA883X_DIG_CTRL_BASE + 0x0039) |
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| 187 | #define WSA883X_CDC_SPK_DSM_A5_1 (WSA883X_DIG_CTRL_BASE + 0x003A) |
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| 188 | #define WSA883X_CDC_SPK_DSM_A6_0 (WSA883X_DIG_CTRL_BASE + 0x003B) |
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| 189 | #define WSA883X_CDC_SPK_DSM_A7_0 (WSA883X_DIG_CTRL_BASE + 0x003C) |
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| 190 | #define WSA883X_CDC_SPK_DSM_C_0 (WSA883X_DIG_CTRL_BASE + 0x003D) |
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| 191 | #define WSA883X_CDC_SPK_DSM_C_1 (WSA883X_DIG_CTRL_BASE + 0x003E) |
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| 192 | #define WSA883X_CDC_SPK_DSM_C_2 (WSA883X_DIG_CTRL_BASE + 0x003F) |
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| 193 | #define WSA883X_CDC_SPK_DSM_C_3 (WSA883X_DIG_CTRL_BASE + 0x0040) |
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| 194 | #define WSA883X_CDC_SPK_DSM_R1 (WSA883X_DIG_CTRL_BASE + 0x0041) |
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| 195 | #define WSA883X_CDC_SPK_DSM_R2 (WSA883X_DIG_CTRL_BASE + 0x0042) |
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| 196 | #define WSA883X_CDC_SPK_DSM_R3 (WSA883X_DIG_CTRL_BASE + 0x0043) |
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| 197 | #define WSA883X_CDC_SPK_DSM_R4 (WSA883X_DIG_CTRL_BASE + 0x0044) |
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| 198 | #define WSA883X_CDC_SPK_DSM_R5 (WSA883X_DIG_CTRL_BASE + 0x0045) |
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| 199 | #define WSA883X_CDC_SPK_DSM_R6 (WSA883X_DIG_CTRL_BASE + 0x0046) |
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| 200 | #define WSA883X_CDC_SPK_DSM_R7 (WSA883X_DIG_CTRL_BASE + 0x0047) |
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| 201 | #define WSA883X_CDC_SPK_GAIN_PDM_0 (WSA883X_DIG_CTRL_BASE + 0x0048) |
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| 202 | #define WSA883X_CDC_SPK_GAIN_PDM_1 (WSA883X_DIG_CTRL_BASE + 0x0049) |
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| 203 | #define WSA883X_CDC_SPK_GAIN_PDM_2 (WSA883X_DIG_CTRL_BASE + 0x004A) |
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| 204 | #define WSA883X_PDM_WD_CTL (WSA883X_DIG_CTRL_BASE + 0x004B) |
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| 205 | #define WSA883X_PDM_EN_MASK BIT(0) |
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| 206 | #define WSA883X_PDM_ENABLE BIT(0) |
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| 207 | #define WSA883X_DEM_BYPASS_DATA0 (WSA883X_DIG_CTRL_BASE + 0x004C) |
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| 208 | #define WSA883X_DEM_BYPASS_DATA1 (WSA883X_DIG_CTRL_BASE + 0x004D) |
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| 209 | #define WSA883X_DEM_BYPASS_DATA2 (WSA883X_DIG_CTRL_BASE + 0x004E) |
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| 210 | #define WSA883X_DEM_BYPASS_DATA3 (WSA883X_DIG_CTRL_BASE + 0x004F) |
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| 211 | #define WSA883X_WAVG_CTL (WSA883X_DIG_CTRL_BASE + 0x0050) |
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| 212 | #define WSA883X_WAVG_LRA_PER_0 (WSA883X_DIG_CTRL_BASE + 0x0051) |
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| 213 | #define WSA883X_WAVG_LRA_PER_1 (WSA883X_DIG_CTRL_BASE + 0x0052) |
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| 214 | #define WSA883X_WAVG_DELTA_THETA_0 (WSA883X_DIG_CTRL_BASE + 0x0053) |
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| 215 | #define WSA883X_WAVG_DELTA_THETA_1 (WSA883X_DIG_CTRL_BASE + 0x0054) |
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| 216 | #define WSA883X_WAVG_DIRECT_AMP_0 (WSA883X_DIG_CTRL_BASE + 0x0055) |
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| 217 | #define WSA883X_WAVG_DIRECT_AMP_1 (WSA883X_DIG_CTRL_BASE + 0x0056) |
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| 218 | #define WSA883X_WAVG_PTRN_AMP0_0 (WSA883X_DIG_CTRL_BASE + 0x0057) |
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| 219 | #define WSA883X_WAVG_PTRN_AMP0_1 (WSA883X_DIG_CTRL_BASE + 0x0058) |
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| 220 | #define WSA883X_WAVG_PTRN_AMP1_0 (WSA883X_DIG_CTRL_BASE + 0x0059) |
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| 221 | #define WSA883X_WAVG_PTRN_AMP1_1 (WSA883X_DIG_CTRL_BASE + 0x005A) |
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| 222 | #define WSA883X_WAVG_PTRN_AMP2_0 (WSA883X_DIG_CTRL_BASE + 0x005B) |
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| 223 | #define WSA883X_WAVG_PTRN_AMP2_1 (WSA883X_DIG_CTRL_BASE + 0x005C) |
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| 224 | #define WSA883X_WAVG_PTRN_AMP3_0 (WSA883X_DIG_CTRL_BASE + 0x005D) |
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| 225 | #define WSA883X_WAVG_PTRN_AMP3_1 (WSA883X_DIG_CTRL_BASE + 0x005E) |
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| 226 | #define WSA883X_WAVG_PTRN_AMP4_0 (WSA883X_DIG_CTRL_BASE + 0x005F) |
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| 227 | #define WSA883X_WAVG_PTRN_AMP4_1 (WSA883X_DIG_CTRL_BASE + 0x0060) |
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| 228 | #define WSA883X_WAVG_PTRN_AMP5_0 (WSA883X_DIG_CTRL_BASE + 0x0061) |
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| 229 | #define WSA883X_WAVG_PTRN_AMP5_1 (WSA883X_DIG_CTRL_BASE + 0x0062) |
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| 230 | #define WSA883X_WAVG_PTRN_AMP6_0 (WSA883X_DIG_CTRL_BASE + 0x0063) |
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| 231 | #define WSA883X_WAVG_PTRN_AMP6_1 (WSA883X_DIG_CTRL_BASE + 0x0064) |
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| 232 | #define WSA883X_WAVG_PTRN_AMP7_0 (WSA883X_DIG_CTRL_BASE + 0x0065) |
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| 233 | #define WSA883X_WAVG_PTRN_AMP7_1 (WSA883X_DIG_CTRL_BASE + 0x0066) |
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| 234 | #define WSA883X_WAVG_PER_0_1 (WSA883X_DIG_CTRL_BASE + 0x0067) |
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| 235 | #define WSA883X_WAVG_PER_2_3 (WSA883X_DIG_CTRL_BASE + 0x0068) |
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| 236 | #define WSA883X_WAVG_PER_4_5 (WSA883X_DIG_CTRL_BASE + 0x0069) |
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| 237 | #define WSA883X_WAVG_PER_6_7 (WSA883X_DIG_CTRL_BASE + 0x006A) |
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| 238 | #define WSA883X_WAVG_STA (WSA883X_DIG_CTRL_BASE + 0x006B) |
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| 239 | #define WSA883X_DRE_CTL_0 (WSA883X_DIG_CTRL_BASE + 0x006C) |
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| 240 | #define WSA883X_DRE_OFFSET_MASK GENMASK(2, 0) |
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| 241 | #define WSA883X_DRE_PROG_DELAY_MASK GENMASK(7, 4) |
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| 242 | #define WSA883X_DRE_CTL_1 (WSA883X_DIG_CTRL_BASE + 0x006D) |
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| 243 | #define WSA883X_DRE_GAIN_EN_MASK BIT(0) |
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| 244 | #define WSA883X_DRE_GAIN_FROM_CSR 1 |
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| 245 | #define WSA883X_DRE_IDLE_DET_CTL (WSA883X_DIG_CTRL_BASE + 0x006E) |
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| 246 | #define WSA883X_CLSH_CTL_0 (WSA883X_DIG_CTRL_BASE + 0x0070) |
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| 247 | #define WSA883X_CLSH_CTL_1 (WSA883X_DIG_CTRL_BASE + 0x0071) |
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| 248 | #define WSA883X_CLSH_V_HD_PA (WSA883X_DIG_CTRL_BASE + 0x0072) |
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| 249 | #define WSA883X_CLSH_V_PA_MIN (WSA883X_DIG_CTRL_BASE + 0x0073) |
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| 250 | #define WSA883X_CLSH_OVRD_VAL (WSA883X_DIG_CTRL_BASE + 0x0074) |
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| 251 | #define WSA883X_CLSH_HARD_MAX (WSA883X_DIG_CTRL_BASE + 0x0075) |
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| 252 | #define WSA883X_CLSH_SOFT_MAX (WSA883X_DIG_CTRL_BASE + 0x0076) |
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| 253 | #define WSA883X_CLSH_SIG_DP (WSA883X_DIG_CTRL_BASE + 0x0077) |
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| 254 | #define WSA883X_TAGC_CTL (WSA883X_DIG_CTRL_BASE + 0x0078) |
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| 255 | #define WSA883X_TAGC_TIME (WSA883X_DIG_CTRL_BASE + 0x0079) |
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| 256 | #define WSA883X_TAGC_E2E_GAIN (WSA883X_DIG_CTRL_BASE + 0x007A) |
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| 257 | #define WSA883X_TAGC_FORCE_VAL (WSA883X_DIG_CTRL_BASE + 0x007B) |
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| 258 | #define WSA883X_VAGC_CTL (WSA883X_DIG_CTRL_BASE + 0x007C) |
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| 259 | #define WSA883X_VAGC_TIME (WSA883X_DIG_CTRL_BASE + 0x007D) |
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| 260 | #define WSA883X_VAGC_ATTN_LVL_1_2 (WSA883X_DIG_CTRL_BASE + 0x007E) |
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| 261 | #define WSA883X_VAGC_ATTN_LVL_3 (WSA883X_DIG_CTRL_BASE + 0x007F) |
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| 262 | #define WSA883X_INTR_MODE (WSA883X_DIG_CTRL_BASE + 0x0080) |
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| 263 | #define WSA883X_INTR_MASK0 (WSA883X_DIG_CTRL_BASE + 0x0081) |
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| 264 | #define WSA883X_INTR_MASK1 (WSA883X_DIG_CTRL_BASE + 0x0082) |
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| 265 | #define WSA883X_INTR_STATUS0 (WSA883X_DIG_CTRL_BASE + 0x0083) |
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| 266 | #define WSA883X_INTR_STATUS1 (WSA883X_DIG_CTRL_BASE + 0x0084) |
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| 267 | #define WSA883X_INTR_CLEAR0 (WSA883X_DIG_CTRL_BASE + 0x0085) |
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| 268 | #define WSA883X_INTR_CLEAR1 (WSA883X_DIG_CTRL_BASE + 0x0086) |
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| 269 | #define WSA883X_INTR_LEVEL0 (WSA883X_DIG_CTRL_BASE + 0x0087) |
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| 270 | #define WSA883X_INTR_LEVEL1 (WSA883X_DIG_CTRL_BASE + 0x0088) |
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| 271 | #define WSA883X_INTR_SET0 (WSA883X_DIG_CTRL_BASE + 0x0089) |
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| 272 | #define WSA883X_INTR_SET1 (WSA883X_DIG_CTRL_BASE + 0x008A) |
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| 273 | #define WSA883X_INTR_TEST0 (WSA883X_DIG_CTRL_BASE + 0x008B) |
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| 274 | #define WSA883X_INTR_TEST1 (WSA883X_DIG_CTRL_BASE + 0x008C) |
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| 275 | #define WSA883X_OTP_CTRL0 (WSA883X_DIG_CTRL_BASE + 0x0090) |
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| 276 | #define WSA883X_OTP_CTRL1 (WSA883X_DIG_CTRL_BASE + 0x0091) |
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| 277 | #define WSA883X_HDRIVE_CTL_GROUP1 (WSA883X_DIG_CTRL_BASE + 0x0092) |
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| 278 | #define WSA883X_PIN_CTL (WSA883X_DIG_CTRL_BASE + 0x0093) |
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| 279 | #define WSA883X_PIN_CTL_OE (WSA883X_DIG_CTRL_BASE + 0x0094) |
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| 280 | #define WSA883X_PIN_WDATA_IOPAD (WSA883X_DIG_CTRL_BASE + 0x0095) |
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| 281 | #define WSA883X_PIN_STATUS (WSA883X_DIG_CTRL_BASE + 0x0096) |
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| 282 | #define WSA883X_I2C_SLAVE_CTL (WSA883X_DIG_CTRL_BASE + 0x0097) |
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| 283 | #define WSA883X_PDM_TEST_MODE (WSA883X_DIG_CTRL_BASE + 0x00A0) |
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| 284 | #define WSA883X_ATE_TEST_MODE (WSA883X_DIG_CTRL_BASE + 0x00A1) |
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| 285 | #define WSA883X_DIG_DEBUG_MODE (WSA883X_DIG_CTRL_BASE + 0x00A3) |
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| 286 | #define WSA883X_DIG_DEBUG_SEL (WSA883X_DIG_CTRL_BASE + 0x00A4) |
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| 287 | #define WSA883X_DIG_DEBUG_EN (WSA883X_DIG_CTRL_BASE + 0x00A5) |
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| 288 | #define WSA883X_SWR_HM_TEST0 (WSA883X_DIG_CTRL_BASE + 0x00A6) |
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| 289 | #define WSA883X_SWR_HM_TEST1 (WSA883X_DIG_CTRL_BASE + 0x00A7) |
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| 290 | #define WSA883X_SWR_PAD_CTL (WSA883X_DIG_CTRL_BASE + 0x00A8) |
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| 291 | #define WSA883X_TADC_DETECT_DBG_CTL (WSA883X_DIG_CTRL_BASE + 0x00A9) |
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| 292 | #define WSA883X_TADC_DEBUG_MSB (WSA883X_DIG_CTRL_BASE + 0x00AA) |
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| 293 | #define WSA883X_TADC_DEBUG_LSB (WSA883X_DIG_CTRL_BASE + 0x00AB) |
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| 294 | #define WSA883X_SAMPLE_EDGE_SEL (WSA883X_DIG_CTRL_BASE + 0x00AC) |
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| 295 | #define WSA883X_SWR_EDGE_SEL (WSA883X_DIG_CTRL_BASE + 0x00AD) |
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| 296 | #define WSA883X_TEST_MODE_CTL (WSA883X_DIG_CTRL_BASE + 0x00AE) |
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| 297 | #define WSA883X_IOPAD_CTL (WSA883X_DIG_CTRL_BASE + 0x00AF) |
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| 298 | #define WSA883X_ANA_CSR_DBG_ADD (WSA883X_DIG_CTRL_BASE + 0x00B0) |
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| 299 | #define WSA883X_ANA_CSR_DBG_CTL (WSA883X_DIG_CTRL_BASE + 0x00B1) |
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| 300 | #define WSA883X_SPARE_R (WSA883X_DIG_CTRL_BASE + 0x00BC) |
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| 301 | #define WSA883X_SPARE_0 (WSA883X_DIG_CTRL_BASE + 0x00BD) |
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| 302 | #define WSA883X_SPARE_1 (WSA883X_DIG_CTRL_BASE + 0x00BE) |
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| 303 | #define WSA883X_SPARE_2 (WSA883X_DIG_CTRL_BASE + 0x00BF) |
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| 304 | #define WSA883X_SCODE (WSA883X_DIG_CTRL_BASE + 0x00C0) |
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| 305 | |
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| 306 | #define WSA883X_DIG_TRIM_BASE (WSA883X_BASE + 0x00000500) |
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| 307 | #define WSA883X_OTP_REG_0 (WSA883X_DIG_TRIM_BASE + 0x0080) |
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| 308 | #define WSA883X_ID_MASK GENMASK(3, 0) |
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| 309 | #define WSA883X_OTP_REG_1 (WSA883X_DIG_TRIM_BASE + 0x0081) |
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| 310 | #define WSA883X_OTP_REG_2 (WSA883X_DIG_TRIM_BASE + 0x0082) |
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| 311 | #define WSA883X_OTP_REG_3 (WSA883X_DIG_TRIM_BASE + 0x0083) |
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| 312 | #define WSA883X_OTP_REG_4 (WSA883X_DIG_TRIM_BASE + 0x0084) |
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| 313 | #define WSA883X_OTP_REG_5 (WSA883X_DIG_TRIM_BASE + 0x0085) |
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| 314 | #define WSA883X_OTP_REG_6 (WSA883X_DIG_TRIM_BASE + 0x0086) |
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| 315 | #define WSA883X_OTP_REG_7 (WSA883X_DIG_TRIM_BASE + 0x0087) |
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| 316 | #define WSA883X_OTP_REG_8 (WSA883X_DIG_TRIM_BASE + 0x0088) |
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| 317 | #define WSA883X_OTP_REG_9 (WSA883X_DIG_TRIM_BASE + 0x0089) |
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| 318 | #define WSA883X_OTP_REG_10 (WSA883X_DIG_TRIM_BASE + 0x008A) |
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| 319 | #define WSA883X_OTP_REG_11 (WSA883X_DIG_TRIM_BASE + 0x008B) |
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| 320 | #define WSA883X_OTP_REG_12 (WSA883X_DIG_TRIM_BASE + 0x008C) |
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| 321 | #define WSA883X_OTP_REG_13 (WSA883X_DIG_TRIM_BASE + 0x008D) |
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| 322 | #define WSA883X_OTP_REG_14 (WSA883X_DIG_TRIM_BASE + 0x008E) |
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| 323 | #define WSA883X_OTP_REG_15 (WSA883X_DIG_TRIM_BASE + 0x008F) |
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| 324 | #define WSA883X_OTP_REG_16 (WSA883X_DIG_TRIM_BASE + 0x0090) |
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| 325 | #define WSA883X_OTP_REG_17 (WSA883X_DIG_TRIM_BASE + 0x0091) |
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| 326 | #define WSA883X_OTP_REG_18 (WSA883X_DIG_TRIM_BASE + 0x0092) |
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| 327 | #define WSA883X_OTP_REG_19 (WSA883X_DIG_TRIM_BASE + 0x0093) |
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| 328 | #define WSA883X_OTP_REG_20 (WSA883X_DIG_TRIM_BASE + 0x0094) |
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| 329 | #define WSA883X_OTP_REG_21 (WSA883X_DIG_TRIM_BASE + 0x0095) |
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| 330 | #define WSA883X_OTP_REG_22 (WSA883X_DIG_TRIM_BASE + 0x0096) |
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| 331 | #define WSA883X_OTP_REG_23 (WSA883X_DIG_TRIM_BASE + 0x0097) |
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| 332 | #define WSA883X_OTP_REG_24 (WSA883X_DIG_TRIM_BASE + 0x0098) |
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| 333 | #define WSA883X_OTP_REG_25 (WSA883X_DIG_TRIM_BASE + 0x0099) |
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| 334 | #define WSA883X_OTP_REG_26 (WSA883X_DIG_TRIM_BASE + 0x009A) |
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| 335 | #define WSA883X_OTP_REG_27 (WSA883X_DIG_TRIM_BASE + 0x009B) |
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| 336 | #define WSA883X_OTP_REG_28 (WSA883X_DIG_TRIM_BASE + 0x009C) |
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| 337 | #define WSA883X_OTP_REG_29 (WSA883X_DIG_TRIM_BASE + 0x009D) |
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| 338 | #define WSA883X_OTP_REG_30 (WSA883X_DIG_TRIM_BASE + 0x009E) |
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| 339 | #define WSA883X_OTP_REG_31 (WSA883X_DIG_TRIM_BASE + 0x009F) |
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| 340 | #define WSA883X_OTP_REG_32 (WSA883X_DIG_TRIM_BASE + 0x00A0) |
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| 341 | #define WSA883X_OTP_REG_33 (WSA883X_DIG_TRIM_BASE + 0x00A1) |
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| 342 | #define WSA883X_OTP_REG_34 (WSA883X_DIG_TRIM_BASE + 0x00A2) |
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| 343 | #define WSA883X_OTP_REG_35 (WSA883X_DIG_TRIM_BASE + 0x00A3) |
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| 344 | #define WSA883X_OTP_REG_63 (WSA883X_DIG_TRIM_BASE + 0x00BF) |
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| 345 | |
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| 346 | #define WSA883X_DIG_EMEM_BASE (WSA883X_BASE + 0x000005C0) |
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| 347 | #define WSA883X_EMEM_0 (WSA883X_DIG_EMEM_BASE + 0x0000) |
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| 348 | #define WSA883X_EMEM_1 (WSA883X_DIG_EMEM_BASE + 0x0001) |
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| 349 | #define WSA883X_EMEM_2 (WSA883X_DIG_EMEM_BASE + 0x0002) |
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| 350 | #define WSA883X_EMEM_3 (WSA883X_DIG_EMEM_BASE + 0x0003) |
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| 351 | #define WSA883X_EMEM_4 (WSA883X_DIG_EMEM_BASE + 0x0004) |
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| 352 | #define WSA883X_EMEM_5 (WSA883X_DIG_EMEM_BASE + 0x0005) |
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| 353 | #define WSA883X_EMEM_6 (WSA883X_DIG_EMEM_BASE + 0x0006) |
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| 354 | #define WSA883X_EMEM_7 (WSA883X_DIG_EMEM_BASE + 0x0007) |
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| 355 | #define WSA883X_EMEM_8 (WSA883X_DIG_EMEM_BASE + 0x0008) |
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| 356 | #define WSA883X_EMEM_9 (WSA883X_DIG_EMEM_BASE + 0x0009) |
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| 357 | #define WSA883X_EMEM_10 (WSA883X_DIG_EMEM_BASE + 0x000A) |
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| 358 | #define WSA883X_EMEM_11 (WSA883X_DIG_EMEM_BASE + 0x000B) |
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| 359 | #define WSA883X_EMEM_12 (WSA883X_DIG_EMEM_BASE + 0x000C) |
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| 360 | #define WSA883X_EMEM_13 (WSA883X_DIG_EMEM_BASE + 0x000D) |
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| 361 | #define WSA883X_EMEM_14 (WSA883X_DIG_EMEM_BASE + 0x000E) |
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| 362 | #define WSA883X_EMEM_15 (WSA883X_DIG_EMEM_BASE + 0x000F) |
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| 363 | #define WSA883X_EMEM_16 (WSA883X_DIG_EMEM_BASE + 0x0010) |
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| 364 | #define WSA883X_EMEM_17 (WSA883X_DIG_EMEM_BASE + 0x0011) |
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| 365 | #define WSA883X_EMEM_18 (WSA883X_DIG_EMEM_BASE + 0x0012) |
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| 366 | #define WSA883X_EMEM_19 (WSA883X_DIG_EMEM_BASE + 0x0013) |
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| 367 | #define WSA883X_EMEM_20 (WSA883X_DIG_EMEM_BASE + 0x0014) |
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| 368 | #define WSA883X_EMEM_21 (WSA883X_DIG_EMEM_BASE + 0x0015) |
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| 369 | #define WSA883X_EMEM_22 (WSA883X_DIG_EMEM_BASE + 0x0016) |
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| 370 | #define WSA883X_EMEM_23 (WSA883X_DIG_EMEM_BASE + 0x0017) |
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| 371 | #define WSA883X_EMEM_24 (WSA883X_DIG_EMEM_BASE + 0x0018) |
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| 372 | #define WSA883X_EMEM_25 (WSA883X_DIG_EMEM_BASE + 0x0019) |
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| 373 | #define WSA883X_EMEM_26 (WSA883X_DIG_EMEM_BASE + 0x001A) |
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| 374 | #define WSA883X_EMEM_27 (WSA883X_DIG_EMEM_BASE + 0x001B) |
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| 375 | #define WSA883X_EMEM_28 (WSA883X_DIG_EMEM_BASE + 0x001C) |
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| 376 | #define WSA883X_EMEM_29 (WSA883X_DIG_EMEM_BASE + 0x001D) |
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| 377 | #define WSA883X_EMEM_30 (WSA883X_DIG_EMEM_BASE + 0x001E) |
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| 378 | #define WSA883X_EMEM_31 (WSA883X_DIG_EMEM_BASE + 0x001F) |
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| 379 | #define WSA883X_EMEM_32 (WSA883X_DIG_EMEM_BASE + 0x0020) |
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| 380 | #define WSA883X_EMEM_33 (WSA883X_DIG_EMEM_BASE + 0x0021) |
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| 381 | #define WSA883X_EMEM_34 (WSA883X_DIG_EMEM_BASE + 0x0022) |
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| 382 | #define WSA883X_EMEM_35 (WSA883X_DIG_EMEM_BASE + 0x0023) |
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| 383 | #define WSA883X_EMEM_36 (WSA883X_DIG_EMEM_BASE + 0x0024) |
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| 384 | #define WSA883X_EMEM_37 (WSA883X_DIG_EMEM_BASE + 0x0025) |
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| 385 | #define WSA883X_EMEM_38 (WSA883X_DIG_EMEM_BASE + 0x0026) |
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| 386 | #define WSA883X_EMEM_39 (WSA883X_DIG_EMEM_BASE + 0x0027) |
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| 387 | #define WSA883X_EMEM_40 (WSA883X_DIG_EMEM_BASE + 0x0028) |
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| 388 | #define WSA883X_EMEM_41 (WSA883X_DIG_EMEM_BASE + 0x0029) |
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| 389 | #define WSA883X_EMEM_42 (WSA883X_DIG_EMEM_BASE + 0x002A) |
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| 390 | #define WSA883X_EMEM_43 (WSA883X_DIG_EMEM_BASE + 0x002B) |
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| 391 | #define WSA883X_EMEM_44 (WSA883X_DIG_EMEM_BASE + 0x002C) |
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| 392 | #define WSA883X_EMEM_45 (WSA883X_DIG_EMEM_BASE + 0x002D) |
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| 393 | #define WSA883X_EMEM_46 (WSA883X_DIG_EMEM_BASE + 0x002E) |
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| 394 | #define WSA883X_EMEM_47 (WSA883X_DIG_EMEM_BASE + 0x002F) |
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| 395 | #define WSA883X_EMEM_48 (WSA883X_DIG_EMEM_BASE + 0x0030) |
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| 396 | #define WSA883X_EMEM_49 (WSA883X_DIG_EMEM_BASE + 0x0031) |
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| 397 | #define WSA883X_EMEM_50 (WSA883X_DIG_EMEM_BASE + 0x0032) |
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| 398 | #define WSA883X_EMEM_51 (WSA883X_DIG_EMEM_BASE + 0x0033) |
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| 399 | #define WSA883X_EMEM_52 (WSA883X_DIG_EMEM_BASE + 0x0034) |
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| 400 | #define WSA883X_EMEM_53 (WSA883X_DIG_EMEM_BASE + 0x0035) |
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| 401 | #define WSA883X_EMEM_54 (WSA883X_DIG_EMEM_BASE + 0x0036) |
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| 402 | #define WSA883X_EMEM_55 (WSA883X_DIG_EMEM_BASE + 0x0037) |
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| 403 | #define WSA883X_EMEM_56 (WSA883X_DIG_EMEM_BASE + 0x0038) |
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| 404 | #define WSA883X_EMEM_57 (WSA883X_DIG_EMEM_BASE + 0x0039) |
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| 405 | #define WSA883X_EMEM_58 (WSA883X_DIG_EMEM_BASE + 0x003A) |
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| 406 | #define WSA883X_EMEM_59 (WSA883X_DIG_EMEM_BASE + 0x003B) |
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| 407 | #define WSA883X_EMEM_60 (WSA883X_DIG_EMEM_BASE + 0x003C) |
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| 408 | #define WSA883X_EMEM_61 (WSA883X_DIG_EMEM_BASE + 0x003D) |
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| 409 | #define WSA883X_EMEM_62 (WSA883X_DIG_EMEM_BASE + 0x003E) |
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| 410 | #define WSA883X_EMEM_63 (WSA883X_DIG_EMEM_BASE + 0x003F) |
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| 411 | |
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| 412 | #define WSA883X_NUM_REGISTERS (WSA883X_EMEM_63 + 1) |
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| 413 | #define WSA883X_MAX_REGISTER (WSA883X_NUM_REGISTERS - 1) |
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| 414 | |
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| 415 | #define WSA883X_VERSION_1_0 0 |
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| 416 | #define WSA883X_VERSION_1_1 1 |
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| 417 | |
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| 418 | #define WSA883X_MAX_SWR_PORTS 4 |
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| 419 | #define WSA883X_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |\ |
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| 420 | SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_48000 |\ |
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| 421 | SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_192000 |\ |
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| 422 | SNDRV_PCM_RATE_384000) |
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| 423 | /* Fractional Rates */ |
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| 424 | #define WSA883X_FRAC_RATES (SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_88200 |\ |
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| 425 | SNDRV_PCM_RATE_176400 | SNDRV_PCM_RATE_352800) |
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| 426 | |
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| 427 | #define WSA883X_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\ |
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| 428 | SNDRV_PCM_FMTBIT_S24_LE |\ |
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| 429 | SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S32_LE) |
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| 430 | |
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| 431 | struct wsa883x_priv { |
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| 432 | struct regmap *regmap; |
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| 433 | struct device *dev; |
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| 434 | struct regulator *vdd; |
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| 435 | struct sdw_slave *slave; |
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| 436 | struct sdw_stream_config sconfig; |
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| 437 | struct sdw_stream_runtime *sruntime; |
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| 438 | struct sdw_port_config port_config[WSA883X_MAX_SWR_PORTS]; |
|---|
| 439 | struct gpio_desc *sd_n; |
|---|
| 440 | bool port_prepared[WSA883X_MAX_SWR_PORTS]; |
|---|
| 441 | bool port_enable[WSA883X_MAX_SWR_PORTS]; |
|---|
| 442 | int version; |
|---|
| 443 | int variant; |
|---|
| 444 | int active_ports; |
|---|
| 445 | int dev_mode; |
|---|
| 446 | int comp_offset; |
|---|
| 447 | }; |
|---|
| 448 | |
|---|
| 449 | enum { |
|---|
| 450 | WSA8830 = 0, |
|---|
| 451 | WSA8835, |
|---|
| 452 | WSA8832, |
|---|
| 453 | WSA8835_V2 = 5, |
|---|
| 454 | }; |
|---|
| 455 | |
|---|
| 456 | enum { |
|---|
| 457 | COMP_OFFSET0, |
|---|
| 458 | COMP_OFFSET1, |
|---|
| 459 | COMP_OFFSET2, |
|---|
| 460 | COMP_OFFSET3, |
|---|
| 461 | COMP_OFFSET4, |
|---|
| 462 | }; |
|---|
| 463 | |
|---|
| 464 | enum wsa_port_ids { |
|---|
| 465 | WSA883X_PORT_DAC, |
|---|
| 466 | WSA883X_PORT_COMP, |
|---|
| 467 | WSA883X_PORT_BOOST, |
|---|
| 468 | WSA883X_PORT_VISENSE, |
|---|
| 469 | }; |
|---|
| 470 | |
|---|
| 471 | static const char * const wsa_dev_mode_text[] = { |
|---|
| 472 | "Speaker" , "Receiver" , "Ultrasound" |
|---|
| 473 | }; |
|---|
| 474 | |
|---|
| 475 | enum { |
|---|
| 476 | SPEAKER, |
|---|
| 477 | RECEIVER, |
|---|
| 478 | ULTRASOUND, |
|---|
| 479 | }; |
|---|
| 480 | |
|---|
| 481 | static const struct soc_enum wsa_dev_mode_enum = |
|---|
| 482 | SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(wsa_dev_mode_text), wsa_dev_mode_text); |
|---|
| 483 | |
|---|
| 484 | /* 4 ports */ |
|---|
| 485 | static struct sdw_dpn_prop wsa_sink_dpn_prop[WSA883X_MAX_SWR_PORTS] = { |
|---|
| 486 | { |
|---|
| 487 | /* DAC */ |
|---|
| 488 | .num = 1, |
|---|
| 489 | .type = SDW_DPN_SIMPLE, |
|---|
| 490 | .min_ch = 1, |
|---|
| 491 | .max_ch = 1, |
|---|
| 492 | .simple_ch_prep_sm = true, |
|---|
| 493 | .read_only_wordlength = true, |
|---|
| 494 | }, { |
|---|
| 495 | /* COMP */ |
|---|
| 496 | .num = 2, |
|---|
| 497 | .type = SDW_DPN_SIMPLE, |
|---|
| 498 | .min_ch = 1, |
|---|
| 499 | .max_ch = 1, |
|---|
| 500 | .simple_ch_prep_sm = true, |
|---|
| 501 | .read_only_wordlength = true, |
|---|
| 502 | }, { |
|---|
| 503 | /* BOOST */ |
|---|
| 504 | .num = 3, |
|---|
| 505 | .type = SDW_DPN_SIMPLE, |
|---|
| 506 | .min_ch = 1, |
|---|
| 507 | .max_ch = 1, |
|---|
| 508 | .simple_ch_prep_sm = true, |
|---|
| 509 | .read_only_wordlength = true, |
|---|
| 510 | }, { |
|---|
| 511 | /* VISENSE */ |
|---|
| 512 | .num = 4, |
|---|
| 513 | .type = SDW_DPN_SIMPLE, |
|---|
| 514 | .min_ch = 1, |
|---|
| 515 | .max_ch = 1, |
|---|
| 516 | .simple_ch_prep_sm = true, |
|---|
| 517 | .read_only_wordlength = true, |
|---|
| 518 | } |
|---|
| 519 | }; |
|---|
| 520 | |
|---|
| 521 | static const struct sdw_port_config wsa883x_pconfig[WSA883X_MAX_SWR_PORTS] = { |
|---|
| 522 | { |
|---|
| 523 | .num = 1, |
|---|
| 524 | .ch_mask = 0x1, |
|---|
| 525 | }, { |
|---|
| 526 | .num = 2, |
|---|
| 527 | .ch_mask = 0xf, |
|---|
| 528 | }, { |
|---|
| 529 | .num = 3, |
|---|
| 530 | .ch_mask = 0x3, |
|---|
| 531 | }, { /* IV feedback */ |
|---|
| 532 | .num = 4, |
|---|
| 533 | .ch_mask = 0x3, |
|---|
| 534 | }, |
|---|
| 535 | }; |
|---|
| 536 | |
|---|
| 537 | static struct reg_default wsa883x_defaults[] = { |
|---|
| 538 | { WSA883X_REF_CTRL, 0xD5 }, |
|---|
| 539 | { WSA883X_TEST_CTL_0, 0x06 }, |
|---|
| 540 | { WSA883X_BIAS_0, 0xD2 }, |
|---|
| 541 | { WSA883X_OP_CTL, 0xE0 }, |
|---|
| 542 | { WSA883X_IREF_CTL, 0x57 }, |
|---|
| 543 | { WSA883X_ISENS_CTL, 0x47 }, |
|---|
| 544 | { WSA883X_CLK_CTL, 0x87 }, |
|---|
| 545 | { WSA883X_TEST_CTL_1, 0x00 }, |
|---|
| 546 | { WSA883X_BIAS_1, 0x51 }, |
|---|
| 547 | { WSA883X_ADC_CTL, 0x01 }, |
|---|
| 548 | { WSA883X_DOUT_MSB, 0x00 }, |
|---|
| 549 | { WSA883X_DOUT_LSB, 0x00 }, |
|---|
| 550 | { WSA883X_VBAT_SNS, 0x40 }, |
|---|
| 551 | { WSA883X_ITRIM_CODE, 0x9F }, |
|---|
| 552 | { WSA883X_EN, 0x20 }, |
|---|
| 553 | { WSA883X_OVERRIDE1, 0x00 }, |
|---|
| 554 | { WSA883X_OVERRIDE2, 0x08 }, |
|---|
| 555 | { WSA883X_VSENSE1, 0xD3 }, |
|---|
| 556 | { WSA883X_ISENSE1, 0xD4 }, |
|---|
| 557 | { WSA883X_ISENSE2, 0x20 }, |
|---|
| 558 | { WSA883X_ISENSE_CAL, 0x00 }, |
|---|
| 559 | { WSA883X_MISC, 0x08 }, |
|---|
| 560 | { WSA883X_ADC_0, 0x00 }, |
|---|
| 561 | { WSA883X_ADC_1, 0x00 }, |
|---|
| 562 | { WSA883X_ADC_2, 0x40 }, |
|---|
| 563 | { WSA883X_ADC_3, 0x80 }, |
|---|
| 564 | { WSA883X_ADC_4, 0x25 }, |
|---|
| 565 | { WSA883X_ADC_5, 0x25 }, |
|---|
| 566 | { WSA883X_ADC_6, 0x08 }, |
|---|
| 567 | { WSA883X_ADC_7, 0x81 }, |
|---|
| 568 | { WSA883X_STATUS, 0x00 }, |
|---|
| 569 | { WSA883X_DAC_CTRL_REG, 0x53 }, |
|---|
| 570 | { WSA883X_DAC_EN_DEBUG_REG, 0x00 }, |
|---|
| 571 | { WSA883X_DAC_OPAMP_BIAS1_REG, 0x48 }, |
|---|
| 572 | { WSA883X_DAC_OPAMP_BIAS2_REG, 0x48 }, |
|---|
| 573 | { WSA883X_DAC_VCM_CTRL_REG, 0x88 }, |
|---|
| 574 | { WSA883X_DAC_VOLTAGE_CTRL_REG, 0xA5 }, |
|---|
| 575 | { WSA883X_ATEST1_REG, 0x00 }, |
|---|
| 576 | { WSA883X_ATEST2_REG, 0x00 }, |
|---|
| 577 | { WSA883X_SPKR_TOP_BIAS_REG1, 0x6A }, |
|---|
| 578 | { WSA883X_SPKR_TOP_BIAS_REG2, 0x65 }, |
|---|
| 579 | { WSA883X_SPKR_TOP_BIAS_REG3, 0x55 }, |
|---|
| 580 | { WSA883X_SPKR_TOP_BIAS_REG4, 0xA9 }, |
|---|
| 581 | { WSA883X_SPKR_CLIP_DET_REG, 0x9C }, |
|---|
| 582 | { WSA883X_SPKR_DRV_LF_BLK_EN, 0x0F }, |
|---|
| 583 | { WSA883X_SPKR_DRV_LF_EN, 0x0A }, |
|---|
| 584 | { WSA883X_SPKR_DRV_LF_MASK_DCC_CTL, 0x00 }, |
|---|
| 585 | { WSA883X_SPKR_DRV_LF_MISC_CTL, 0x3A }, |
|---|
| 586 | { WSA883X_SPKR_DRV_LF_REG_GAIN, 0x00 }, |
|---|
| 587 | { WSA883X_SPKR_DRV_OS_CAL_CTL, 0x00 }, |
|---|
| 588 | { WSA883X_SPKR_DRV_OS_CAL_CTL1, 0x90 }, |
|---|
| 589 | { WSA883X_SPKR_PWM_CLK_CTL, 0x00 }, |
|---|
| 590 | { WSA883X_SPKR_PDRV_HS_CTL, 0x52 }, |
|---|
| 591 | { WSA883X_SPKR_PDRV_LS_CTL, 0x48 }, |
|---|
| 592 | { WSA883X_SPKR_PWRSTG_DBG, 0x08 }, |
|---|
| 593 | { WSA883X_SPKR_OCP_CTL, 0xE2 }, |
|---|
| 594 | { WSA883X_SPKR_BBM_CTL, 0x92 }, |
|---|
| 595 | { WSA883X_PA_STATUS0, 0x00 }, |
|---|
| 596 | { WSA883X_PA_STATUS1, 0x00 }, |
|---|
| 597 | { WSA883X_PA_STATUS2, 0x80 }, |
|---|
| 598 | { WSA883X_EN_CTRL, 0x44 }, |
|---|
| 599 | { WSA883X_CURRENT_LIMIT, 0xCC }, |
|---|
| 600 | { WSA883X_IBIAS1, 0x00 }, |
|---|
| 601 | { WSA883X_IBIAS2, 0x00 }, |
|---|
| 602 | { WSA883X_IBIAS3, 0x00 }, |
|---|
| 603 | { WSA883X_LDO_PROG, 0x02 }, |
|---|
| 604 | { WSA883X_STABILITY_CTRL1, 0x8E }, |
|---|
| 605 | { WSA883X_STABILITY_CTRL2, 0x10 }, |
|---|
| 606 | { WSA883X_PWRSTAGE_CTRL1, 0x06 }, |
|---|
| 607 | { WSA883X_PWRSTAGE_CTRL2, 0x00 }, |
|---|
| 608 | { WSA883X_BYPASS_1, 0x19 }, |
|---|
| 609 | { WSA883X_BYPASS_2, 0x13 }, |
|---|
| 610 | { WSA883X_ZX_CTRL_1, 0xF0 }, |
|---|
| 611 | { WSA883X_ZX_CTRL_2, 0x04 }, |
|---|
| 612 | { WSA883X_MISC1, 0x06 }, |
|---|
| 613 | { WSA883X_MISC2, 0xA0 }, |
|---|
| 614 | { WSA883X_GMAMP_SUP1, 0x82 }, |
|---|
| 615 | { WSA883X_PWRSTAGE_CTRL3, 0x39 }, |
|---|
| 616 | { WSA883X_PWRSTAGE_CTRL4, 0x5F }, |
|---|
| 617 | { WSA883X_TEST1, 0x00 }, |
|---|
| 618 | { WSA883X_SPARE1, 0x00 }, |
|---|
| 619 | { WSA883X_SPARE2, 0x00 }, |
|---|
| 620 | { WSA883X_PON_CTL_0, 0x10 }, |
|---|
| 621 | { WSA883X_PON_CLT_1, 0xE0 }, |
|---|
| 622 | { WSA883X_PON_CTL_2, 0x90 }, |
|---|
| 623 | { WSA883X_PON_CTL_3, 0x70 }, |
|---|
| 624 | { WSA883X_CKWD_CTL_0, 0x34 }, |
|---|
| 625 | { WSA883X_CKWD_CTL_1, 0x0F }, |
|---|
| 626 | { WSA883X_CKWD_CTL_2, 0x00 }, |
|---|
| 627 | { WSA883X_CKSK_CTL_0, 0x00 }, |
|---|
| 628 | { WSA883X_PADSW_CTL_0, 0x00 }, |
|---|
| 629 | { WSA883X_TEST_0, 0x00 }, |
|---|
| 630 | { WSA883X_TEST_1, 0x00 }, |
|---|
| 631 | { WSA883X_STATUS_0, 0x00 }, |
|---|
| 632 | { WSA883X_STATUS_1, 0x00 }, |
|---|
| 633 | { WSA883X_CHIP_ID0, 0x00 }, |
|---|
| 634 | { WSA883X_CHIP_ID1, 0x00 }, |
|---|
| 635 | { WSA883X_CHIP_ID2, 0x02 }, |
|---|
| 636 | { WSA883X_CHIP_ID3, 0x02 }, |
|---|
| 637 | { WSA883X_BUS_ID, 0x00 }, |
|---|
| 638 | { WSA883X_CDC_RST_CTL, 0x01 }, |
|---|
| 639 | { WSA883X_TOP_CLK_CFG, 0x00 }, |
|---|
| 640 | { WSA883X_CDC_PATH_MODE, 0x00 }, |
|---|
| 641 | { WSA883X_CDC_CLK_CTL, 0xFF }, |
|---|
| 642 | { WSA883X_SWR_RESET_EN, 0x00 }, |
|---|
| 643 | { WSA883X_RESET_CTL, 0x00 }, |
|---|
| 644 | { WSA883X_PA_FSM_CTL, 0x00 }, |
|---|
| 645 | { WSA883X_PA_FSM_TIMER0, 0x80 }, |
|---|
| 646 | { WSA883X_PA_FSM_TIMER1, 0x80 }, |
|---|
| 647 | { WSA883X_PA_FSM_STA, 0x00 }, |
|---|
| 648 | { WSA883X_PA_FSM_ERR_COND, 0x00 }, |
|---|
| 649 | { WSA883X_PA_FSM_MSK, 0x00 }, |
|---|
| 650 | { WSA883X_PA_FSM_BYP, 0x01 }, |
|---|
| 651 | { WSA883X_PA_FSM_DBG, 0x00 }, |
|---|
| 652 | { WSA883X_TADC_VALUE_CTL, 0x03 }, |
|---|
| 653 | { WSA883X_TEMP_DETECT_CTL, 0x01 }, |
|---|
| 654 | { WSA883X_TEMP_MSB, 0x00 }, |
|---|
| 655 | { WSA883X_TEMP_LSB, 0x00 }, |
|---|
| 656 | { WSA883X_TEMP_CONFIG0, 0x00 }, |
|---|
| 657 | { WSA883X_TEMP_CONFIG1, 0x00 }, |
|---|
| 658 | { WSA883X_VBAT_ADC_FLT_CTL, 0x00 }, |
|---|
| 659 | { WSA883X_VBAT_DIN_MSB, 0x00 }, |
|---|
| 660 | { WSA883X_VBAT_DIN_LSB, 0x00 }, |
|---|
| 661 | { WSA883X_VBAT_DOUT, 0x00 }, |
|---|
| 662 | { WSA883X_SDM_PDM9_LSB, 0x00 }, |
|---|
| 663 | { WSA883X_SDM_PDM9_MSB, 0x00 }, |
|---|
| 664 | { WSA883X_CDC_RX_CTL, 0xFE }, |
|---|
| 665 | { WSA883X_CDC_SPK_DSM_A1_0, 0x00 }, |
|---|
| 666 | { WSA883X_CDC_SPK_DSM_A1_1, 0x01 }, |
|---|
| 667 | { WSA883X_CDC_SPK_DSM_A2_0, 0x96 }, |
|---|
| 668 | { WSA883X_CDC_SPK_DSM_A2_1, 0x09 }, |
|---|
| 669 | { WSA883X_CDC_SPK_DSM_A3_0, 0xAB }, |
|---|
| 670 | { WSA883X_CDC_SPK_DSM_A3_1, 0x05 }, |
|---|
| 671 | { WSA883X_CDC_SPK_DSM_A4_0, 0x1C }, |
|---|
| 672 | { WSA883X_CDC_SPK_DSM_A4_1, 0x02 }, |
|---|
| 673 | { WSA883X_CDC_SPK_DSM_A5_0, 0x17 }, |
|---|
| 674 | { WSA883X_CDC_SPK_DSM_A5_1, 0x02 }, |
|---|
| 675 | { WSA883X_CDC_SPK_DSM_A6_0, 0xAA }, |
|---|
| 676 | { WSA883X_CDC_SPK_DSM_A7_0, 0xE3 }, |
|---|
| 677 | { WSA883X_CDC_SPK_DSM_C_0, 0x69 }, |
|---|
| 678 | { WSA883X_CDC_SPK_DSM_C_1, 0x54 }, |
|---|
| 679 | { WSA883X_CDC_SPK_DSM_C_2, 0x02 }, |
|---|
| 680 | { WSA883X_CDC_SPK_DSM_C_3, 0x15 }, |
|---|
| 681 | { WSA883X_CDC_SPK_DSM_R1, 0xA4 }, |
|---|
| 682 | { WSA883X_CDC_SPK_DSM_R2, 0xB5 }, |
|---|
| 683 | { WSA883X_CDC_SPK_DSM_R3, 0x86 }, |
|---|
| 684 | { WSA883X_CDC_SPK_DSM_R4, 0x85 }, |
|---|
| 685 | { WSA883X_CDC_SPK_DSM_R5, 0xAA }, |
|---|
| 686 | { WSA883X_CDC_SPK_DSM_R6, 0xE2 }, |
|---|
| 687 | { WSA883X_CDC_SPK_DSM_R7, 0x62 }, |
|---|
| 688 | { WSA883X_CDC_SPK_GAIN_PDM_0, 0x00 }, |
|---|
| 689 | { WSA883X_CDC_SPK_GAIN_PDM_1, 0xFC }, |
|---|
| 690 | { WSA883X_CDC_SPK_GAIN_PDM_2, 0x05 }, |
|---|
| 691 | { WSA883X_PDM_WD_CTL, 0x00 }, |
|---|
| 692 | { WSA883X_DEM_BYPASS_DATA0, 0x00 }, |
|---|
| 693 | { WSA883X_DEM_BYPASS_DATA1, 0x00 }, |
|---|
| 694 | { WSA883X_DEM_BYPASS_DATA2, 0x00 }, |
|---|
| 695 | { WSA883X_DEM_BYPASS_DATA3, 0x00 }, |
|---|
| 696 | { WSA883X_WAVG_CTL, 0x06 }, |
|---|
| 697 | { WSA883X_WAVG_LRA_PER_0, 0xD1 }, |
|---|
| 698 | { WSA883X_WAVG_LRA_PER_1, 0x00 }, |
|---|
| 699 | { WSA883X_WAVG_DELTA_THETA_0, 0xE6 }, |
|---|
| 700 | { WSA883X_WAVG_DELTA_THETA_1, 0x04 }, |
|---|
| 701 | { WSA883X_WAVG_DIRECT_AMP_0, 0x50 }, |
|---|
| 702 | { WSA883X_WAVG_DIRECT_AMP_1, 0x00 }, |
|---|
| 703 | { WSA883X_WAVG_PTRN_AMP0_0, 0x50 }, |
|---|
| 704 | { WSA883X_WAVG_PTRN_AMP0_1, 0x00 }, |
|---|
| 705 | { WSA883X_WAVG_PTRN_AMP1_0, 0x50 }, |
|---|
| 706 | { WSA883X_WAVG_PTRN_AMP1_1, 0x00 }, |
|---|
| 707 | { WSA883X_WAVG_PTRN_AMP2_0, 0x50 }, |
|---|
| 708 | { WSA883X_WAVG_PTRN_AMP2_1, 0x00 }, |
|---|
| 709 | { WSA883X_WAVG_PTRN_AMP3_0, 0x50 }, |
|---|
| 710 | { WSA883X_WAVG_PTRN_AMP3_1, 0x00 }, |
|---|
| 711 | { WSA883X_WAVG_PTRN_AMP4_0, 0x50 }, |
|---|
| 712 | { WSA883X_WAVG_PTRN_AMP4_1, 0x00 }, |
|---|
| 713 | { WSA883X_WAVG_PTRN_AMP5_0, 0x50 }, |
|---|
| 714 | { WSA883X_WAVG_PTRN_AMP5_1, 0x00 }, |
|---|
| 715 | { WSA883X_WAVG_PTRN_AMP6_0, 0x50 }, |
|---|
| 716 | { WSA883X_WAVG_PTRN_AMP6_1, 0x00 }, |
|---|
| 717 | { WSA883X_WAVG_PTRN_AMP7_0, 0x50 }, |
|---|
| 718 | { WSA883X_WAVG_PTRN_AMP7_1, 0x00 }, |
|---|
| 719 | { WSA883X_WAVG_PER_0_1, 0x88 }, |
|---|
| 720 | { WSA883X_WAVG_PER_2_3, 0x88 }, |
|---|
| 721 | { WSA883X_WAVG_PER_4_5, 0x88 }, |
|---|
| 722 | { WSA883X_WAVG_PER_6_7, 0x88 }, |
|---|
| 723 | { WSA883X_WAVG_STA, 0x00 }, |
|---|
| 724 | { WSA883X_DRE_CTL_0, 0x70 }, |
|---|
| 725 | { WSA883X_DRE_CTL_1, 0x08 }, |
|---|
| 726 | { WSA883X_DRE_IDLE_DET_CTL, 0x1F }, |
|---|
| 727 | { WSA883X_CLSH_CTL_0, 0x37 }, |
|---|
| 728 | { WSA883X_CLSH_CTL_1, 0x81 }, |
|---|
| 729 | { WSA883X_CLSH_V_HD_PA, 0x0F }, |
|---|
| 730 | { WSA883X_CLSH_V_PA_MIN, 0x00 }, |
|---|
| 731 | { WSA883X_CLSH_OVRD_VAL, 0x00 }, |
|---|
| 732 | { WSA883X_CLSH_HARD_MAX, 0xFF }, |
|---|
| 733 | { WSA883X_CLSH_SOFT_MAX, 0xF5 }, |
|---|
| 734 | { WSA883X_CLSH_SIG_DP, 0x00 }, |
|---|
| 735 | { WSA883X_TAGC_CTL, 0x10 }, |
|---|
| 736 | { WSA883X_TAGC_TIME, 0x20 }, |
|---|
| 737 | { WSA883X_TAGC_E2E_GAIN, 0x02 }, |
|---|
| 738 | { WSA883X_TAGC_FORCE_VAL, 0x00 }, |
|---|
| 739 | { WSA883X_VAGC_CTL, 0x00 }, |
|---|
| 740 | { WSA883X_VAGC_TIME, 0x08 }, |
|---|
| 741 | { WSA883X_VAGC_ATTN_LVL_1_2, 0x21 }, |
|---|
| 742 | { WSA883X_VAGC_ATTN_LVL_3, 0x03 }, |
|---|
| 743 | { WSA883X_INTR_MODE, 0x00 }, |
|---|
| 744 | { WSA883X_INTR_MASK0, 0x90 }, |
|---|
| 745 | { WSA883X_INTR_MASK1, 0x00 }, |
|---|
| 746 | { WSA883X_INTR_STATUS0, 0x00 }, |
|---|
| 747 | { WSA883X_INTR_STATUS1, 0x00 }, |
|---|
| 748 | { WSA883X_INTR_CLEAR0, 0x00 }, |
|---|
| 749 | { WSA883X_INTR_CLEAR1, 0x00 }, |
|---|
| 750 | { WSA883X_INTR_LEVEL0, 0x00 }, |
|---|
| 751 | { WSA883X_INTR_LEVEL1, 0x00 }, |
|---|
| 752 | { WSA883X_INTR_SET0, 0x00 }, |
|---|
| 753 | { WSA883X_INTR_SET1, 0x00 }, |
|---|
| 754 | { WSA883X_INTR_TEST0, 0x00 }, |
|---|
| 755 | { WSA883X_INTR_TEST1, 0x00 }, |
|---|
| 756 | { WSA883X_OTP_CTRL0, 0x00 }, |
|---|
| 757 | { WSA883X_OTP_CTRL1, 0x00 }, |
|---|
| 758 | { WSA883X_HDRIVE_CTL_GROUP1, 0x00 }, |
|---|
| 759 | { WSA883X_PIN_CTL, 0x04 }, |
|---|
| 760 | { WSA883X_PIN_CTL_OE, 0x00 }, |
|---|
| 761 | { WSA883X_PIN_WDATA_IOPAD, 0x00 }, |
|---|
| 762 | { WSA883X_PIN_STATUS, 0x00 }, |
|---|
| 763 | { WSA883X_I2C_SLAVE_CTL, 0x00 }, |
|---|
| 764 | { WSA883X_PDM_TEST_MODE, 0x00 }, |
|---|
| 765 | { WSA883X_ATE_TEST_MODE, 0x00 }, |
|---|
| 766 | { WSA883X_DIG_DEBUG_MODE, 0x00 }, |
|---|
| 767 | { WSA883X_DIG_DEBUG_SEL, 0x00 }, |
|---|
| 768 | { WSA883X_DIG_DEBUG_EN, 0x00 }, |
|---|
| 769 | { WSA883X_SWR_HM_TEST0, 0x08 }, |
|---|
| 770 | { WSA883X_SWR_HM_TEST1, 0x00 }, |
|---|
| 771 | { WSA883X_SWR_PAD_CTL, 0x37 }, |
|---|
| 772 | { WSA883X_TADC_DETECT_DBG_CTL, 0x00 }, |
|---|
| 773 | { WSA883X_TADC_DEBUG_MSB, 0x00 }, |
|---|
| 774 | { WSA883X_TADC_DEBUG_LSB, 0x00 }, |
|---|
| 775 | { WSA883X_SAMPLE_EDGE_SEL, 0x7F }, |
|---|
| 776 | { WSA883X_SWR_EDGE_SEL, 0x00 }, |
|---|
| 777 | { WSA883X_TEST_MODE_CTL, 0x04 }, |
|---|
| 778 | { WSA883X_IOPAD_CTL, 0x00 }, |
|---|
| 779 | { WSA883X_ANA_CSR_DBG_ADD, 0x00 }, |
|---|
| 780 | { WSA883X_ANA_CSR_DBG_CTL, 0x12 }, |
|---|
| 781 | { WSA883X_SPARE_R, 0x00 }, |
|---|
| 782 | { WSA883X_SPARE_0, 0x00 }, |
|---|
| 783 | { WSA883X_SPARE_1, 0x00 }, |
|---|
| 784 | { WSA883X_SPARE_2, 0x00 }, |
|---|
| 785 | { WSA883X_SCODE, 0x00 }, |
|---|
| 786 | { WSA883X_OTP_REG_0, 0x05 }, |
|---|
| 787 | { WSA883X_OTP_REG_1, 0xFF }, |
|---|
| 788 | { WSA883X_OTP_REG_2, 0xC0 }, |
|---|
| 789 | { WSA883X_OTP_REG_3, 0xFF }, |
|---|
| 790 | { WSA883X_OTP_REG_4, 0xC0 }, |
|---|
| 791 | { WSA883X_OTP_REG_5, 0xFF }, |
|---|
| 792 | { WSA883X_OTP_REG_6, 0xFF }, |
|---|
| 793 | { WSA883X_OTP_REG_7, 0xFF }, |
|---|
| 794 | { WSA883X_OTP_REG_8, 0xFF }, |
|---|
| 795 | { WSA883X_OTP_REG_9, 0xFF }, |
|---|
| 796 | { WSA883X_OTP_REG_10, 0xFF }, |
|---|
| 797 | { WSA883X_OTP_REG_11, 0xFF }, |
|---|
| 798 | { WSA883X_OTP_REG_12, 0xFF }, |
|---|
| 799 | { WSA883X_OTP_REG_13, 0xFF }, |
|---|
| 800 | { WSA883X_OTP_REG_14, 0xFF }, |
|---|
| 801 | { WSA883X_OTP_REG_15, 0xFF }, |
|---|
| 802 | { WSA883X_OTP_REG_16, 0xFF }, |
|---|
| 803 | { WSA883X_OTP_REG_17, 0xFF }, |
|---|
| 804 | { WSA883X_OTP_REG_18, 0xFF }, |
|---|
| 805 | { WSA883X_OTP_REG_19, 0xFF }, |
|---|
| 806 | { WSA883X_OTP_REG_20, 0xFF }, |
|---|
| 807 | { WSA883X_OTP_REG_21, 0xFF }, |
|---|
| 808 | { WSA883X_OTP_REG_22, 0xFF }, |
|---|
| 809 | { WSA883X_OTP_REG_23, 0xFF }, |
|---|
| 810 | { WSA883X_OTP_REG_24, 0x37 }, |
|---|
| 811 | { WSA883X_OTP_REG_25, 0x3F }, |
|---|
| 812 | { WSA883X_OTP_REG_26, 0x03 }, |
|---|
| 813 | { WSA883X_OTP_REG_27, 0x00 }, |
|---|
| 814 | { WSA883X_OTP_REG_28, 0x00 }, |
|---|
| 815 | { WSA883X_OTP_REG_29, 0x00 }, |
|---|
| 816 | { WSA883X_OTP_REG_30, 0x00 }, |
|---|
| 817 | { WSA883X_OTP_REG_31, 0x03 }, |
|---|
| 818 | { WSA883X_OTP_REG_32, 0x00 }, |
|---|
| 819 | { WSA883X_OTP_REG_33, 0xFF }, |
|---|
| 820 | { WSA883X_OTP_REG_34, 0x00 }, |
|---|
| 821 | { WSA883X_OTP_REG_35, 0x00 }, |
|---|
| 822 | { WSA883X_OTP_REG_63, 0x40 }, |
|---|
| 823 | { WSA883X_EMEM_0, 0x00 }, |
|---|
| 824 | { WSA883X_EMEM_1, 0x00 }, |
|---|
| 825 | { WSA883X_EMEM_2, 0x00 }, |
|---|
| 826 | { WSA883X_EMEM_3, 0x00 }, |
|---|
| 827 | { WSA883X_EMEM_4, 0x00 }, |
|---|
| 828 | { WSA883X_EMEM_5, 0x00 }, |
|---|
| 829 | { WSA883X_EMEM_6, 0x00 }, |
|---|
| 830 | { WSA883X_EMEM_7, 0x00 }, |
|---|
| 831 | { WSA883X_EMEM_8, 0x00 }, |
|---|
| 832 | { WSA883X_EMEM_9, 0x00 }, |
|---|
| 833 | { WSA883X_EMEM_10, 0x00 }, |
|---|
| 834 | { WSA883X_EMEM_11, 0x00 }, |
|---|
| 835 | { WSA883X_EMEM_12, 0x00 }, |
|---|
| 836 | { WSA883X_EMEM_13, 0x00 }, |
|---|
| 837 | { WSA883X_EMEM_14, 0x00 }, |
|---|
| 838 | { WSA883X_EMEM_15, 0x00 }, |
|---|
| 839 | { WSA883X_EMEM_16, 0x00 }, |
|---|
| 840 | { WSA883X_EMEM_17, 0x00 }, |
|---|
| 841 | { WSA883X_EMEM_18, 0x00 }, |
|---|
| 842 | { WSA883X_EMEM_19, 0x00 }, |
|---|
| 843 | { WSA883X_EMEM_20, 0x00 }, |
|---|
| 844 | { WSA883X_EMEM_21, 0x00 }, |
|---|
| 845 | { WSA883X_EMEM_22, 0x00 }, |
|---|
| 846 | { WSA883X_EMEM_23, 0x00 }, |
|---|
| 847 | { WSA883X_EMEM_24, 0x00 }, |
|---|
| 848 | { WSA883X_EMEM_25, 0x00 }, |
|---|
| 849 | { WSA883X_EMEM_26, 0x00 }, |
|---|
| 850 | { WSA883X_EMEM_27, 0x00 }, |
|---|
| 851 | { WSA883X_EMEM_28, 0x00 }, |
|---|
| 852 | { WSA883X_EMEM_29, 0x00 }, |
|---|
| 853 | { WSA883X_EMEM_30, 0x00 }, |
|---|
| 854 | { WSA883X_EMEM_31, 0x00 }, |
|---|
| 855 | { WSA883X_EMEM_32, 0x00 }, |
|---|
| 856 | { WSA883X_EMEM_33, 0x00 }, |
|---|
| 857 | { WSA883X_EMEM_34, 0x00 }, |
|---|
| 858 | { WSA883X_EMEM_35, 0x00 }, |
|---|
| 859 | { WSA883X_EMEM_36, 0x00 }, |
|---|
| 860 | { WSA883X_EMEM_37, 0x00 }, |
|---|
| 861 | { WSA883X_EMEM_38, 0x00 }, |
|---|
| 862 | { WSA883X_EMEM_39, 0x00 }, |
|---|
| 863 | { WSA883X_EMEM_40, 0x00 }, |
|---|
| 864 | { WSA883X_EMEM_41, 0x00 }, |
|---|
| 865 | { WSA883X_EMEM_42, 0x00 }, |
|---|
| 866 | { WSA883X_EMEM_43, 0x00 }, |
|---|
| 867 | { WSA883X_EMEM_44, 0x00 }, |
|---|
| 868 | { WSA883X_EMEM_45, 0x00 }, |
|---|
| 869 | { WSA883X_EMEM_46, 0x00 }, |
|---|
| 870 | { WSA883X_EMEM_47, 0x00 }, |
|---|
| 871 | { WSA883X_EMEM_48, 0x00 }, |
|---|
| 872 | { WSA883X_EMEM_49, 0x00 }, |
|---|
| 873 | { WSA883X_EMEM_50, 0x00 }, |
|---|
| 874 | { WSA883X_EMEM_51, 0x00 }, |
|---|
| 875 | { WSA883X_EMEM_52, 0x00 }, |
|---|
| 876 | { WSA883X_EMEM_53, 0x00 }, |
|---|
| 877 | { WSA883X_EMEM_54, 0x00 }, |
|---|
| 878 | { WSA883X_EMEM_55, 0x00 }, |
|---|
| 879 | { WSA883X_EMEM_56, 0x00 }, |
|---|
| 880 | { WSA883X_EMEM_57, 0x00 }, |
|---|
| 881 | { WSA883X_EMEM_58, 0x00 }, |
|---|
| 882 | { WSA883X_EMEM_59, 0x00 }, |
|---|
| 883 | { WSA883X_EMEM_60, 0x00 }, |
|---|
| 884 | { WSA883X_EMEM_61, 0x00 }, |
|---|
| 885 | { WSA883X_EMEM_62, 0x00 }, |
|---|
| 886 | { WSA883X_EMEM_63, 0x00 }, |
|---|
| 887 | }; |
|---|
| 888 | |
|---|
| 889 | static bool wsa883x_readonly_register(struct device *dev, unsigned int reg) |
|---|
| 890 | { |
|---|
| 891 | switch (reg) { |
|---|
| 892 | case WSA883X_DOUT_MSB: |
|---|
| 893 | case WSA883X_DOUT_LSB: |
|---|
| 894 | case WSA883X_STATUS: |
|---|
| 895 | case WSA883X_PA_STATUS0: |
|---|
| 896 | case WSA883X_PA_STATUS1: |
|---|
| 897 | case WSA883X_PA_STATUS2: |
|---|
| 898 | case WSA883X_STATUS_0: |
|---|
| 899 | case WSA883X_STATUS_1: |
|---|
| 900 | case WSA883X_CHIP_ID0: |
|---|
| 901 | case WSA883X_CHIP_ID1: |
|---|
| 902 | case WSA883X_CHIP_ID2: |
|---|
| 903 | case WSA883X_CHIP_ID3: |
|---|
| 904 | case WSA883X_BUS_ID: |
|---|
| 905 | case WSA883X_PA_FSM_STA: |
|---|
| 906 | case WSA883X_PA_FSM_ERR_COND: |
|---|
| 907 | case WSA883X_TEMP_MSB: |
|---|
| 908 | case WSA883X_TEMP_LSB: |
|---|
| 909 | case WSA883X_VBAT_DIN_MSB: |
|---|
| 910 | case WSA883X_VBAT_DIN_LSB: |
|---|
| 911 | case WSA883X_VBAT_DOUT: |
|---|
| 912 | case WSA883X_SDM_PDM9_LSB: |
|---|
| 913 | case WSA883X_SDM_PDM9_MSB: |
|---|
| 914 | case WSA883X_WAVG_STA: |
|---|
| 915 | case WSA883X_INTR_STATUS0: |
|---|
| 916 | case WSA883X_INTR_STATUS1: |
|---|
| 917 | case WSA883X_OTP_CTRL1: |
|---|
| 918 | case WSA883X_PIN_STATUS: |
|---|
| 919 | case WSA883X_ATE_TEST_MODE: |
|---|
| 920 | case WSA883X_SWR_HM_TEST1: |
|---|
| 921 | case WSA883X_SPARE_R: |
|---|
| 922 | case WSA883X_OTP_REG_0: |
|---|
| 923 | return true; |
|---|
| 924 | } |
|---|
| 925 | return false; |
|---|
| 926 | } |
|---|
| 927 | |
|---|
| 928 | static bool wsa883x_writeable_register(struct device *dev, unsigned int reg) |
|---|
| 929 | { |
|---|
| 930 | return !wsa883x_readonly_register(dev, reg); |
|---|
| 931 | } |
|---|
| 932 | |
|---|
| 933 | static bool wsa883x_volatile_register(struct device *dev, unsigned int reg) |
|---|
| 934 | { |
|---|
| 935 | return wsa883x_readonly_register(dev, reg); |
|---|
| 936 | } |
|---|
| 937 | |
|---|
| 938 | static struct regmap_config wsa883x_regmap_config = { |
|---|
| 939 | .reg_bits = 32, |
|---|
| 940 | .val_bits = 8, |
|---|
| 941 | .cache_type = REGCACHE_MAPLE, |
|---|
| 942 | .reg_defaults = wsa883x_defaults, |
|---|
| 943 | .max_register = WSA883X_MAX_REGISTER, |
|---|
| 944 | .num_reg_defaults = ARRAY_SIZE(wsa883x_defaults), |
|---|
| 945 | .volatile_reg = wsa883x_volatile_register, |
|---|
| 946 | .writeable_reg = wsa883x_writeable_register, |
|---|
| 947 | .reg_format_endian = REGMAP_ENDIAN_NATIVE, |
|---|
| 948 | .val_format_endian = REGMAP_ENDIAN_NATIVE, |
|---|
| 949 | .use_single_read = true, |
|---|
| 950 | }; |
|---|
| 951 | |
|---|
| 952 | static const struct reg_sequence reg_init[] = { |
|---|
| 953 | {WSA883X_PA_FSM_BYP, 0x00}, |
|---|
| 954 | {WSA883X_ADC_6, 0x02}, |
|---|
| 955 | {WSA883X_CDC_SPK_DSM_A2_0, 0x0A}, |
|---|
| 956 | {WSA883X_CDC_SPK_DSM_A2_1, 0x08}, |
|---|
| 957 | {WSA883X_CDC_SPK_DSM_A3_0, 0xF3}, |
|---|
| 958 | {WSA883X_CDC_SPK_DSM_A3_1, 0x07}, |
|---|
| 959 | {WSA883X_CDC_SPK_DSM_A4_0, 0x79}, |
|---|
| 960 | {WSA883X_CDC_SPK_DSM_A4_1, 0x02}, |
|---|
| 961 | {WSA883X_CDC_SPK_DSM_A5_0, 0x0B}, |
|---|
| 962 | {WSA883X_CDC_SPK_DSM_A5_1, 0x02}, |
|---|
| 963 | {WSA883X_CDC_SPK_DSM_A6_0, 0x8A}, |
|---|
| 964 | {WSA883X_CDC_SPK_DSM_A7_0, 0x9B}, |
|---|
| 965 | {WSA883X_CDC_SPK_DSM_C_0, 0x68}, |
|---|
| 966 | {WSA883X_CDC_SPK_DSM_C_1, 0x54}, |
|---|
| 967 | {WSA883X_CDC_SPK_DSM_C_2, 0xF2}, |
|---|
| 968 | {WSA883X_CDC_SPK_DSM_C_3, 0x20}, |
|---|
| 969 | {WSA883X_CDC_SPK_DSM_R1, 0x83}, |
|---|
| 970 | {WSA883X_CDC_SPK_DSM_R2, 0x7F}, |
|---|
| 971 | {WSA883X_CDC_SPK_DSM_R3, 0x9D}, |
|---|
| 972 | {WSA883X_CDC_SPK_DSM_R4, 0x82}, |
|---|
| 973 | {WSA883X_CDC_SPK_DSM_R5, 0x8B}, |
|---|
| 974 | {WSA883X_CDC_SPK_DSM_R6, 0x9B}, |
|---|
| 975 | {WSA883X_CDC_SPK_DSM_R7, 0x3F}, |
|---|
| 976 | {WSA883X_VBAT_SNS, 0x20}, |
|---|
| 977 | {WSA883X_DRE_CTL_0, 0x92}, |
|---|
| 978 | {WSA883X_DRE_IDLE_DET_CTL, 0x0F}, |
|---|
| 979 | {WSA883X_CURRENT_LIMIT, 0xC4}, |
|---|
| 980 | {WSA883X_VAGC_TIME, 0x0F}, |
|---|
| 981 | {WSA883X_VAGC_ATTN_LVL_1_2, 0x00}, |
|---|
| 982 | {WSA883X_VAGC_ATTN_LVL_3, 0x01}, |
|---|
| 983 | {WSA883X_VAGC_CTL, 0x01}, |
|---|
| 984 | {WSA883X_TAGC_CTL, 0x1A}, |
|---|
| 985 | {WSA883X_TAGC_TIME, 0x2C}, |
|---|
| 986 | {WSA883X_TEMP_CONFIG0, 0x02}, |
|---|
| 987 | {WSA883X_TEMP_CONFIG1, 0x02}, |
|---|
| 988 | {WSA883X_OTP_REG_1, 0x49}, |
|---|
| 989 | {WSA883X_OTP_REG_2, 0x80}, |
|---|
| 990 | {WSA883X_OTP_REG_3, 0xC9}, |
|---|
| 991 | {WSA883X_OTP_REG_4, 0x40}, |
|---|
| 992 | {WSA883X_TAGC_CTL, 0x1B}, |
|---|
| 993 | {WSA883X_ADC_2, 0x00}, |
|---|
| 994 | {WSA883X_ADC_7, 0x85}, |
|---|
| 995 | {WSA883X_ADC_7, 0x87}, |
|---|
| 996 | {WSA883X_CKWD_CTL_0, 0x14}, |
|---|
| 997 | {WSA883X_CKWD_CTL_1, 0x1B}, |
|---|
| 998 | {WSA883X_GMAMP_SUP1, 0xE2}, |
|---|
| 999 | }; |
|---|
| 1000 | |
|---|
| 1001 | static void wsa883x_init(struct wsa883x_priv *wsa883x) |
|---|
| 1002 | { |
|---|
| 1003 | struct regmap *regmap = wsa883x->regmap; |
|---|
| 1004 | int variant, version; |
|---|
| 1005 | |
|---|
| 1006 | regmap_read(map: regmap, WSA883X_OTP_REG_0, val: &variant); |
|---|
| 1007 | wsa883x->variant = variant & WSA883X_ID_MASK; |
|---|
| 1008 | |
|---|
| 1009 | regmap_read(map: regmap, WSA883X_CHIP_ID0, val: &version); |
|---|
| 1010 | wsa883x->version = version; |
|---|
| 1011 | |
|---|
| 1012 | switch (wsa883x->variant) { |
|---|
| 1013 | case WSA8830: |
|---|
| 1014 | dev_info(wsa883x->dev, "WSA883X Version 1_%d, Variant: WSA8830\n" , |
|---|
| 1015 | wsa883x->version); |
|---|
| 1016 | break; |
|---|
| 1017 | case WSA8835: |
|---|
| 1018 | dev_info(wsa883x->dev, "WSA883X Version 1_%d, Variant: WSA8835\n" , |
|---|
| 1019 | wsa883x->version); |
|---|
| 1020 | break; |
|---|
| 1021 | case WSA8832: |
|---|
| 1022 | dev_info(wsa883x->dev, "WSA883X Version 1_%d, Variant: WSA8832\n" , |
|---|
| 1023 | wsa883x->version); |
|---|
| 1024 | break; |
|---|
| 1025 | case WSA8835_V2: |
|---|
| 1026 | dev_info(wsa883x->dev, "WSA883X Version 1_%d, Variant: WSA8835_V2\n" , |
|---|
| 1027 | wsa883x->version); |
|---|
| 1028 | break; |
|---|
| 1029 | default: |
|---|
| 1030 | break; |
|---|
| 1031 | } |
|---|
| 1032 | |
|---|
| 1033 | wsa883x->comp_offset = COMP_OFFSET2; |
|---|
| 1034 | |
|---|
| 1035 | /* Initial settings */ |
|---|
| 1036 | regmap_multi_reg_write(map: regmap, regs: reg_init, ARRAY_SIZE(reg_init)); |
|---|
| 1037 | |
|---|
| 1038 | if (wsa883x->variant == WSA8830 || wsa883x->variant == WSA8832) { |
|---|
| 1039 | wsa883x->comp_offset = COMP_OFFSET3; |
|---|
| 1040 | regmap_update_bits(map: regmap, WSA883X_DRE_CTL_0, |
|---|
| 1041 | WSA883X_DRE_OFFSET_MASK, |
|---|
| 1042 | val: wsa883x->comp_offset); |
|---|
| 1043 | } |
|---|
| 1044 | } |
|---|
| 1045 | |
|---|
| 1046 | static int wsa883x_update_status(struct sdw_slave *slave, |
|---|
| 1047 | enum sdw_slave_status status) |
|---|
| 1048 | { |
|---|
| 1049 | struct wsa883x_priv *wsa883x = dev_get_drvdata(dev: &slave->dev); |
|---|
| 1050 | |
|---|
| 1051 | if (status == SDW_SLAVE_ATTACHED && slave->dev_num > 0) |
|---|
| 1052 | wsa883x_init(wsa883x); |
|---|
| 1053 | |
|---|
| 1054 | return 0; |
|---|
| 1055 | } |
|---|
| 1056 | |
|---|
| 1057 | static int wsa883x_port_prep(struct sdw_slave *slave, |
|---|
| 1058 | struct sdw_prepare_ch *prepare_ch, |
|---|
| 1059 | enum sdw_port_prep_ops state) |
|---|
| 1060 | { |
|---|
| 1061 | struct wsa883x_priv *wsa883x = dev_get_drvdata(dev: &slave->dev); |
|---|
| 1062 | |
|---|
| 1063 | if (state == SDW_OPS_PORT_POST_PREP) |
|---|
| 1064 | wsa883x->port_prepared[prepare_ch->num - 1] = true; |
|---|
| 1065 | else |
|---|
| 1066 | wsa883x->port_prepared[prepare_ch->num - 1] = false; |
|---|
| 1067 | |
|---|
| 1068 | return 0; |
|---|
| 1069 | } |
|---|
| 1070 | |
|---|
| 1071 | static const struct sdw_slave_ops wsa883x_slave_ops = { |
|---|
| 1072 | .update_status = wsa883x_update_status, |
|---|
| 1073 | .port_prep = wsa883x_port_prep, |
|---|
| 1074 | }; |
|---|
| 1075 | |
|---|
| 1076 | static int wsa_dev_mode_get(struct snd_kcontrol *kcontrol, |
|---|
| 1077 | struct snd_ctl_elem_value *ucontrol) |
|---|
| 1078 | { |
|---|
| 1079 | struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); |
|---|
| 1080 | struct wsa883x_priv *wsa883x = snd_soc_component_get_drvdata(c: component); |
|---|
| 1081 | |
|---|
| 1082 | ucontrol->value.enumerated.item[0] = wsa883x->dev_mode; |
|---|
| 1083 | |
|---|
| 1084 | return 0; |
|---|
| 1085 | } |
|---|
| 1086 | |
|---|
| 1087 | static int wsa_dev_mode_put(struct snd_kcontrol *kcontrol, |
|---|
| 1088 | struct snd_ctl_elem_value *ucontrol) |
|---|
| 1089 | { |
|---|
| 1090 | struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); |
|---|
| 1091 | struct wsa883x_priv *wsa883x = snd_soc_component_get_drvdata(c: component); |
|---|
| 1092 | |
|---|
| 1093 | if (wsa883x->dev_mode == ucontrol->value.enumerated.item[0]) |
|---|
| 1094 | return 0; |
|---|
| 1095 | |
|---|
| 1096 | wsa883x->dev_mode = ucontrol->value.enumerated.item[0]; |
|---|
| 1097 | |
|---|
| 1098 | return 1; |
|---|
| 1099 | } |
|---|
| 1100 | |
|---|
| 1101 | static const SNDRV_CTL_TLVD_DECLARE_DB_RANGE(pa_gain, |
|---|
| 1102 | 0, 14, TLV_DB_SCALE_ITEM(-300, 0, 0), |
|---|
| 1103 | 15, 29, TLV_DB_SCALE_ITEM(-300, 150, 0), |
|---|
| 1104 | 30, 31, TLV_DB_SCALE_ITEM(1800, 0, 0), |
|---|
| 1105 | ); |
|---|
| 1106 | |
|---|
| 1107 | static int wsa883x_get_swr_port(struct snd_kcontrol *kcontrol, |
|---|
| 1108 | struct snd_ctl_elem_value *ucontrol) |
|---|
| 1109 | { |
|---|
| 1110 | struct snd_soc_component *comp = snd_soc_kcontrol_component(kcontrol); |
|---|
| 1111 | struct wsa883x_priv *data = snd_soc_component_get_drvdata(c: comp); |
|---|
| 1112 | struct soc_mixer_control *mixer = (struct soc_mixer_control *)kcontrol->private_value; |
|---|
| 1113 | int portidx = mixer->reg; |
|---|
| 1114 | |
|---|
| 1115 | ucontrol->value.integer.value[0] = data->port_enable[portidx]; |
|---|
| 1116 | |
|---|
| 1117 | return 0; |
|---|
| 1118 | } |
|---|
| 1119 | |
|---|
| 1120 | static int wsa883x_set_swr_port(struct snd_kcontrol *kcontrol, |
|---|
| 1121 | struct snd_ctl_elem_value *ucontrol) |
|---|
| 1122 | { |
|---|
| 1123 | struct snd_soc_component *comp = snd_soc_kcontrol_component(kcontrol); |
|---|
| 1124 | struct wsa883x_priv *data = snd_soc_component_get_drvdata(c: comp); |
|---|
| 1125 | struct soc_mixer_control *mixer = (struct soc_mixer_control *)kcontrol->private_value; |
|---|
| 1126 | int portidx = mixer->reg; |
|---|
| 1127 | |
|---|
| 1128 | if (ucontrol->value.integer.value[0]) { |
|---|
| 1129 | if (data->port_enable[portidx]) |
|---|
| 1130 | return 0; |
|---|
| 1131 | |
|---|
| 1132 | data->port_enable[portidx] = true; |
|---|
| 1133 | } else { |
|---|
| 1134 | if (!data->port_enable[portidx]) |
|---|
| 1135 | return 0; |
|---|
| 1136 | |
|---|
| 1137 | data->port_enable[portidx] = false; |
|---|
| 1138 | } |
|---|
| 1139 | |
|---|
| 1140 | return 1; |
|---|
| 1141 | } |
|---|
| 1142 | |
|---|
| 1143 | static int wsa883x_get_comp_offset(struct snd_kcontrol *kcontrol, |
|---|
| 1144 | struct snd_ctl_elem_value *ucontrol) |
|---|
| 1145 | { |
|---|
| 1146 | struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); |
|---|
| 1147 | struct wsa883x_priv *wsa883x = snd_soc_component_get_drvdata(c: component); |
|---|
| 1148 | |
|---|
| 1149 | ucontrol->value.integer.value[0] = wsa883x->comp_offset; |
|---|
| 1150 | |
|---|
| 1151 | return 0; |
|---|
| 1152 | } |
|---|
| 1153 | |
|---|
| 1154 | static int wsa883x_set_comp_offset(struct snd_kcontrol *kcontrol, |
|---|
| 1155 | struct snd_ctl_elem_value *ucontrol) |
|---|
| 1156 | { |
|---|
| 1157 | struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); |
|---|
| 1158 | struct wsa883x_priv *wsa883x = snd_soc_component_get_drvdata(c: component); |
|---|
| 1159 | |
|---|
| 1160 | if (wsa883x->comp_offset == ucontrol->value.integer.value[0]) |
|---|
| 1161 | return 0; |
|---|
| 1162 | |
|---|
| 1163 | wsa883x->comp_offset = ucontrol->value.integer.value[0]; |
|---|
| 1164 | |
|---|
| 1165 | return 1; |
|---|
| 1166 | } |
|---|
| 1167 | |
|---|
| 1168 | static int wsa883x_codec_probe(struct snd_soc_component *comp) |
|---|
| 1169 | { |
|---|
| 1170 | struct wsa883x_priv *wsa883x = snd_soc_component_get_drvdata(c: comp); |
|---|
| 1171 | |
|---|
| 1172 | snd_soc_component_init_regmap(component: comp, regmap: wsa883x->regmap); |
|---|
| 1173 | |
|---|
| 1174 | return 0; |
|---|
| 1175 | } |
|---|
| 1176 | |
|---|
| 1177 | static int wsa883x_spkr_event(struct snd_soc_dapm_widget *w, |
|---|
| 1178 | struct snd_kcontrol *kcontrol, int event) |
|---|
| 1179 | { |
|---|
| 1180 | struct snd_soc_component *component = snd_soc_dapm_to_component(dapm: w->dapm); |
|---|
| 1181 | struct wsa883x_priv *wsa883x = snd_soc_component_get_drvdata(c: component); |
|---|
| 1182 | |
|---|
| 1183 | switch (event) { |
|---|
| 1184 | case SND_SOC_DAPM_POST_PMU: |
|---|
| 1185 | switch (wsa883x->dev_mode) { |
|---|
| 1186 | case RECEIVER: |
|---|
| 1187 | snd_soc_component_write_field(component, WSA883X_CDC_PATH_MODE, |
|---|
| 1188 | WSA883X_RXD_MODE_MASK, |
|---|
| 1189 | WSA883X_RXD_MODE_HIFI); |
|---|
| 1190 | snd_soc_component_write_field(component, WSA883X_SPKR_PWM_CLK_CTL, |
|---|
| 1191 | WSA883X_SPKR_PWM_FREQ_SEL_MASK, |
|---|
| 1192 | WSA883X_SPKR_PWM_FREQ_F600KHZ); |
|---|
| 1193 | snd_soc_component_write_field(component, WSA883X_DRE_CTL_0, |
|---|
| 1194 | WSA883X_DRE_PROG_DELAY_MASK, val: 0x0); |
|---|
| 1195 | break; |
|---|
| 1196 | case SPEAKER: |
|---|
| 1197 | snd_soc_component_write_field(component, WSA883X_CDC_PATH_MODE, |
|---|
| 1198 | WSA883X_RXD_MODE_MASK, |
|---|
| 1199 | WSA883X_RXD_MODE_NORMAL); |
|---|
| 1200 | snd_soc_component_write_field(component, WSA883X_SPKR_PWM_CLK_CTL, |
|---|
| 1201 | WSA883X_SPKR_PWM_FREQ_SEL_MASK, |
|---|
| 1202 | WSA883X_SPKR_PWM_FREQ_F300KHZ); |
|---|
| 1203 | snd_soc_component_write_field(component, WSA883X_DRE_CTL_0, |
|---|
| 1204 | WSA883X_DRE_PROG_DELAY_MASK, val: 0x9); |
|---|
| 1205 | break; |
|---|
| 1206 | default: |
|---|
| 1207 | break; |
|---|
| 1208 | } |
|---|
| 1209 | |
|---|
| 1210 | if (wsa883x->port_enable[WSA883X_PORT_COMP]) |
|---|
| 1211 | snd_soc_component_write_field(component, WSA883X_DRE_CTL_0, |
|---|
| 1212 | WSA883X_DRE_OFFSET_MASK, |
|---|
| 1213 | val: wsa883x->comp_offset); |
|---|
| 1214 | snd_soc_component_write_field(component, WSA883X_VBAT_ADC_FLT_CTL, |
|---|
| 1215 | WSA883X_VBAT_ADC_COEF_SEL_MASK, |
|---|
| 1216 | WSA883X_VBAT_ADC_COEF_F_1DIV16); |
|---|
| 1217 | snd_soc_component_write_field(component, WSA883X_VBAT_ADC_FLT_CTL, |
|---|
| 1218 | WSA883X_VBAT_ADC_FLT_EN_MASK, val: 0x1); |
|---|
| 1219 | snd_soc_component_write_field(component, WSA883X_PDM_WD_CTL, |
|---|
| 1220 | WSA883X_PDM_EN_MASK, |
|---|
| 1221 | WSA883X_PDM_ENABLE); |
|---|
| 1222 | |
|---|
| 1223 | break; |
|---|
| 1224 | case SND_SOC_DAPM_PRE_PMD: |
|---|
| 1225 | snd_soc_component_write_field(component, WSA883X_VBAT_ADC_FLT_CTL, |
|---|
| 1226 | WSA883X_VBAT_ADC_FLT_EN_MASK, val: 0x0); |
|---|
| 1227 | snd_soc_component_write_field(component, WSA883X_VBAT_ADC_FLT_CTL, |
|---|
| 1228 | WSA883X_VBAT_ADC_COEF_SEL_MASK, |
|---|
| 1229 | WSA883X_VBAT_ADC_COEF_F_1DIV2); |
|---|
| 1230 | snd_soc_component_write_field(component, WSA883X_PA_FSM_CTL, |
|---|
| 1231 | WSA883X_GLOBAL_PA_EN_MASK, val: 0); |
|---|
| 1232 | snd_soc_component_write_field(component, WSA883X_PDM_WD_CTL, |
|---|
| 1233 | WSA883X_PDM_EN_MASK, val: 0); |
|---|
| 1234 | break; |
|---|
| 1235 | } |
|---|
| 1236 | return 0; |
|---|
| 1237 | } |
|---|
| 1238 | |
|---|
| 1239 | static const struct snd_soc_dapm_widget wsa883x_dapm_widgets[] = { |
|---|
| 1240 | SND_SOC_DAPM_INPUT("IN" ), |
|---|
| 1241 | SND_SOC_DAPM_SPK("SPKR" , wsa883x_spkr_event), |
|---|
| 1242 | }; |
|---|
| 1243 | |
|---|
| 1244 | static const struct snd_kcontrol_new wsa883x_snd_controls[] = { |
|---|
| 1245 | SOC_SINGLE_RANGE_TLV("PA Volume" , WSA883X_DRE_CTL_1, 1, |
|---|
| 1246 | 0x0, 0x1f, 1, pa_gain), |
|---|
| 1247 | SOC_ENUM_EXT("WSA MODE" , wsa_dev_mode_enum, |
|---|
| 1248 | wsa_dev_mode_get, wsa_dev_mode_put), |
|---|
| 1249 | SOC_SINGLE_EXT("COMP Offset" , SND_SOC_NOPM, 0, 4, 0, |
|---|
| 1250 | wsa883x_get_comp_offset, wsa883x_set_comp_offset), |
|---|
| 1251 | SOC_SINGLE_EXT("DAC Switch" , WSA883X_PORT_DAC, 0, 1, 0, |
|---|
| 1252 | wsa883x_get_swr_port, wsa883x_set_swr_port), |
|---|
| 1253 | SOC_SINGLE_EXT("COMP Switch" , WSA883X_PORT_COMP, 0, 1, 0, |
|---|
| 1254 | wsa883x_get_swr_port, wsa883x_set_swr_port), |
|---|
| 1255 | SOC_SINGLE_EXT("BOOST Switch" , WSA883X_PORT_BOOST, 0, 1, 0, |
|---|
| 1256 | wsa883x_get_swr_port, wsa883x_set_swr_port), |
|---|
| 1257 | SOC_SINGLE_EXT("VISENSE Switch" , WSA883X_PORT_VISENSE, 0, 1, 0, |
|---|
| 1258 | wsa883x_get_swr_port, wsa883x_set_swr_port), |
|---|
| 1259 | }; |
|---|
| 1260 | |
|---|
| 1261 | static const struct snd_soc_dapm_route wsa883x_audio_map[] = { |
|---|
| 1262 | {"SPKR" , NULL, "IN" }, |
|---|
| 1263 | }; |
|---|
| 1264 | |
|---|
| 1265 | static const struct snd_soc_component_driver wsa883x_component_drv = { |
|---|
| 1266 | .name = "WSA883x" , |
|---|
| 1267 | .probe = wsa883x_codec_probe, |
|---|
| 1268 | .controls = wsa883x_snd_controls, |
|---|
| 1269 | .num_controls = ARRAY_SIZE(wsa883x_snd_controls), |
|---|
| 1270 | .dapm_widgets = wsa883x_dapm_widgets, |
|---|
| 1271 | .num_dapm_widgets = ARRAY_SIZE(wsa883x_dapm_widgets), |
|---|
| 1272 | .dapm_routes = wsa883x_audio_map, |
|---|
| 1273 | .num_dapm_routes = ARRAY_SIZE(wsa883x_audio_map), |
|---|
| 1274 | }; |
|---|
| 1275 | |
|---|
| 1276 | static int wsa883x_hw_params(struct snd_pcm_substream *substream, |
|---|
| 1277 | struct snd_pcm_hw_params *params, |
|---|
| 1278 | struct snd_soc_dai *dai) |
|---|
| 1279 | { |
|---|
| 1280 | struct wsa883x_priv *wsa883x = dev_get_drvdata(dev: dai->dev); |
|---|
| 1281 | int i; |
|---|
| 1282 | |
|---|
| 1283 | wsa883x->active_ports = 0; |
|---|
| 1284 | for (i = 0; i < WSA883X_MAX_SWR_PORTS; i++) { |
|---|
| 1285 | if (!wsa883x->port_enable[i]) |
|---|
| 1286 | continue; |
|---|
| 1287 | |
|---|
| 1288 | wsa883x->port_config[wsa883x->active_ports] = wsa883x_pconfig[i]; |
|---|
| 1289 | wsa883x->active_ports++; |
|---|
| 1290 | } |
|---|
| 1291 | |
|---|
| 1292 | wsa883x->sconfig.frame_rate = params_rate(p: params); |
|---|
| 1293 | |
|---|
| 1294 | return sdw_stream_add_slave(slave: wsa883x->slave, stream_config: &wsa883x->sconfig, |
|---|
| 1295 | port_config: wsa883x->port_config, num_ports: wsa883x->active_ports, |
|---|
| 1296 | stream: wsa883x->sruntime); |
|---|
| 1297 | } |
|---|
| 1298 | |
|---|
| 1299 | static int wsa883x_hw_free(struct snd_pcm_substream *substream, |
|---|
| 1300 | struct snd_soc_dai *dai) |
|---|
| 1301 | { |
|---|
| 1302 | struct wsa883x_priv *wsa883x = dev_get_drvdata(dev: dai->dev); |
|---|
| 1303 | |
|---|
| 1304 | sdw_stream_remove_slave(slave: wsa883x->slave, stream: wsa883x->sruntime); |
|---|
| 1305 | |
|---|
| 1306 | return 0; |
|---|
| 1307 | } |
|---|
| 1308 | |
|---|
| 1309 | static int wsa883x_set_sdw_stream(struct snd_soc_dai *dai, |
|---|
| 1310 | void *stream, int direction) |
|---|
| 1311 | { |
|---|
| 1312 | struct wsa883x_priv *wsa883x = dev_get_drvdata(dev: dai->dev); |
|---|
| 1313 | |
|---|
| 1314 | wsa883x->sruntime = stream; |
|---|
| 1315 | |
|---|
| 1316 | return 0; |
|---|
| 1317 | } |
|---|
| 1318 | |
|---|
| 1319 | static int wsa883x_digital_mute(struct snd_soc_dai *dai, int mute, int stream) |
|---|
| 1320 | { |
|---|
| 1321 | struct snd_soc_component *component = dai->component; |
|---|
| 1322 | |
|---|
| 1323 | if (mute) { |
|---|
| 1324 | snd_soc_component_write_field(component, WSA883X_DRE_CTL_1, |
|---|
| 1325 | WSA883X_DRE_GAIN_EN_MASK, val: 0); |
|---|
| 1326 | snd_soc_component_write_field(component, WSA883X_PA_FSM_CTL, |
|---|
| 1327 | WSA883X_GLOBAL_PA_EN_MASK, val: 0); |
|---|
| 1328 | |
|---|
| 1329 | } else { |
|---|
| 1330 | snd_soc_component_write_field(component, WSA883X_DRE_CTL_1, |
|---|
| 1331 | WSA883X_DRE_GAIN_EN_MASK, |
|---|
| 1332 | WSA883X_DRE_GAIN_FROM_CSR); |
|---|
| 1333 | snd_soc_component_write_field(component, WSA883X_PA_FSM_CTL, |
|---|
| 1334 | WSA883X_GLOBAL_PA_EN_MASK, |
|---|
| 1335 | WSA883X_GLOBAL_PA_ENABLE); |
|---|
| 1336 | |
|---|
| 1337 | } |
|---|
| 1338 | |
|---|
| 1339 | return 0; |
|---|
| 1340 | } |
|---|
| 1341 | |
|---|
| 1342 | static const struct snd_soc_dai_ops wsa883x_dai_ops = { |
|---|
| 1343 | .hw_params = wsa883x_hw_params, |
|---|
| 1344 | .hw_free = wsa883x_hw_free, |
|---|
| 1345 | .mute_stream = wsa883x_digital_mute, |
|---|
| 1346 | .set_stream = wsa883x_set_sdw_stream, |
|---|
| 1347 | .mute_unmute_on_trigger = true, |
|---|
| 1348 | }; |
|---|
| 1349 | |
|---|
| 1350 | static struct snd_soc_dai_driver wsa883x_dais[] = { |
|---|
| 1351 | { |
|---|
| 1352 | .name = "SPKR" , |
|---|
| 1353 | .playback = { |
|---|
| 1354 | .stream_name = "SPKR Playback" , |
|---|
| 1355 | .rates = WSA883X_RATES | WSA883X_FRAC_RATES, |
|---|
| 1356 | .formats = WSA883X_FORMATS, |
|---|
| 1357 | .rate_min = 8000, |
|---|
| 1358 | .rate_max = 352800, |
|---|
| 1359 | .channels_min = 1, |
|---|
| 1360 | .channels_max = 1, |
|---|
| 1361 | }, |
|---|
| 1362 | .ops = &wsa883x_dai_ops, |
|---|
| 1363 | }, |
|---|
| 1364 | }; |
|---|
| 1365 | |
|---|
| 1366 | static int wsa883x_probe(struct sdw_slave *pdev, |
|---|
| 1367 | const struct sdw_device_id *id) |
|---|
| 1368 | { |
|---|
| 1369 | struct wsa883x_priv *wsa883x; |
|---|
| 1370 | struct device *dev = &pdev->dev; |
|---|
| 1371 | int ret; |
|---|
| 1372 | |
|---|
| 1373 | wsa883x = devm_kzalloc(dev, size: sizeof(*wsa883x), GFP_KERNEL); |
|---|
| 1374 | if (!wsa883x) |
|---|
| 1375 | return -ENOMEM; |
|---|
| 1376 | |
|---|
| 1377 | wsa883x->vdd = devm_regulator_get(dev, id: "vdd" ); |
|---|
| 1378 | if (IS_ERR(ptr: wsa883x->vdd)) |
|---|
| 1379 | return dev_err_probe(dev, err: PTR_ERR(ptr: wsa883x->vdd), |
|---|
| 1380 | fmt: "No vdd regulator found\n" ); |
|---|
| 1381 | |
|---|
| 1382 | ret = regulator_enable(regulator: wsa883x->vdd); |
|---|
| 1383 | if (ret) |
|---|
| 1384 | return dev_err_probe(dev, err: ret, fmt: "Failed to enable vdd regulator\n" ); |
|---|
| 1385 | |
|---|
| 1386 | wsa883x->sd_n = devm_gpiod_get_optional(dev, con_id: "powerdown" , |
|---|
| 1387 | GPIOD_FLAGS_BIT_NONEXCLUSIVE | GPIOD_OUT_HIGH); |
|---|
| 1388 | if (IS_ERR(ptr: wsa883x->sd_n)) { |
|---|
| 1389 | ret = dev_err_probe(dev, err: PTR_ERR(ptr: wsa883x->sd_n), |
|---|
| 1390 | fmt: "Shutdown Control GPIO not found\n" ); |
|---|
| 1391 | goto err; |
|---|
| 1392 | } |
|---|
| 1393 | |
|---|
| 1394 | dev_set_drvdata(dev, data: wsa883x); |
|---|
| 1395 | wsa883x->slave = pdev; |
|---|
| 1396 | wsa883x->dev = dev; |
|---|
| 1397 | wsa883x->sconfig.ch_count = 1; |
|---|
| 1398 | wsa883x->sconfig.bps = 1; |
|---|
| 1399 | wsa883x->sconfig.direction = SDW_DATA_DIR_RX; |
|---|
| 1400 | wsa883x->sconfig.type = SDW_STREAM_PDM; |
|---|
| 1401 | |
|---|
| 1402 | pdev->prop.sink_ports = GENMASK(WSA883X_MAX_SWR_PORTS, 0); |
|---|
| 1403 | pdev->prop.simple_clk_stop_capable = true; |
|---|
| 1404 | pdev->prop.sink_dpn_prop = wsa_sink_dpn_prop; |
|---|
| 1405 | pdev->prop.scp_int1_mask = SDW_SCP_INT1_BUS_CLASH | SDW_SCP_INT1_PARITY; |
|---|
| 1406 | gpiod_direction_output(desc: wsa883x->sd_n, value: 0); |
|---|
| 1407 | |
|---|
| 1408 | wsa883x->regmap = devm_regmap_init_sdw(pdev, &wsa883x_regmap_config); |
|---|
| 1409 | if (IS_ERR(ptr: wsa883x->regmap)) { |
|---|
| 1410 | gpiod_direction_output(desc: wsa883x->sd_n, value: 1); |
|---|
| 1411 | ret = dev_err_probe(dev, err: PTR_ERR(ptr: wsa883x->regmap), |
|---|
| 1412 | fmt: "regmap_init failed\n" ); |
|---|
| 1413 | goto err; |
|---|
| 1414 | } |
|---|
| 1415 | pm_runtime_set_autosuspend_delay(dev, delay: 3000); |
|---|
| 1416 | pm_runtime_use_autosuspend(dev); |
|---|
| 1417 | pm_runtime_mark_last_busy(dev); |
|---|
| 1418 | pm_runtime_set_active(dev); |
|---|
| 1419 | pm_runtime_enable(dev); |
|---|
| 1420 | |
|---|
| 1421 | ret = devm_snd_soc_register_component(dev, |
|---|
| 1422 | component_driver: &wsa883x_component_drv, |
|---|
| 1423 | dai_drv: wsa883x_dais, |
|---|
| 1424 | ARRAY_SIZE(wsa883x_dais)); |
|---|
| 1425 | err: |
|---|
| 1426 | if (ret) |
|---|
| 1427 | regulator_disable(regulator: wsa883x->vdd); |
|---|
| 1428 | |
|---|
| 1429 | return ret; |
|---|
| 1430 | |
|---|
| 1431 | } |
|---|
| 1432 | |
|---|
| 1433 | static int __maybe_unused wsa883x_runtime_suspend(struct device *dev) |
|---|
| 1434 | { |
|---|
| 1435 | struct regmap *regmap = dev_get_regmap(dev, NULL); |
|---|
| 1436 | |
|---|
| 1437 | regcache_cache_only(map: regmap, enable: true); |
|---|
| 1438 | regcache_mark_dirty(map: regmap); |
|---|
| 1439 | |
|---|
| 1440 | return 0; |
|---|
| 1441 | } |
|---|
| 1442 | |
|---|
| 1443 | static int __maybe_unused wsa883x_runtime_resume(struct device *dev) |
|---|
| 1444 | { |
|---|
| 1445 | struct regmap *regmap = dev_get_regmap(dev, NULL); |
|---|
| 1446 | |
|---|
| 1447 | regcache_cache_only(map: regmap, enable: false); |
|---|
| 1448 | regcache_sync(map: regmap); |
|---|
| 1449 | |
|---|
| 1450 | return 0; |
|---|
| 1451 | } |
|---|
| 1452 | |
|---|
| 1453 | static const struct dev_pm_ops wsa883x_pm_ops = { |
|---|
| 1454 | SET_RUNTIME_PM_OPS(wsa883x_runtime_suspend, wsa883x_runtime_resume, NULL) |
|---|
| 1455 | }; |
|---|
| 1456 | |
|---|
| 1457 | static const struct sdw_device_id wsa883x_swr_id[] = { |
|---|
| 1458 | SDW_SLAVE_ENTRY(0x0217, 0x0202, 0), |
|---|
| 1459 | {}, |
|---|
| 1460 | }; |
|---|
| 1461 | |
|---|
| 1462 | MODULE_DEVICE_TABLE(sdw, wsa883x_swr_id); |
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| 1463 | |
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| 1464 | static struct sdw_driver wsa883x_codec_driver = { |
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| 1465 | .driver = { |
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| 1466 | .name = "wsa883x-codec" , |
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| 1467 | .pm = &wsa883x_pm_ops, |
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| 1468 | .suppress_bind_attrs = true, |
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| 1469 | }, |
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| 1470 | .probe = wsa883x_probe, |
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| 1471 | .ops = &wsa883x_slave_ops, |
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| 1472 | .id_table = wsa883x_swr_id, |
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| 1473 | }; |
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| 1474 | |
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| 1475 | module_sdw_driver(wsa883x_codec_driver); |
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| 1476 | |
|---|
| 1477 | MODULE_DESCRIPTION("WSA883x codec driver" ); |
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| 1478 | MODULE_LICENSE("GPL" ); |
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| 1479 | |
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