1// SPDX-License-Identifier: GPL-2.0-only
2//
3// Copyright(c) 2021-2022 Intel Corporation. All rights reserved.
4//
5// Authors: Cezary Rojewski <cezary.rojewski@intel.com>
6// Amadeusz Slawinski <amadeuszx.slawinski@linux.intel.com>
7//
8// Special thanks to:
9// Krzysztof Hejmowski <krzysztof.hejmowski@intel.com>
10// Michal Sienkiewicz <michal.sienkiewicz@intel.com>
11// Filip Proborszcz
12//
13// for sharing Intel AudioDSP expertise and helping shape the very
14// foundation of this driver
15//
16
17#include <linux/module.h>
18#include <linux/pci.h>
19#include <sound/hda_codec.h>
20#include <sound/hda_i915.h>
21#include <sound/hda_register.h>
22#include <sound/hdaudio.h>
23#include <sound/hdaudio_ext.h>
24#include <sound/intel-dsp-config.h>
25#include <sound/intel-nhlt.h>
26#include "../../codecs/hda.h"
27#include "avs.h"
28#include "cldma.h"
29#include "messages.h"
30
31static u32 pgctl_mask = AZX_PGCTL_LSRMD_MASK;
32module_param(pgctl_mask, uint, 0444);
33MODULE_PARM_DESC(pgctl_mask, "PCI PGCTL policy override");
34
35static u32 cgctl_mask = AZX_CGCTL_MISCBDCGE_MASK;
36module_param(cgctl_mask, uint, 0444);
37MODULE_PARM_DESC(cgctl_mask, "PCI CGCTL policy override");
38
39static void
40avs_hda_update_config_dword(struct hdac_bus *bus, u32 reg, u32 mask, u32 value)
41{
42 struct pci_dev *pci = to_pci_dev(bus->dev);
43 u32 data;
44
45 pci_read_config_dword(dev: pci, where: reg, val: &data);
46 data &= ~mask;
47 data |= (value & mask);
48 pci_write_config_dword(dev: pci, where: reg, val: data);
49}
50
51void avs_hda_power_gating_enable(struct avs_dev *adev, bool enable)
52{
53 u32 value = enable ? 0 : pgctl_mask;
54
55 avs_hda_update_config_dword(bus: &adev->base.core, AZX_PCIREG_PGCTL, mask: pgctl_mask, value);
56}
57
58static void avs_hdac_clock_gating_enable(struct hdac_bus *bus, bool enable)
59{
60 u32 value = enable ? cgctl_mask : 0;
61
62 avs_hda_update_config_dword(bus, AZX_PCIREG_CGCTL, mask: cgctl_mask, value);
63}
64
65void avs_hda_clock_gating_enable(struct avs_dev *adev, bool enable)
66{
67 avs_hdac_clock_gating_enable(bus: &adev->base.core, enable);
68}
69
70void avs_hda_l1sen_enable(struct avs_dev *adev, bool enable)
71{
72 if (enable) {
73 if (atomic_inc_and_test(v: &adev->l1sen_counter))
74 snd_hdac_chip_updatel(&adev->base.core, VS_EM2, AZX_VS_EM2_L1SEN,
75 AZX_VS_EM2_L1SEN);
76 } else {
77 if (atomic_dec_return(v: &adev->l1sen_counter) == -1)
78 snd_hdac_chip_updatel(&adev->base.core, VS_EM2, AZX_VS_EM2_L1SEN, 0);
79 }
80}
81
82static int avs_hdac_bus_init_streams(struct hdac_bus *bus)
83{
84 unsigned int cp_streams, pb_streams;
85 unsigned int gcap;
86
87 gcap = snd_hdac_chip_readw(bus, GCAP);
88 cp_streams = (gcap >> 8) & 0x0F;
89 pb_streams = (gcap >> 12) & 0x0F;
90 bus->num_streams = cp_streams + pb_streams;
91
92 snd_hdac_ext_stream_init_all(bus, start_idx: 0, num_stream: cp_streams, dir: SNDRV_PCM_STREAM_CAPTURE);
93 snd_hdac_ext_stream_init_all(bus, start_idx: cp_streams, num_stream: pb_streams, dir: SNDRV_PCM_STREAM_PLAYBACK);
94
95 return snd_hdac_bus_alloc_stream_pages(bus);
96}
97
98static bool avs_hdac_bus_init_chip(struct hdac_bus *bus, bool full_reset)
99{
100 struct hdac_ext_link *hlink;
101 bool ret;
102
103 avs_hdac_clock_gating_enable(bus, enable: false);
104 ret = snd_hdac_bus_init_chip(bus, full_reset);
105
106 /* Reset stream-to-link mapping */
107 list_for_each_entry(hlink, &bus->hlink_list, list)
108 writel(val: 0, addr: hlink->ml_addr + AZX_REG_ML_LOSIDV);
109
110 avs_hdac_clock_gating_enable(bus, enable: true);
111
112 /* Set DUM bit to address incorrect position reporting for capture
113 * streams. In order to do so, CTRL needs to be out of reset state
114 */
115 snd_hdac_chip_updatel(bus, VS_EM2, AZX_VS_EM2_DUM, AZX_VS_EM2_DUM);
116
117 return ret;
118}
119
120static int probe_codec(struct hdac_bus *bus, int addr)
121{
122 struct hda_codec *codec;
123 unsigned int cmd = (addr << 28) | (AC_NODE_ROOT << 20) |
124 (AC_VERB_PARAMETERS << 8) | AC_PAR_VENDOR_ID;
125 unsigned int res = -1;
126 int ret;
127
128 mutex_lock(&bus->cmd_mutex);
129 snd_hdac_bus_send_cmd(bus, val: cmd);
130 snd_hdac_bus_get_response(bus, addr, res: &res);
131 mutex_unlock(lock: &bus->cmd_mutex);
132 if (res == -1)
133 return -EIO;
134
135 dev_dbg(bus->dev, "codec #%d probed OK: 0x%x\n", addr, res);
136
137 codec = snd_hda_codec_device_init(to_hda_bus(bus), codec_addr: addr, fmt: "hdaudioB%dD%d", bus->idx, addr);
138 if (IS_ERR(ptr: codec)) {
139 dev_err(bus->dev, "init codec failed: %ld\n", PTR_ERR(codec));
140 return PTR_ERR(ptr: codec);
141 }
142 /*
143 * Allow avs_core suspend by forcing suspended state on all
144 * of its codec child devices. Component interested in
145 * dealing with hda codecs directly takes pm responsibilities
146 */
147 pm_runtime_set_suspended(hda_codec_dev(codec));
148
149 /* configure effectively creates new ASoC component */
150 ret = snd_hda_codec_configure(codec);
151 if (ret < 0) {
152 dev_warn(bus->dev, "failed to config codec #%d: %d\n", addr, ret);
153 return ret;
154 }
155
156 return 0;
157}
158
159static void avs_hdac_bus_probe_codecs(struct hdac_bus *bus)
160{
161 int ret, c;
162
163 /* First try to probe all given codec slots */
164 for (c = 0; c < HDA_MAX_CODECS; c++) {
165 if (!(bus->codec_mask & BIT(c)))
166 continue;
167
168 ret = probe_codec(bus, addr: c);
169 /* Ignore codecs with no supporting driver. */
170 if (!ret || ret == -ENODEV)
171 continue;
172
173 /*
174 * Some BIOSen give you wrong codec addresses
175 * that don't exist
176 */
177 dev_warn(bus->dev, "Codec #%d probe error; disabling it...\n", c);
178 bus->codec_mask &= ~BIT(c);
179 /*
180 * More badly, accessing to a non-existing
181 * codec often screws up the controller bus,
182 * and disturbs the further communications.
183 * Thus if an error occurs during probing,
184 * better to reset the controller bus to get
185 * back to the sanity state.
186 */
187 snd_hdac_bus_stop_chip(bus);
188 avs_hdac_bus_init_chip(bus, full_reset: true);
189 }
190}
191
192static void avs_hda_probe_work(struct work_struct *work)
193{
194 struct avs_dev *adev = container_of(work, struct avs_dev, probe_work);
195 struct hdac_bus *bus = &adev->base.core;
196 struct hdac_ext_link *hlink;
197 int ret;
198
199 pm_runtime_set_active(dev: bus->dev); /* clear runtime_error flag */
200
201 snd_hdac_display_power(bus, HDA_CODEC_IDX_CONTROLLER, enable: true);
202 avs_hdac_bus_init_chip(bus, full_reset: true);
203 avs_hdac_bus_probe_codecs(bus);
204 snd_hdac_display_power(bus, HDA_CODEC_IDX_CONTROLLER, enable: false);
205
206 /* with all codecs probed, links can be powered down */
207 list_for_each_entry(hlink, &bus->hlink_list, list)
208 snd_hdac_ext_bus_link_put(bus, hlink);
209
210 snd_hdac_ext_bus_ppcap_enable(chip: bus, enable: true);
211 snd_hdac_ext_bus_ppcap_int_enable(chip: bus, enable: true);
212
213 ret = avs_dsp_first_boot_firmware(adev);
214 if (ret < 0)
215 return;
216
217 adev->nhlt = intel_nhlt_init(dev: adev->dev);
218 if (!adev->nhlt)
219 dev_info(bus->dev, "platform has no NHLT\n");
220 avs_debugfs_init(adev);
221
222 avs_register_all_boards(adev);
223
224 /* configure PM */
225 pm_runtime_set_autosuspend_delay(dev: bus->dev, delay: 2000);
226 pm_runtime_use_autosuspend(dev: bus->dev);
227 pm_runtime_mark_last_busy(dev: bus->dev);
228 pm_runtime_put_autosuspend(dev: bus->dev);
229 pm_runtime_allow(dev: bus->dev);
230}
231
232static void hdac_stream_update_pos(struct hdac_stream *stream, u64 buffer_size)
233{
234 u64 prev_pos, pos, num_bytes;
235
236 div64_u64_rem(dividend: stream->curr_pos, divisor: buffer_size, remainder: &prev_pos);
237 pos = snd_hdac_stream_get_pos_posbuf(stream);
238
239 if (pos < prev_pos)
240 num_bytes = (buffer_size - prev_pos) + pos;
241 else
242 num_bytes = pos - prev_pos;
243
244 stream->curr_pos += num_bytes;
245}
246
247/* called from IRQ */
248static void hdac_update_stream(struct hdac_bus *bus, struct hdac_stream *stream)
249{
250 if (stream->substream) {
251 snd_pcm_period_elapsed(substream: stream->substream);
252 } else if (stream->cstream) {
253 u64 buffer_size = stream->cstream->runtime->buffer_size;
254
255 hdac_stream_update_pos(stream, buffer_size);
256 snd_compr_fragment_elapsed(stream: stream->cstream);
257 }
258}
259
260static irqreturn_t hdac_bus_irq_handler(int irq, void *context)
261{
262 struct hdac_bus *bus = context;
263 u32 mask, int_enable;
264 u32 status;
265 int ret = IRQ_NONE;
266
267 if (!pm_runtime_active(dev: bus->dev))
268 return ret;
269
270 spin_lock(lock: &bus->reg_lock);
271
272 status = snd_hdac_chip_readl(bus, INTSTS);
273 if (status == 0 || status == UINT_MAX) {
274 spin_unlock(lock: &bus->reg_lock);
275 return ret;
276 }
277
278 /* clear rirb int */
279 status = snd_hdac_chip_readb(bus, RIRBSTS);
280 if (status & RIRB_INT_MASK) {
281 if (status & RIRB_INT_RESPONSE)
282 snd_hdac_bus_update_rirb(bus);
283 snd_hdac_chip_writeb(bus, RIRBSTS, RIRB_INT_MASK);
284 }
285
286 mask = (0x1 << bus->num_streams) - 1;
287
288 status = snd_hdac_chip_readl(bus, INTSTS);
289 status &= mask;
290 if (status) {
291 /* Disable stream interrupts; Re-enable in bottom half */
292 int_enable = snd_hdac_chip_readl(bus, INTCTL);
293 snd_hdac_chip_writel(bus, INTCTL, (int_enable & (~mask)));
294 ret = IRQ_WAKE_THREAD;
295 } else {
296 ret = IRQ_HANDLED;
297 }
298
299 spin_unlock(lock: &bus->reg_lock);
300 return ret;
301}
302
303static irqreturn_t hdac_bus_irq_thread(int irq, void *context)
304{
305 struct hdac_bus *bus = context;
306 u32 status;
307 u32 int_enable;
308 u32 mask;
309 unsigned long flags;
310
311 status = snd_hdac_chip_readl(bus, INTSTS);
312
313 snd_hdac_bus_handle_stream_irq(bus, status, ack: hdac_update_stream);
314
315 /* Re-enable stream interrupts */
316 mask = (0x1 << bus->num_streams) - 1;
317 spin_lock_irqsave(&bus->reg_lock, flags);
318 int_enable = snd_hdac_chip_readl(bus, INTCTL);
319 snd_hdac_chip_writel(bus, INTCTL, (int_enable | mask));
320 spin_unlock_irqrestore(lock: &bus->reg_lock, flags);
321
322 return IRQ_HANDLED;
323}
324
325static irqreturn_t avs_dsp_irq_handler(int irq, void *dev_id)
326{
327 struct avs_dev *adev = dev_id;
328
329 return avs_dsp_op(adev, irq_handler);
330}
331
332static irqreturn_t avs_dsp_irq_thread(int irq, void *dev_id)
333{
334 struct avs_dev *adev = dev_id;
335
336 return avs_dsp_op(adev, irq_thread);
337}
338
339static int avs_hdac_acquire_irq(struct avs_dev *adev)
340{
341 struct hdac_bus *bus = &adev->base.core;
342 struct pci_dev *pci = to_pci_dev(bus->dev);
343 int ret;
344
345 /* request one and check that we only got one interrupt */
346 ret = pci_alloc_irq_vectors(dev: pci, min_vecs: 1, max_vecs: 1, PCI_IRQ_MSI | PCI_IRQ_LEGACY);
347 if (ret != 1) {
348 dev_err(adev->dev, "Failed to allocate IRQ vector: %d\n", ret);
349 return ret;
350 }
351
352 ret = pci_request_irq(dev: pci, nr: 0, handler: hdac_bus_irq_handler, thread_fn: hdac_bus_irq_thread, dev_id: bus,
353 KBUILD_MODNAME);
354 if (ret < 0) {
355 dev_err(adev->dev, "Failed to request stream IRQ handler: %d\n", ret);
356 goto free_vector;
357 }
358
359 ret = pci_request_irq(dev: pci, nr: 0, handler: avs_dsp_irq_handler, thread_fn: avs_dsp_irq_thread, dev_id: adev,
360 KBUILD_MODNAME);
361 if (ret < 0) {
362 dev_err(adev->dev, "Failed to request IPC IRQ handler: %d\n", ret);
363 goto free_stream_irq;
364 }
365
366 return 0;
367
368free_stream_irq:
369 pci_free_irq(dev: pci, nr: 0, dev_id: bus);
370free_vector:
371 pci_free_irq_vectors(dev: pci);
372 return ret;
373}
374
375static int avs_bus_init(struct avs_dev *adev, struct pci_dev *pci, const struct pci_device_id *id)
376{
377 struct hda_bus *bus = &adev->base;
378 struct avs_ipc *ipc;
379 struct device *dev = &pci->dev;
380 int ret;
381
382 ret = snd_hdac_ext_bus_init(bus: &bus->core, dev, NULL, ext_ops: &soc_hda_ext_bus_ops);
383 if (ret < 0)
384 return ret;
385
386 bus->core.use_posbuf = 1;
387 bus->core.bdl_pos_adj = 0;
388 bus->core.sync_write = 1;
389 bus->pci = pci;
390 bus->mixer_assigned = -1;
391 mutex_init(&bus->prepare_mutex);
392
393 ipc = devm_kzalloc(dev, size: sizeof(*ipc), GFP_KERNEL);
394 if (!ipc)
395 return -ENOMEM;
396 ret = avs_ipc_init(ipc, dev);
397 if (ret < 0)
398 return ret;
399
400 adev->modcfg_buf = devm_kzalloc(dev, AVS_MAILBOX_SIZE, GFP_KERNEL);
401 if (!adev->modcfg_buf)
402 return -ENOMEM;
403
404 adev->dev = dev;
405 adev->spec = (const struct avs_spec *)id->driver_data;
406 adev->ipc = ipc;
407 adev->hw_cfg.dsp_cores = hweight_long(AVS_MAIN_CORE_MASK);
408 INIT_WORK(&adev->probe_work, avs_hda_probe_work);
409 INIT_LIST_HEAD(list: &adev->comp_list);
410 INIT_LIST_HEAD(list: &adev->path_list);
411 INIT_LIST_HEAD(list: &adev->fw_list);
412 init_completion(x: &adev->fw_ready);
413 spin_lock_init(&adev->path_list_lock);
414 mutex_init(&adev->modres_mutex);
415 mutex_init(&adev->comp_list_mutex);
416 mutex_init(&adev->path_mutex);
417
418 return 0;
419}
420
421static int avs_pci_probe(struct pci_dev *pci, const struct pci_device_id *id)
422{
423 struct hdac_bus *bus;
424 struct avs_dev *adev;
425 struct device *dev = &pci->dev;
426 int ret;
427
428 ret = snd_intel_dsp_driver_probe(pci);
429 if (ret != SND_INTEL_DSP_DRIVER_ANY && ret != SND_INTEL_DSP_DRIVER_AVS)
430 return -ENODEV;
431
432 ret = pcim_enable_device(pdev: pci);
433 if (ret < 0)
434 return ret;
435
436 adev = devm_kzalloc(dev, size: sizeof(*adev), GFP_KERNEL);
437 if (!adev)
438 return -ENOMEM;
439 ret = avs_bus_init(adev, pci, id);
440 if (ret < 0) {
441 dev_err(dev, "failed to init avs bus: %d\n", ret);
442 return ret;
443 }
444
445 ret = pci_request_regions(pci, "AVS HDAudio");
446 if (ret < 0)
447 return ret;
448
449 bus = &adev->base.core;
450 bus->addr = pci_resource_start(pci, 0);
451 bus->remap_addr = pci_ioremap_bar(pdev: pci, bar: 0);
452 if (!bus->remap_addr) {
453 dev_err(bus->dev, "ioremap error\n");
454 ret = -ENXIO;
455 goto err_remap_bar0;
456 }
457
458 adev->dsp_ba = pci_ioremap_bar(pdev: pci, bar: 4);
459 if (!adev->dsp_ba) {
460 dev_err(bus->dev, "ioremap error\n");
461 ret = -ENXIO;
462 goto err_remap_bar4;
463 }
464
465 snd_hdac_bus_parse_capabilities(bus);
466 if (bus->mlcap)
467 snd_hdac_ext_bus_get_ml_capabilities(bus);
468
469 if (dma_set_mask_and_coherent(dev, DMA_BIT_MASK(64)))
470 dma_set_mask_and_coherent(dev, DMA_BIT_MASK(32));
471 dma_set_max_seg_size(dev, UINT_MAX);
472
473 ret = avs_hdac_bus_init_streams(bus);
474 if (ret < 0) {
475 dev_err(dev, "failed to init streams: %d\n", ret);
476 goto err_init_streams;
477 }
478
479 ret = avs_hdac_acquire_irq(adev);
480 if (ret < 0) {
481 dev_err(bus->dev, "failed to acquire irq: %d\n", ret);
482 goto err_acquire_irq;
483 }
484
485 pci_set_master(dev: pci);
486 pci_set_drvdata(pdev: pci, data: bus);
487 device_disable_async_suspend(dev);
488
489 ret = snd_hdac_i915_init(bus);
490 if (ret == -EPROBE_DEFER)
491 goto err_i915_init;
492 else if (ret < 0)
493 dev_info(bus->dev, "i915 init unsuccessful: %d\n", ret);
494
495 schedule_work(work: &adev->probe_work);
496
497 return 0;
498
499err_i915_init:
500 pci_free_irq(dev: pci, nr: 0, dev_id: adev);
501 pci_free_irq(dev: pci, nr: 0, dev_id: bus);
502 pci_free_irq_vectors(dev: pci);
503 pci_clear_master(dev: pci);
504 pci_set_drvdata(pdev: pci, NULL);
505err_acquire_irq:
506 snd_hdac_bus_free_stream_pages(bus);
507 snd_hdac_ext_stream_free_all(bus);
508err_init_streams:
509 iounmap(addr: adev->dsp_ba);
510err_remap_bar4:
511 iounmap(addr: bus->remap_addr);
512err_remap_bar0:
513 pci_release_regions(pci);
514 return ret;
515}
516
517static void avs_pci_shutdown(struct pci_dev *pci)
518{
519 struct hdac_bus *bus = pci_get_drvdata(pdev: pci);
520 struct avs_dev *adev = hdac_to_avs(bus);
521
522 cancel_work_sync(work: &adev->probe_work);
523 avs_ipc_block(ipc: adev->ipc);
524
525 snd_hdac_stop_streams(bus);
526 avs_dsp_op(adev, int_control, false);
527 snd_hdac_ext_bus_ppcap_int_enable(chip: bus, enable: false);
528 snd_hdac_ext_bus_link_power_down_all(bus);
529
530 snd_hdac_bus_stop_chip(bus);
531 snd_hdac_display_power(bus, HDA_CODEC_IDX_CONTROLLER, enable: false);
532
533 if (avs_platattr_test(adev, CLDMA))
534 pci_free_irq(dev: pci, nr: 0, dev_id: &code_loader);
535 pci_free_irq(dev: pci, nr: 0, dev_id: adev);
536 pci_free_irq(dev: pci, nr: 0, dev_id: bus);
537 pci_free_irq_vectors(dev: pci);
538}
539
540static void avs_pci_remove(struct pci_dev *pci)
541{
542 struct hdac_device *hdev, *save;
543 struct hdac_bus *bus = pci_get_drvdata(pdev: pci);
544 struct avs_dev *adev = hdac_to_avs(bus);
545
546 cancel_work_sync(work: &adev->probe_work);
547 avs_ipc_block(ipc: adev->ipc);
548
549 avs_unregister_all_boards(adev);
550
551 avs_debugfs_exit(adev);
552 if (adev->nhlt)
553 intel_nhlt_free(addr: adev->nhlt);
554
555 if (avs_platattr_test(adev, CLDMA))
556 hda_cldma_free(cl: &code_loader);
557
558 snd_hdac_stop_streams_and_chip(bus);
559 avs_dsp_op(adev, int_control, false);
560 snd_hdac_ext_bus_ppcap_int_enable(chip: bus, enable: false);
561
562 /* it is safe to remove all codecs from the system now */
563 list_for_each_entry_safe(hdev, save, &bus->codec_list, list)
564 snd_hda_codec_unregister(hdac_to_hda_codec(hdev));
565
566 snd_hdac_bus_free_stream_pages(bus);
567 snd_hdac_ext_stream_free_all(bus);
568 /* reverse ml_capabilities */
569 snd_hdac_ext_link_free_all(bus);
570 snd_hdac_ext_bus_exit(bus);
571
572 avs_dsp_core_disable(adev, GENMASK(adev->hw_cfg.dsp_cores - 1, 0));
573 snd_hdac_ext_bus_ppcap_enable(chip: bus, enable: false);
574
575 /* snd_hdac_stop_streams_and_chip does that already? */
576 snd_hdac_bus_stop_chip(bus);
577 snd_hdac_display_power(bus, HDA_CODEC_IDX_CONTROLLER, enable: false);
578 if (bus->audio_component)
579 snd_hdac_i915_exit(bus);
580
581 avs_module_info_free(adev);
582 pci_free_irq(dev: pci, nr: 0, dev_id: adev);
583 pci_free_irq(dev: pci, nr: 0, dev_id: bus);
584 pci_free_irq_vectors(dev: pci);
585 iounmap(addr: bus->remap_addr);
586 iounmap(addr: adev->dsp_ba);
587 pci_release_regions(pci);
588
589 /* Firmware is not needed anymore */
590 avs_release_firmwares(adev);
591
592 /* pm_runtime_forbid() can rpm_resume() which we do not want */
593 pm_runtime_disable(dev: &pci->dev);
594 pm_runtime_forbid(dev: &pci->dev);
595 pm_runtime_enable(dev: &pci->dev);
596 pm_runtime_get_noresume(dev: &pci->dev);
597}
598
599static int avs_suspend_standby(struct avs_dev *adev)
600{
601 struct hdac_bus *bus = &adev->base.core;
602 struct pci_dev *pci = adev->base.pci;
603
604 if (bus->cmd_dma_state)
605 snd_hdac_bus_stop_cmd_io(bus);
606
607 snd_hdac_ext_bus_link_power_down_all(bus);
608
609 enable_irq_wake(irq: pci->irq);
610 pci_save_state(dev: pci);
611
612 return 0;
613}
614
615static int __maybe_unused avs_suspend_common(struct avs_dev *adev, bool low_power)
616{
617 struct hdac_bus *bus = &adev->base.core;
618 int ret;
619
620 flush_work(work: &adev->probe_work);
621 if (low_power && adev->num_lp_paths)
622 return avs_suspend_standby(adev);
623
624 snd_hdac_ext_bus_link_power_down_all(bus);
625
626 ret = avs_ipc_set_dx(adev, AVS_MAIN_CORE_MASK, powerup: false);
627 /*
628 * pm_runtime is blocked on DSP failure but system-wide suspend is not.
629 * Do not block entire system from suspending if that's the case.
630 */
631 if (ret && ret != -EPERM) {
632 dev_err(adev->dev, "set dx failed: %d\n", ret);
633 return AVS_IPC_RET(ret);
634 }
635
636 avs_ipc_block(ipc: adev->ipc);
637 avs_dsp_op(adev, int_control, false);
638 snd_hdac_ext_bus_ppcap_int_enable(chip: bus, enable: false);
639
640 ret = avs_dsp_core_disable(adev, AVS_MAIN_CORE_MASK);
641 if (ret < 0) {
642 dev_err(adev->dev, "core_mask %ld disable failed: %d\n", AVS_MAIN_CORE_MASK, ret);
643 return ret;
644 }
645
646 snd_hdac_ext_bus_ppcap_enable(chip: bus, enable: false);
647 /* disable LP SRAM retention */
648 avs_hda_power_gating_enable(adev, enable: false);
649 snd_hdac_bus_stop_chip(bus);
650 /* disable CG when putting controller to reset */
651 avs_hdac_clock_gating_enable(bus, enable: false);
652 snd_hdac_bus_enter_link_reset(bus);
653 avs_hdac_clock_gating_enable(bus, enable: true);
654
655 snd_hdac_display_power(bus, HDA_CODEC_IDX_CONTROLLER, enable: false);
656
657 return 0;
658}
659
660static int avs_resume_standby(struct avs_dev *adev)
661{
662 struct hdac_bus *bus = &adev->base.core;
663 struct pci_dev *pci = adev->base.pci;
664
665 pci_restore_state(dev: pci);
666 disable_irq_wake(irq: pci->irq);
667
668 snd_hdac_ext_bus_link_power_up_all(bus);
669
670 if (bus->cmd_dma_state)
671 snd_hdac_bus_init_cmd_io(bus);
672
673 return 0;
674}
675
676static int __maybe_unused avs_resume_common(struct avs_dev *adev, bool low_power, bool purge)
677{
678 struct hdac_bus *bus = &adev->base.core;
679 int ret;
680
681 if (low_power && adev->num_lp_paths)
682 return avs_resume_standby(adev);
683
684 snd_hdac_display_power(bus, HDA_CODEC_IDX_CONTROLLER, enable: true);
685 avs_hdac_bus_init_chip(bus, full_reset: true);
686
687 snd_hdac_ext_bus_ppcap_enable(chip: bus, enable: true);
688 snd_hdac_ext_bus_ppcap_int_enable(chip: bus, enable: true);
689
690 ret = avs_dsp_boot_firmware(adev, purge);
691 if (ret < 0) {
692 dev_err(adev->dev, "firmware boot failed: %d\n", ret);
693 return ret;
694 }
695
696 return 0;
697}
698
699static int __maybe_unused avs_suspend(struct device *dev)
700{
701 return avs_suspend_common(to_avs_dev(dev), low_power: true);
702}
703
704static int __maybe_unused avs_resume(struct device *dev)
705{
706 return avs_resume_common(to_avs_dev(dev), low_power: true, purge: true);
707}
708
709static int __maybe_unused avs_runtime_suspend(struct device *dev)
710{
711 return avs_suspend_common(to_avs_dev(dev), low_power: true);
712}
713
714static int __maybe_unused avs_runtime_resume(struct device *dev)
715{
716 return avs_resume_common(to_avs_dev(dev), low_power: true, purge: false);
717}
718
719static int __maybe_unused avs_freeze(struct device *dev)
720{
721 return avs_suspend_common(to_avs_dev(dev), low_power: false);
722}
723static int __maybe_unused avs_thaw(struct device *dev)
724{
725 return avs_resume_common(to_avs_dev(dev), low_power: false, purge: true);
726}
727
728static int __maybe_unused avs_poweroff(struct device *dev)
729{
730 return avs_suspend_common(to_avs_dev(dev), low_power: false);
731}
732
733static int __maybe_unused avs_restore(struct device *dev)
734{
735 return avs_resume_common(to_avs_dev(dev), low_power: false, purge: true);
736}
737
738static const struct dev_pm_ops avs_dev_pm = {
739 .suspend = avs_suspend,
740 .resume = avs_resume,
741 .freeze = avs_freeze,
742 .thaw = avs_thaw,
743 .poweroff = avs_poweroff,
744 .restore = avs_restore,
745 SET_RUNTIME_PM_OPS(avs_runtime_suspend, avs_runtime_resume, NULL)
746};
747
748static const struct avs_sram_spec skl_sram_spec = {
749 .base_offset = SKL_ADSP_SRAM_BASE_OFFSET,
750 .window_size = SKL_ADSP_SRAM_WINDOW_SIZE,
751 .rom_status_offset = SKL_ADSP_SRAM_BASE_OFFSET,
752};
753
754static const struct avs_sram_spec apl_sram_spec = {
755 .base_offset = APL_ADSP_SRAM_BASE_OFFSET,
756 .window_size = APL_ADSP_SRAM_WINDOW_SIZE,
757 .rom_status_offset = APL_ADSP_SRAM_BASE_OFFSET,
758};
759
760static const struct avs_hipc_spec skl_hipc_spec = {
761 .req_offset = SKL_ADSP_REG_HIPCI,
762 .req_ext_offset = SKL_ADSP_REG_HIPCIE,
763 .req_busy_mask = SKL_ADSP_HIPCI_BUSY,
764 .ack_offset = SKL_ADSP_REG_HIPCIE,
765 .ack_done_mask = SKL_ADSP_HIPCIE_DONE,
766 .rsp_offset = SKL_ADSP_REG_HIPCT,
767 .rsp_busy_mask = SKL_ADSP_HIPCT_BUSY,
768 .ctl_offset = SKL_ADSP_REG_HIPCCTL,
769};
770
771static const struct avs_hipc_spec cnl_hipc_spec = {
772 .req_offset = CNL_ADSP_REG_HIPCIDR,
773 .req_ext_offset = CNL_ADSP_REG_HIPCIDD,
774 .req_busy_mask = CNL_ADSP_HIPCIDR_BUSY,
775 .ack_offset = CNL_ADSP_REG_HIPCIDA,
776 .ack_done_mask = CNL_ADSP_HIPCIDA_DONE,
777 .rsp_offset = CNL_ADSP_REG_HIPCTDR,
778 .rsp_busy_mask = CNL_ADSP_HIPCTDR_BUSY,
779 .ctl_offset = CNL_ADSP_REG_HIPCCTL,
780};
781
782static const struct avs_spec skl_desc = {
783 .name = "skl",
784 .min_fw_version = { 9, 21, 0, 4732 },
785 .dsp_ops = &avs_skl_dsp_ops,
786 .core_init_mask = 1,
787 .attributes = AVS_PLATATTR_CLDMA,
788 .sram = &skl_sram_spec,
789 .hipc = &skl_hipc_spec,
790};
791
792static const struct avs_spec apl_desc = {
793 .name = "apl",
794 .min_fw_version = { 9, 22, 1, 4323 },
795 .dsp_ops = &avs_apl_dsp_ops,
796 .core_init_mask = 3,
797 .attributes = AVS_PLATATTR_IMR,
798 .sram = &apl_sram_spec,
799 .hipc = &skl_hipc_spec,
800};
801
802static const struct avs_spec cnl_desc = {
803 .name = "cnl",
804 .min_fw_version = { 10, 23, 0, 5314 },
805 .dsp_ops = &avs_cnl_dsp_ops,
806 .core_init_mask = 1,
807 .attributes = AVS_PLATATTR_IMR,
808 .sram = &apl_sram_spec,
809 .hipc = &cnl_hipc_spec,
810};
811
812static const struct avs_spec icl_desc = {
813 .name = "icl",
814 .min_fw_version = { 10, 23, 0, 5040 },
815 .dsp_ops = &avs_icl_dsp_ops,
816 .core_init_mask = 1,
817 .attributes = AVS_PLATATTR_IMR,
818 .sram = &apl_sram_spec,
819 .hipc = &cnl_hipc_spec,
820};
821
822static const struct avs_spec jsl_desc = {
823 .name = "jsl",
824 .min_fw_version = { 10, 26, 0, 5872 },
825 .dsp_ops = &avs_icl_dsp_ops,
826 .core_init_mask = 1,
827 .attributes = AVS_PLATATTR_IMR,
828 .sram = &apl_sram_spec,
829 .hipc = &cnl_hipc_spec,
830};
831
832#define AVS_TGL_BASED_SPEC(sname) \
833static const struct avs_spec sname##_desc = { \
834 .name = #sname, \
835 .min_fw_version = { 10, 29, 0, 5646 }, \
836 .dsp_ops = &avs_tgl_dsp_ops, \
837 .core_init_mask = 1, \
838 .attributes = AVS_PLATATTR_IMR, \
839 .sram = &apl_sram_spec, \
840 .hipc = &cnl_hipc_spec, \
841}
842
843AVS_TGL_BASED_SPEC(lkf);
844AVS_TGL_BASED_SPEC(tgl);
845AVS_TGL_BASED_SPEC(ehl);
846AVS_TGL_BASED_SPEC(adl);
847AVS_TGL_BASED_SPEC(adl_n);
848
849static const struct pci_device_id avs_ids[] = {
850 { PCI_DEVICE_DATA(INTEL, HDA_SKL_LP, &skl_desc) },
851 { PCI_DEVICE_DATA(INTEL, HDA_SKL, &skl_desc) },
852 { PCI_DEVICE_DATA(INTEL, HDA_KBL_LP, &skl_desc) },
853 { PCI_DEVICE_DATA(INTEL, HDA_KBL, &skl_desc) },
854 { PCI_DEVICE_DATA(INTEL, HDA_KBL_H, &skl_desc) },
855 { PCI_DEVICE_DATA(INTEL, HDA_CML_S, &skl_desc) },
856 { PCI_DEVICE_DATA(INTEL, HDA_APL, &apl_desc) },
857 { PCI_DEVICE_DATA(INTEL, HDA_GML, &apl_desc) },
858 { PCI_DEVICE_DATA(INTEL, HDA_CNL_LP, &cnl_desc) },
859 { PCI_DEVICE_DATA(INTEL, HDA_CNL_H, &cnl_desc) },
860 { PCI_DEVICE_DATA(INTEL, HDA_CML_LP, &cnl_desc) },
861 { PCI_DEVICE_DATA(INTEL, HDA_CML_H, &cnl_desc) },
862 { PCI_DEVICE_DATA(INTEL, HDA_RKL_S, &cnl_desc) },
863 { PCI_DEVICE_DATA(INTEL, HDA_ICL_LP, &icl_desc) },
864 { PCI_DEVICE_DATA(INTEL, HDA_ICL_N, &icl_desc) },
865 { PCI_DEVICE_DATA(INTEL, HDA_ICL_H, &icl_desc) },
866 { PCI_DEVICE_DATA(INTEL, HDA_JSL_N, &jsl_desc) },
867 { PCI_DEVICE_DATA(INTEL, HDA_LKF, &lkf_desc) },
868 { PCI_DEVICE_DATA(INTEL, HDA_TGL_LP, &tgl_desc) },
869 { PCI_DEVICE_DATA(INTEL, HDA_TGL_H, &tgl_desc) },
870 { PCI_DEVICE_DATA(INTEL, HDA_CML_R, &tgl_desc) },
871 { PCI_DEVICE_DATA(INTEL, HDA_EHL_0, &ehl_desc) },
872 { PCI_DEVICE_DATA(INTEL, HDA_EHL_3, &ehl_desc) },
873 { PCI_DEVICE_DATA(INTEL, HDA_ADL_S, &adl_desc) },
874 { PCI_DEVICE_DATA(INTEL, HDA_ADL_P, &adl_desc) },
875 { PCI_DEVICE_DATA(INTEL, HDA_ADL_PS, &adl_desc) },
876 { PCI_DEVICE_DATA(INTEL, HDA_ADL_M, &adl_desc) },
877 { PCI_DEVICE_DATA(INTEL, HDA_ADL_PX, &adl_desc) },
878 { PCI_DEVICE_DATA(INTEL, HDA_ADL_N, &adl_n_desc) },
879 { PCI_DEVICE_DATA(INTEL, HDA_RPL_S, &adl_desc) },
880 { PCI_DEVICE_DATA(INTEL, HDA_RPL_P_0, &adl_desc) },
881 { PCI_DEVICE_DATA(INTEL, HDA_RPL_P_1, &adl_desc) },
882 { PCI_DEVICE_DATA(INTEL, HDA_RPL_M, &adl_desc) },
883 { PCI_DEVICE_DATA(INTEL, HDA_RPL_PX, &adl_desc) },
884 { 0 }
885};
886MODULE_DEVICE_TABLE(pci, avs_ids);
887
888static struct pci_driver avs_pci_driver = {
889 .name = KBUILD_MODNAME,
890 .id_table = avs_ids,
891 .probe = avs_pci_probe,
892 .remove = avs_pci_remove,
893 .shutdown = avs_pci_shutdown,
894 .dev_groups = avs_attr_groups,
895 .driver = {
896 .pm = &avs_dev_pm,
897 },
898};
899module_pci_driver(avs_pci_driver);
900
901MODULE_AUTHOR("Cezary Rojewski <cezary.rojewski@intel.com>");
902MODULE_AUTHOR("Amadeusz Slawinski <amadeuszx.slawinski@linux.intel.com>");
903MODULE_DESCRIPTION("Intel cAVS sound driver");
904MODULE_LICENSE("GPL");
905

source code of linux/sound/soc/intel/avs/core.c