1/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */
2/*
3 * This file is provided under a dual BSD/GPLv2 license. When using or
4 * redistributing this file, you may do so under either license.
5 *
6 * Copyright(c) 2021, 2023 Advanced Micro Devices, Inc. All rights reserved.
7 *
8 * Author: Ajit Kumar Pandey <AjitKumar.Pandey@amd.com>
9 */
10
11#ifndef __SOF_AMD_ACP_H
12#define __SOF_AMD_ACP_H
13
14#include <linux/dmi.h>
15#include <linux/soundwire/sdw_amd.h>
16#include "../sof-priv.h"
17#include "../sof-audio.h"
18
19#define ACP_MAX_STREAM 8
20
21#define ACP_DSP_BAR 0
22
23#define ACP_HW_SEM_RETRY_COUNT 10000
24#define ACP_REG_POLL_INTERVAL 500
25#define ACP_REG_POLL_TIMEOUT_US 2000
26#define ACP_DMA_COMPLETE_TIMEOUT_US 5000
27
28#define ACP_PGFSM_CNTL_POWER_ON_MASK 0x01
29#define ACP_PGFSM_STATUS_MASK 0x03
30#define ACP_POWERED_ON 0x00
31#define ACP_ASSERT_RESET 0x01
32#define ACP_RELEASE_RESET 0x00
33#define ACP_SOFT_RESET_DONE_MASK 0x00010001
34#define ACP_DSP_ASSERT_RESET 0x04
35#define ACP_DSP_RELEASE_RESET 0x00
36#define ACP_DSP_SOFT_RESET_DONE_MASK 0x00050004
37
38#define ACP_DSP_INTR_EN_MASK 0x00000001
39#define ACP3X_SRAM_PTE_OFFSET 0x02050000
40#define ACP5X_SRAM_PTE_OFFSET 0x02050000
41#define ACP6X_SRAM_PTE_OFFSET 0x03800000
42#define PAGE_SIZE_4K_ENABLE 0x2
43#define ACP_PAGE_SIZE 0x1000
44#define ACP_DMA_CH_RUN 0x02
45#define ACP_MAX_DESC_CNT 0x02
46#define DSP_FW_RUN_ENABLE 0x01
47#define ACP_SHA_RUN 0x01
48#define ACP_SHA_RESET 0x02
49#define ACP_SHA_HEADER 0x01
50#define ACP_DMA_CH_RST 0x01
51#define ACP_DMA_CH_GRACEFUL_RST_EN 0x10
52#define ACP_ATU_CACHE_INVALID 0x01
53#define ACP_MAX_DESC 128
54#define ACPBUS_REG_BASE_OFFSET ACP_DMA_CNTL_0
55
56#define ACP_DEFAULT_DRAM_LENGTH 0x00080000
57#define ACP3X_SCRATCH_MEMORY_ADDRESS 0x02050000
58#define ACP_SYSTEM_MEMORY_WINDOW 0x4000000
59#define ACP_IRAM_BASE_ADDRESS 0x000000
60#define ACP_DRAM_BASE_ADDRESS 0x01000000
61#define ACP_DRAM_PAGE_COUNT 128
62#define ACP_SRAM_BASE_ADDRESS 0x3806000
63#define ACP_DSP_TO_HOST_IRQ 0x04
64
65#define ACP_RN_PCI_ID 0x01
66#define ACP_VANGOGH_PCI_ID 0x50
67#define ACP_RMB_PCI_ID 0x6F
68#define ACP63_PCI_ID 0x63
69
70#define HOST_BRIDGE_CZN 0x1630
71#define HOST_BRIDGE_VGH 0x1645
72#define HOST_BRIDGE_RMB 0x14B5
73#define HOST_BRIDGE_ACP63 0x14E8
74#define ACP_SHA_STAT 0x8000
75#define ACP_PSP_TIMEOUT_US 1000000
76#define ACP_EXT_INTR_ERROR_STAT 0x20000000
77#define MP0_C2PMSG_114_REG 0x3810AC8
78#define MP0_C2PMSG_73_REG 0x3810A24
79#define MBOX_ACP_SHA_DMA_COMMAND 0x70000
80#define MBOX_ACP_IRAM_DRAM_FENCE_COMMAND 0x80000
81#define MBOX_DELAY_US 1000
82#define MBOX_READY_MASK 0x80000000
83#define MBOX_STATUS_MASK 0xFFFF
84#define MBOX_ISREADY_FLAG 0x40000000
85#define IRAM_DRAM_FENCE_0 0X0
86#define IRAM_DRAM_FENCE_1 0X01
87#define IRAM_DRAM_FENCE_2 0X02
88
89#define BOX_SIZE_512 0x200
90#define BOX_SIZE_1024 0x400
91
92#define EXCEPT_MAX_HDR_SIZE 0x400
93#define AMD_STACK_DUMP_SIZE 32
94
95#define SRAM1_SIZE 0x280000
96#define PROBE_STATUS_BIT BIT(31)
97
98#define ACP_FIRMWARE_SIGNATURE 0x100
99#define ACP_ERROR_IRQ_MASK BIT(29)
100#define ACP_SDW0_IRQ_MASK BIT(21)
101#define ACP_SDW1_IRQ_MASK BIT(2)
102#define SDW_ACPI_ADDR_ACP63 5
103#define ACP_DEFAULT_SRAM_LENGTH 0x00080000
104#define ACP_SRAM_PAGE_COUNT 128
105#define ACP6X_SDW_MAX_MANAGER_COUNT 2
106
107enum clock_source {
108 ACP_CLOCK_96M = 0,
109 ACP_CLOCK_48M,
110 ACP_CLOCK_24M,
111 ACP_CLOCK_ACLK,
112 ACP_CLOCK_MCLK,
113};
114
115struct acp_atu_grp_pte {
116 u32 low;
117 u32 high;
118};
119
120union dma_tx_cnt {
121 struct {
122 unsigned int count : 19;
123 unsigned int reserved : 12;
124 unsigned ioc : 1;
125 } bitfields, bits;
126 unsigned int u32_all;
127 signed int i32_all;
128};
129
130struct dma_descriptor {
131 unsigned int src_addr;
132 unsigned int dest_addr;
133 union dma_tx_cnt tx_cnt;
134 unsigned int reserved;
135};
136
137/* Scratch memory structure for communication b/w host and dsp */
138struct scratch_ipc_conf {
139 /* Debug memory */
140 u8 sof_debug_box[1024];
141 /* Exception memory*/
142 u8 sof_except_box[1024];
143 /* Stream buffer */
144 u8 sof_stream_box[1024];
145 /* Trace buffer */
146 u8 sof_trace_box[1024];
147 /* Host msg flag */
148 u32 sof_host_msg_write;
149 /* Host ack flag*/
150 u32 sof_host_ack_write;
151 /* DSP msg flag */
152 u32 sof_dsp_msg_write;
153 /* Dsp ack flag */
154 u32 sof_dsp_ack_write;
155};
156
157struct scratch_reg_conf {
158 struct scratch_ipc_conf info;
159 struct acp_atu_grp_pte grp1_pte[16];
160 struct acp_atu_grp_pte grp2_pte[16];
161 struct acp_atu_grp_pte grp3_pte[16];
162 struct acp_atu_grp_pte grp4_pte[16];
163 struct acp_atu_grp_pte grp5_pte[16];
164 struct acp_atu_grp_pte grp6_pte[16];
165 struct acp_atu_grp_pte grp7_pte[16];
166 struct acp_atu_grp_pte grp8_pte[16];
167 struct dma_descriptor dma_desc[64];
168 unsigned int reg_offset[8];
169 unsigned int buf_size[8];
170 u8 acp_tx_fifo_buf[256];
171 u8 acp_rx_fifo_buf[256];
172 unsigned int reserve[];
173};
174
175struct acp_dsp_stream {
176 struct list_head list;
177 struct snd_sof_dev *sdev;
178 struct snd_pcm_substream *substream;
179 struct snd_dma_buffer *dmab;
180 int num_pages;
181 int stream_tag;
182 int active;
183 unsigned int reg_offset;
184 size_t posn_offset;
185 struct snd_compr_stream *cstream;
186 u64 cstream_posn;
187};
188
189struct sof_amd_acp_desc {
190 unsigned int rev;
191 const char *name;
192 unsigned int host_bridge_id;
193 u32 pgfsm_base;
194 u32 ext_intr_enb;
195 u32 ext_intr_cntl;
196 u32 ext_intr_stat;
197 u32 ext_intr_stat1;
198 u32 dsp_intr_base;
199 u32 sram_pte_offset;
200 u32 hw_semaphore_offset;
201 u32 acp_clkmux_sel;
202 u32 fusion_dsp_offset;
203 u32 probe_reg_offset;
204 u32 reg_start_addr;
205 u32 reg_end_addr;
206 u32 sdw_max_link_count;
207 u64 sdw_acpi_dev_addr;
208};
209
210struct acp_quirk_entry {
211 bool signed_fw_image;
212 bool skip_iram_dram_size_mod;
213};
214
215/* Common device data struct for ACP devices */
216struct acp_dev_data {
217 struct snd_sof_dev *dev;
218 const struct firmware *fw_dbin;
219 /* DMIC device */
220 struct platform_device *dmic_dev;
221 /* mutex lock to protect ACP common registers access */
222 struct mutex acp_lock;
223 /* ACPI information stored between scan and probe steps */
224 struct sdw_amd_acpi_info info;
225 /* sdw context allocated by SoundWire driver */
226 struct sdw_amd_ctx *sdw;
227 unsigned int fw_bin_size;
228 unsigned int fw_data_bin_size;
229 unsigned int fw_sram_data_bin_size;
230 const char *fw_code_bin;
231 const char *fw_data_bin;
232 const char *fw_sram_data_bin;
233 u32 fw_bin_page_count;
234 u32 fw_data_bin_page_count;
235 u32 addr;
236 u32 reg_range;
237 u32 blk_type;
238 dma_addr_t sha_dma_addr;
239 u8 *bin_buf;
240 dma_addr_t dma_addr;
241 u8 *data_buf;
242 dma_addr_t sram_dma_addr;
243 u8 *sram_data_buf;
244 struct acp_quirk_entry *quirks;
245 struct dma_descriptor dscr_info[ACP_MAX_DESC];
246 struct acp_dsp_stream stream_buf[ACP_MAX_STREAM];
247 struct acp_dsp_stream *dtrace_stream;
248 struct pci_dev *smn_dev;
249 struct acp_dsp_stream *probe_stream;
250 bool enable_fw_debug;
251 bool is_dram_in_use;
252 bool is_sram_in_use;
253 bool sdw_en_stat;
254};
255
256void memcpy_to_scratch(struct snd_sof_dev *sdev, u32 offset, unsigned int *src, size_t bytes);
257void memcpy_from_scratch(struct snd_sof_dev *sdev, u32 offset, unsigned int *dst, size_t bytes);
258
259int acp_dma_status(struct acp_dev_data *adata, unsigned char ch);
260int configure_and_run_dma(struct acp_dev_data *adata, unsigned int src_addr,
261 unsigned int dest_addr, int dsp_data_size);
262int configure_and_run_sha_dma(struct acp_dev_data *adata, void *image_addr,
263 unsigned int start_addr, unsigned int dest_addr,
264 unsigned int image_length);
265
266/* ACP device probe/remove */
267int amd_sof_acp_probe(struct snd_sof_dev *sdev);
268void amd_sof_acp_remove(struct snd_sof_dev *sdev);
269
270/* DSP Loader callbacks */
271int acp_sof_dsp_run(struct snd_sof_dev *sdev);
272int acp_dsp_pre_fw_run(struct snd_sof_dev *sdev);
273int acp_sof_load_signed_firmware(struct snd_sof_dev *sdev);
274int acp_get_bar_index(struct snd_sof_dev *sdev, u32 type);
275
276/* Block IO callbacks */
277int acp_dsp_block_write(struct snd_sof_dev *sdev, enum snd_sof_fw_blk_type blk_type,
278 u32 offset, void *src, size_t size);
279int acp_dsp_block_read(struct snd_sof_dev *sdev, enum snd_sof_fw_blk_type blk_type,
280 u32 offset, void *dest, size_t size);
281
282/* IPC callbacks */
283irqreturn_t acp_sof_ipc_irq_thread(int irq, void *context);
284int acp_sof_ipc_msg_data(struct snd_sof_dev *sdev, struct snd_sof_pcm_stream *sps,
285 void *p, size_t sz);
286int acp_set_stream_data_offset(struct snd_sof_dev *sdev,
287 struct snd_sof_pcm_stream *sps,
288 size_t posn_offset);
289int acp_sof_ipc_send_msg(struct snd_sof_dev *sdev,
290 struct snd_sof_ipc_msg *msg);
291int acp_sof_ipc_get_mailbox_offset(struct snd_sof_dev *sdev);
292int acp_sof_ipc_get_window_offset(struct snd_sof_dev *sdev, u32 id);
293void acp_mailbox_write(struct snd_sof_dev *sdev, u32 offset, void *message, size_t bytes);
294void acp_mailbox_read(struct snd_sof_dev *sdev, u32 offset, void *message, size_t bytes);
295
296/* ACP - DSP stream callbacks */
297int acp_dsp_stream_config(struct snd_sof_dev *sdev, struct acp_dsp_stream *stream);
298int acp_dsp_stream_init(struct snd_sof_dev *sdev);
299struct acp_dsp_stream *acp_dsp_stream_get(struct snd_sof_dev *sdev, int tag);
300int acp_dsp_stream_put(struct snd_sof_dev *sdev, struct acp_dsp_stream *acp_stream);
301
302/*
303 * DSP PCM Operations.
304 */
305int acp_pcm_open(struct snd_sof_dev *sdev, struct snd_pcm_substream *substream);
306int acp_pcm_close(struct snd_sof_dev *sdev, struct snd_pcm_substream *substream);
307int acp_pcm_hw_params(struct snd_sof_dev *sdev, struct snd_pcm_substream *substream,
308 struct snd_pcm_hw_params *params,
309 struct snd_sof_platform_stream_params *platform_params);
310snd_pcm_uframes_t acp_pcm_pointer(struct snd_sof_dev *sdev,
311 struct snd_pcm_substream *substream);
312
313extern struct snd_sof_dsp_ops sof_acp_common_ops;
314
315extern struct snd_sof_dsp_ops sof_renoir_ops;
316int sof_renoir_ops_init(struct snd_sof_dev *sdev);
317extern struct snd_sof_dsp_ops sof_vangogh_ops;
318int sof_vangogh_ops_init(struct snd_sof_dev *sdev);
319extern struct snd_sof_dsp_ops sof_rembrandt_ops;
320int sof_rembrandt_ops_init(struct snd_sof_dev *sdev);
321extern struct snd_sof_dsp_ops sof_acp63_ops;
322int sof_acp63_ops_init(struct snd_sof_dev *sdev);
323
324struct snd_soc_acpi_mach *amd_sof_machine_select(struct snd_sof_dev *sdev);
325/* Machine configuration */
326int snd_amd_acp_find_config(struct pci_dev *pci);
327
328/* Trace */
329int acp_sof_trace_init(struct snd_sof_dev *sdev, struct snd_dma_buffer *dmab,
330 struct sof_ipc_dma_trace_params_ext *dtrace_params);
331int acp_sof_trace_release(struct snd_sof_dev *sdev);
332
333/* PM Callbacks */
334int amd_sof_acp_suspend(struct snd_sof_dev *sdev, u32 target_state);
335int amd_sof_acp_resume(struct snd_sof_dev *sdev);
336
337void amd_sof_ipc_dump(struct snd_sof_dev *sdev);
338void amd_sof_dump(struct snd_sof_dev *sdev, u32 flags);
339
340static inline const struct sof_amd_acp_desc *get_chip_info(struct snd_sof_pdata *pdata)
341{
342 const struct sof_dev_desc *desc = pdata->desc;
343
344 return desc->chip_info;
345}
346
347int acp_probes_register(struct snd_sof_dev *sdev);
348void acp_probes_unregister(struct snd_sof_dev *sdev);
349
350extern struct snd_soc_acpi_mach snd_soc_acpi_amd_vangogh_sof_machines[];
351extern const struct dmi_system_id acp_sof_quirk_table[];
352#endif
353

source code of linux/sound/soc/sof/amd/acp.h