1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
2 | /* |
3 | * tegra30_i2s.h - Definitions for Tegra30 I2S driver |
4 | * |
5 | * Copyright (c) 2011,2012, NVIDIA CORPORATION. All rights reserved. |
6 | */ |
7 | |
8 | #ifndef __TEGRA30_I2S_H__ |
9 | #define __TEGRA30_I2S_H__ |
10 | |
11 | #include "tegra_pcm.h" |
12 | |
13 | /* Register offsets from TEGRA30_I2S*_BASE */ |
14 | |
15 | #define TEGRA30_I2S_CTRL 0x0 |
16 | #define TEGRA30_I2S_TIMING 0x4 |
17 | #define TEGRA30_I2S_OFFSET 0x08 |
18 | #define TEGRA30_I2S_CH_CTRL 0x0c |
19 | #define TEGRA30_I2S_SLOT_CTRL 0x10 |
20 | #define TEGRA30_I2S_CIF_RX_CTRL 0x14 |
21 | #define TEGRA30_I2S_CIF_TX_CTRL 0x18 |
22 | #define TEGRA30_I2S_FLOWCTL 0x1c |
23 | #define TEGRA30_I2S_TX_STEP 0x20 |
24 | #define TEGRA30_I2S_FLOW_STATUS 0x24 |
25 | #define TEGRA30_I2S_FLOW_TOTAL 0x28 |
26 | #define TEGRA30_I2S_FLOW_OVER 0x2c |
27 | #define TEGRA30_I2S_FLOW_UNDER 0x30 |
28 | #define TEGRA30_I2S_LCOEF_1_4_0 0x34 |
29 | #define TEGRA30_I2S_LCOEF_1_4_1 0x38 |
30 | #define TEGRA30_I2S_LCOEF_1_4_2 0x3c |
31 | #define TEGRA30_I2S_LCOEF_1_4_3 0x40 |
32 | #define TEGRA30_I2S_LCOEF_1_4_4 0x44 |
33 | #define TEGRA30_I2S_LCOEF_1_4_5 0x48 |
34 | #define TEGRA30_I2S_LCOEF_2_4_0 0x4c |
35 | #define TEGRA30_I2S_LCOEF_2_4_1 0x50 |
36 | #define TEGRA30_I2S_LCOEF_2_4_2 0x54 |
37 | |
38 | /* Fields in TEGRA30_I2S_CTRL */ |
39 | |
40 | #define TEGRA30_I2S_CTRL_XFER_EN_TX (1 << 31) |
41 | #define TEGRA30_I2S_CTRL_XFER_EN_RX (1 << 30) |
42 | #define TEGRA30_I2S_CTRL_CG_EN (1 << 29) |
43 | #define TEGRA30_I2S_CTRL_SOFT_RESET (1 << 28) |
44 | #define TEGRA30_I2S_CTRL_TX_FLOWCTL_EN (1 << 27) |
45 | |
46 | #define TEGRA30_I2S_CTRL_OBS_SEL_SHIFT 24 |
47 | #define TEGRA30_I2S_CTRL_OBS_SEL_MASK (7 << TEGRA30_I2S_CTRL_OBS_SEL_SHIFT) |
48 | |
49 | #define TEGRA30_I2S_FRAME_FORMAT_LRCK 0 |
50 | #define TEGRA30_I2S_FRAME_FORMAT_FSYNC 1 |
51 | |
52 | #define TEGRA30_I2S_CTRL_FRAME_FORMAT_SHIFT 12 |
53 | #define TEGRA30_I2S_CTRL_FRAME_FORMAT_MASK (7 << TEGRA30_I2S_CTRL_FRAME_FORMAT_SHIFT) |
54 | #define TEGRA30_I2S_CTRL_FRAME_FORMAT_LRCK (TEGRA30_I2S_FRAME_FORMAT_LRCK << TEGRA30_I2S_CTRL_FRAME_FORMAT_SHIFT) |
55 | #define TEGRA30_I2S_CTRL_FRAME_FORMAT_FSYNC (TEGRA30_I2S_FRAME_FORMAT_FSYNC << TEGRA30_I2S_CTRL_FRAME_FORMAT_SHIFT) |
56 | |
57 | #define TEGRA30_I2S_CTRL_MASTER_ENABLE (1 << 10) |
58 | |
59 | #define TEGRA30_I2S_LRCK_LEFT_LOW 0 |
60 | #define TEGRA30_I2S_LRCK_RIGHT_LOW 1 |
61 | |
62 | #define TEGRA30_I2S_CTRL_LRCK_SHIFT 9 |
63 | #define TEGRA30_I2S_CTRL_LRCK_MASK (1 << TEGRA30_I2S_CTRL_LRCK_SHIFT) |
64 | #define TEGRA30_I2S_CTRL_LRCK_L_LOW (TEGRA30_I2S_LRCK_LEFT_LOW << TEGRA30_I2S_CTRL_LRCK_SHIFT) |
65 | #define TEGRA30_I2S_CTRL_LRCK_R_LOW (TEGRA30_I2S_LRCK_RIGHT_LOW << TEGRA30_I2S_CTRL_LRCK_SHIFT) |
66 | |
67 | #define TEGRA30_I2S_CTRL_LPBK_ENABLE (1 << 8) |
68 | |
69 | #define TEGRA30_I2S_BIT_CODE_LINEAR 0 |
70 | #define TEGRA30_I2S_BIT_CODE_ULAW 1 |
71 | #define TEGRA30_I2S_BIT_CODE_ALAW 2 |
72 | |
73 | #define TEGRA30_I2S_CTRL_BIT_CODE_SHIFT 4 |
74 | #define TEGRA30_I2S_CTRL_BIT_CODE_MASK (3 << TEGRA30_I2S_CTRL_BIT_CODE_SHIFT) |
75 | #define TEGRA30_I2S_CTRL_BIT_CODE_LINEAR (TEGRA30_I2S_BIT_CODE_LINEAR << TEGRA30_I2S_CTRL_BIT_CODE_SHIFT) |
76 | #define TEGRA30_I2S_CTRL_BIT_CODE_ULAW (TEGRA30_I2S_BIT_CODE_ULAW << TEGRA30_I2S_CTRL_BIT_CODE_SHIFT) |
77 | #define TEGRA30_I2S_CTRL_BIT_CODE_ALAW (TEGRA30_I2S_BIT_CODE_ALAW << TEGRA30_I2S_CTRL_BIT_CODE_SHIFT) |
78 | |
79 | #define TEGRA30_I2S_BITS_8 1 |
80 | #define TEGRA30_I2S_BITS_12 2 |
81 | #define TEGRA30_I2S_BITS_16 3 |
82 | #define TEGRA30_I2S_BITS_20 4 |
83 | #define TEGRA30_I2S_BITS_24 5 |
84 | #define TEGRA30_I2S_BITS_28 6 |
85 | #define TEGRA30_I2S_BITS_32 7 |
86 | |
87 | /* Sample container size; see {RX,TX}_MASK field in CH_CTRL below */ |
88 | #define TEGRA30_I2S_CTRL_BIT_SIZE_SHIFT 0 |
89 | #define TEGRA30_I2S_CTRL_BIT_SIZE_MASK (7 << TEGRA30_I2S_CTRL_BIT_SIZE_SHIFT) |
90 | #define TEGRA30_I2S_CTRL_BIT_SIZE_8 (TEGRA30_I2S_BITS_8 << TEGRA30_I2S_CTRL_BIT_SIZE_SHIFT) |
91 | #define TEGRA30_I2S_CTRL_BIT_SIZE_12 (TEGRA30_I2S_BITS_12 << TEGRA30_I2S_CTRL_BIT_SIZE_SHIFT) |
92 | #define TEGRA30_I2S_CTRL_BIT_SIZE_16 (TEGRA30_I2S_BITS_16 << TEGRA30_I2S_CTRL_BIT_SIZE_SHIFT) |
93 | #define TEGRA30_I2S_CTRL_BIT_SIZE_20 (TEGRA30_I2S_BITS_20 << TEGRA30_I2S_CTRL_BIT_SIZE_SHIFT) |
94 | #define TEGRA30_I2S_CTRL_BIT_SIZE_24 (TEGRA30_I2S_BITS_24 << TEGRA30_I2S_CTRL_BIT_SIZE_SHIFT) |
95 | #define TEGRA30_I2S_CTRL_BIT_SIZE_28 (TEGRA30_I2S_BITS_28 << TEGRA30_I2S_CTRL_BIT_SIZE_SHIFT) |
96 | #define TEGRA30_I2S_CTRL_BIT_SIZE_32 (TEGRA30_I2S_BITS_32 << TEGRA30_I2S_CTRL_BIT_SIZE_SHIFT) |
97 | |
98 | /* Fields in TEGRA30_I2S_TIMING */ |
99 | |
100 | #define TEGRA30_I2S_TIMING_NON_SYM_ENABLE (1 << 12) |
101 | #define TEGRA30_I2S_TIMING_CHANNEL_BIT_COUNT_SHIFT 0 |
102 | #define TEGRA30_I2S_TIMING_CHANNEL_BIT_COUNT_MASK_US 0x7ff |
103 | #define TEGRA30_I2S_TIMING_CHANNEL_BIT_COUNT_MASK (TEGRA30_I2S_TIMING_CHANNEL_BIT_COUNT_MASK_US << TEGRA30_I2S_TIMING_CHANNEL_BIT_COUNT_SHIFT) |
104 | |
105 | /* Fields in TEGRA30_I2S_OFFSET */ |
106 | |
107 | #define TEGRA30_I2S_OFFSET_RX_DATA_OFFSET_SHIFT 16 |
108 | #define TEGRA30_I2S_OFFSET_RX_DATA_OFFSET_MASK_US 0x7ff |
109 | #define TEGRA30_I2S_OFFSET_RX_DATA_OFFSET_MASK (TEGRA30_I2S_OFFSET_RX_DATA_OFFSET_MASK_US << TEGRA30_I2S_OFFSET_RX_DATA_OFFSET_SHIFT) |
110 | #define TEGRA30_I2S_OFFSET_TX_DATA_OFFSET_SHIFT 0 |
111 | #define TEGRA30_I2S_OFFSET_TX_DATA_OFFSET_MASK_US 0x7ff |
112 | #define TEGRA30_I2S_OFFSET_TX_DATA_OFFSET_MASK (TEGRA30_I2S_OFFSET_TX_DATA_OFFSET_MASK_US << TEGRA30_I2S_OFFSET_TX_DATA_OFFSET_SHIFT) |
113 | |
114 | /* Fields in TEGRA30_I2S_CH_CTRL */ |
115 | |
116 | /* (FSYNC width - 1) in bit clocks */ |
117 | #define TEGRA30_I2S_CH_CTRL_FSYNC_WIDTH_SHIFT 24 |
118 | #define TEGRA30_I2S_CH_CTRL_FSYNC_WIDTH_MASK_US 0xff |
119 | #define TEGRA30_I2S_CH_CTRL_FSYNC_WIDTH_MASK (TEGRA30_I2S_CH_CTRL_FSYNC_WIDTH_MASK_US << TEGRA30_I2S_CH_CTRL_FSYNC_WIDTH_SHIFT) |
120 | |
121 | #define TEGRA30_I2S_HIGHZ_NO 0 |
122 | #define TEGRA30_I2S_HIGHZ_YES 1 |
123 | #define TEGRA30_I2S_HIGHZ_ON_HALF_BIT_CLK 2 |
124 | |
125 | #define TEGRA30_I2S_CH_CTRL_HIGHZ_CTRL_SHIFT 12 |
126 | #define TEGRA30_I2S_CH_CTRL_HIGHZ_CTRL_MASK (3 << TEGRA30_I2S_CH_CTRL_HIGHZ_CTRL_SHIFT) |
127 | #define TEGRA30_I2S_CH_CTRL_HIGHZ_CTRL_NO (TEGRA30_I2S_HIGHZ_NO << TEGRA30_I2S_CH_CTRL_HIGHZ_CTRL_SHIFT) |
128 | #define TEGRA30_I2S_CH_CTRL_HIGHZ_CTRL_YES (TEGRA30_I2S_HIGHZ_YES << TEGRA30_I2S_CH_CTRL_HIGHZ_CTRL_SHIFT) |
129 | #define TEGRA30_I2S_CH_CTRL_HIGHZ_CTRL_ON_HALF_BIT_CLK (TEGRA30_I2S_HIGHZ_ON_HALF_BIT_CLK << TEGRA30_I2S_CH_CTRL_HIGHZ_CTRL_SHIFT) |
130 | |
131 | #define TEGRA30_I2S_MSB_FIRST 0 |
132 | #define TEGRA30_I2S_LSB_FIRST 1 |
133 | |
134 | #define TEGRA30_I2S_CH_CTRL_RX_BIT_ORDER_SHIFT 10 |
135 | #define TEGRA30_I2S_CH_CTRL_RX_BIT_ORDER_MASK (1 << TEGRA30_I2S_CH_CTRL_RX_BIT_ORDER_SHIFT) |
136 | #define TEGRA30_I2S_CH_CTRL_RX_BIT_ORDER_MSB_FIRST (TEGRA30_I2S_MSB_FIRST << TEGRA30_I2S_CH_CTRL_RX_BIT_ORDER_SHIFT) |
137 | #define TEGRA30_I2S_CH_CTRL_RX_BIT_ORDER_LSB_FIRST (TEGRA30_I2S_LSB_FIRST << TEGRA30_I2S_CH_CTRL_RX_BIT_ORDER_SHIFT) |
138 | #define TEGRA30_I2S_CH_CTRL_TX_BIT_ORDER_SHIFT 9 |
139 | #define TEGRA30_I2S_CH_CTRL_TX_BIT_ORDER_MASK (1 << TEGRA30_I2S_CH_CTRL_TX_BIT_ORDER_SHIFT) |
140 | #define TEGRA30_I2S_CH_CTRL_TX_BIT_ORDER_MSB_FIRST (TEGRA30_I2S_MSB_FIRST << TEGRA30_I2S_CH_CTRL_TX_BIT_ORDER_SHIFT) |
141 | #define TEGRA30_I2S_CH_CTRL_TX_BIT_ORDER_LSB_FIRST (TEGRA30_I2S_LSB_FIRST << TEGRA30_I2S_CH_CTRL_TX_BIT_ORDER_SHIFT) |
142 | |
143 | #define TEGRA30_I2S_POS_EDGE 0 |
144 | #define TEGRA30_I2S_NEG_EDGE 1 |
145 | |
146 | #define TEGRA30_I2S_CH_CTRL_EGDE_CTRL_SHIFT 8 |
147 | #define TEGRA30_I2S_CH_CTRL_EGDE_CTRL_MASK (1 << TEGRA30_I2S_CH_CTRL_EGDE_CTRL_SHIFT) |
148 | #define TEGRA30_I2S_CH_CTRL_EGDE_CTRL_POS_EDGE (TEGRA30_I2S_POS_EDGE << TEGRA30_I2S_CH_CTRL_EGDE_CTRL_SHIFT) |
149 | #define TEGRA30_I2S_CH_CTRL_EGDE_CTRL_NEG_EDGE (TEGRA30_I2S_NEG_EDGE << TEGRA30_I2S_CH_CTRL_EGDE_CTRL_SHIFT) |
150 | |
151 | /* Sample size is # bits from BIT_SIZE minus this field */ |
152 | #define TEGRA30_I2S_CH_CTRL_RX_MASK_BITS_SHIFT 4 |
153 | #define TEGRA30_I2S_CH_CTRL_RX_MASK_BITS_MASK_US 7 |
154 | #define TEGRA30_I2S_CH_CTRL_RX_MASK_BITS_MASK (TEGRA30_I2S_CH_CTRL_RX_MASK_BITS_MASK_US << TEGRA30_I2S_CH_CTRL_RX_MASK_BITS_SHIFT) |
155 | |
156 | #define TEGRA30_I2S_CH_CTRL_TX_MASK_BITS_SHIFT 0 |
157 | #define TEGRA30_I2S_CH_CTRL_TX_MASK_BITS_MASK_US 7 |
158 | #define TEGRA30_I2S_CH_CTRL_TX_MASK_BITS_MASK (TEGRA30_I2S_CH_CTRL_TX_MASK_BITS_MASK_US << TEGRA30_I2S_CH_CTRL_TX_MASK_BITS_SHIFT) |
159 | |
160 | /* Fields in TEGRA30_I2S_SLOT_CTRL */ |
161 | |
162 | /* Number of slots in frame, minus 1 */ |
163 | #define TEGRA30_I2S_SLOT_CTRL_TOTAL_SLOTS_SHIFT 16 |
164 | #define TEGRA30_I2S_SLOT_CTRL_TOTAL_SLOTS_MASK_US 7 |
165 | #define TEGRA30_I2S_SLOT_CTRL_TOTAL_SLOTS_MASK (TEGRA30_I2S_SLOT_CTRL_TOTAL_SLOTS_MASK_US << TEGRA30_I2S_SLOT_CTRL_TOTAL_SLOTS_SHIFT) |
166 | |
167 | /* TDM mode slot enable bitmask */ |
168 | #define TEGRA30_I2S_SLOT_CTRL_RX_SLOT_ENABLES_SHIFT 8 |
169 | #define TEGRA30_I2S_SLOT_CTRL_RX_SLOT_ENABLES_MASK (0xff << TEGRA30_I2S_SLOT_CTRL_RX_SLOT_ENABLES_SHIFT) |
170 | |
171 | #define TEGRA30_I2S_SLOT_CTRL_TX_SLOT_ENABLES_SHIFT 0 |
172 | #define TEGRA30_I2S_SLOT_CTRL_TX_SLOT_ENABLES_MASK (0xff << TEGRA30_I2S_SLOT_CTRL_TX_SLOT_ENABLES_SHIFT) |
173 | |
174 | /* Fields in TEGRA30_I2S_CIF_RX_CTRL */ |
175 | /* Uses field from TEGRA30_AUDIOCIF_CTRL_* in tegra30_ahub.h */ |
176 | |
177 | /* Fields in TEGRA30_I2S_CIF_TX_CTRL */ |
178 | /* Uses field from TEGRA30_AUDIOCIF_CTRL_* in tegra30_ahub.h */ |
179 | |
180 | /* Fields in TEGRA30_I2S_FLOWCTL */ |
181 | |
182 | #define TEGRA30_I2S_FILTER_LINEAR 0 |
183 | #define TEGRA30_I2S_FILTER_QUAD 1 |
184 | |
185 | #define TEGRA30_I2S_FLOWCTL_FILTER_SHIFT 31 |
186 | #define TEGRA30_I2S_FLOWCTL_FILTER_MASK (1 << TEGRA30_I2S_FLOWCTL_FILTER_SHIFT) |
187 | #define TEGRA30_I2S_FLOWCTL_FILTER_LINEAR (TEGRA30_I2S_FILTER_LINEAR << TEGRA30_I2S_FLOWCTL_FILTER_SHIFT) |
188 | #define TEGRA30_I2S_FLOWCTL_FILTER_QUAD (TEGRA30_I2S_FILTER_QUAD << TEGRA30_I2S_FLOWCTL_FILTER_SHIFT) |
189 | |
190 | /* Fields in TEGRA30_I2S_TX_STEP */ |
191 | |
192 | #define TEGRA30_I2S_TX_STEP_SHIFT 0 |
193 | #define TEGRA30_I2S_TX_STEP_MASK_US 0xffff |
194 | #define TEGRA30_I2S_TX_STEP_MASK (TEGRA30_I2S_TX_STEP_MASK_US << TEGRA30_I2S_TX_STEP_SHIFT) |
195 | |
196 | /* Fields in TEGRA30_I2S_FLOW_STATUS */ |
197 | |
198 | #define TEGRA30_I2S_FLOW_STATUS_UNDERFLOW (1 << 31) |
199 | #define TEGRA30_I2S_FLOW_STATUS_OVERFLOW (1 << 30) |
200 | #define TEGRA30_I2S_FLOW_STATUS_MONITOR_INT_EN (1 << 4) |
201 | #define TEGRA30_I2S_FLOW_STATUS_COUNTER_CLR (1 << 3) |
202 | #define TEGRA30_I2S_FLOW_STATUS_MONITOR_CLR (1 << 2) |
203 | #define TEGRA30_I2S_FLOW_STATUS_COUNTER_EN (1 << 1) |
204 | #define TEGRA30_I2S_FLOW_STATUS_MONITOR_EN (1 << 0) |
205 | |
206 | /* |
207 | * There are no fields in TEGRA30_I2S_FLOW_TOTAL, TEGRA30_I2S_FLOW_OVER, |
208 | * TEGRA30_I2S_FLOW_UNDER; they are counters taking the whole register. |
209 | */ |
210 | |
211 | /* Fields in TEGRA30_I2S_LCOEF_* */ |
212 | |
213 | #define TEGRA30_I2S_LCOEF_COEF_SHIFT 0 |
214 | #define TEGRA30_I2S_LCOEF_COEF_MASK_US 0xffff |
215 | #define TEGRA30_I2S_LCOEF_COEF_MASK (TEGRA30_I2S_LCOEF_COEF_MASK_US << TEGRA30_I2S_LCOEF_COEF_SHIFT) |
216 | |
217 | struct tegra30_i2s_soc_data { |
218 | void (*set_audio_cif)(struct regmap *regmap, |
219 | unsigned int reg, |
220 | struct tegra30_ahub_cif_conf *conf); |
221 | }; |
222 | |
223 | struct tegra30_i2s { |
224 | const struct tegra30_i2s_soc_data *soc_data; |
225 | struct snd_soc_dai_driver dai; |
226 | int cif_id; |
227 | struct clk *clk_i2s; |
228 | enum tegra30_ahub_txcif capture_i2s_cif; |
229 | enum tegra30_ahub_rxcif capture_fifo_cif; |
230 | char capture_dma_chan[8]; |
231 | struct snd_dmaengine_dai_dma_data capture_dma_data; |
232 | enum tegra30_ahub_rxcif playback_i2s_cif; |
233 | enum tegra30_ahub_txcif playback_fifo_cif; |
234 | char playback_dma_chan[8]; |
235 | struct snd_dmaengine_dai_dma_data playback_dma_data; |
236 | struct regmap *regmap; |
237 | struct snd_dmaengine_pcm_config dma_config; |
238 | }; |
239 | |
240 | #endif |
241 | |