1 | //===-- RISCVVTypes.def - Metadata for the RISC-V V types ------*- C++ -*--===// |
2 | // |
3 | // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. |
4 | // See https://llvm.org/LICENSE.txt for license information. |
5 | // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception |
6 | // |
7 | //===----------------------------------------------------------------------===// |
8 | // |
9 | // This file defines various RISC-V V builtin types. The macros are: |
10 | // |
11 | // - RVV_TYPE(Name, Id, SingletonId) |
12 | // A builtin type that has not been covered by any other #define |
13 | // Defining this macro covers all the builtins. |
14 | // |
15 | // - RVV_VECTOR_TYPE(Name, Id, SingletonId, NumEls, ElBits, IsSigned, IsFP) |
16 | // A RISC-V V scalable vector. |
17 | // |
18 | // - RVV_PREDICATE_TYPE(Name, Id, SingletonId, NumEls) |
19 | // An RISC-V V scalable mask. |
20 | // |
21 | // where: |
22 | // |
23 | // - Name is the name of the builtin type. |
24 | // |
25 | // - Id is the enumerator defining the type. |
26 | // |
27 | // - SingletonId is the global singleton of this type. |
28 | // |
29 | // - NumEls enumerates the number of the elements. |
30 | // |
31 | // - ElBits is the size of one element in bits (SEW). |
32 | // |
33 | // - NF is the number of fields (NFIELDS) used in the Zvlsseg instructions |
34 | // (TODO). |
35 | // |
36 | // - IsSigned is true for vectors of signed integer elements and |
37 | // for vectors of floating-point elements. |
38 | // |
39 | // - IsFP is true for vectors of floating-point elements. |
40 | // |
41 | //===----------------------------------------------------------------------===// |
42 | |
43 | #ifndef RVV_VECTOR_TYPE |
44 | #define RVV_VECTOR_TYPE(Name, Id, SingletonId, NumEls, ElBits, NF, IsSigned, IsFP)\ |
45 | RVV_TYPE(Name, Id, SingletonId) |
46 | #endif |
47 | |
48 | #ifndef RVV_PREDICATE_TYPE |
49 | #define RVV_PREDICATE_TYPE(Name, Id, SingletonId, NumEls)\ |
50 | RVV_TYPE(Name, Id, SingletonId) |
51 | #endif |
52 | |
53 | #ifndef RVV_VECTOR_TYPE_INT |
54 | #define RVV_VECTOR_TYPE_INT(Name, Id, SingletonId, NumEls, ElBits, NF, IsSigned) \ |
55 | RVV_VECTOR_TYPE(Name, Id, SingletonId, NumEls, ElBits, NF, IsSigned, false) |
56 | #endif |
57 | |
58 | #ifndef RVV_VECTOR_TYPE_FLOAT |
59 | #define RVV_VECTOR_TYPE_FLOAT(Name, Id, SingletonId, NumEls, ElBits, NF) \ |
60 | RVV_VECTOR_TYPE(Name, Id, SingletonId, NumEls, ElBits, NF, false, true) |
61 | #endif |
62 | |
63 | //===- Vector types -------------------------------------------------------===// |
64 | |
65 | RVV_VECTOR_TYPE_INT("__rvv_int8mf8_t" , RvvInt8mf8, RvvInt8mf8Ty, 1, 8, 1, true) |
66 | RVV_VECTOR_TYPE_INT("__rvv_int8mf4_t" , RvvInt8mf4, RvvInt8mf4Ty, 2, 8, 1, true) |
67 | RVV_VECTOR_TYPE_INT("__rvv_int8mf2_t" , RvvInt8mf2, RvvInt8mf2Ty, 4, 8, 1, true) |
68 | RVV_VECTOR_TYPE_INT("__rvv_int8m1_t" , RvvInt8m1, RvvInt8m1Ty, 8, 8, 1, true) |
69 | RVV_VECTOR_TYPE_INT("__rvv_int8m2_t" , RvvInt8m2, RvvInt8m2Ty, 16, 8, 1, true) |
70 | RVV_VECTOR_TYPE_INT("__rvv_int8m4_t" , RvvInt8m4, RvvInt8m4Ty, 32, 8, 1, true) |
71 | RVV_VECTOR_TYPE_INT("__rvv_int8m8_t" , RvvInt8m8, RvvInt8m8Ty, 64, 8, 1, true) |
72 | |
73 | RVV_VECTOR_TYPE_INT("__rvv_uint8mf8_t" ,RvvUint8mf8,RvvUint8mf8Ty,1, 8, 1, false) |
74 | RVV_VECTOR_TYPE_INT("__rvv_uint8mf4_t" ,RvvUint8mf4,RvvUint8mf4Ty,2, 8, 1, false) |
75 | RVV_VECTOR_TYPE_INT("__rvv_uint8mf2_t" ,RvvUint8mf2,RvvUint8mf2Ty,4, 8, 1, false) |
76 | RVV_VECTOR_TYPE_INT("__rvv_uint8m1_t" , RvvUint8m1, RvvUint8m1Ty, 8, 8, 1, false) |
77 | RVV_VECTOR_TYPE_INT("__rvv_uint8m2_t" , RvvUint8m2, RvvUint8m2Ty, 16, 8, 1, false) |
78 | RVV_VECTOR_TYPE_INT("__rvv_uint8m4_t" , RvvUint8m4, RvvUint8m4Ty, 32, 8, 1, false) |
79 | RVV_VECTOR_TYPE_INT("__rvv_uint8m8_t" , RvvUint8m8, RvvUint8m8Ty, 64, 8, 1, false) |
80 | |
81 | RVV_VECTOR_TYPE_INT("__rvv_int16mf4_t" ,RvvInt16mf4,RvvInt16mf4Ty,1, 16, 1, true) |
82 | RVV_VECTOR_TYPE_INT("__rvv_int16mf2_t" ,RvvInt16mf2,RvvInt16mf2Ty,2, 16, 1, true) |
83 | RVV_VECTOR_TYPE_INT("__rvv_int16m1_t" , RvvInt16m1, RvvInt16m1Ty, 4, 16, 1, true) |
84 | RVV_VECTOR_TYPE_INT("__rvv_int16m2_t" , RvvInt16m2, RvvInt16m2Ty, 8, 16, 1, true) |
85 | RVV_VECTOR_TYPE_INT("__rvv_int16m4_t" , RvvInt16m4, RvvInt16m4Ty, 16, 16, 1, true) |
86 | RVV_VECTOR_TYPE_INT("__rvv_int16m8_t" , RvvInt16m8, RvvInt16m8Ty, 32, 16, 1, true) |
87 | |
88 | RVV_VECTOR_TYPE_INT("__rvv_uint16mf4_t" ,RvvUint16mf4,RvvUint16mf4Ty,1, 16, 1, false) |
89 | RVV_VECTOR_TYPE_INT("__rvv_uint16mf2_t" ,RvvUint16mf2,RvvUint16mf2Ty,2, 16, 1, false) |
90 | RVV_VECTOR_TYPE_INT("__rvv_uint16m1_t" , RvvUint16m1, RvvUint16m1Ty, 4, 16, 1, false) |
91 | RVV_VECTOR_TYPE_INT("__rvv_uint16m2_t" , RvvUint16m2, RvvUint16m2Ty, 8, 16, 1, false) |
92 | RVV_VECTOR_TYPE_INT("__rvv_uint16m4_t" , RvvUint16m4, RvvUint16m4Ty, 16, 16, 1, false) |
93 | RVV_VECTOR_TYPE_INT("__rvv_uint16m8_t" , RvvUint16m8, RvvUint16m8Ty, 32, 16, 1, false) |
94 | |
95 | RVV_VECTOR_TYPE_INT("__rvv_int32mf2_t" ,RvvInt32mf2,RvvInt32mf2Ty,1, 32, 1, true) |
96 | RVV_VECTOR_TYPE_INT("__rvv_int32m1_t" , RvvInt32m1, RvvInt32m1Ty, 2, 32, 1, true) |
97 | RVV_VECTOR_TYPE_INT("__rvv_int32m2_t" , RvvInt32m2, RvvInt32m2Ty, 4, 32, 1, true) |
98 | RVV_VECTOR_TYPE_INT("__rvv_int32m4_t" , RvvInt32m4, RvvInt32m4Ty, 8, 32, 1, true) |
99 | RVV_VECTOR_TYPE_INT("__rvv_int32m8_t" , RvvInt32m8, RvvInt32m8Ty, 16, 32, 1, true) |
100 | |
101 | RVV_VECTOR_TYPE_INT("__rvv_uint32mf2_t" ,RvvUint32mf2,RvvUint32mf2Ty,1, 32, 1, false) |
102 | RVV_VECTOR_TYPE_INT("__rvv_uint32m1_t" , RvvUint32m1, RvvUint32m1Ty, 2, 32, 1, false) |
103 | RVV_VECTOR_TYPE_INT("__rvv_uint32m2_t" , RvvUint32m2, RvvUint32m2Ty, 4, 32, 1, false) |
104 | RVV_VECTOR_TYPE_INT("__rvv_uint32m4_t" , RvvUint32m4, RvvUint32m4Ty, 8, 32, 1, false) |
105 | RVV_VECTOR_TYPE_INT("__rvv_uint32m8_t" , RvvUint32m8, RvvUint32m8Ty, 16, 32, 1, false) |
106 | |
107 | RVV_VECTOR_TYPE_INT("__rvv_int64m1_t" , RvvInt64m1, RvvInt64m1Ty, 1, 64, 1, true) |
108 | RVV_VECTOR_TYPE_INT("__rvv_int64m2_t" , RvvInt64m2, RvvInt64m2Ty, 2, 64, 1, true) |
109 | RVV_VECTOR_TYPE_INT("__rvv_int64m4_t" , RvvInt64m4, RvvInt64m4Ty, 4, 64, 1, true) |
110 | RVV_VECTOR_TYPE_INT("__rvv_int64m8_t" , RvvInt64m8, RvvInt64m8Ty, 8, 64, 1, true) |
111 | |
112 | RVV_VECTOR_TYPE_INT("__rvv_uint64m1_t" ,RvvUint64m1,RvvUint64m1Ty,1, 64, 1, false) |
113 | RVV_VECTOR_TYPE_INT("__rvv_uint64m2_t" ,RvvUint64m2,RvvUint64m2Ty,2, 64, 1, false) |
114 | RVV_VECTOR_TYPE_INT("__rvv_uint64m4_t" ,RvvUint64m4,RvvUint64m4Ty,4, 64, 1, false) |
115 | RVV_VECTOR_TYPE_INT("__rvv_uint64m8_t" ,RvvUint64m8,RvvUint64m8Ty,8, 64, 1, false) |
116 | |
117 | RVV_VECTOR_TYPE_FLOAT("__rvv_float16mf4_t" ,RvvFloat16mf4,RvvFloat16mf4Ty,1, 16, 1) |
118 | RVV_VECTOR_TYPE_FLOAT("__rvv_float16mf2_t" ,RvvFloat16mf2,RvvFloat16mf2Ty,2, 16, 1) |
119 | RVV_VECTOR_TYPE_FLOAT("__rvv_float16m1_t" , RvvFloat16m1, RvvFloat16m1Ty, 4, 16, 1) |
120 | RVV_VECTOR_TYPE_FLOAT("__rvv_float16m2_t" , RvvFloat16m2, RvvFloat16m2Ty, 8, 16, 1) |
121 | RVV_VECTOR_TYPE_FLOAT("__rvv_float16m4_t" , RvvFloat16m4, RvvFloat16m4Ty, 16, 16, 1) |
122 | RVV_VECTOR_TYPE_FLOAT("__rvv_float16m8_t" , RvvFloat16m8, RvvFloat16m8Ty, 32, 16, 1) |
123 | |
124 | RVV_VECTOR_TYPE_FLOAT("__rvv_float32mf2_t" ,RvvFloat32mf2,RvvFloat32mf2Ty,1, 32, 1) |
125 | RVV_VECTOR_TYPE_FLOAT("__rvv_float32m1_t" , RvvFloat32m1, RvvFloat32m1Ty, 2, 32, 1) |
126 | RVV_VECTOR_TYPE_FLOAT("__rvv_float32m2_t" , RvvFloat32m2, RvvFloat32m2Ty, 4, 32, 1) |
127 | RVV_VECTOR_TYPE_FLOAT("__rvv_float32m4_t" , RvvFloat32m4, RvvFloat32m4Ty, 8, 32, 1) |
128 | RVV_VECTOR_TYPE_FLOAT("__rvv_float32m8_t" , RvvFloat32m8, RvvFloat32m8Ty, 16, 32, 1) |
129 | |
130 | RVV_VECTOR_TYPE_FLOAT("__rvv_float64m1_t" , RvvFloat64m1, RvvFloat64m1Ty, 1, 64, 1) |
131 | RVV_VECTOR_TYPE_FLOAT("__rvv_float64m2_t" , RvvFloat64m2, RvvFloat64m2Ty, 2, 64, 1) |
132 | RVV_VECTOR_TYPE_FLOAT("__rvv_float64m4_t" , RvvFloat64m4, RvvFloat64m4Ty, 4, 64, 1) |
133 | RVV_VECTOR_TYPE_FLOAT("__rvv_float64m8_t" , RvvFloat64m8, RvvFloat64m8Ty, 8, 64, 1) |
134 | |
135 | RVV_PREDICATE_TYPE("__rvv_bool1_t" , RvvBool1, RvvBool1Ty, 64) |
136 | RVV_PREDICATE_TYPE("__rvv_bool2_t" , RvvBool2, RvvBool2Ty, 32) |
137 | RVV_PREDICATE_TYPE("__rvv_bool4_t" , RvvBool4, RvvBool4Ty, 16) |
138 | RVV_PREDICATE_TYPE("__rvv_bool8_t" , RvvBool8, RvvBool8Ty, 8) |
139 | RVV_PREDICATE_TYPE("__rvv_bool16_t" , RvvBool16, RvvBool16Ty, 4) |
140 | RVV_PREDICATE_TYPE("__rvv_bool32_t" , RvvBool32, RvvBool32Ty, 2) |
141 | RVV_PREDICATE_TYPE("__rvv_bool64_t" , RvvBool64, RvvBool64Ty, 1) |
142 | |
143 | #undef RVV_VECTOR_TYPE_FLOAT |
144 | #undef RVV_VECTOR_TYPE_INT |
145 | #undef RVV_VECTOR_TYPE |
146 | #undef RVV_PREDICATE_TYPE |
147 | #undef RVV_TYPE |
148 | |