1 | //===-- llvm/CodeGen/ISDOpcodes.h - CodeGen opcodes -------------*- C++ -*-===// |
2 | // |
3 | // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. |
4 | // See https://llvm.org/LICENSE.txt for license information. |
5 | // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception |
6 | // |
7 | //===----------------------------------------------------------------------===// |
8 | // |
9 | // This file declares codegen opcodes and related utilities. |
10 | // |
11 | //===----------------------------------------------------------------------===// |
12 | |
13 | #ifndef LLVM_CODEGEN_ISDOPCODES_H |
14 | #define LLVM_CODEGEN_ISDOPCODES_H |
15 | |
16 | #include "llvm/CodeGen/ValueTypes.h" |
17 | |
18 | namespace llvm { |
19 | |
20 | /// ISD namespace - This namespace contains an enum which represents all of the |
21 | /// SelectionDAG node types and value types. |
22 | /// |
23 | namespace ISD { |
24 | |
25 | //===--------------------------------------------------------------------===// |
26 | /// ISD::NodeType enum - This enum defines the target-independent operators |
27 | /// for a SelectionDAG. |
28 | /// |
29 | /// Targets may also define target-dependent operator codes for SDNodes. For |
30 | /// example, on x86, these are the enum values in the X86ISD namespace. |
31 | /// Targets should aim to use target-independent operators to model their |
32 | /// instruction sets as much as possible, and only use target-dependent |
33 | /// operators when they have special requirements. |
34 | /// |
35 | /// Finally, during and after selection proper, SNodes may use special |
36 | /// operator codes that correspond directly with MachineInstr opcodes. These |
37 | /// are used to represent selected instructions. See the isMachineOpcode() |
38 | /// and getMachineOpcode() member functions of SDNode. |
39 | /// |
40 | enum NodeType { |
41 | |
42 | /// DELETED_NODE - This is an illegal value that is used to catch |
43 | /// errors. This opcode is not a legal opcode for any node. |
44 | DELETED_NODE, |
45 | |
46 | /// EntryToken - This is the marker used to indicate the start of a region. |
47 | EntryToken, |
48 | |
49 | /// TokenFactor - This node takes multiple tokens as input and produces a |
50 | /// single token result. This is used to represent the fact that the operand |
51 | /// operators are independent of each other. |
52 | TokenFactor, |
53 | |
54 | /// AssertSext, AssertZext - These nodes record if a register contains a |
55 | /// value that has already been zero or sign extended from a narrower type. |
56 | /// These nodes take two operands. The first is the node that has already |
57 | /// been extended, and the second is a value type node indicating the width |
58 | /// of the extension. |
59 | /// NOTE: In case of the source value (or any vector element value) is |
60 | /// poisoned the assertion will not be true for that value. |
61 | AssertSext, |
62 | AssertZext, |
63 | |
64 | /// AssertAlign - These nodes record if a register contains a value that |
65 | /// has a known alignment and the trailing bits are known to be zero. |
66 | /// NOTE: In case of the source value (or any vector element value) is |
67 | /// poisoned the assertion will not be true for that value. |
68 | AssertAlign, |
69 | |
70 | /// Various leaf nodes. |
71 | BasicBlock, |
72 | VALUETYPE, |
73 | CONDCODE, |
74 | Register, |
75 | RegisterMask, |
76 | Constant, |
77 | ConstantFP, |
78 | GlobalAddress, |
79 | GlobalTLSAddress, |
80 | FrameIndex, |
81 | JumpTable, |
82 | ConstantPool, |
83 | ExternalSymbol, |
84 | BlockAddress, |
85 | |
86 | /// The address of the GOT |
87 | GLOBAL_OFFSET_TABLE, |
88 | |
89 | /// FRAMEADDR, RETURNADDR - These nodes represent llvm.frameaddress and |
90 | /// llvm.returnaddress on the DAG. These nodes take one operand, the index |
91 | /// of the frame or return address to return. An index of zero corresponds |
92 | /// to the current function's frame or return address, an index of one to |
93 | /// the parent's frame or return address, and so on. |
94 | FRAMEADDR, |
95 | RETURNADDR, |
96 | |
97 | /// ADDROFRETURNADDR - Represents the llvm.addressofreturnaddress intrinsic. |
98 | /// This node takes no operand, returns a target-specific pointer to the |
99 | /// place in the stack frame where the return address of the current |
100 | /// function is stored. |
101 | ADDROFRETURNADDR, |
102 | |
103 | /// SPONENTRY - Represents the llvm.sponentry intrinsic. Takes no argument |
104 | /// and returns the stack pointer value at the entry of the current |
105 | /// function calling this intrinsic. |
106 | SPONENTRY, |
107 | |
108 | /// LOCAL_RECOVER - Represents the llvm.localrecover intrinsic. |
109 | /// Materializes the offset from the local object pointer of another |
110 | /// function to a particular local object passed to llvm.localescape. The |
111 | /// operand is the MCSymbol label used to represent this offset, since |
112 | /// typically the offset is not known until after code generation of the |
113 | /// parent. |
114 | LOCAL_RECOVER, |
115 | |
116 | /// READ_REGISTER, WRITE_REGISTER - This node represents llvm.register on |
117 | /// the DAG, which implements the named register global variables extension. |
118 | READ_REGISTER, |
119 | WRITE_REGISTER, |
120 | |
121 | /// FRAME_TO_ARGS_OFFSET - This node represents offset from frame pointer to |
122 | /// first (possible) on-stack argument. This is needed for correct stack |
123 | /// adjustment during unwind. |
124 | FRAME_TO_ARGS_OFFSET, |
125 | |
126 | /// EH_DWARF_CFA - This node represents the pointer to the DWARF Canonical |
127 | /// Frame Address (CFA), generally the value of the stack pointer at the |
128 | /// call site in the previous frame. |
129 | EH_DWARF_CFA, |
130 | |
131 | /// OUTCHAIN = EH_RETURN(INCHAIN, OFFSET, HANDLER) - This node represents |
132 | /// 'eh_return' gcc dwarf builtin, which is used to return from |
133 | /// exception. The general meaning is: adjust stack by OFFSET and pass |
134 | /// execution to HANDLER. Many platform-related details also :) |
135 | EH_RETURN, |
136 | |
137 | /// RESULT, OUTCHAIN = EH_SJLJ_SETJMP(INCHAIN, buffer) |
138 | /// This corresponds to the eh.sjlj.setjmp intrinsic. |
139 | /// It takes an input chain and a pointer to the jump buffer as inputs |
140 | /// and returns an outchain. |
141 | EH_SJLJ_SETJMP, |
142 | |
143 | /// OUTCHAIN = EH_SJLJ_LONGJMP(INCHAIN, buffer) |
144 | /// This corresponds to the eh.sjlj.longjmp intrinsic. |
145 | /// It takes an input chain and a pointer to the jump buffer as inputs |
146 | /// and returns an outchain. |
147 | EH_SJLJ_LONGJMP, |
148 | |
149 | /// OUTCHAIN = EH_SJLJ_SETUP_DISPATCH(INCHAIN) |
150 | /// The target initializes the dispatch table here. |
151 | EH_SJLJ_SETUP_DISPATCH, |
152 | |
153 | /// TargetConstant* - Like Constant*, but the DAG does not do any folding, |
154 | /// simplification, or lowering of the constant. They are used for constants |
155 | /// which are known to fit in the immediate fields of their users, or for |
156 | /// carrying magic numbers which are not values which need to be |
157 | /// materialized in registers. |
158 | TargetConstant, |
159 | TargetConstantFP, |
160 | |
161 | /// TargetGlobalAddress - Like GlobalAddress, but the DAG does no folding or |
162 | /// anything else with this node, and this is valid in the target-specific |
163 | /// dag, turning into a GlobalAddress operand. |
164 | TargetGlobalAddress, |
165 | TargetGlobalTLSAddress, |
166 | TargetFrameIndex, |
167 | TargetJumpTable, |
168 | TargetConstantPool, |
169 | TargetExternalSymbol, |
170 | TargetBlockAddress, |
171 | |
172 | MCSymbol, |
173 | |
174 | /// TargetIndex - Like a constant pool entry, but with completely |
175 | /// target-dependent semantics. Holds target flags, a 32-bit index, and a |
176 | /// 64-bit index. Targets can use this however they like. |
177 | TargetIndex, |
178 | |
179 | /// RESULT = INTRINSIC_WO_CHAIN(INTRINSICID, arg1, arg2, ...) |
180 | /// This node represents a target intrinsic function with no side effects. |
181 | /// The first operand is the ID number of the intrinsic from the |
182 | /// llvm::Intrinsic namespace. The operands to the intrinsic follow. The |
183 | /// node returns the result of the intrinsic. |
184 | INTRINSIC_WO_CHAIN, |
185 | |
186 | /// RESULT,OUTCHAIN = INTRINSIC_W_CHAIN(INCHAIN, INTRINSICID, arg1, ...) |
187 | /// This node represents a target intrinsic function with side effects that |
188 | /// returns a result. The first operand is a chain pointer. The second is |
189 | /// the ID number of the intrinsic from the llvm::Intrinsic namespace. The |
190 | /// operands to the intrinsic follow. The node has two results, the result |
191 | /// of the intrinsic and an output chain. |
192 | INTRINSIC_W_CHAIN, |
193 | |
194 | /// OUTCHAIN = INTRINSIC_VOID(INCHAIN, INTRINSICID, arg1, arg2, ...) |
195 | /// This node represents a target intrinsic function with side effects that |
196 | /// does not return a result. The first operand is a chain pointer. The |
197 | /// second is the ID number of the intrinsic from the llvm::Intrinsic |
198 | /// namespace. The operands to the intrinsic follow. |
199 | INTRINSIC_VOID, |
200 | |
201 | /// CopyToReg - This node has three operands: a chain, a register number to |
202 | /// set to this value, and a value. |
203 | CopyToReg, |
204 | |
205 | /// CopyFromReg - This node indicates that the input value is a virtual or |
206 | /// physical register that is defined outside of the scope of this |
207 | /// SelectionDAG. The register is available from the RegisterSDNode object. |
208 | CopyFromReg, |
209 | |
210 | /// UNDEF - An undefined node. |
211 | UNDEF, |
212 | |
213 | // FREEZE - FREEZE(VAL) returns an arbitrary value if VAL is UNDEF (or |
214 | // is evaluated to UNDEF), or returns VAL otherwise. Note that each |
215 | // read of UNDEF can yield different value, but FREEZE(UNDEF) cannot. |
216 | FREEZE, |
217 | |
218 | /// EXTRACT_ELEMENT - This is used to get the lower or upper (determined by |
219 | /// a Constant, which is required to be operand #1) half of the integer or |
220 | /// float value specified as operand #0. This is only for use before |
221 | /// legalization, for values that will be broken into multiple registers. |
222 | , |
223 | |
224 | /// BUILD_PAIR - This is the opposite of EXTRACT_ELEMENT in some ways. |
225 | /// Given two values of the same integer value type, this produces a value |
226 | /// twice as big. Like EXTRACT_ELEMENT, this can only be used before |
227 | /// legalization. The lower part of the composite value should be in |
228 | /// element 0 and the upper part should be in element 1. |
229 | BUILD_PAIR, |
230 | |
231 | /// MERGE_VALUES - This node takes multiple discrete operands and returns |
232 | /// them all as its individual results. This nodes has exactly the same |
233 | /// number of inputs and outputs. This node is useful for some pieces of the |
234 | /// code generator that want to think about a single node with multiple |
235 | /// results, not multiple nodes. |
236 | MERGE_VALUES, |
237 | |
238 | /// Simple integer binary arithmetic operators. |
239 | ADD, |
240 | SUB, |
241 | MUL, |
242 | SDIV, |
243 | UDIV, |
244 | SREM, |
245 | UREM, |
246 | |
247 | /// SMUL_LOHI/UMUL_LOHI - Multiply two integers of type iN, producing |
248 | /// a signed/unsigned value of type i[2*N], and return the full value as |
249 | /// two results, each of type iN. |
250 | SMUL_LOHI, |
251 | UMUL_LOHI, |
252 | |
253 | /// SDIVREM/UDIVREM - Divide two integers and produce both a quotient and |
254 | /// remainder result. |
255 | SDIVREM, |
256 | UDIVREM, |
257 | |
258 | /// CARRY_FALSE - This node is used when folding other nodes, |
259 | /// like ADDC/SUBC, which indicate the carry result is always false. |
260 | CARRY_FALSE, |
261 | |
262 | /// Carry-setting nodes for multiple precision addition and subtraction. |
263 | /// These nodes take two operands of the same value type, and produce two |
264 | /// results. The first result is the normal add or sub result, the second |
265 | /// result is the carry flag result. |
266 | /// FIXME: These nodes are deprecated in favor of UADDO_CARRY and USUBO_CARRY. |
267 | /// They are kept around for now to provide a smooth transition path |
268 | /// toward the use of UADDO_CARRY/USUBO_CARRY and will eventually be removed. |
269 | ADDC, |
270 | SUBC, |
271 | |
272 | /// Carry-using nodes for multiple precision addition and subtraction. These |
273 | /// nodes take three operands: The first two are the normal lhs and rhs to |
274 | /// the add or sub, and the third is the input carry flag. These nodes |
275 | /// produce two results; the normal result of the add or sub, and the output |
276 | /// carry flag. These nodes both read and write a carry flag to allow them |
277 | /// to them to be chained together for add and sub of arbitrarily large |
278 | /// values. |
279 | ADDE, |
280 | SUBE, |
281 | |
282 | /// Carry-using nodes for multiple precision addition and subtraction. |
283 | /// These nodes take three operands: The first two are the normal lhs and |
284 | /// rhs to the add or sub, and the third is a boolean value that is 1 if and |
285 | /// only if there is an incoming carry/borrow. These nodes produce two |
286 | /// results: the normal result of the add or sub, and a boolean value that is |
287 | /// 1 if and only if there is an outgoing carry/borrow. |
288 | /// |
289 | /// Care must be taken if these opcodes are lowered to hardware instructions |
290 | /// that use the inverse logic -- 0 if and only if there is an |
291 | /// incoming/outgoing carry/borrow. In such cases, you must preserve the |
292 | /// semantics of these opcodes by inverting the incoming carry/borrow, feeding |
293 | /// it to the add/sub hardware instruction, and then inverting the outgoing |
294 | /// carry/borrow. |
295 | /// |
296 | /// The use of these opcodes is preferable to adde/sube if the target supports |
297 | /// it, as the carry is a regular value rather than a glue, which allows |
298 | /// further optimisation. |
299 | /// |
300 | /// These opcodes are different from [US]{ADD,SUB}O in that |
301 | /// U{ADD,SUB}O_CARRY consume and produce a carry/borrow, whereas |
302 | /// [US]{ADD,SUB}O produce an overflow. |
303 | UADDO_CARRY, |
304 | USUBO_CARRY, |
305 | |
306 | /// Carry-using overflow-aware nodes for multiple precision addition and |
307 | /// subtraction. These nodes take three operands: The first two are normal lhs |
308 | /// and rhs to the add or sub, and the third is a boolean indicating if there |
309 | /// is an incoming carry. They produce two results: the normal result of the |
310 | /// add or sub, and a boolean that indicates if an overflow occurred (*not* |
311 | /// flag, because it may be a store to memory, etc.). If the type of the |
312 | /// boolean is not i1 then the high bits conform to getBooleanContents. |
313 | SADDO_CARRY, |
314 | SSUBO_CARRY, |
315 | |
316 | /// RESULT, BOOL = [SU]ADDO(LHS, RHS) - Overflow-aware nodes for addition. |
317 | /// These nodes take two operands: the normal LHS and RHS to the add. They |
318 | /// produce two results: the normal result of the add, and a boolean that |
319 | /// indicates if an overflow occurred (*not* a flag, because it may be store |
320 | /// to memory, etc.). If the type of the boolean is not i1 then the high |
321 | /// bits conform to getBooleanContents. |
322 | /// These nodes are generated from llvm.[su]add.with.overflow intrinsics. |
323 | SADDO, |
324 | UADDO, |
325 | |
326 | /// Same for subtraction. |
327 | SSUBO, |
328 | USUBO, |
329 | |
330 | /// Same for multiplication. |
331 | SMULO, |
332 | UMULO, |
333 | |
334 | /// RESULT = [US]ADDSAT(LHS, RHS) - Perform saturation addition on 2 |
335 | /// integers with the same bit width (W). If the true value of LHS + RHS |
336 | /// exceeds the largest value that can be represented by W bits, the |
337 | /// resulting value is this maximum value. Otherwise, if this value is less |
338 | /// than the smallest value that can be represented by W bits, the |
339 | /// resulting value is this minimum value. |
340 | SADDSAT, |
341 | UADDSAT, |
342 | |
343 | /// RESULT = [US]SUBSAT(LHS, RHS) - Perform saturation subtraction on 2 |
344 | /// integers with the same bit width (W). If the true value of LHS - RHS |
345 | /// exceeds the largest value that can be represented by W bits, the |
346 | /// resulting value is this maximum value. Otherwise, if this value is less |
347 | /// than the smallest value that can be represented by W bits, the |
348 | /// resulting value is this minimum value. |
349 | SSUBSAT, |
350 | USUBSAT, |
351 | |
352 | /// RESULT = [US]SHLSAT(LHS, RHS) - Perform saturation left shift. The first |
353 | /// operand is the value to be shifted, and the second argument is the amount |
354 | /// to shift by. Both must be integers of the same bit width (W). If the true |
355 | /// value of LHS << RHS exceeds the largest value that can be represented by |
356 | /// W bits, the resulting value is this maximum value, Otherwise, if this |
357 | /// value is less than the smallest value that can be represented by W bits, |
358 | /// the resulting value is this minimum value. |
359 | SSHLSAT, |
360 | USHLSAT, |
361 | |
362 | /// RESULT = [US]MULFIX(LHS, RHS, SCALE) - Perform fixed point multiplication |
363 | /// on 2 integers with the same width and scale. SCALE represents the scale |
364 | /// of both operands as fixed point numbers. This SCALE parameter must be a |
365 | /// constant integer. A scale of zero is effectively performing |
366 | /// multiplication on 2 integers. |
367 | SMULFIX, |
368 | UMULFIX, |
369 | |
370 | /// Same as the corresponding unsaturated fixed point instructions, but the |
371 | /// result is clamped between the min and max values representable by the |
372 | /// bits of the first 2 operands. |
373 | SMULFIXSAT, |
374 | UMULFIXSAT, |
375 | |
376 | /// RESULT = [US]DIVFIX(LHS, RHS, SCALE) - Perform fixed point division on |
377 | /// 2 integers with the same width and scale. SCALE represents the scale |
378 | /// of both operands as fixed point numbers. This SCALE parameter must be a |
379 | /// constant integer. |
380 | SDIVFIX, |
381 | UDIVFIX, |
382 | |
383 | /// Same as the corresponding unsaturated fixed point instructions, but the |
384 | /// result is clamped between the min and max values representable by the |
385 | /// bits of the first 2 operands. |
386 | SDIVFIXSAT, |
387 | UDIVFIXSAT, |
388 | |
389 | /// Simple binary floating point operators. |
390 | FADD, |
391 | FSUB, |
392 | FMUL, |
393 | FDIV, |
394 | FREM, |
395 | |
396 | /// Constrained versions of the binary floating point operators. |
397 | /// These will be lowered to the simple operators before final selection. |
398 | /// They are used to limit optimizations while the DAG is being |
399 | /// optimized. |
400 | STRICT_FADD, |
401 | STRICT_FSUB, |
402 | STRICT_FMUL, |
403 | STRICT_FDIV, |
404 | STRICT_FREM, |
405 | STRICT_FMA, |
406 | |
407 | /// Constrained versions of libm-equivalent floating point intrinsics. |
408 | /// These will be lowered to the equivalent non-constrained pseudo-op |
409 | /// (or expanded to the equivalent library call) before final selection. |
410 | /// They are used to limit optimizations while the DAG is being optimized. |
411 | STRICT_FSQRT, |
412 | STRICT_FPOW, |
413 | STRICT_FPOWI, |
414 | STRICT_FLDEXP, |
415 | STRICT_FSIN, |
416 | STRICT_FCOS, |
417 | STRICT_FEXP, |
418 | STRICT_FEXP2, |
419 | STRICT_FLOG, |
420 | STRICT_FLOG10, |
421 | STRICT_FLOG2, |
422 | STRICT_FRINT, |
423 | STRICT_FNEARBYINT, |
424 | STRICT_FMAXNUM, |
425 | STRICT_FMINNUM, |
426 | STRICT_FCEIL, |
427 | STRICT_FFLOOR, |
428 | STRICT_FROUND, |
429 | STRICT_FROUNDEVEN, |
430 | STRICT_FTRUNC, |
431 | STRICT_LROUND, |
432 | STRICT_LLROUND, |
433 | STRICT_LRINT, |
434 | STRICT_LLRINT, |
435 | STRICT_FMAXIMUM, |
436 | STRICT_FMINIMUM, |
437 | |
438 | /// STRICT_FP_TO_[US]INT - Convert a floating point value to a signed or |
439 | /// unsigned integer. These have the same semantics as fptosi and fptoui |
440 | /// in IR. |
441 | /// They are used to limit optimizations while the DAG is being optimized. |
442 | STRICT_FP_TO_SINT, |
443 | STRICT_FP_TO_UINT, |
444 | |
445 | /// STRICT_[US]INT_TO_FP - Convert a signed or unsigned integer to |
446 | /// a floating point value. These have the same semantics as sitofp and |
447 | /// uitofp in IR. |
448 | /// They are used to limit optimizations while the DAG is being optimized. |
449 | STRICT_SINT_TO_FP, |
450 | STRICT_UINT_TO_FP, |
451 | |
452 | /// X = STRICT_FP_ROUND(Y, TRUNC) - Rounding 'Y' from a larger floating |
453 | /// point type down to the precision of the destination VT. TRUNC is a |
454 | /// flag, which is always an integer that is zero or one. If TRUNC is 0, |
455 | /// this is a normal rounding, if it is 1, this FP_ROUND is known to not |
456 | /// change the value of Y. |
457 | /// |
458 | /// The TRUNC = 1 case is used in cases where we know that the value will |
459 | /// not be modified by the node, because Y is not using any of the extra |
460 | /// precision of source type. This allows certain transformations like |
461 | /// STRICT_FP_EXTEND(STRICT_FP_ROUND(X,1)) -> X which are not safe for |
462 | /// STRICT_FP_EXTEND(STRICT_FP_ROUND(X,0)) because the extra bits aren't |
463 | /// removed. |
464 | /// It is used to limit optimizations while the DAG is being optimized. |
465 | STRICT_FP_ROUND, |
466 | |
467 | /// X = STRICT_FP_EXTEND(Y) - Extend a smaller FP type into a larger FP |
468 | /// type. |
469 | /// It is used to limit optimizations while the DAG is being optimized. |
470 | STRICT_FP_EXTEND, |
471 | |
472 | /// STRICT_FSETCC/STRICT_FSETCCS - Constrained versions of SETCC, used |
473 | /// for floating-point operands only. STRICT_FSETCC performs a quiet |
474 | /// comparison operation, while STRICT_FSETCCS performs a signaling |
475 | /// comparison operation. |
476 | STRICT_FSETCC, |
477 | STRICT_FSETCCS, |
478 | |
479 | // FPTRUNC_ROUND - This corresponds to the fptrunc_round intrinsic. |
480 | FPTRUNC_ROUND, |
481 | |
482 | /// FMA - Perform a * b + c with no intermediate rounding step. |
483 | FMA, |
484 | |
485 | /// FMAD - Perform a * b + c, while getting the same result as the |
486 | /// separately rounded operations. |
487 | FMAD, |
488 | |
489 | /// FCOPYSIGN(X, Y) - Return the value of X with the sign of Y. NOTE: This |
490 | /// DAG node does not require that X and Y have the same type, just that |
491 | /// they are both floating point. X and the result must have the same type. |
492 | /// FCOPYSIGN(f32, f64) is allowed. |
493 | FCOPYSIGN, |
494 | |
495 | /// INT = FGETSIGN(FP) - Return the sign bit of the specified floating point |
496 | /// value as an integer 0/1 value. |
497 | FGETSIGN, |
498 | |
499 | /// Returns platform specific canonical encoding of a floating point number. |
500 | FCANONICALIZE, |
501 | |
502 | /// Performs a check of floating point class property, defined by IEEE-754. |
503 | /// The first operand is the floating point value to check. The second operand |
504 | /// specifies the checked property and is a TargetConstant which specifies |
505 | /// test in the same way as intrinsic 'is_fpclass'. |
506 | /// Returns boolean value. |
507 | IS_FPCLASS, |
508 | |
509 | /// BUILD_VECTOR(ELT0, ELT1, ELT2, ELT3,...) - Return a fixed-width vector |
510 | /// with the specified, possibly variable, elements. The types of the |
511 | /// operands must match the vector element type, except that integer types |
512 | /// are allowed to be larger than the element type, in which case the |
513 | /// operands are implicitly truncated. The types of the operands must all |
514 | /// be the same. |
515 | BUILD_VECTOR, |
516 | |
517 | /// INSERT_VECTOR_ELT(VECTOR, VAL, IDX) - Returns VECTOR with the element |
518 | /// at IDX replaced with VAL. If the type of VAL is larger than the vector |
519 | /// element type then VAL is truncated before replacement. |
520 | /// |
521 | /// If VECTOR is a scalable vector, then IDX may be larger than the minimum |
522 | /// vector width. IDX is not first scaled by the runtime scaling factor of |
523 | /// VECTOR. |
524 | INSERT_VECTOR_ELT, |
525 | |
526 | /// EXTRACT_VECTOR_ELT(VECTOR, IDX) - Returns a single element from VECTOR |
527 | /// identified by the (potentially variable) element number IDX. If the return |
528 | /// type is an integer type larger than the element type of the vector, the |
529 | /// result is extended to the width of the return type. In that case, the high |
530 | /// bits are undefined. |
531 | /// |
532 | /// If VECTOR is a scalable vector, then IDX may be larger than the minimum |
533 | /// vector width. IDX is not first scaled by the runtime scaling factor of |
534 | /// VECTOR. |
535 | , |
536 | |
537 | /// CONCAT_VECTORS(VECTOR0, VECTOR1, ...) - Given a number of values of |
538 | /// vector type with the same length and element type, this produces a |
539 | /// concatenated vector result value, with length equal to the sum of the |
540 | /// lengths of the input vectors. If VECTOR0 is a fixed-width vector, then |
541 | /// VECTOR1..VECTORN must all be fixed-width vectors. Similarly, if VECTOR0 |
542 | /// is a scalable vector, then VECTOR1..VECTORN must all be scalable vectors. |
543 | CONCAT_VECTORS, |
544 | |
545 | /// INSERT_SUBVECTOR(VECTOR1, VECTOR2, IDX) - Returns a vector with VECTOR2 |
546 | /// inserted into VECTOR1. IDX represents the starting element number at which |
547 | /// VECTOR2 will be inserted. IDX must be a constant multiple of T's known |
548 | /// minimum vector length. Let the type of VECTOR2 be T, then if T is a |
549 | /// scalable vector, IDX is first scaled by the runtime scaling factor of T. |
550 | /// The elements of VECTOR1 starting at IDX are overwritten with VECTOR2. |
551 | /// Elements IDX through (IDX + num_elements(T) - 1) must be valid VECTOR1 |
552 | /// indices. If this condition cannot be determined statically but is false at |
553 | /// runtime, then the result vector is undefined. The IDX parameter must be a |
554 | /// vector index constant type, which for most targets will be an integer |
555 | /// pointer type. |
556 | /// |
557 | /// This operation supports inserting a fixed-width vector into a scalable |
558 | /// vector, but not the other way around. |
559 | INSERT_SUBVECTOR, |
560 | |
561 | /// EXTRACT_SUBVECTOR(VECTOR, IDX) - Returns a subvector from VECTOR. |
562 | /// Let the result type be T, then IDX represents the starting element number |
563 | /// from which a subvector of type T is extracted. IDX must be a constant |
564 | /// multiple of T's known minimum vector length. If T is a scalable vector, |
565 | /// IDX is first scaled by the runtime scaling factor of T. Elements IDX |
566 | /// through (IDX + num_elements(T) - 1) must be valid VECTOR indices. If this |
567 | /// condition cannot be determined statically but is false at runtime, then |
568 | /// the result vector is undefined. The IDX parameter must be a vector index |
569 | /// constant type, which for most targets will be an integer pointer type. |
570 | /// |
571 | /// This operation supports extracting a fixed-width vector from a scalable |
572 | /// vector, but not the other way around. |
573 | , |
574 | |
575 | /// VECTOR_DEINTERLEAVE(VEC1, VEC2) - Returns two vectors with all input and |
576 | /// output vectors having the same type. The first output contains the even |
577 | /// indices from CONCAT_VECTORS(VEC1, VEC2), with the second output |
578 | /// containing the odd indices. The relative order of elements within an |
579 | /// output match that of the concatenated input. |
580 | VECTOR_DEINTERLEAVE, |
581 | |
582 | /// VECTOR_INTERLEAVE(VEC1, VEC2) - Returns two vectors with all input and |
583 | /// output vectors having the same type. The first output contains the |
584 | /// result of interleaving the low half of CONCAT_VECTORS(VEC1, VEC2), with |
585 | /// the second output containing the result of interleaving the high half. |
586 | VECTOR_INTERLEAVE, |
587 | |
588 | /// VECTOR_REVERSE(VECTOR) - Returns a vector, of the same type as VECTOR, |
589 | /// whose elements are shuffled using the following algorithm: |
590 | /// RESULT[i] = VECTOR[VECTOR.ElementCount - 1 - i] |
591 | VECTOR_REVERSE, |
592 | |
593 | /// VECTOR_SHUFFLE(VEC1, VEC2) - Returns a vector, of the same type as |
594 | /// VEC1/VEC2. A VECTOR_SHUFFLE node also contains an array of constant int |
595 | /// values that indicate which value (or undef) each result element will |
596 | /// get. These constant ints are accessible through the |
597 | /// ShuffleVectorSDNode class. This is quite similar to the Altivec |
598 | /// 'vperm' instruction, except that the indices must be constants and are |
599 | /// in terms of the element size of VEC1/VEC2, not in terms of bytes. |
600 | VECTOR_SHUFFLE, |
601 | |
602 | /// VECTOR_SPLICE(VEC1, VEC2, IMM) - Returns a subvector of the same type as |
603 | /// VEC1/VEC2 from CONCAT_VECTORS(VEC1, VEC2), based on the IMM in two ways. |
604 | /// Let the result type be T, if IMM is positive it represents the starting |
605 | /// element number (an index) from which a subvector of type T is extracted |
606 | /// from CONCAT_VECTORS(VEC1, VEC2). If IMM is negative it represents a count |
607 | /// specifying the number of trailing elements to extract from VEC1, where the |
608 | /// elements of T are selected using the following algorithm: |
609 | /// RESULT[i] = CONCAT_VECTORS(VEC1,VEC2)[VEC1.ElementCount - ABS(IMM) + i] |
610 | /// If IMM is not in the range [-VL, VL-1] the result vector is undefined. IMM |
611 | /// is a constant integer. |
612 | VECTOR_SPLICE, |
613 | |
614 | /// SCALAR_TO_VECTOR(VAL) - This represents the operation of loading a |
615 | /// scalar value into element 0 of the resultant vector type. The top |
616 | /// elements 1 to N-1 of the N-element vector are undefined. The type |
617 | /// of the operand must match the vector element type, except when they |
618 | /// are integer types. In this case the operand is allowed to be wider |
619 | /// than the vector element type, and is implicitly truncated to it. |
620 | SCALAR_TO_VECTOR, |
621 | |
622 | /// SPLAT_VECTOR(VAL) - Returns a vector with the scalar value VAL |
623 | /// duplicated in all lanes. The type of the operand must match the vector |
624 | /// element type, except when they are integer types. In this case the |
625 | /// operand is allowed to be wider than the vector element type, and is |
626 | /// implicitly truncated to it. |
627 | SPLAT_VECTOR, |
628 | |
629 | /// SPLAT_VECTOR_PARTS(SCALAR1, SCALAR2, ...) - Returns a vector with the |
630 | /// scalar values joined together and then duplicated in all lanes. This |
631 | /// represents a SPLAT_VECTOR that has had its scalar operand expanded. This |
632 | /// allows representing a 64-bit splat on a target with 32-bit integers. The |
633 | /// total width of the scalars must cover the element width. SCALAR1 contains |
634 | /// the least significant bits of the value regardless of endianness and all |
635 | /// scalars should have the same type. |
636 | SPLAT_VECTOR_PARTS, |
637 | |
638 | /// STEP_VECTOR(IMM) - Returns a scalable vector whose lanes are comprised |
639 | /// of a linear sequence of unsigned values starting from 0 with a step of |
640 | /// IMM, where IMM must be a TargetConstant with type equal to the vector |
641 | /// element type. The arithmetic is performed modulo the bitwidth of the |
642 | /// element. |
643 | /// |
644 | /// The operation does not support returning fixed-width vectors or |
645 | /// non-constant operands. |
646 | STEP_VECTOR, |
647 | |
648 | /// MULHU/MULHS - Multiply high - Multiply two integers of type iN, |
649 | /// producing an unsigned/signed value of type i[2*N], then return the top |
650 | /// part. |
651 | MULHU, |
652 | MULHS, |
653 | |
654 | /// AVGFLOORS/AVGFLOORU - Averaging add - Add two integers using an integer of |
655 | /// type i[N+1], halving the result by shifting it one bit right. |
656 | /// shr(add(ext(X), ext(Y)), 1) |
657 | AVGFLOORS, |
658 | AVGFLOORU, |
659 | /// AVGCEILS/AVGCEILU - Rounding averaging add - Add two integers using an |
660 | /// integer of type i[N+2], add 1 and halve the result by shifting it one bit |
661 | /// right. shr(add(ext(X), ext(Y), 1), 1) |
662 | AVGCEILS, |
663 | AVGCEILU, |
664 | |
665 | // ABDS/ABDU - Absolute difference - Return the absolute difference between |
666 | // two numbers interpreted as signed/unsigned. |
667 | // i.e trunc(abs(sext(Op0) - sext(Op1))) becomes abds(Op0, Op1) |
668 | // or trunc(abs(zext(Op0) - zext(Op1))) becomes abdu(Op0, Op1) |
669 | ABDS, |
670 | ABDU, |
671 | |
672 | /// [US]{MIN/MAX} - Binary minimum or maximum of signed or unsigned |
673 | /// integers. |
674 | SMIN, |
675 | SMAX, |
676 | UMIN, |
677 | UMAX, |
678 | |
679 | /// Bitwise operators - logical and, logical or, logical xor. |
680 | AND, |
681 | OR, |
682 | XOR, |
683 | |
684 | /// ABS - Determine the unsigned absolute value of a signed integer value of |
685 | /// the same bitwidth. |
686 | /// Note: A value of INT_MIN will return INT_MIN, no saturation or overflow |
687 | /// is performed. |
688 | ABS, |
689 | |
690 | /// Shift and rotation operations. After legalization, the type of the |
691 | /// shift amount is known to be TLI.getShiftAmountTy(). Before legalization |
692 | /// the shift amount can be any type, but care must be taken to ensure it is |
693 | /// large enough. TLI.getShiftAmountTy() is i8 on some targets, but before |
694 | /// legalization, types like i1024 can occur and i8 doesn't have enough bits |
695 | /// to represent the shift amount. |
696 | /// When the 1st operand is a vector, the shift amount must be in the same |
697 | /// type. (TLI.getShiftAmountTy() will return the same type when the input |
698 | /// type is a vector.) |
699 | /// For rotates and funnel shifts, the shift amount is treated as an unsigned |
700 | /// amount modulo the element size of the first operand. |
701 | /// |
702 | /// Funnel 'double' shifts take 3 operands, 2 inputs and the shift amount. |
703 | /// fshl(X,Y,Z): (X << (Z % BW)) | (Y >> (BW - (Z % BW))) |
704 | /// fshr(X,Y,Z): (X << (BW - (Z % BW))) | (Y >> (Z % BW)) |
705 | SHL, |
706 | SRA, |
707 | SRL, |
708 | ROTL, |
709 | ROTR, |
710 | FSHL, |
711 | FSHR, |
712 | |
713 | /// Byte Swap and Counting operators. |
714 | BSWAP, |
715 | CTTZ, |
716 | CTLZ, |
717 | CTPOP, |
718 | BITREVERSE, |
719 | PARITY, |
720 | |
721 | /// Bit counting operators with an undefined result for zero inputs. |
722 | CTTZ_ZERO_UNDEF, |
723 | CTLZ_ZERO_UNDEF, |
724 | |
725 | /// Select(COND, TRUEVAL, FALSEVAL). If the type of the boolean COND is not |
726 | /// i1 then the high bits must conform to getBooleanContents. |
727 | SELECT, |
728 | |
729 | /// Select with a vector condition (op #0) and two vector operands (ops #1 |
730 | /// and #2), returning a vector result. All vectors have the same length. |
731 | /// Much like the scalar select and setcc, each bit in the condition selects |
732 | /// whether the corresponding result element is taken from op #1 or op #2. |
733 | /// At first, the VSELECT condition is of vXi1 type. Later, targets may |
734 | /// change the condition type in order to match the VSELECT node using a |
735 | /// pattern. The condition follows the BooleanContent format of the target. |
736 | VSELECT, |
737 | |
738 | /// Select with condition operator - This selects between a true value and |
739 | /// a false value (ops #2 and #3) based on the boolean result of comparing |
740 | /// the lhs and rhs (ops #0 and #1) of a conditional expression with the |
741 | /// condition code in op #4, a CondCodeSDNode. |
742 | SELECT_CC, |
743 | |
744 | /// SetCC operator - This evaluates to a true value iff the condition is |
745 | /// true. If the result value type is not i1 then the high bits conform |
746 | /// to getBooleanContents. The operands to this are the left and right |
747 | /// operands to compare (ops #0, and #1) and the condition code to compare |
748 | /// them with (op #2) as a CondCodeSDNode. If the operands are vector types |
749 | /// then the result type must also be a vector type. |
750 | SETCC, |
751 | |
752 | /// Like SetCC, ops #0 and #1 are the LHS and RHS operands to compare, but |
753 | /// op #2 is a boolean indicating if there is an incoming carry. This |
754 | /// operator checks the result of "LHS - RHS - Carry", and can be used to |
755 | /// compare two wide integers: |
756 | /// (setcccarry lhshi rhshi (usubo_carry lhslo rhslo) cc). |
757 | /// Only valid for integers. |
758 | SETCCCARRY, |
759 | |
760 | /// SHL_PARTS/SRA_PARTS/SRL_PARTS - These operators are used for expanded |
761 | /// integer shift operations. The operation ordering is: |
762 | /// [Lo,Hi] = op [LoLHS,HiLHS], Amt |
763 | SHL_PARTS, |
764 | SRA_PARTS, |
765 | SRL_PARTS, |
766 | |
767 | /// Conversion operators. These are all single input single output |
768 | /// operations. For all of these, the result type must be strictly |
769 | /// wider or narrower (depending on the operation) than the source |
770 | /// type. |
771 | |
772 | /// SIGN_EXTEND - Used for integer types, replicating the sign bit |
773 | /// into new bits. |
774 | SIGN_EXTEND, |
775 | |
776 | /// ZERO_EXTEND - Used for integer types, zeroing the new bits. Can carry |
777 | /// the NonNeg SDNodeFlag to indicate that the input is known to be |
778 | /// non-negative. If the flag is present and the input is negative, the result |
779 | /// is poison. |
780 | ZERO_EXTEND, |
781 | |
782 | /// ANY_EXTEND - Used for integer types. The high bits are undefined. |
783 | ANY_EXTEND, |
784 | |
785 | /// TRUNCATE - Completely drop the high bits. |
786 | TRUNCATE, |
787 | |
788 | /// [SU]INT_TO_FP - These operators convert integers (whose interpreted sign |
789 | /// depends on the first letter) to floating point. |
790 | SINT_TO_FP, |
791 | UINT_TO_FP, |
792 | |
793 | /// SIGN_EXTEND_INREG - This operator atomically performs a SHL/SRA pair to |
794 | /// sign extend a small value in a large integer register (e.g. sign |
795 | /// extending the low 8 bits of a 32-bit register to fill the top 24 bits |
796 | /// with the 7th bit). The size of the smaller type is indicated by the 1th |
797 | /// operand, a ValueType node. |
798 | SIGN_EXTEND_INREG, |
799 | |
800 | /// ANY_EXTEND_VECTOR_INREG(Vector) - This operator represents an |
801 | /// in-register any-extension of the low lanes of an integer vector. The |
802 | /// result type must have fewer elements than the operand type, and those |
803 | /// elements must be larger integer types such that the total size of the |
804 | /// operand type is less than or equal to the size of the result type. Each |
805 | /// of the low operand elements is any-extended into the corresponding, |
806 | /// wider result elements with the high bits becoming undef. |
807 | /// NOTE: The type legalizer prefers to make the operand and result size |
808 | /// the same to allow expansion to shuffle vector during op legalization. |
809 | ANY_EXTEND_VECTOR_INREG, |
810 | |
811 | /// SIGN_EXTEND_VECTOR_INREG(Vector) - This operator represents an |
812 | /// in-register sign-extension of the low lanes of an integer vector. The |
813 | /// result type must have fewer elements than the operand type, and those |
814 | /// elements must be larger integer types such that the total size of the |
815 | /// operand type is less than or equal to the size of the result type. Each |
816 | /// of the low operand elements is sign-extended into the corresponding, |
817 | /// wider result elements. |
818 | /// NOTE: The type legalizer prefers to make the operand and result size |
819 | /// the same to allow expansion to shuffle vector during op legalization. |
820 | SIGN_EXTEND_VECTOR_INREG, |
821 | |
822 | /// ZERO_EXTEND_VECTOR_INREG(Vector) - This operator represents an |
823 | /// in-register zero-extension of the low lanes of an integer vector. The |
824 | /// result type must have fewer elements than the operand type, and those |
825 | /// elements must be larger integer types such that the total size of the |
826 | /// operand type is less than or equal to the size of the result type. Each |
827 | /// of the low operand elements is zero-extended into the corresponding, |
828 | /// wider result elements. |
829 | /// NOTE: The type legalizer prefers to make the operand and result size |
830 | /// the same to allow expansion to shuffle vector during op legalization. |
831 | ZERO_EXTEND_VECTOR_INREG, |
832 | |
833 | /// FP_TO_[US]INT - Convert a floating point value to a signed or unsigned |
834 | /// integer. These have the same semantics as fptosi and fptoui in IR. If |
835 | /// the FP value cannot fit in the integer type, the results are undefined. |
836 | FP_TO_SINT, |
837 | FP_TO_UINT, |
838 | |
839 | /// FP_TO_[US]INT_SAT - Convert floating point value in operand 0 to a |
840 | /// signed or unsigned scalar integer type given in operand 1 with the |
841 | /// following semantics: |
842 | /// |
843 | /// * If the value is NaN, zero is returned. |
844 | /// * If the value is larger/smaller than the largest/smallest integer, |
845 | /// the largest/smallest integer is returned (saturation). |
846 | /// * Otherwise the result of rounding the value towards zero is returned. |
847 | /// |
848 | /// The scalar width of the type given in operand 1 must be equal to, or |
849 | /// smaller than, the scalar result type width. It may end up being smaller |
850 | /// than the result width as a result of integer type legalization. |
851 | /// |
852 | /// After converting to the scalar integer type in operand 1, the value is |
853 | /// extended to the result VT. FP_TO_SINT_SAT sign extends and FP_TO_UINT_SAT |
854 | /// zero extends. |
855 | FP_TO_SINT_SAT, |
856 | FP_TO_UINT_SAT, |
857 | |
858 | /// X = FP_ROUND(Y, TRUNC) - Rounding 'Y' from a larger floating point type |
859 | /// down to the precision of the destination VT. TRUNC is a flag, which is |
860 | /// always an integer that is zero or one. If TRUNC is 0, this is a |
861 | /// normal rounding, if it is 1, this FP_ROUND is known to not change the |
862 | /// value of Y. |
863 | /// |
864 | /// The TRUNC = 1 case is used in cases where we know that the value will |
865 | /// not be modified by the node, because Y is not using any of the extra |
866 | /// precision of source type. This allows certain transformations like |
867 | /// FP_EXTEND(FP_ROUND(X,1)) -> X which are not safe for |
868 | /// FP_EXTEND(FP_ROUND(X,0)) because the extra bits aren't removed. |
869 | FP_ROUND, |
870 | |
871 | /// Returns current rounding mode: |
872 | /// -1 Undefined |
873 | /// 0 Round to 0 |
874 | /// 1 Round to nearest, ties to even |
875 | /// 2 Round to +inf |
876 | /// 3 Round to -inf |
877 | /// 4 Round to nearest, ties to zero |
878 | /// Other values are target dependent. |
879 | /// Result is rounding mode and chain. Input is a chain. |
880 | GET_ROUNDING, |
881 | |
882 | /// Set rounding mode. |
883 | /// The first operand is a chain pointer. The second specifies the required |
884 | /// rounding mode, encoded in the same way as used in '``GET_ROUNDING``'. |
885 | SET_ROUNDING, |
886 | |
887 | /// X = FP_EXTEND(Y) - Extend a smaller FP type into a larger FP type. |
888 | FP_EXTEND, |
889 | |
890 | /// BITCAST - This operator converts between integer, vector and FP |
891 | /// values, as if the value was stored to memory with one type and loaded |
892 | /// from the same address with the other type (or equivalently for vector |
893 | /// format conversions, etc). The source and result are required to have |
894 | /// the same bit size (e.g. f32 <-> i32). This can also be used for |
895 | /// int-to-int or fp-to-fp conversions, but that is a noop, deleted by |
896 | /// getNode(). |
897 | /// |
898 | /// This operator is subtly different from the bitcast instruction from |
899 | /// LLVM-IR since this node may change the bits in the register. For |
900 | /// example, this occurs on big-endian NEON and big-endian MSA where the |
901 | /// layout of the bits in the register depends on the vector type and this |
902 | /// operator acts as a shuffle operation for some vector type combinations. |
903 | BITCAST, |
904 | |
905 | /// ADDRSPACECAST - This operator converts between pointers of different |
906 | /// address spaces. |
907 | ADDRSPACECAST, |
908 | |
909 | /// FP16_TO_FP, FP_TO_FP16 - These operators are used to perform promotions |
910 | /// and truncation for half-precision (16 bit) floating numbers. These nodes |
911 | /// form a semi-softened interface for dealing with f16 (as an i16), which |
912 | /// is often a storage-only type but has native conversions. |
913 | FP16_TO_FP, |
914 | FP_TO_FP16, |
915 | STRICT_FP16_TO_FP, |
916 | STRICT_FP_TO_FP16, |
917 | |
918 | /// BF16_TO_FP, FP_TO_BF16 - These operators are used to perform promotions |
919 | /// and truncation for bfloat16. These nodes form a semi-softened interface |
920 | /// for dealing with bf16 (as an i16), which is often a storage-only type but |
921 | /// has native conversions. |
922 | BF16_TO_FP, |
923 | FP_TO_BF16, |
924 | |
925 | /// Perform various unary floating-point operations inspired by libm. For |
926 | /// FPOWI, the result is undefined if the integer operand doesn't fit into |
927 | /// sizeof(int). |
928 | FNEG, |
929 | FABS, |
930 | FSQRT, |
931 | FCBRT, |
932 | FSIN, |
933 | FCOS, |
934 | FPOW, |
935 | FPOWI, |
936 | /// FLDEXP - ldexp, inspired by libm (op0 * 2**op1). |
937 | FLDEXP, |
938 | |
939 | /// FFREXP - frexp, extract fractional and exponent component of a |
940 | /// floating-point value. Returns the two components as separate return |
941 | /// values. |
942 | FFREXP, |
943 | |
944 | FLOG, |
945 | FLOG2, |
946 | FLOG10, |
947 | FEXP, |
948 | FEXP2, |
949 | FEXP10, |
950 | FCEIL, |
951 | FTRUNC, |
952 | FRINT, |
953 | FNEARBYINT, |
954 | FROUND, |
955 | FROUNDEVEN, |
956 | FFLOOR, |
957 | LROUND, |
958 | LLROUND, |
959 | LRINT, |
960 | LLRINT, |
961 | |
962 | /// FMINNUM/FMAXNUM - Perform floating-point minimum or maximum on two |
963 | /// values. |
964 | // |
965 | /// In the case where a single input is a NaN (either signaling or quiet), |
966 | /// the non-NaN input is returned. |
967 | /// |
968 | /// The return value of (FMINNUM 0.0, -0.0) could be either 0.0 or -0.0. |
969 | FMINNUM, |
970 | FMAXNUM, |
971 | |
972 | /// FMINNUM_IEEE/FMAXNUM_IEEE - Perform floating-point minimum or maximum on |
973 | /// two values, following the IEEE-754 2008 definition. This differs from |
974 | /// FMINNUM/FMAXNUM in the handling of signaling NaNs. If one input is a |
975 | /// signaling NaN, returns a quiet NaN. |
976 | FMINNUM_IEEE, |
977 | FMAXNUM_IEEE, |
978 | |
979 | /// FMINIMUM/FMAXIMUM - NaN-propagating minimum/maximum that also treat -0.0 |
980 | /// as less than 0.0. While FMINNUM_IEEE/FMAXNUM_IEEE follow IEEE 754-2008 |
981 | /// semantics, FMINIMUM/FMAXIMUM follow IEEE 754-2018 draft semantics. |
982 | FMINIMUM, |
983 | FMAXIMUM, |
984 | |
985 | /// FSINCOS - Compute both fsin and fcos as a single operation. |
986 | FSINCOS, |
987 | |
988 | /// Gets the current floating-point environment. The first operand is a token |
989 | /// chain. The results are FP environment, represented by an integer value, |
990 | /// and a token chain. |
991 | GET_FPENV, |
992 | |
993 | /// Sets the current floating-point environment. The first operand is a token |
994 | /// chain, the second is FP environment, represented by an integer value. The |
995 | /// result is a token chain. |
996 | SET_FPENV, |
997 | |
998 | /// Set floating-point environment to default state. The first operand and the |
999 | /// result are token chains. |
1000 | RESET_FPENV, |
1001 | |
1002 | /// Gets the current floating-point environment. The first operand is a token |
1003 | /// chain, the second is a pointer to memory, where FP environment is stored |
1004 | /// to. The result is a token chain. |
1005 | GET_FPENV_MEM, |
1006 | |
1007 | /// Sets the current floating point environment. The first operand is a token |
1008 | /// chain, the second is a pointer to memory, where FP environment is loaded |
1009 | /// from. The result is a token chain. |
1010 | SET_FPENV_MEM, |
1011 | |
1012 | /// Reads the current dynamic floating-point control modes. The operand is |
1013 | /// a token chain. |
1014 | GET_FPMODE, |
1015 | |
1016 | /// Sets the current dynamic floating-point control modes. The first operand |
1017 | /// is a token chain, the second is control modes set represented as integer |
1018 | /// value. |
1019 | SET_FPMODE, |
1020 | |
1021 | /// Sets default dynamic floating-point control modes. The operand is a |
1022 | /// token chain. |
1023 | RESET_FPMODE, |
1024 | |
1025 | /// LOAD and STORE have token chains as their first operand, then the same |
1026 | /// operands as an LLVM load/store instruction, then an offset node that |
1027 | /// is added / subtracted from the base pointer to form the address (for |
1028 | /// indexed memory ops). |
1029 | LOAD, |
1030 | STORE, |
1031 | |
1032 | /// DYNAMIC_STACKALLOC - Allocate some number of bytes on the stack aligned |
1033 | /// to a specified boundary. This node always has two return values: a new |
1034 | /// stack pointer value and a chain. The first operand is the token chain, |
1035 | /// the second is the number of bytes to allocate, and the third is the |
1036 | /// alignment boundary. The size is guaranteed to be a multiple of the |
1037 | /// stack alignment, and the alignment is guaranteed to be bigger than the |
1038 | /// stack alignment (if required) or 0 to get standard stack alignment. |
1039 | DYNAMIC_STACKALLOC, |
1040 | |
1041 | /// Control flow instructions. These all have token chains. |
1042 | |
1043 | /// BR - Unconditional branch. The first operand is the chain |
1044 | /// operand, the second is the MBB to branch to. |
1045 | BR, |
1046 | |
1047 | /// BRIND - Indirect branch. The first operand is the chain, the second |
1048 | /// is the value to branch to, which must be of the same type as the |
1049 | /// target's pointer type. |
1050 | BRIND, |
1051 | |
1052 | /// BR_JT - Jumptable branch. The first operand is the chain, the second |
1053 | /// is the jumptable index, the last one is the jumptable entry index. |
1054 | BR_JT, |
1055 | |
1056 | /// JUMP_TABLE_DEBUG_INFO - Jumptable debug info. The first operand is the |
1057 | /// chain, the second is the jumptable index. |
1058 | JUMP_TABLE_DEBUG_INFO, |
1059 | |
1060 | /// BRCOND - Conditional branch. The first operand is the chain, the |
1061 | /// second is the condition, the third is the block to branch to if the |
1062 | /// condition is true. If the type of the condition is not i1, then the |
1063 | /// high bits must conform to getBooleanContents. If the condition is undef, |
1064 | /// it nondeterministically jumps to the block. |
1065 | /// TODO: Its semantics w.r.t undef requires further discussion; we need to |
1066 | /// make it sure that it is consistent with optimizations in MIR & the |
1067 | /// meaning of IMPLICIT_DEF. See https://reviews.llvm.org/D92015 |
1068 | BRCOND, |
1069 | |
1070 | /// BR_CC - Conditional branch. The behavior is like that of SELECT_CC, in |
1071 | /// that the condition is represented as condition code, and two nodes to |
1072 | /// compare, rather than as a combined SetCC node. The operands in order |
1073 | /// are chain, cc, lhs, rhs, block to branch to if condition is true. If |
1074 | /// condition is undef, it nondeterministically jumps to the block. |
1075 | BR_CC, |
1076 | |
1077 | /// INLINEASM - Represents an inline asm block. This node always has two |
1078 | /// return values: a chain and a flag result. The inputs are as follows: |
1079 | /// Operand #0 : Input chain. |
1080 | /// Operand #1 : a ExternalSymbolSDNode with a pointer to the asm string. |
1081 | /// Operand #2 : a MDNodeSDNode with the !srcloc metadata. |
1082 | /// Operand #3 : HasSideEffect, IsAlignStack bits. |
1083 | /// After this, it is followed by a list of operands with this format: |
1084 | /// ConstantSDNode: Flags that encode whether it is a mem or not, the |
1085 | /// of operands that follow, etc. See InlineAsm.h. |
1086 | /// ... however many operands ... |
1087 | /// Operand #last: Optional, an incoming flag. |
1088 | /// |
1089 | /// The variable width operands are required to represent target addressing |
1090 | /// modes as a single "operand", even though they may have multiple |
1091 | /// SDOperands. |
1092 | INLINEASM, |
1093 | |
1094 | /// INLINEASM_BR - Branching version of inline asm. Used by asm-goto. |
1095 | INLINEASM_BR, |
1096 | |
1097 | /// EH_LABEL - Represents a label in mid basic block used to track |
1098 | /// locations needed for debug and exception handling tables. These nodes |
1099 | /// take a chain as input and return a chain. |
1100 | EH_LABEL, |
1101 | |
1102 | /// ANNOTATION_LABEL - Represents a mid basic block label used by |
1103 | /// annotations. This should remain within the basic block and be ordered |
1104 | /// with respect to other call instructions, but loads and stores may float |
1105 | /// past it. |
1106 | ANNOTATION_LABEL, |
1107 | |
1108 | /// CATCHRET - Represents a return from a catch block funclet. Used for |
1109 | /// MSVC compatible exception handling. Takes a chain operand and a |
1110 | /// destination basic block operand. |
1111 | CATCHRET, |
1112 | |
1113 | /// CLEANUPRET - Represents a return from a cleanup block funclet. Used for |
1114 | /// MSVC compatible exception handling. Takes only a chain operand. |
1115 | CLEANUPRET, |
1116 | |
1117 | /// STACKSAVE - STACKSAVE has one operand, an input chain. It produces a |
1118 | /// value, the same type as the pointer type for the system, and an output |
1119 | /// chain. |
1120 | STACKSAVE, |
1121 | |
1122 | /// STACKRESTORE has two operands, an input chain and a pointer to restore |
1123 | /// to it returns an output chain. |
1124 | STACKRESTORE, |
1125 | |
1126 | /// CALLSEQ_START/CALLSEQ_END - These operators mark the beginning and end |
1127 | /// of a call sequence, and carry arbitrary information that target might |
1128 | /// want to know. The first operand is a chain, the rest are specified by |
1129 | /// the target and not touched by the DAG optimizers. |
1130 | /// Targets that may use stack to pass call arguments define additional |
1131 | /// operands: |
1132 | /// - size of the call frame part that must be set up within the |
1133 | /// CALLSEQ_START..CALLSEQ_END pair, |
1134 | /// - part of the call frame prepared prior to CALLSEQ_START. |
1135 | /// Both these parameters must be constants, their sum is the total call |
1136 | /// frame size. |
1137 | /// CALLSEQ_START..CALLSEQ_END pairs may not be nested. |
1138 | CALLSEQ_START, // Beginning of a call sequence |
1139 | CALLSEQ_END, // End of a call sequence |
1140 | |
1141 | /// VAARG - VAARG has four operands: an input chain, a pointer, a SRCVALUE, |
1142 | /// and the alignment. It returns a pair of values: the vaarg value and a |
1143 | /// new chain. |
1144 | VAARG, |
1145 | |
1146 | /// VACOPY - VACOPY has 5 operands: an input chain, a destination pointer, |
1147 | /// a source pointer, a SRCVALUE for the destination, and a SRCVALUE for the |
1148 | /// source. |
1149 | VACOPY, |
1150 | |
1151 | /// VAEND, VASTART - VAEND and VASTART have three operands: an input chain, |
1152 | /// pointer, and a SRCVALUE. |
1153 | VAEND, |
1154 | VASTART, |
1155 | |
1156 | // PREALLOCATED_SETUP - This has 2 operands: an input chain and a SRCVALUE |
1157 | // with the preallocated call Value. |
1158 | PREALLOCATED_SETUP, |
1159 | // PREALLOCATED_ARG - This has 3 operands: an input chain, a SRCVALUE |
1160 | // with the preallocated call Value, and a constant int. |
1161 | PREALLOCATED_ARG, |
1162 | |
1163 | /// SRCVALUE - This is a node type that holds a Value* that is used to |
1164 | /// make reference to a value in the LLVM IR. |
1165 | SRCVALUE, |
1166 | |
1167 | /// MDNODE_SDNODE - This is a node that holdes an MDNode*, which is used to |
1168 | /// reference metadata in the IR. |
1169 | MDNODE_SDNODE, |
1170 | |
1171 | /// PCMARKER - This corresponds to the pcmarker intrinsic. |
1172 | PCMARKER, |
1173 | |
1174 | /// READCYCLECOUNTER - This corresponds to the readcyclecounter intrinsic. |
1175 | /// It produces a chain and one i64 value. The only operand is a chain. |
1176 | /// If i64 is not legal, the result will be expanded into smaller values. |
1177 | /// Still, it returns an i64, so targets should set legality for i64. |
1178 | /// The result is the content of the architecture-specific cycle |
1179 | /// counter-like register (or other high accuracy low latency clock source). |
1180 | READCYCLECOUNTER, |
1181 | |
1182 | /// READSTEADYCOUNTER - This corresponds to the readfixedcounter intrinsic. |
1183 | /// It has the same semantics as the READCYCLECOUNTER implementation except |
1184 | /// that the result is the content of the architecture-specific fixed |
1185 | /// frequency counter suitable for measuring elapsed time. |
1186 | READSTEADYCOUNTER, |
1187 | |
1188 | /// HANDLENODE node - Used as a handle for various purposes. |
1189 | HANDLENODE, |
1190 | |
1191 | /// INIT_TRAMPOLINE - This corresponds to the init_trampoline intrinsic. It |
1192 | /// takes as input a token chain, the pointer to the trampoline, the pointer |
1193 | /// to the nested function, the pointer to pass for the 'nest' parameter, a |
1194 | /// SRCVALUE for the trampoline and another for the nested function |
1195 | /// (allowing targets to access the original Function*). |
1196 | /// It produces a token chain as output. |
1197 | INIT_TRAMPOLINE, |
1198 | |
1199 | /// ADJUST_TRAMPOLINE - This corresponds to the adjust_trampoline intrinsic. |
1200 | /// It takes a pointer to the trampoline and produces a (possibly) new |
1201 | /// pointer to the same trampoline with platform-specific adjustments |
1202 | /// applied. The pointer it returns points to an executable block of code. |
1203 | ADJUST_TRAMPOLINE, |
1204 | |
1205 | /// TRAP - Trapping instruction |
1206 | TRAP, |
1207 | |
1208 | /// DEBUGTRAP - Trap intended to get the attention of a debugger. |
1209 | DEBUGTRAP, |
1210 | |
1211 | /// UBSANTRAP - Trap with an immediate describing the kind of sanitizer |
1212 | /// failure. |
1213 | UBSANTRAP, |
1214 | |
1215 | /// PREFETCH - This corresponds to a prefetch intrinsic. The first operand |
1216 | /// is the chain. The other operands are the address to prefetch, |
1217 | /// read / write specifier, locality specifier and instruction / data cache |
1218 | /// specifier. |
1219 | PREFETCH, |
1220 | |
1221 | /// ARITH_FENCE - This corresponds to a arithmetic fence intrinsic. Both its |
1222 | /// operand and output are the same floating type. |
1223 | ARITH_FENCE, |
1224 | |
1225 | /// MEMBARRIER - Compiler barrier only; generate a no-op. |
1226 | MEMBARRIER, |
1227 | |
1228 | /// OUTCHAIN = ATOMIC_FENCE(INCHAIN, ordering, scope) |
1229 | /// This corresponds to the fence instruction. It takes an input chain, and |
1230 | /// two integer constants: an AtomicOrdering and a SynchronizationScope. |
1231 | ATOMIC_FENCE, |
1232 | |
1233 | /// Val, OUTCHAIN = ATOMIC_LOAD(INCHAIN, ptr) |
1234 | /// This corresponds to "load atomic" instruction. |
1235 | ATOMIC_LOAD, |
1236 | |
1237 | /// OUTCHAIN = ATOMIC_STORE(INCHAIN, ptr, val) |
1238 | /// This corresponds to "store atomic" instruction. |
1239 | ATOMIC_STORE, |
1240 | |
1241 | /// Val, OUTCHAIN = ATOMIC_CMP_SWAP(INCHAIN, ptr, cmp, swap) |
1242 | /// For double-word atomic operations: |
1243 | /// ValLo, ValHi, OUTCHAIN = ATOMIC_CMP_SWAP(INCHAIN, ptr, cmpLo, cmpHi, |
1244 | /// swapLo, swapHi) |
1245 | /// This corresponds to the cmpxchg instruction. |
1246 | ATOMIC_CMP_SWAP, |
1247 | |
1248 | /// Val, Success, OUTCHAIN |
1249 | /// = ATOMIC_CMP_SWAP_WITH_SUCCESS(INCHAIN, ptr, cmp, swap) |
1250 | /// N.b. this is still a strong cmpxchg operation, so |
1251 | /// Success == "Val == cmp". |
1252 | ATOMIC_CMP_SWAP_WITH_SUCCESS, |
1253 | |
1254 | /// Val, OUTCHAIN = ATOMIC_SWAP(INCHAIN, ptr, amt) |
1255 | /// Val, OUTCHAIN = ATOMIC_LOAD_[OpName](INCHAIN, ptr, amt) |
1256 | /// For double-word atomic operations: |
1257 | /// ValLo, ValHi, OUTCHAIN = ATOMIC_SWAP(INCHAIN, ptr, amtLo, amtHi) |
1258 | /// ValLo, ValHi, OUTCHAIN = ATOMIC_LOAD_[OpName](INCHAIN, ptr, amtLo, amtHi) |
1259 | /// These correspond to the atomicrmw instruction. |
1260 | ATOMIC_SWAP, |
1261 | ATOMIC_LOAD_ADD, |
1262 | ATOMIC_LOAD_SUB, |
1263 | ATOMIC_LOAD_AND, |
1264 | ATOMIC_LOAD_CLR, |
1265 | ATOMIC_LOAD_OR, |
1266 | ATOMIC_LOAD_XOR, |
1267 | ATOMIC_LOAD_NAND, |
1268 | ATOMIC_LOAD_MIN, |
1269 | ATOMIC_LOAD_MAX, |
1270 | ATOMIC_LOAD_UMIN, |
1271 | ATOMIC_LOAD_UMAX, |
1272 | ATOMIC_LOAD_FADD, |
1273 | ATOMIC_LOAD_FSUB, |
1274 | ATOMIC_LOAD_FMAX, |
1275 | ATOMIC_LOAD_FMIN, |
1276 | ATOMIC_LOAD_UINC_WRAP, |
1277 | ATOMIC_LOAD_UDEC_WRAP, |
1278 | |
1279 | // Masked load and store - consecutive vector load and store operations |
1280 | // with additional mask operand that prevents memory accesses to the |
1281 | // masked-off lanes. |
1282 | // |
1283 | // Val, OutChain = MLOAD(BasePtr, Mask, PassThru) |
1284 | // OutChain = MSTORE(Value, BasePtr, Mask) |
1285 | MLOAD, |
1286 | MSTORE, |
1287 | |
1288 | // Masked gather and scatter - load and store operations for a vector of |
1289 | // random addresses with additional mask operand that prevents memory |
1290 | // accesses to the masked-off lanes. |
1291 | // |
1292 | // Val, OutChain = GATHER(InChain, PassThru, Mask, BasePtr, Index, Scale) |
1293 | // OutChain = SCATTER(InChain, Value, Mask, BasePtr, Index, Scale) |
1294 | // |
1295 | // The Index operand can have more vector elements than the other operands |
1296 | // due to type legalization. The extra elements are ignored. |
1297 | MGATHER, |
1298 | MSCATTER, |
1299 | |
1300 | /// This corresponds to the llvm.lifetime.* intrinsics. The first operand |
1301 | /// is the chain and the second operand is the alloca pointer. |
1302 | LIFETIME_START, |
1303 | LIFETIME_END, |
1304 | |
1305 | /// GC_TRANSITION_START/GC_TRANSITION_END - These operators mark the |
1306 | /// beginning and end of GC transition sequence, and carry arbitrary |
1307 | /// information that target might need for lowering. The first operand is |
1308 | /// a chain, the rest are specified by the target and not touched by the DAG |
1309 | /// optimizers. GC_TRANSITION_START..GC_TRANSITION_END pairs may not be |
1310 | /// nested. |
1311 | GC_TRANSITION_START, |
1312 | GC_TRANSITION_END, |
1313 | |
1314 | /// GET_DYNAMIC_AREA_OFFSET - get offset from native SP to the address of |
1315 | /// the most recent dynamic alloca. For most targets that would be 0, but |
1316 | /// for some others (e.g. PowerPC, PowerPC64) that would be compile-time |
1317 | /// known nonzero constant. The only operand here is the chain. |
1318 | GET_DYNAMIC_AREA_OFFSET, |
1319 | |
1320 | /// Pseudo probe for AutoFDO, as a place holder in a basic block to improve |
1321 | /// the sample counts quality. |
1322 | PSEUDO_PROBE, |
1323 | |
1324 | /// VSCALE(IMM) - Returns the runtime scaling factor used to calculate the |
1325 | /// number of elements within a scalable vector. IMM is a constant integer |
1326 | /// multiplier that is applied to the runtime value. |
1327 | VSCALE, |
1328 | |
1329 | /// Generic reduction nodes. These nodes represent horizontal vector |
1330 | /// reduction operations, producing a scalar result. |
1331 | /// The SEQ variants perform reductions in sequential order. The first |
1332 | /// operand is an initial scalar accumulator value, and the second operand |
1333 | /// is the vector to reduce. |
1334 | /// E.g. RES = VECREDUCE_SEQ_FADD f32 ACC, <4 x f32> SRC_VEC |
1335 | /// ... is equivalent to |
1336 | /// RES = (((ACC + SRC_VEC[0]) + SRC_VEC[1]) + SRC_VEC[2]) + SRC_VEC[3] |
1337 | VECREDUCE_SEQ_FADD, |
1338 | VECREDUCE_SEQ_FMUL, |
1339 | |
1340 | /// These reductions have relaxed evaluation order semantics, and have a |
1341 | /// single vector operand. The order of evaluation is unspecified. For |
1342 | /// pow-of-2 vectors, one valid legalizer expansion is to use a tree |
1343 | /// reduction, i.e.: |
1344 | /// For RES = VECREDUCE_FADD <8 x f16> SRC_VEC |
1345 | /// PART_RDX = FADD SRC_VEC[0:3], SRC_VEC[4:7] |
1346 | /// PART_RDX2 = FADD PART_RDX[0:1], PART_RDX[2:3] |
1347 | /// RES = FADD PART_RDX2[0], PART_RDX2[1] |
1348 | /// For non-pow-2 vectors, this can be computed by extracting each element |
1349 | /// and performing the operation as if it were scalarized. |
1350 | VECREDUCE_FADD, |
1351 | VECREDUCE_FMUL, |
1352 | /// FMIN/FMAX nodes can have flags, for NaN/NoNaN variants. |
1353 | VECREDUCE_FMAX, |
1354 | VECREDUCE_FMIN, |
1355 | /// FMINIMUM/FMAXIMUM nodes propatate NaNs and signed zeroes using the |
1356 | /// llvm.minimum and llvm.maximum semantics. |
1357 | VECREDUCE_FMAXIMUM, |
1358 | VECREDUCE_FMINIMUM, |
1359 | /// Integer reductions may have a result type larger than the vector element |
1360 | /// type. However, the reduction is performed using the vector element type |
1361 | /// and the value in the top bits is unspecified. |
1362 | VECREDUCE_ADD, |
1363 | VECREDUCE_MUL, |
1364 | VECREDUCE_AND, |
1365 | VECREDUCE_OR, |
1366 | VECREDUCE_XOR, |
1367 | VECREDUCE_SMAX, |
1368 | VECREDUCE_SMIN, |
1369 | VECREDUCE_UMAX, |
1370 | VECREDUCE_UMIN, |
1371 | |
1372 | // The `llvm.experimental.stackmap` intrinsic. |
1373 | // Operands: input chain, glue, <id>, <numShadowBytes>, [live0[, live1...]] |
1374 | // Outputs: output chain, glue |
1375 | STACKMAP, |
1376 | |
1377 | // The `llvm.experimental.patchpoint.*` intrinsic. |
1378 | // Operands: input chain, [glue], reg-mask, <id>, <numShadowBytes>, callee, |
1379 | // <numArgs>, cc, ... |
1380 | // Outputs: [rv], output chain, glue |
1381 | PATCHPOINT, |
1382 | |
1383 | // Vector Predication |
1384 | #define BEGIN_REGISTER_VP_SDNODE(VPSDID, ...) VPSDID, |
1385 | #include "llvm/IR/VPIntrinsics.def" |
1386 | |
1387 | /// BUILTIN_OP_END - This must be the last enum value in this list. |
1388 | /// The target-specific pre-isel opcode values start here. |
1389 | BUILTIN_OP_END |
1390 | }; |
1391 | |
1392 | /// FIRST_TARGET_STRICTFP_OPCODE - Target-specific pre-isel operations |
1393 | /// which cannot raise FP exceptions should be less than this value. |
1394 | /// Those that do must not be less than this value. |
1395 | static const int FIRST_TARGET_STRICTFP_OPCODE = BUILTIN_OP_END + 400; |
1396 | |
1397 | /// FIRST_TARGET_MEMORY_OPCODE - Target-specific pre-isel operations |
1398 | /// which do not reference a specific memory location should be less than |
1399 | /// this value. Those that do must not be less than this value, and can |
1400 | /// be used with SelectionDAG::getMemIntrinsicNode. |
1401 | static const int FIRST_TARGET_MEMORY_OPCODE = BUILTIN_OP_END + 500; |
1402 | |
1403 | /// Whether this is bitwise logic opcode. |
1404 | inline bool isBitwiseLogicOp(unsigned Opcode) { |
1405 | return Opcode == ISD::AND || Opcode == ISD::OR || Opcode == ISD::XOR; |
1406 | } |
1407 | |
1408 | /// Get underlying scalar opcode for VECREDUCE opcode. |
1409 | /// For example ISD::AND for ISD::VECREDUCE_AND. |
1410 | NodeType getVecReduceBaseOpcode(unsigned VecReduceOpcode); |
1411 | |
1412 | /// Whether this is a vector-predicated Opcode. |
1413 | bool isVPOpcode(unsigned Opcode); |
1414 | |
1415 | /// Whether this is a vector-predicated binary operation opcode. |
1416 | bool isVPBinaryOp(unsigned Opcode); |
1417 | |
1418 | /// Whether this is a vector-predicated reduction opcode. |
1419 | bool isVPReduction(unsigned Opcode); |
1420 | |
1421 | /// The operand position of the vector mask. |
1422 | std::optional<unsigned> getVPMaskIdx(unsigned Opcode); |
1423 | |
1424 | /// The operand position of the explicit vector length parameter. |
1425 | std::optional<unsigned> getVPExplicitVectorLengthIdx(unsigned Opcode); |
1426 | |
1427 | /// Translate this VP Opcode to its corresponding non-VP Opcode. |
1428 | std::optional<unsigned> getBaseOpcodeForVP(unsigned Opcode, bool hasFPExcept); |
1429 | |
1430 | /// Translate this non-VP Opcode to its corresponding VP Opcode. |
1431 | unsigned getVPForBaseOpcode(unsigned Opcode); |
1432 | |
1433 | //===--------------------------------------------------------------------===// |
1434 | /// MemIndexedMode enum - This enum defines the load / store indexed |
1435 | /// addressing modes. |
1436 | /// |
1437 | /// UNINDEXED "Normal" load / store. The effective address is already |
1438 | /// computed and is available in the base pointer. The offset |
1439 | /// operand is always undefined. In addition to producing a |
1440 | /// chain, an unindexed load produces one value (result of the |
1441 | /// load); an unindexed store does not produce a value. |
1442 | /// |
1443 | /// PRE_INC Similar to the unindexed mode where the effective address is |
1444 | /// PRE_DEC the value of the base pointer add / subtract the offset. |
1445 | /// It considers the computation as being folded into the load / |
1446 | /// store operation (i.e. the load / store does the address |
1447 | /// computation as well as performing the memory transaction). |
1448 | /// The base operand is always undefined. In addition to |
1449 | /// producing a chain, pre-indexed load produces two values |
1450 | /// (result of the load and the result of the address |
1451 | /// computation); a pre-indexed store produces one value (result |
1452 | /// of the address computation). |
1453 | /// |
1454 | /// POST_INC The effective address is the value of the base pointer. The |
1455 | /// POST_DEC value of the offset operand is then added to / subtracted |
1456 | /// from the base after memory transaction. In addition to |
1457 | /// producing a chain, post-indexed load produces two values |
1458 | /// (the result of the load and the result of the base +/- offset |
1459 | /// computation); a post-indexed store produces one value (the |
1460 | /// the result of the base +/- offset computation). |
1461 | enum MemIndexedMode { UNINDEXED = 0, PRE_INC, PRE_DEC, POST_INC, POST_DEC }; |
1462 | |
1463 | static const int LAST_INDEXED_MODE = POST_DEC + 1; |
1464 | |
1465 | //===--------------------------------------------------------------------===// |
1466 | /// MemIndexType enum - This enum defines how to interpret MGATHER/SCATTER's |
1467 | /// index parameter when calculating addresses. |
1468 | /// |
1469 | /// SIGNED_SCALED Addr = Base + ((signed)Index * Scale) |
1470 | /// UNSIGNED_SCALED Addr = Base + ((unsigned)Index * Scale) |
1471 | /// |
1472 | /// NOTE: The value of Scale is typically only known to the node owning the |
1473 | /// IndexType, with a value of 1 the equivalent of being unscaled. |
1474 | enum MemIndexType { SIGNED_SCALED = 0, UNSIGNED_SCALED }; |
1475 | |
1476 | static const int LAST_MEM_INDEX_TYPE = UNSIGNED_SCALED + 1; |
1477 | |
1478 | inline bool isIndexTypeSigned(MemIndexType IndexType) { |
1479 | return IndexType == SIGNED_SCALED; |
1480 | } |
1481 | |
1482 | //===--------------------------------------------------------------------===// |
1483 | /// LoadExtType enum - This enum defines the three variants of LOADEXT |
1484 | /// (load with extension). |
1485 | /// |
1486 | /// SEXTLOAD loads the integer operand and sign extends it to a larger |
1487 | /// integer result type. |
1488 | /// ZEXTLOAD loads the integer operand and zero extends it to a larger |
1489 | /// integer result type. |
1490 | /// EXTLOAD is used for two things: floating point extending loads and |
1491 | /// integer extending loads [the top bits are undefined]. |
1492 | enum LoadExtType { NON_EXTLOAD = 0, EXTLOAD, SEXTLOAD, ZEXTLOAD }; |
1493 | |
1494 | static const int LAST_LOADEXT_TYPE = ZEXTLOAD + 1; |
1495 | |
1496 | NodeType getExtForLoadExtType(bool IsFP, LoadExtType); |
1497 | |
1498 | //===--------------------------------------------------------------------===// |
1499 | /// ISD::CondCode enum - These are ordered carefully to make the bitfields |
1500 | /// below work out, when considering SETFALSE (something that never exists |
1501 | /// dynamically) as 0. "U" -> Unsigned (for integer operands) or Unordered |
1502 | /// (for floating point), "L" -> Less than, "G" -> Greater than, "E" -> Equal |
1503 | /// to. If the "N" column is 1, the result of the comparison is undefined if |
1504 | /// the input is a NAN. |
1505 | /// |
1506 | /// All of these (except for the 'always folded ops') should be handled for |
1507 | /// floating point. For integer, only the SETEQ,SETNE,SETLT,SETLE,SETGT, |
1508 | /// SETGE,SETULT,SETULE,SETUGT, and SETUGE opcodes are used. |
1509 | /// |
1510 | /// Note that these are laid out in a specific order to allow bit-twiddling |
1511 | /// to transform conditions. |
1512 | enum CondCode { |
1513 | // Opcode N U L G E Intuitive operation |
1514 | SETFALSE, // 0 0 0 0 Always false (always folded) |
1515 | SETOEQ, // 0 0 0 1 True if ordered and equal |
1516 | SETOGT, // 0 0 1 0 True if ordered and greater than |
1517 | SETOGE, // 0 0 1 1 True if ordered and greater than or equal |
1518 | SETOLT, // 0 1 0 0 True if ordered and less than |
1519 | SETOLE, // 0 1 0 1 True if ordered and less than or equal |
1520 | SETONE, // 0 1 1 0 True if ordered and operands are unequal |
1521 | SETO, // 0 1 1 1 True if ordered (no nans) |
1522 | SETUO, // 1 0 0 0 True if unordered: isnan(X) | isnan(Y) |
1523 | SETUEQ, // 1 0 0 1 True if unordered or equal |
1524 | SETUGT, // 1 0 1 0 True if unordered or greater than |
1525 | SETUGE, // 1 0 1 1 True if unordered, greater than, or equal |
1526 | SETULT, // 1 1 0 0 True if unordered or less than |
1527 | SETULE, // 1 1 0 1 True if unordered, less than, or equal |
1528 | SETUNE, // 1 1 1 0 True if unordered or not equal |
1529 | SETTRUE, // 1 1 1 1 Always true (always folded) |
1530 | // Don't care operations: undefined if the input is a nan. |
1531 | SETFALSE2, // 1 X 0 0 0 Always false (always folded) |
1532 | SETEQ, // 1 X 0 0 1 True if equal |
1533 | SETGT, // 1 X 0 1 0 True if greater than |
1534 | SETGE, // 1 X 0 1 1 True if greater than or equal |
1535 | SETLT, // 1 X 1 0 0 True if less than |
1536 | SETLE, // 1 X 1 0 1 True if less than or equal |
1537 | SETNE, // 1 X 1 1 0 True if not equal |
1538 | SETTRUE2, // 1 X 1 1 1 Always true (always folded) |
1539 | |
1540 | SETCC_INVALID // Marker value. |
1541 | }; |
1542 | |
1543 | /// Return true if this is a setcc instruction that performs a signed |
1544 | /// comparison when used with integer operands. |
1545 | inline bool isSignedIntSetCC(CondCode Code) { |
1546 | return Code == SETGT || Code == SETGE || Code == SETLT || Code == SETLE; |
1547 | } |
1548 | |
1549 | /// Return true if this is a setcc instruction that performs an unsigned |
1550 | /// comparison when used with integer operands. |
1551 | inline bool isUnsignedIntSetCC(CondCode Code) { |
1552 | return Code == SETUGT || Code == SETUGE || Code == SETULT || Code == SETULE; |
1553 | } |
1554 | |
1555 | /// Return true if this is a setcc instruction that performs an equality |
1556 | /// comparison when used with integer operands. |
1557 | inline bool isIntEqualitySetCC(CondCode Code) { |
1558 | return Code == SETEQ || Code == SETNE; |
1559 | } |
1560 | |
1561 | /// Return true if this is a setcc instruction that performs an equality |
1562 | /// comparison when used with floating point operands. |
1563 | inline bool isFPEqualitySetCC(CondCode Code) { |
1564 | return Code == SETOEQ || Code == SETONE || Code == SETUEQ || Code == SETUNE; |
1565 | } |
1566 | |
1567 | /// Return true if the specified condition returns true if the two operands to |
1568 | /// the condition are equal. Note that if one of the two operands is a NaN, |
1569 | /// this value is meaningless. |
1570 | inline bool isTrueWhenEqual(CondCode Cond) { return ((int)Cond & 1) != 0; } |
1571 | |
1572 | /// This function returns 0 if the condition is always false if an operand is |
1573 | /// a NaN, 1 if the condition is always true if the operand is a NaN, and 2 if |
1574 | /// the condition is undefined if the operand is a NaN. |
1575 | inline unsigned getUnorderedFlavor(CondCode Cond) { |
1576 | return ((int)Cond >> 3) & 3; |
1577 | } |
1578 | |
1579 | /// Return the operation corresponding to !(X op Y), where 'op' is a valid |
1580 | /// SetCC operation. |
1581 | CondCode getSetCCInverse(CondCode Operation, EVT Type); |
1582 | |
1583 | inline bool isExtOpcode(unsigned Opcode) { |
1584 | return Opcode == ISD::ANY_EXTEND || Opcode == ISD::ZERO_EXTEND || |
1585 | Opcode == ISD::SIGN_EXTEND; |
1586 | } |
1587 | |
1588 | inline bool isExtVecInRegOpcode(unsigned Opcode) { |
1589 | return Opcode == ISD::ANY_EXTEND_VECTOR_INREG || |
1590 | Opcode == ISD::ZERO_EXTEND_VECTOR_INREG || |
1591 | Opcode == ISD::SIGN_EXTEND_VECTOR_INREG; |
1592 | } |
1593 | |
1594 | namespace GlobalISel { |
1595 | /// Return the operation corresponding to !(X op Y), where 'op' is a valid |
1596 | /// SetCC operation. The U bit of the condition code has different meanings |
1597 | /// between floating point and integer comparisons and LLT's don't provide |
1598 | /// this distinction. As such we need to be told whether the comparison is |
1599 | /// floating point or integer-like. Pointers should use integer-like |
1600 | /// comparisons. |
1601 | CondCode getSetCCInverse(CondCode Operation, bool isIntegerLike); |
1602 | } // end namespace GlobalISel |
1603 | |
1604 | /// Return the operation corresponding to (Y op X) when given the operation |
1605 | /// for (X op Y). |
1606 | CondCode getSetCCSwappedOperands(CondCode Operation); |
1607 | |
1608 | /// Return the result of a logical OR between different comparisons of |
1609 | /// identical values: ((X op1 Y) | (X op2 Y)). This function returns |
1610 | /// SETCC_INVALID if it is not possible to represent the resultant comparison. |
1611 | CondCode getSetCCOrOperation(CondCode Op1, CondCode Op2, EVT Type); |
1612 | |
1613 | /// Return the result of a logical AND between different comparisons of |
1614 | /// identical values: ((X op1 Y) & (X op2 Y)). This function returns |
1615 | /// SETCC_INVALID if it is not possible to represent the resultant comparison. |
1616 | CondCode getSetCCAndOperation(CondCode Op1, CondCode Op2, EVT Type); |
1617 | |
1618 | } // namespace ISD |
1619 | |
1620 | } // namespace llvm |
1621 | |
1622 | #endif |
1623 | |