| 1 | //===-- ARM.h - Top-level interface for ARM representation ------*- C++ -*-===// |
|---|---|
| 2 | // |
| 3 | // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. |
| 4 | // See https://llvm.org/LICENSE.txt for license information. |
| 5 | // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception |
| 6 | // |
| 7 | //===----------------------------------------------------------------------===// |
| 8 | // |
| 9 | // This file contains the entry points for global functions defined in the LLVM |
| 10 | // ARM back-end. |
| 11 | // |
| 12 | //===----------------------------------------------------------------------===// |
| 13 | |
| 14 | #ifndef LLVM_LIB_TARGET_ARM_ARM_H |
| 15 | #define LLVM_LIB_TARGET_ARM_ARM_H |
| 16 | |
| 17 | #include "llvm/IR/LegacyPassManager.h" |
| 18 | #include "llvm/Support/CodeGen.h" |
| 19 | #include <functional> |
| 20 | |
| 21 | namespace llvm { |
| 22 | |
| 23 | class ARMAsmPrinter; |
| 24 | class ARMBaseTargetMachine; |
| 25 | class ARMRegisterBankInfo; |
| 26 | class ARMSubtarget; |
| 27 | class Function; |
| 28 | class FunctionPass; |
| 29 | class InstructionSelector; |
| 30 | class MCInst; |
| 31 | class MachineInstr; |
| 32 | class PassRegistry; |
| 33 | |
| 34 | Pass *createMVETailPredicationPass(); |
| 35 | FunctionPass *createARMLowOverheadLoopsPass(); |
| 36 | FunctionPass *createARMBlockPlacementPass(); |
| 37 | Pass *createARMParallelDSPPass(); |
| 38 | FunctionPass *createARMISelDag(ARMBaseTargetMachine &TM, |
| 39 | CodeGenOptLevel OptLevel); |
| 40 | FunctionPass *createA15SDOptimizerPass(); |
| 41 | FunctionPass *createARMLoadStoreOptimizationPass(bool PreAlloc = false); |
| 42 | FunctionPass *createARMExpandPseudoPass(); |
| 43 | FunctionPass *createARMBranchTargetsPass(); |
| 44 | FunctionPass *createARMConstantIslandPass(); |
| 45 | FunctionPass *createMLxExpansionPass(); |
| 46 | FunctionPass *createThumb2ITBlockPass(); |
| 47 | FunctionPass *createMVEVPTBlockPass(); |
| 48 | FunctionPass *createMVETPAndVPTOptimisationsPass(); |
| 49 | FunctionPass *createARMOptimizeBarriersPass(); |
| 50 | FunctionPass *createThumb2SizeReductionPass( |
| 51 | std::function<bool(const Function &)> Ftor = nullptr); |
| 52 | InstructionSelector * |
| 53 | createARMInstructionSelector(const ARMBaseTargetMachine &TM, const ARMSubtarget &STI, |
| 54 | const ARMRegisterBankInfo &RBI); |
| 55 | Pass *createMVEGatherScatterLoweringPass(); |
| 56 | FunctionPass *createARMSLSHardeningPass(); |
| 57 | FunctionPass *createARMIndirectThunks(); |
| 58 | Pass *createMVELaneInterleavingPass(); |
| 59 | FunctionPass *createARMFixCortexA57AES1742098Pass(); |
| 60 | |
| 61 | void LowerARMMachineInstrToMCInst(const MachineInstr *MI, MCInst &OutMI, |
| 62 | ARMAsmPrinter &AP); |
| 63 | |
| 64 | void initializeARMBlockPlacementPass(PassRegistry &); |
| 65 | void initializeARMBranchTargetsPass(PassRegistry &); |
| 66 | void initializeARMConstantIslandsPass(PassRegistry &); |
| 67 | void initializeARMDAGToDAGISelPass(PassRegistry &); |
| 68 | void initializeARMExpandPseudoPass(PassRegistry &); |
| 69 | void initializeARMFixCortexA57AES1742098Pass(PassRegistry &); |
| 70 | void initializeARMLoadStoreOptPass(PassRegistry &); |
| 71 | void initializeARMLowOverheadLoopsPass(PassRegistry &); |
| 72 | void initializeARMParallelDSPPass(PassRegistry &); |
| 73 | void initializeARMPreAllocLoadStoreOptPass(PassRegistry &); |
| 74 | void initializeARMSLSHardeningPass(PassRegistry &); |
| 75 | void initializeMVEGatherScatterLoweringPass(PassRegistry &); |
| 76 | void initializeMVELaneInterleavingPass(PassRegistry &); |
| 77 | void initializeMVETPAndVPTOptimisationsPass(PassRegistry &); |
| 78 | void initializeMVETailPredicationPass(PassRegistry &); |
| 79 | void initializeMVEVPTBlockPass(PassRegistry &); |
| 80 | void initializeThumb2ITBlockPass(PassRegistry &); |
| 81 | void initializeThumb2SizeReducePass(PassRegistry &); |
| 82 | |
| 83 | } // end namespace llvm |
| 84 | |
| 85 | #endif // LLVM_LIB_TARGET_ARM_ARM_H |
| 86 |