1//===-- MipsSubtarget.h - Define Subtarget for the Mips ---------*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file declares the Mips specific subclass of TargetSubtargetInfo.
10//
11//===----------------------------------------------------------------------===//
12
13#ifndef LLVM_LIB_TARGET_MIPS_MIPSSUBTARGET_H
14#define LLVM_LIB_TARGET_MIPS_MIPSSUBTARGET_H
15
16#include "MCTargetDesc/MipsABIInfo.h"
17#include "MipsFrameLowering.h"
18#include "MipsISelLowering.h"
19#include "MipsInstrInfo.h"
20#include "llvm/CodeGen/GlobalISel/CallLowering.h"
21#include "llvm/CodeGen/GlobalISel/InstructionSelector.h"
22#include "llvm/CodeGen/GlobalISel/LegalizerInfo.h"
23#include "llvm/CodeGen/RegisterBankInfo.h"
24#include "llvm/CodeGen/SelectionDAGTargetInfo.h"
25#include "llvm/CodeGen/TargetSubtargetInfo.h"
26#include "llvm/IR/DataLayout.h"
27#include "llvm/MC/MCInstrItineraries.h"
28#include "llvm/Support/ErrorHandling.h"
29
30#define GET_SUBTARGETINFO_HEADER
31#include "MipsGenSubtargetInfo.inc"
32
33namespace llvm {
34class StringRef;
35
36class MipsTargetMachine;
37
38class MipsSubtarget : public MipsGenSubtargetInfo {
39 virtual void anchor();
40
41 enum MipsArchEnum {
42 MipsDefault,
43 Mips1, Mips2, Mips32, Mips32r2, Mips32r3, Mips32r5, Mips32r6, Mips32Max,
44 Mips3, Mips4, Mips5, Mips64, Mips64r2, Mips64r3, Mips64r5, Mips64r6
45 };
46
47 enum class CPU { P5600 };
48
49 // Used to avoid printing dsp warnings multiple times.
50 static bool DspWarningPrinted;
51
52 // Used to avoid printing msa warnings multiple times.
53 static bool MSAWarningPrinted;
54
55 // Used to avoid printing crc warnings multiple times.
56 static bool CRCWarningPrinted;
57
58 // Used to avoid printing ginv warnings multiple times.
59 static bool GINVWarningPrinted;
60
61 // Used to avoid printing Mips1 warnings multiple times.
62 static bool MIPS1WarningPrinted;
63
64 // Used to avoid printing virt warnings multiple times.
65 static bool VirtWarningPrinted;
66
67 // Mips architecture version
68 MipsArchEnum MipsArchVersion;
69
70 // Processor implementation (unused but required to exist by
71 // tablegen-erated code).
72 CPU ProcImpl;
73
74 // IsLittle - The target is Little Endian
75 bool IsLittle;
76
77 // IsSoftFloat - The target does not support any floating point instructions.
78 bool IsSoftFloat;
79
80 // IsSingleFloat - The target only supports single precision float
81 // point operations. This enable the target to use all 32 32-bit
82 // floating point registers instead of only using even ones.
83 bool IsSingleFloat;
84
85 // IsFPXX - MIPS O32 modeless ABI.
86 bool IsFPXX;
87
88 // NoABICalls - Disable SVR4-style position-independent code.
89 bool NoABICalls;
90
91 // Abs2008 - Use IEEE 754-2008 abs.fmt instruction.
92 bool Abs2008;
93
94 // IsFP64bit - The target processor has 64-bit floating point registers.
95 bool IsFP64bit;
96
97 /// Are odd single-precision registers permitted?
98 /// This corresponds to -modd-spreg and -mno-odd-spreg
99 bool UseOddSPReg;
100
101 // IsNan2008 - IEEE 754-2008 NaN encoding.
102 bool IsNaN2008bit;
103
104 // IsGP64bit - General-purpose registers are 64 bits wide
105 bool IsGP64bit;
106
107 // IsPTR64bit - Pointers are 64 bit wide
108 bool IsPTR64bit;
109
110 // HasVFPU - Processor has a vector floating point unit.
111 bool HasVFPU;
112
113 // CPU supports cnMIPS (Cavium Networks Octeon CPU).
114 bool HasCnMips;
115
116 // CPU supports cnMIPSP (Cavium Networks Octeon+ CPU).
117 bool HasCnMipsP;
118
119 // isLinux - Target system is Linux. Is false we consider ELFOS for now.
120 bool IsLinux;
121
122 // UseSmallSection - Small section is used.
123 bool UseSmallSection;
124
125 /// Features related to the presence of specific instructions.
126
127 // HasMips3_32 - The subset of MIPS-III instructions added to MIPS32
128 bool HasMips3_32;
129
130 // HasMips3_32r2 - The subset of MIPS-III instructions added to MIPS32r2
131 bool HasMips3_32r2;
132
133 // HasMips4_32 - Has the subset of MIPS-IV present in MIPS32
134 bool HasMips4_32;
135
136 // HasMips4_32r2 - Has the subset of MIPS-IV present in MIPS32r2
137 bool HasMips4_32r2;
138
139 // HasMips5_32r2 - Has the subset of MIPS-V present in MIPS32r2
140 bool HasMips5_32r2;
141
142 // InMips16 -- can process Mips16 instructions
143 bool InMips16Mode;
144
145 // Mips16 hard float
146 bool InMips16HardFloat;
147
148 // InMicroMips -- can process MicroMips instructions
149 bool InMicroMipsMode;
150
151 // HasDSP, HasDSPR2, HasDSPR3 -- supports DSP ASE.
152 bool HasDSP, HasDSPR2, HasDSPR3;
153
154 // Has3D -- Supports Mips3D ASE.
155 bool Has3D;
156
157 // Allow mixed Mips16 and Mips32 in one source file
158 bool AllowMixed16_32;
159
160 // Optimize for space by compiling all functions as Mips 16 unless
161 // it needs floating point. Functions needing floating point are
162 // compiled as Mips32
163 bool Os16;
164
165 // HasMSA -- supports MSA ASE.
166 bool HasMSA;
167
168 // UseTCCInDIV -- Enables the use of trapping in the assembler.
169 bool UseTCCInDIV;
170
171 // Sym32 -- On Mips64 symbols are 32 bits.
172 bool HasSym32;
173
174 // HasEVA -- supports EVA ASE.
175 bool HasEVA;
176
177 // nomadd4 - disables generation of 4-operand madd.s, madd.d and
178 // related instructions.
179 bool DisableMadd4;
180
181 // HasMT -- support MT ASE.
182 bool HasMT;
183
184 // HasCRC -- supports R6 CRC ASE
185 bool HasCRC;
186
187 // HasVirt -- supports Virtualization ASE
188 bool HasVirt;
189
190 // HasGINV -- supports R6 Global INValidate ASE
191 bool HasGINV;
192
193 // Use hazard variants of the jump register instructions for indirect
194 // function calls and jump tables.
195 bool UseIndirectJumpsHazard;
196
197 // Disable use of the `jal` instruction.
198 bool UseLongCalls = false;
199
200 // Assume 32-bit GOT.
201 bool UseXGOT = false;
202
203 // Disable unaligned load store for r6.
204 bool StrictAlign;
205
206 /// The minimum alignment known to hold of the stack frame on
207 /// entry to the function and which must be maintained by every function.
208 Align stackAlignment;
209
210 /// The overridden stack alignment.
211 MaybeAlign StackAlignOverride;
212
213 InstrItineraryData InstrItins;
214
215 // We can override the determination of whether we are in mips16 mode
216 // as from the command line
217 enum {NoOverride, Mips16Override, NoMips16Override} OverrideMode;
218
219 const MipsTargetMachine &TM;
220
221 Triple TargetTriple;
222
223 const SelectionDAGTargetInfo TSInfo;
224 std::unique_ptr<const MipsInstrInfo> InstrInfo;
225 std::unique_ptr<const MipsFrameLowering> FrameLowering;
226 std::unique_ptr<const MipsTargetLowering> TLInfo;
227
228public:
229 bool isPositionIndependent() const;
230 /// This overrides the PostRAScheduler bit in the SchedModel for each CPU.
231 bool enablePostRAScheduler() const override;
232 void getCriticalPathRCs(RegClassVector &CriticalPathRCs) const override;
233 CodeGenOptLevel getOptLevelToEnablePostRAScheduler() const override;
234
235 bool isABI_N64() const;
236 bool isABI_N32() const;
237 bool isABI_O32() const;
238 const MipsABIInfo &getABI() const;
239 bool isABI_FPXX() const { return isABI_O32() && IsFPXX; }
240
241 /// This constructor initializes the data members to match that
242 /// of the specified triple.
243 MipsSubtarget(const Triple &TT, StringRef CPU, StringRef FS, bool little,
244 const MipsTargetMachine &TM, MaybeAlign StackAlignOverride);
245
246 /// ParseSubtargetFeatures - Parses features string setting specified
247 /// subtarget options. Definition of function is auto generated by tblgen.
248 void ParseSubtargetFeatures(StringRef CPU, StringRef TuneCPU, StringRef FS);
249
250 bool hasMips1() const { return MipsArchVersion >= Mips1; }
251 bool hasMips2() const { return MipsArchVersion >= Mips2; }
252 bool hasMips3() const { return MipsArchVersion >= Mips3; }
253 bool hasMips4() const { return MipsArchVersion >= Mips4; }
254 bool hasMips5() const { return MipsArchVersion >= Mips5; }
255 bool hasMips4_32() const { return HasMips4_32; }
256 bool hasMips4_32r2() const { return HasMips4_32r2; }
257 bool hasMips32() const {
258 return (MipsArchVersion >= Mips32 && MipsArchVersion < Mips32Max) ||
259 hasMips64();
260 }
261 bool hasMips32r2() const {
262 return (MipsArchVersion >= Mips32r2 && MipsArchVersion < Mips32Max) ||
263 hasMips64r2();
264 }
265 bool hasMips32r3() const {
266 return (MipsArchVersion >= Mips32r3 && MipsArchVersion < Mips32Max) ||
267 hasMips64r2();
268 }
269 bool hasMips32r5() const {
270 return (MipsArchVersion >= Mips32r5 && MipsArchVersion < Mips32Max) ||
271 hasMips64r5();
272 }
273 bool hasMips32r6() const {
274 return (MipsArchVersion >= Mips32r6 && MipsArchVersion < Mips32Max) ||
275 hasMips64r6();
276 }
277 bool hasMips64() const { return MipsArchVersion >= Mips64; }
278 bool hasMips64r2() const { return MipsArchVersion >= Mips64r2; }
279 bool hasMips64r3() const { return MipsArchVersion >= Mips64r3; }
280 bool hasMips64r5() const { return MipsArchVersion >= Mips64r5; }
281 bool hasMips64r6() const { return MipsArchVersion >= Mips64r6; }
282
283 bool hasCnMips() const { return HasCnMips; }
284 bool hasCnMipsP() const { return HasCnMipsP; }
285
286 bool isLittle() const { return IsLittle; }
287 bool isABICalls() const { return !NoABICalls; }
288 bool isFPXX() const { return IsFPXX; }
289 bool isFP64bit() const { return IsFP64bit; }
290 bool useOddSPReg() const { return UseOddSPReg; }
291 bool noOddSPReg() const { return !UseOddSPReg; }
292 bool isNaN2008() const { return IsNaN2008bit; }
293 bool inAbs2008Mode() const { return Abs2008; }
294 bool isGP64bit() const { return IsGP64bit; }
295 bool isGP32bit() const { return !IsGP64bit; }
296 unsigned getGPRSizeInBytes() const { return isGP64bit() ? 8 : 4; }
297 bool isPTR64bit() const { return IsPTR64bit; }
298 bool isPTR32bit() const { return !IsPTR64bit; }
299 bool hasSym32() const {
300 return (HasSym32 && isABI_N64()) || isABI_N32() || isABI_O32();
301 }
302 bool isSingleFloat() const { return IsSingleFloat; }
303 bool isTargetELF() const { return TargetTriple.isOSBinFormatELF(); }
304 bool hasVFPU() const { return HasVFPU; }
305 bool inMips16Mode() const { return InMips16Mode; }
306 bool inMips16ModeDefault() const {
307 return InMips16Mode;
308 }
309 // Hard float for mips16 means essentially to compile as soft float
310 // but to use a runtime library for soft float that is written with
311 // native mips32 floating point instructions (those runtime routines
312 // run in mips32 hard float mode).
313 bool inMips16HardFloat() const {
314 return inMips16Mode() && InMips16HardFloat;
315 }
316 bool inMicroMipsMode() const { return InMicroMipsMode && !InMips16Mode; }
317 bool inMicroMips32r6Mode() const {
318 return inMicroMipsMode() && hasMips32r6();
319 }
320 bool hasDSP() const { return HasDSP; }
321 bool hasDSPR2() const { return HasDSPR2; }
322 bool hasDSPR3() const { return HasDSPR3; }
323 bool has3D() const { return Has3D; }
324 bool hasMSA() const { return HasMSA; }
325 bool disableMadd4() const { return DisableMadd4; }
326 bool hasEVA() const { return HasEVA; }
327 bool hasMT() const { return HasMT; }
328 bool hasCRC() const { return HasCRC; }
329 bool hasVirt() const { return HasVirt; }
330 bool hasGINV() const { return HasGINV; }
331 bool useIndirectJumpsHazard() const {
332 return UseIndirectJumpsHazard && hasMips32r2();
333 }
334 bool useSmallSection() const { return UseSmallSection; }
335
336 bool hasStandardEncoding() const { return !InMips16Mode && !InMicroMipsMode; }
337
338 bool useSoftFloat() const { return IsSoftFloat; }
339
340 bool useLongCalls() const { return UseLongCalls; }
341
342 bool useXGOT() const { return UseXGOT; }
343
344 bool enableLongBranchPass() const {
345 return hasStandardEncoding() || inMicroMipsMode() || allowMixed16_32();
346 }
347
348 /// Features related to the presence of specific instructions.
349 bool hasExtractInsert() const { return !inMips16Mode() && hasMips32r2(); }
350 bool hasMTHC1() const { return hasMips32r2(); }
351
352 bool allowMixed16_32() const { return inMips16ModeDefault() |
353 AllowMixed16_32; }
354
355 bool os16() const { return Os16; }
356
357 bool isTargetNaCl() const { return TargetTriple.isOSNaCl(); }
358
359 bool isXRaySupported() const override { return true; }
360
361 // for now constant islands are on for the whole compilation unit but we only
362 // really use them if in addition we are in mips16 mode
363 static bool useConstantIslands();
364
365 Align getStackAlignment() const { return stackAlignment; }
366
367 // Grab relocation model
368 Reloc::Model getRelocationModel() const;
369
370 MipsSubtarget &initializeSubtargetDependencies(StringRef CPU, StringRef FS,
371 const TargetMachine &TM);
372
373 /// Does the system support unaligned memory access.
374 ///
375 /// MIPS32r6/MIPS64r6 require full unaligned access support but does not
376 /// specify which component of the system provides it. Hardware, software, and
377 /// hybrid implementations are all valid.
378 bool systemSupportsUnalignedAccess() const {
379 return hasMips32r6() && !StrictAlign;
380 }
381
382 // Set helper classes
383 void setHelperClassesMips16();
384 void setHelperClassesMipsSE();
385
386 const SelectionDAGTargetInfo *getSelectionDAGInfo() const override {
387 return &TSInfo;
388 }
389 const MipsInstrInfo *getInstrInfo() const override { return InstrInfo.get(); }
390 const TargetFrameLowering *getFrameLowering() const override {
391 return FrameLowering.get();
392 }
393 const MipsRegisterInfo *getRegisterInfo() const override {
394 return &InstrInfo->getRegisterInfo();
395 }
396 const MipsTargetLowering *getTargetLowering() const override {
397 return TLInfo.get();
398 }
399 const InstrItineraryData *getInstrItineraryData() const override {
400 return &InstrItins;
401 }
402
403protected:
404 // GlobalISel related APIs.
405 std::unique_ptr<CallLowering> CallLoweringInfo;
406 std::unique_ptr<LegalizerInfo> Legalizer;
407 std::unique_ptr<RegisterBankInfo> RegBankInfo;
408 std::unique_ptr<InstructionSelector> InstSelector;
409
410public:
411 const CallLowering *getCallLowering() const override;
412 const LegalizerInfo *getLegalizerInfo() const override;
413 const RegisterBankInfo *getRegBankInfo() const override;
414 InstructionSelector *getInstructionSelector() const override;
415};
416} // End llvm namespace
417
418#endif
419

source code of llvm/lib/Target/Mips/MipsSubtarget.h