1//===-- RISCVBaseInfo.h - Top level definitions for RISC-V MC ---*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file contains small standalone enum definitions for the RISC-V target
10// useful for the compiler back-end and the MC libraries.
11//
12//===----------------------------------------------------------------------===//
13#ifndef LLVM_LIB_TARGET_RISCV_MCTARGETDESC_RISCVBASEINFO_H
14#define LLVM_LIB_TARGET_RISCV_MCTARGETDESC_RISCVBASEINFO_H
15
16#include "MCTargetDesc/RISCVMCTargetDesc.h"
17#include "llvm/ADT/APFloat.h"
18#include "llvm/ADT/APInt.h"
19#include "llvm/ADT/StringRef.h"
20#include "llvm/ADT/StringSwitch.h"
21#include "llvm/MC/MCInstrDesc.h"
22#include "llvm/TargetParser/RISCVISAInfo.h"
23#include "llvm/TargetParser/RISCVTargetParser.h"
24#include "llvm/TargetParser/SubtargetFeature.h"
25
26namespace llvm {
27
28// RISCVII - This namespace holds all of the target specific flags that
29// instruction info tracks. All definitions must match RISCVInstrFormats.td.
30namespace RISCVII {
31enum {
32 InstFormatPseudo = 0,
33 InstFormatR = 1,
34 InstFormatR4 = 2,
35 InstFormatI = 3,
36 InstFormatS = 4,
37 InstFormatB = 5,
38 InstFormatU = 6,
39 InstFormatJ = 7,
40 InstFormatCR = 8,
41 InstFormatCI = 9,
42 InstFormatCSS = 10,
43 InstFormatCIW = 11,
44 InstFormatCL = 12,
45 InstFormatCS = 13,
46 InstFormatCA = 14,
47 InstFormatCB = 15,
48 InstFormatCJ = 16,
49 InstFormatCU = 17,
50 InstFormatCLB = 18,
51 InstFormatCLH = 19,
52 InstFormatCSB = 20,
53 InstFormatCSH = 21,
54 InstFormatOther = 22,
55
56 InstFormatMask = 31,
57 InstFormatShift = 0,
58
59 ConstraintShift = InstFormatShift + 5,
60 VS2Constraint = 0b001 << ConstraintShift,
61 VS1Constraint = 0b010 << ConstraintShift,
62 VMConstraint = 0b100 << ConstraintShift,
63 ConstraintMask = 0b111 << ConstraintShift,
64
65 VLMulShift = ConstraintShift + 3,
66 VLMulMask = 0b111 << VLMulShift,
67
68 // Force a tail agnostic policy even this instruction has a tied destination.
69 ForceTailAgnosticShift = VLMulShift + 3,
70 ForceTailAgnosticMask = 1 << ForceTailAgnosticShift,
71
72 // Is this a _TIED vector pseudo instruction. For these instructions we
73 // shouldn't skip the tied operand when converting to MC instructions.
74 IsTiedPseudoShift = ForceTailAgnosticShift + 1,
75 IsTiedPseudoMask = 1 << IsTiedPseudoShift,
76
77 // Does this instruction have a SEW operand. It will be the last explicit
78 // operand unless there is a vector policy operand. Used by RVV Pseudos.
79 HasSEWOpShift = IsTiedPseudoShift + 1,
80 HasSEWOpMask = 1 << HasSEWOpShift,
81
82 // Does this instruction have a VL operand. It will be the second to last
83 // explicit operand unless there is a vector policy operand. Used by RVV
84 // Pseudos.
85 HasVLOpShift = HasSEWOpShift + 1,
86 HasVLOpMask = 1 << HasVLOpShift,
87
88 // Does this instruction have a vector policy operand. It will be the last
89 // explicit operand. Used by RVV Pseudos.
90 HasVecPolicyOpShift = HasVLOpShift + 1,
91 HasVecPolicyOpMask = 1 << HasVecPolicyOpShift,
92
93 // Is this instruction a vector widening reduction instruction. Used by RVV
94 // Pseudos.
95 IsRVVWideningReductionShift = HasVecPolicyOpShift + 1,
96 IsRVVWideningReductionMask = 1 << IsRVVWideningReductionShift,
97
98 // Does this instruction care about mask policy. If it is not, the mask policy
99 // could be either agnostic or undisturbed. For example, unmasked, store, and
100 // reduction operations result would not be affected by mask policy, so
101 // compiler has free to select either one.
102 UsesMaskPolicyShift = IsRVVWideningReductionShift + 1,
103 UsesMaskPolicyMask = 1 << UsesMaskPolicyShift,
104
105 // Indicates that the result can be considered sign extended from bit 31. Some
106 // instructions with this flag aren't W instructions, but are either sign
107 // extended from a smaller size, always outputs a small integer, or put zeros
108 // in bits 63:31. Used by the SExtWRemoval pass.
109 IsSignExtendingOpWShift = UsesMaskPolicyShift + 1,
110 IsSignExtendingOpWMask = 1ULL << IsSignExtendingOpWShift,
111
112 HasRoundModeOpShift = IsSignExtendingOpWShift + 1,
113 HasRoundModeOpMask = 1 << HasRoundModeOpShift,
114
115 UsesVXRMShift = HasRoundModeOpShift + 1,
116 UsesVXRMMask = 1 << UsesVXRMShift,
117
118 // Indicates whether these instructions can partially overlap between source
119 // registers and destination registers according to the vector spec.
120 // 0 -> not a vector pseudo
121 // 1 -> default value for vector pseudos. not widening or narrowing.
122 // 2 -> narrowing case
123 // 3 -> widening case
124 TargetOverlapConstraintTypeShift = UsesVXRMShift + 1,
125 TargetOverlapConstraintTypeMask = 3ULL << TargetOverlapConstraintTypeShift,
126};
127
128// Helper functions to read TSFlags.
129/// \returns the format of the instruction.
130static inline unsigned getFormat(uint64_t TSFlags) {
131 return (TSFlags & InstFormatMask) >> InstFormatShift;
132}
133/// \returns the LMUL for the instruction.
134static inline VLMUL getLMul(uint64_t TSFlags) {
135 return static_cast<VLMUL>((TSFlags & VLMulMask) >> VLMulShift);
136}
137/// \returns true if tail agnostic is enforced for the instruction.
138static inline bool doesForceTailAgnostic(uint64_t TSFlags) {
139 return TSFlags & ForceTailAgnosticMask;
140}
141/// \returns true if this a _TIED pseudo.
142static inline bool isTiedPseudo(uint64_t TSFlags) {
143 return TSFlags & IsTiedPseudoMask;
144}
145/// \returns true if there is a SEW operand for the instruction.
146static inline bool hasSEWOp(uint64_t TSFlags) {
147 return TSFlags & HasSEWOpMask;
148}
149/// \returns true if there is a VL operand for the instruction.
150static inline bool hasVLOp(uint64_t TSFlags) {
151 return TSFlags & HasVLOpMask;
152}
153/// \returns true if there is a vector policy operand for this instruction.
154static inline bool hasVecPolicyOp(uint64_t TSFlags) {
155 return TSFlags & HasVecPolicyOpMask;
156}
157/// \returns true if it is a vector widening reduction instruction.
158static inline bool isRVVWideningReduction(uint64_t TSFlags) {
159 return TSFlags & IsRVVWideningReductionMask;
160}
161/// \returns true if mask policy is valid for the instruction.
162static inline bool usesMaskPolicy(uint64_t TSFlags) {
163 return TSFlags & UsesMaskPolicyMask;
164}
165
166/// \returns true if there is a rounding mode operand for this instruction
167static inline bool hasRoundModeOp(uint64_t TSFlags) {
168 return TSFlags & HasRoundModeOpMask;
169}
170
171/// \returns true if this instruction uses vxrm
172static inline bool usesVXRM(uint64_t TSFlags) { return TSFlags & UsesVXRMMask; }
173
174static inline unsigned getVLOpNum(const MCInstrDesc &Desc) {
175 const uint64_t TSFlags = Desc.TSFlags;
176 // This method is only called if we expect to have a VL operand, and all
177 // instructions with VL also have SEW.
178 assert(hasSEWOp(TSFlags) && hasVLOp(TSFlags));
179 unsigned Offset = 2;
180 if (hasVecPolicyOp(TSFlags))
181 Offset = 3;
182 return Desc.getNumOperands() - Offset;
183}
184
185static inline unsigned getSEWOpNum(const MCInstrDesc &Desc) {
186 const uint64_t TSFlags = Desc.TSFlags;
187 assert(hasSEWOp(TSFlags));
188 unsigned Offset = 1;
189 if (hasVecPolicyOp(TSFlags))
190 Offset = 2;
191 return Desc.getNumOperands() - Offset;
192}
193
194static inline unsigned getVecPolicyOpNum(const MCInstrDesc &Desc) {
195 assert(hasVecPolicyOp(Desc.TSFlags));
196 return Desc.getNumOperands() - 1;
197}
198
199/// \returns the index to the rounding mode immediate value if any, otherwise
200/// returns -1.
201static inline int getFRMOpNum(const MCInstrDesc &Desc) {
202 const uint64_t TSFlags = Desc.TSFlags;
203 if (!hasRoundModeOp(TSFlags) || usesVXRM(TSFlags))
204 return -1;
205
206 // The operand order
207 // --------------------------------------
208 // | n-1 (if any) | n-2 | n-3 | n-4 |
209 // | policy | sew | vl | frm |
210 // --------------------------------------
211 return getVLOpNum(Desc) - 1;
212}
213
214/// \returns the index to the rounding mode immediate value if any, otherwise
215/// returns -1.
216static inline int getVXRMOpNum(const MCInstrDesc &Desc) {
217 const uint64_t TSFlags = Desc.TSFlags;
218 if (!hasRoundModeOp(TSFlags) || !usesVXRM(TSFlags))
219 return -1;
220 // The operand order
221 // --------------------------------------
222 // | n-1 (if any) | n-2 | n-3 | n-4 |
223 // | policy | sew | vl | vxrm |
224 // --------------------------------------
225 return getVLOpNum(Desc) - 1;
226}
227
228// Is the first def operand tied to the first use operand. This is true for
229// vector pseudo instructions that have a merge operand for tail/mask
230// undisturbed. It's also true for vector FMA instructions where one of the
231// operands is also the destination register.
232static inline bool isFirstDefTiedToFirstUse(const MCInstrDesc &Desc) {
233 return Desc.getNumDefs() < Desc.getNumOperands() &&
234 Desc.getOperandConstraint(OpNum: Desc.getNumDefs(), Constraint: MCOI::TIED_TO) == 0;
235}
236
237// RISC-V Specific Machine Operand Flags
238enum {
239 MO_None = 0,
240 MO_CALL = 1,
241 MO_LO = 3,
242 MO_HI = 4,
243 MO_PCREL_LO = 5,
244 MO_PCREL_HI = 6,
245 MO_GOT_HI = 7,
246 MO_TPREL_LO = 8,
247 MO_TPREL_HI = 9,
248 MO_TPREL_ADD = 10,
249 MO_TLS_GOT_HI = 11,
250 MO_TLS_GD_HI = 12,
251 MO_TLSDESC_HI = 13,
252 MO_TLSDESC_LOAD_LO = 14,
253 MO_TLSDESC_ADD_LO = 15,
254 MO_TLSDESC_CALL = 16,
255
256 // Used to differentiate between target-specific "direct" flags and "bitmask"
257 // flags. A machine operand can only have one "direct" flag, but can have
258 // multiple "bitmask" flags.
259 MO_DIRECT_FLAG_MASK = 31
260};
261} // namespace RISCVII
262
263namespace RISCVOp {
264enum OperandType : unsigned {
265 OPERAND_FIRST_RISCV_IMM = MCOI::OPERAND_FIRST_TARGET,
266 OPERAND_UIMM1 = OPERAND_FIRST_RISCV_IMM,
267 OPERAND_UIMM2,
268 OPERAND_UIMM2_LSB0,
269 OPERAND_UIMM3,
270 OPERAND_UIMM4,
271 OPERAND_UIMM5,
272 OPERAND_UIMM6,
273 OPERAND_UIMM7,
274 OPERAND_UIMM7_LSB00,
275 OPERAND_UIMM8_LSB00,
276 OPERAND_UIMM8,
277 OPERAND_UIMM8_LSB000,
278 OPERAND_UIMM8_GE32,
279 OPERAND_UIMM9_LSB000,
280 OPERAND_UIMM10_LSB00_NONZERO,
281 OPERAND_UIMM12,
282 OPERAND_ZERO,
283 OPERAND_SIMM5,
284 OPERAND_SIMM5_PLUS1,
285 OPERAND_SIMM6,
286 OPERAND_SIMM6_NONZERO,
287 OPERAND_SIMM10_LSB0000_NONZERO,
288 OPERAND_SIMM12,
289 OPERAND_SIMM12_LSB00000,
290 OPERAND_UIMM20,
291 OPERAND_UIMMLOG2XLEN,
292 OPERAND_UIMMLOG2XLEN_NONZERO,
293 OPERAND_CLUI_IMM,
294 OPERAND_VTYPEI10,
295 OPERAND_VTYPEI11,
296 OPERAND_RVKRNUM,
297 OPERAND_RVKRNUM_0_7,
298 OPERAND_RVKRNUM_1_10,
299 OPERAND_RVKRNUM_2_14,
300 OPERAND_SPIMM,
301 OPERAND_LAST_RISCV_IMM = OPERAND_SPIMM,
302 // Operand is either a register or uimm5, this is used by V extension pseudo
303 // instructions to represent a value that be passed as AVL to either vsetvli
304 // or vsetivli.
305 OPERAND_AVL,
306};
307} // namespace RISCVOp
308
309// Describes the predecessor/successor bits used in the FENCE instruction.
310namespace RISCVFenceField {
311enum FenceField {
312 I = 8,
313 O = 4,
314 R = 2,
315 W = 1
316};
317}
318
319// Describes the supported floating point rounding mode encodings.
320namespace RISCVFPRndMode {
321enum RoundingMode {
322 RNE = 0,
323 RTZ = 1,
324 RDN = 2,
325 RUP = 3,
326 RMM = 4,
327 DYN = 7,
328 Invalid
329};
330
331inline static StringRef roundingModeToString(RoundingMode RndMode) {
332 switch (RndMode) {
333 default:
334 llvm_unreachable("Unknown floating point rounding mode");
335 case RISCVFPRndMode::RNE:
336 return "rne";
337 case RISCVFPRndMode::RTZ:
338 return "rtz";
339 case RISCVFPRndMode::RDN:
340 return "rdn";
341 case RISCVFPRndMode::RUP:
342 return "rup";
343 case RISCVFPRndMode::RMM:
344 return "rmm";
345 case RISCVFPRndMode::DYN:
346 return "dyn";
347 }
348}
349
350inline static RoundingMode stringToRoundingMode(StringRef Str) {
351 return StringSwitch<RoundingMode>(Str)
352 .Case(S: "rne", Value: RISCVFPRndMode::RNE)
353 .Case(S: "rtz", Value: RISCVFPRndMode::RTZ)
354 .Case(S: "rdn", Value: RISCVFPRndMode::RDN)
355 .Case(S: "rup", Value: RISCVFPRndMode::RUP)
356 .Case(S: "rmm", Value: RISCVFPRndMode::RMM)
357 .Case(S: "dyn", Value: RISCVFPRndMode::DYN)
358 .Default(Value: RISCVFPRndMode::Invalid);
359}
360
361inline static bool isValidRoundingMode(unsigned Mode) {
362 switch (Mode) {
363 default:
364 return false;
365 case RISCVFPRndMode::RNE:
366 case RISCVFPRndMode::RTZ:
367 case RISCVFPRndMode::RDN:
368 case RISCVFPRndMode::RUP:
369 case RISCVFPRndMode::RMM:
370 case RISCVFPRndMode::DYN:
371 return true;
372 }
373}
374} // namespace RISCVFPRndMode
375
376//===----------------------------------------------------------------------===//
377// Floating-point Immediates
378//
379
380namespace RISCVLoadFPImm {
381float getFPImm(unsigned Imm);
382
383/// getLoadFPImm - Return a 5-bit binary encoding of the floating-point
384/// immediate value. If the value cannot be represented as a 5-bit binary
385/// encoding, then return -1.
386int getLoadFPImm(APFloat FPImm);
387} // namespace RISCVLoadFPImm
388
389namespace RISCVSysReg {
390struct SysReg {
391 const char *Name;
392 const char *AltName;
393 const char *DeprecatedName;
394 unsigned Encoding;
395 // FIXME: add these additional fields when needed.
396 // Privilege Access: Read, Write, Read-Only.
397 // unsigned ReadWrite;
398 // Privilege Mode: User, System or Machine.
399 // unsigned Mode;
400 // Check field name.
401 // unsigned Extra;
402 // Register number without the privilege bits.
403 // unsigned Number;
404 FeatureBitset FeaturesRequired;
405 bool isRV32Only;
406
407 bool haveRequiredFeatures(const FeatureBitset &ActiveFeatures) const {
408 // Not in 32-bit mode.
409 if (isRV32Only && ActiveFeatures[RISCV::Feature64Bit])
410 return false;
411 // No required feature associated with the system register.
412 if (FeaturesRequired.none())
413 return true;
414 return (FeaturesRequired & ActiveFeatures) == FeaturesRequired;
415 }
416};
417
418#define GET_SysRegsList_DECL
419#include "RISCVGenSearchableTables.inc"
420} // end namespace RISCVSysReg
421
422namespace RISCVInsnOpcode {
423struct RISCVOpcode {
424 const char *Name;
425 unsigned Value;
426};
427
428#define GET_RISCVOpcodesList_DECL
429#include "RISCVGenSearchableTables.inc"
430} // end namespace RISCVInsnOpcode
431
432namespace RISCVABI {
433
434enum ABI {
435 ABI_ILP32,
436 ABI_ILP32F,
437 ABI_ILP32D,
438 ABI_ILP32E,
439 ABI_LP64,
440 ABI_LP64F,
441 ABI_LP64D,
442 ABI_LP64E,
443 ABI_Unknown
444};
445
446// Returns the target ABI, or else a StringError if the requested ABIName is
447// not supported for the given TT and FeatureBits combination.
448ABI computeTargetABI(const Triple &TT, const FeatureBitset &FeatureBits,
449 StringRef ABIName);
450
451ABI getTargetABI(StringRef ABIName);
452
453// Returns the register used to hold the stack pointer after realignment.
454MCRegister getBPReg();
455
456// Returns the register holding shadow call stack pointer.
457MCRegister getSCSPReg();
458
459} // namespace RISCVABI
460
461namespace RISCVFeatures {
462
463// Validates if the given combination of features are valid for the target
464// triple. Exits with report_fatal_error if not.
465void validate(const Triple &TT, const FeatureBitset &FeatureBits);
466
467llvm::Expected<std::unique_ptr<RISCVISAInfo>>
468parseFeatureBits(bool IsRV64, const FeatureBitset &FeatureBits);
469
470} // namespace RISCVFeatures
471
472namespace RISCVRVC {
473bool compress(MCInst &OutInst, const MCInst &MI, const MCSubtargetInfo &STI);
474bool uncompress(MCInst &OutInst, const MCInst &MI, const MCSubtargetInfo &STI);
475} // namespace RISCVRVC
476
477namespace RISCVZC {
478enum RLISTENCODE {
479 RA = 4,
480 RA_S0,
481 RA_S0_S1,
482 RA_S0_S2,
483 RA_S0_S3,
484 RA_S0_S4,
485 RA_S0_S5,
486 RA_S0_S6,
487 RA_S0_S7,
488 RA_S0_S8,
489 RA_S0_S9,
490 // note - to include s10, s11 must also be included
491 RA_S0_S11,
492 INVALID_RLIST,
493};
494
495inline unsigned encodeRlist(MCRegister EndReg, bool IsRV32E = false) {
496 assert((!IsRV32E || EndReg <= RISCV::X9) && "Invalid Rlist for RV32E");
497 switch (EndReg) {
498 case RISCV::X1:
499 return RLISTENCODE::RA;
500 case RISCV::X8:
501 return RLISTENCODE::RA_S0;
502 case RISCV::X9:
503 return RLISTENCODE::RA_S0_S1;
504 case RISCV::X18:
505 return RLISTENCODE::RA_S0_S2;
506 case RISCV::X19:
507 return RLISTENCODE::RA_S0_S3;
508 case RISCV::X20:
509 return RLISTENCODE::RA_S0_S4;
510 case RISCV::X21:
511 return RLISTENCODE::RA_S0_S5;
512 case RISCV::X22:
513 return RLISTENCODE::RA_S0_S6;
514 case RISCV::X23:
515 return RLISTENCODE::RA_S0_S7;
516 case RISCV::X24:
517 return RLISTENCODE::RA_S0_S8;
518 case RISCV::X25:
519 return RLISTENCODE::RA_S0_S9;
520 case RISCV::X26:
521 return RLISTENCODE::INVALID_RLIST;
522 case RISCV::X27:
523 return RLISTENCODE::RA_S0_S11;
524 default:
525 llvm_unreachable("Undefined input.");
526 }
527}
528
529inline static unsigned getStackAdjBase(unsigned RlistVal, bool IsRV64) {
530 assert(RlistVal != RLISTENCODE::INVALID_RLIST &&
531 "{ra, s0-s10} is not supported, s11 must be included.");
532 if (!IsRV64) {
533 switch (RlistVal) {
534 case RLISTENCODE::RA:
535 case RLISTENCODE::RA_S0:
536 case RLISTENCODE::RA_S0_S1:
537 case RLISTENCODE::RA_S0_S2:
538 return 16;
539 case RLISTENCODE::RA_S0_S3:
540 case RLISTENCODE::RA_S0_S4:
541 case RLISTENCODE::RA_S0_S5:
542 case RLISTENCODE::RA_S0_S6:
543 return 32;
544 case RLISTENCODE::RA_S0_S7:
545 case RLISTENCODE::RA_S0_S8:
546 case RLISTENCODE::RA_S0_S9:
547 return 48;
548 case RLISTENCODE::RA_S0_S11:
549 return 64;
550 }
551 } else {
552 switch (RlistVal) {
553 case RLISTENCODE::RA:
554 case RLISTENCODE::RA_S0:
555 return 16;
556 case RLISTENCODE::RA_S0_S1:
557 case RLISTENCODE::RA_S0_S2:
558 return 32;
559 case RLISTENCODE::RA_S0_S3:
560 case RLISTENCODE::RA_S0_S4:
561 return 48;
562 case RLISTENCODE::RA_S0_S5:
563 case RLISTENCODE::RA_S0_S6:
564 return 64;
565 case RLISTENCODE::RA_S0_S7:
566 case RLISTENCODE::RA_S0_S8:
567 return 80;
568 case RLISTENCODE::RA_S0_S9:
569 return 96;
570 case RLISTENCODE::RA_S0_S11:
571 return 112;
572 }
573 }
574 llvm_unreachable("Unexpected RlistVal");
575}
576
577inline static bool getSpimm(unsigned RlistVal, unsigned &SpimmVal,
578 int64_t StackAdjustment, bool IsRV64) {
579 if (RlistVal == RLISTENCODE::INVALID_RLIST)
580 return false;
581 unsigned StackAdjBase = getStackAdjBase(RlistVal, IsRV64);
582 StackAdjustment -= StackAdjBase;
583 if (StackAdjustment % 16 != 0)
584 return false;
585 SpimmVal = StackAdjustment / 16;
586 if (SpimmVal > 3)
587 return false;
588 return true;
589}
590
591void printRlist(unsigned SlistEncode, raw_ostream &OS);
592} // namespace RISCVZC
593
594} // namespace llvm
595
596#endif
597

source code of llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h