1 | // SPDX-License-Identifier: GPL-2.0-only |
2 | /* |
3 | * Coherency fabric (Aurora) support for Armada 370, 375, 38x and XP |
4 | * platforms. |
5 | * |
6 | * Copyright (C) 2012 Marvell |
7 | * |
8 | * Yehuda Yitschak <yehuday@marvell.com> |
9 | * Gregory Clement <gregory.clement@free-electrons.com> |
10 | * Thomas Petazzoni <thomas.petazzoni@free-electrons.com> |
11 | * |
12 | * The Armada 370, 375, 38x and XP SOCs have a coherency fabric which is |
13 | * responsible for ensuring hardware coherency between all CPUs and between |
14 | * CPUs and I/O masters. This file initializes the coherency fabric and |
15 | * supplies basic routines for configuring and controlling hardware coherency |
16 | */ |
17 | |
18 | #define pr_fmt(fmt) "mvebu-coherency: " fmt |
19 | |
20 | #include <linux/kernel.h> |
21 | #include <linux/init.h> |
22 | #include <linux/of_address.h> |
23 | #include <linux/io.h> |
24 | #include <linux/smp.h> |
25 | #include <linux/dma-map-ops.h> |
26 | #include <linux/platform_device.h> |
27 | #include <linux/slab.h> |
28 | #include <linux/mbus.h> |
29 | #include <linux/pci.h> |
30 | #include <asm/smp_plat.h> |
31 | #include <asm/cacheflush.h> |
32 | #include <asm/mach/map.h> |
33 | #include <asm/dma-mapping.h> |
34 | #include "coherency.h" |
35 | #include "mvebu-soc-id.h" |
36 | |
37 | unsigned long coherency_phys_base; |
38 | void __iomem *coherency_base; |
39 | static void __iomem *coherency_cpu_base; |
40 | static void __iomem *cpu_config_base; |
41 | |
42 | /* Coherency fabric registers */ |
43 | #define IO_SYNC_BARRIER_CTL_OFFSET 0x0 |
44 | |
45 | enum { |
46 | COHERENCY_FABRIC_TYPE_NONE, |
47 | COHERENCY_FABRIC_TYPE_ARMADA_370_XP, |
48 | COHERENCY_FABRIC_TYPE_ARMADA_375, |
49 | COHERENCY_FABRIC_TYPE_ARMADA_380, |
50 | }; |
51 | |
52 | static const struct of_device_id of_coherency_table[] = { |
53 | {.compatible = "marvell,coherency-fabric" , |
54 | .data = (void *) COHERENCY_FABRIC_TYPE_ARMADA_370_XP }, |
55 | {.compatible = "marvell,armada-375-coherency-fabric" , |
56 | .data = (void *) COHERENCY_FABRIC_TYPE_ARMADA_375 }, |
57 | {.compatible = "marvell,armada-380-coherency-fabric" , |
58 | .data = (void *) COHERENCY_FABRIC_TYPE_ARMADA_380 }, |
59 | { /* end of list */ }, |
60 | }; |
61 | |
62 | /* Functions defined in coherency_ll.S */ |
63 | int ll_enable_coherency(void); |
64 | void ll_add_cpu_to_smp_group(void); |
65 | |
66 | #define CPU_CONFIG_SHARED_L2 BIT(16) |
67 | |
68 | /* |
69 | * Disable the "Shared L2 Present" bit in CPU Configuration register |
70 | * on Armada XP. |
71 | * |
72 | * The "Shared L2 Present" bit affects the "level of coherence" value |
73 | * in the clidr CP15 register. Cache operation functions such as |
74 | * "flush all" and "invalidate all" operate on all the cache levels |
75 | * that included in the defined level of coherence. When HW I/O |
76 | * coherency is used, this bit causes unnecessary flushes of the L2 |
77 | * cache. |
78 | */ |
79 | static void armada_xp_clear_shared_l2(void) |
80 | { |
81 | u32 reg; |
82 | |
83 | if (!cpu_config_base) |
84 | return; |
85 | |
86 | reg = readl(addr: cpu_config_base); |
87 | reg &= ~CPU_CONFIG_SHARED_L2; |
88 | writel(val: reg, addr: cpu_config_base); |
89 | } |
90 | |
91 | static int mvebu_hwcc_notifier(struct notifier_block *nb, |
92 | unsigned long event, void *__dev) |
93 | { |
94 | struct device *dev = __dev; |
95 | |
96 | if (event != BUS_NOTIFY_ADD_DEVICE) |
97 | return NOTIFY_DONE; |
98 | dev->dma_coherent = true; |
99 | |
100 | return NOTIFY_OK; |
101 | } |
102 | |
103 | static struct notifier_block mvebu_hwcc_nb = { |
104 | .notifier_call = mvebu_hwcc_notifier, |
105 | }; |
106 | |
107 | static struct notifier_block mvebu_hwcc_pci_nb __maybe_unused = { |
108 | .notifier_call = mvebu_hwcc_notifier, |
109 | }; |
110 | |
111 | static int armada_xp_clear_l2_starting(unsigned int cpu) |
112 | { |
113 | armada_xp_clear_shared_l2(); |
114 | return 0; |
115 | } |
116 | |
117 | static void __init armada_370_coherency_init(struct device_node *np) |
118 | { |
119 | struct resource res; |
120 | struct device_node *cpu_config_np; |
121 | |
122 | of_address_to_resource(dev: np, index: 0, r: &res); |
123 | coherency_phys_base = res.start; |
124 | /* |
125 | * Ensure secondary CPUs will see the updated value, |
126 | * which they read before they join the coherency |
127 | * fabric, and therefore before they are coherent with |
128 | * the boot CPU cache. |
129 | */ |
130 | sync_cache_w(&coherency_phys_base); |
131 | coherency_base = of_iomap(node: np, index: 0); |
132 | coherency_cpu_base = of_iomap(node: np, index: 1); |
133 | |
134 | cpu_config_np = of_find_compatible_node(NULL, NULL, |
135 | compat: "marvell,armada-xp-cpu-config" ); |
136 | if (!cpu_config_np) |
137 | goto exit; |
138 | |
139 | cpu_config_base = of_iomap(node: cpu_config_np, index: 0); |
140 | if (!cpu_config_base) { |
141 | of_node_put(node: cpu_config_np); |
142 | goto exit; |
143 | } |
144 | |
145 | of_node_put(node: cpu_config_np); |
146 | |
147 | cpuhp_setup_state_nocalls(CPUHP_AP_ARM_MVEBU_COHERENCY, |
148 | "arm/mvebu/coherency:starting" , |
149 | armada_xp_clear_l2_starting, NULL); |
150 | exit: |
151 | set_cpu_coherent(); |
152 | } |
153 | |
154 | /* |
155 | * This ioremap hook is used on Armada 375/38x to ensure that all MMIO |
156 | * areas are mapped as MT_UNCACHED instead of MT_DEVICE. This is |
157 | * needed for the HW I/O coherency mechanism to work properly without |
158 | * deadlock. |
159 | */ |
160 | static void __iomem * |
161 | armada_wa_ioremap_caller(phys_addr_t phys_addr, size_t size, |
162 | unsigned int mtype, void *caller) |
163 | { |
164 | mtype = MT_UNCACHED; |
165 | return __arm_ioremap_caller(phys_addr, size, mtype, caller); |
166 | } |
167 | |
168 | static void __init armada_375_380_coherency_init(struct device_node *np) |
169 | { |
170 | struct device_node *cache_dn; |
171 | |
172 | coherency_cpu_base = of_iomap(node: np, index: 0); |
173 | arch_ioremap_caller = armada_wa_ioremap_caller; |
174 | pci_ioremap_set_mem_type(MT_UNCACHED); |
175 | |
176 | /* |
177 | * We should switch the PL310 to I/O coherency mode only if |
178 | * I/O coherency is actually enabled. |
179 | */ |
180 | if (!coherency_available()) |
181 | return; |
182 | |
183 | /* |
184 | * Add the PL310 property "arm,io-coherent". This makes sure the |
185 | * outer sync operation is not used, which allows to |
186 | * workaround the system erratum that causes deadlocks when |
187 | * doing PCIe in an SMP situation on Armada 375 and Armada |
188 | * 38x. |
189 | */ |
190 | for_each_compatible_node(cache_dn, NULL, "arm,pl310-cache" ) { |
191 | struct property *p; |
192 | |
193 | p = kzalloc(size: sizeof(*p), GFP_KERNEL); |
194 | p->name = kstrdup(s: "arm,io-coherent" , GFP_KERNEL); |
195 | of_add_property(np: cache_dn, prop: p); |
196 | } |
197 | } |
198 | |
199 | static int coherency_type(void) |
200 | { |
201 | struct device_node *np; |
202 | const struct of_device_id *match; |
203 | int type; |
204 | |
205 | /* |
206 | * The coherency fabric is needed: |
207 | * - For coherency between processors on Armada XP, so only |
208 | * when SMP is enabled. |
209 | * - For coherency between the processor and I/O devices, but |
210 | * this coherency requires many pre-requisites (write |
211 | * allocate cache policy, shareable pages, SMP bit set) that |
212 | * are only meant in SMP situations. |
213 | * |
214 | * Note that this means that on Armada 370, there is currently |
215 | * no way to use hardware I/O coherency, because even when |
216 | * CONFIG_SMP is enabled, is_smp() returns false due to the |
217 | * Armada 370 being a single-core processor. To lift this |
218 | * limitation, we would have to find a way to make the cache |
219 | * policy set to write-allocate (on all Armada SoCs), and to |
220 | * set the shareable attribute in page tables (on all Armada |
221 | * SoCs except the Armada 370). Unfortunately, such decisions |
222 | * are taken very early in the kernel boot process, at a point |
223 | * where we don't know yet on which SoC we are running. |
224 | |
225 | */ |
226 | if (!is_smp()) |
227 | return COHERENCY_FABRIC_TYPE_NONE; |
228 | |
229 | np = of_find_matching_node_and_match(NULL, matches: of_coherency_table, match: &match); |
230 | if (!np) |
231 | return COHERENCY_FABRIC_TYPE_NONE; |
232 | |
233 | type = (int) match->data; |
234 | |
235 | of_node_put(node: np); |
236 | |
237 | return type; |
238 | } |
239 | |
240 | int set_cpu_coherent(void) |
241 | { |
242 | int type = coherency_type(); |
243 | |
244 | if (type == COHERENCY_FABRIC_TYPE_ARMADA_370_XP) { |
245 | if (!coherency_base) { |
246 | pr_warn("Can't make current CPU cache coherent.\n" ); |
247 | pr_warn("Coherency fabric is not initialized\n" ); |
248 | return 1; |
249 | } |
250 | |
251 | armada_xp_clear_shared_l2(); |
252 | ll_add_cpu_to_smp_group(); |
253 | return ll_enable_coherency(); |
254 | } |
255 | |
256 | return 0; |
257 | } |
258 | |
259 | int coherency_available(void) |
260 | { |
261 | return coherency_type() != COHERENCY_FABRIC_TYPE_NONE; |
262 | } |
263 | |
264 | int __init coherency_init(void) |
265 | { |
266 | int type = coherency_type(); |
267 | struct device_node *np; |
268 | |
269 | np = of_find_matching_node(NULL, matches: of_coherency_table); |
270 | |
271 | if (type == COHERENCY_FABRIC_TYPE_ARMADA_370_XP) |
272 | armada_370_coherency_init(np); |
273 | else if (type == COHERENCY_FABRIC_TYPE_ARMADA_375 || |
274 | type == COHERENCY_FABRIC_TYPE_ARMADA_380) |
275 | armada_375_380_coherency_init(np); |
276 | |
277 | of_node_put(node: np); |
278 | |
279 | return 0; |
280 | } |
281 | |
282 | static int __init coherency_late_init(void) |
283 | { |
284 | if (coherency_available()) |
285 | bus_register_notifier(bus: &platform_bus_type, |
286 | nb: &mvebu_hwcc_nb); |
287 | return 0; |
288 | } |
289 | |
290 | postcore_initcall(coherency_late_init); |
291 | |
292 | #if IS_ENABLED(CONFIG_PCI) |
293 | static int __init coherency_pci_init(void) |
294 | { |
295 | if (coherency_available()) |
296 | bus_register_notifier(bus: &pci_bus_type, |
297 | nb: &mvebu_hwcc_pci_nb); |
298 | return 0; |
299 | } |
300 | |
301 | arch_initcall(coherency_pci_init); |
302 | #endif |
303 | |