1 | /* |
2 | * This file is subject to the terms and conditions of the GNU General Public |
3 | * License. See the file "COPYING" in the main directory of this archive |
4 | * for more details. |
5 | * |
6 | * Copyright (C) 2007, 2008, 2009, 2010, 2011 Cavium Networks |
7 | */ |
8 | #include <linux/kernel.h> |
9 | #include <linux/init.h> |
10 | #include <linux/pci.h> |
11 | #include <linux/interrupt.h> |
12 | #include <linux/time.h> |
13 | #include <linux/delay.h> |
14 | #include <linux/moduleparam.h> |
15 | |
16 | #include <asm/octeon/octeon.h> |
17 | #include <asm/octeon/cvmx-npei-defs.h> |
18 | #include <asm/octeon/cvmx-pciercx-defs.h> |
19 | #include <asm/octeon/cvmx-pescx-defs.h> |
20 | #include <asm/octeon/cvmx-pexp-defs.h> |
21 | #include <asm/octeon/cvmx-pemx-defs.h> |
22 | #include <asm/octeon/cvmx-dpi-defs.h> |
23 | #include <asm/octeon/cvmx-sli-defs.h> |
24 | #include <asm/octeon/cvmx-sriox-defs.h> |
25 | #include <asm/octeon/cvmx-helper-errata.h> |
26 | #include <asm/octeon/pci-octeon.h> |
27 | |
28 | #define MRRS_CN5XXX 0 /* 128 byte Max Read Request Size */ |
29 | #define MPS_CN5XXX 0 /* 128 byte Max Packet Size (Limit of most PCs) */ |
30 | #define MRRS_CN6XXX 3 /* 1024 byte Max Read Request Size */ |
31 | #define MPS_CN6XXX 0 /* 128 byte Max Packet Size (Limit of most PCs) */ |
32 | |
33 | /* Module parameter to disable PCI probing */ |
34 | static int pcie_disable; |
35 | module_param(pcie_disable, int, S_IRUGO); |
36 | |
37 | static int enable_pcie_14459_war; |
38 | static int enable_pcie_bus_num_war[2]; |
39 | |
40 | union cvmx_pcie_address { |
41 | uint64_t u64; |
42 | struct { |
43 | uint64_t upper:2; /* Normally 2 for XKPHYS */ |
44 | uint64_t reserved_49_61:13; /* Must be zero */ |
45 | uint64_t io:1; /* 1 for IO space access */ |
46 | uint64_t did:5; /* PCIe DID = 3 */ |
47 | uint64_t subdid:3; /* PCIe SubDID = 1 */ |
48 | uint64_t reserved_36_39:4; /* Must be zero */ |
49 | uint64_t es:2; /* Endian swap = 1 */ |
50 | uint64_t port:2; /* PCIe port 0,1 */ |
51 | uint64_t reserved_29_31:3; /* Must be zero */ |
52 | /* |
53 | * Selects the type of the configuration request (0 = type 0, |
54 | * 1 = type 1). |
55 | */ |
56 | uint64_t ty:1; |
57 | /* Target bus number sent in the ID in the request. */ |
58 | uint64_t bus:8; |
59 | /* |
60 | * Target device number sent in the ID in the |
61 | * request. Note that Dev must be zero for type 0 |
62 | * configuration requests. |
63 | */ |
64 | uint64_t dev:5; |
65 | /* Target function number sent in the ID in the request. */ |
66 | uint64_t func:3; |
67 | /* |
68 | * Selects a register in the configuration space of |
69 | * the target. |
70 | */ |
71 | uint64_t reg:12; |
72 | } config; |
73 | struct { |
74 | uint64_t upper:2; /* Normally 2 for XKPHYS */ |
75 | uint64_t reserved_49_61:13; /* Must be zero */ |
76 | uint64_t io:1; /* 1 for IO space access */ |
77 | uint64_t did:5; /* PCIe DID = 3 */ |
78 | uint64_t subdid:3; /* PCIe SubDID = 2 */ |
79 | uint64_t reserved_36_39:4; /* Must be zero */ |
80 | uint64_t es:2; /* Endian swap = 1 */ |
81 | uint64_t port:2; /* PCIe port 0,1 */ |
82 | uint64_t address:32; /* PCIe IO address */ |
83 | } io; |
84 | struct { |
85 | uint64_t upper:2; /* Normally 2 for XKPHYS */ |
86 | uint64_t reserved_49_61:13; /* Must be zero */ |
87 | uint64_t io:1; /* 1 for IO space access */ |
88 | uint64_t did:5; /* PCIe DID = 3 */ |
89 | uint64_t subdid:3; /* PCIe SubDID = 3-6 */ |
90 | uint64_t reserved_36_39:4; /* Must be zero */ |
91 | uint64_t address:36; /* PCIe Mem address */ |
92 | } mem; |
93 | }; |
94 | |
95 | static int cvmx_pcie_rc_initialize(int pcie_port); |
96 | |
97 | /** |
98 | * Return the Core virtual base address for PCIe IO access. IOs are |
99 | * read/written as an offset from this address. |
100 | * |
101 | * @pcie_port: PCIe port the IO is for |
102 | * |
103 | * Returns 64bit Octeon IO base address for read/write |
104 | */ |
105 | static inline uint64_t cvmx_pcie_get_io_base_address(int pcie_port) |
106 | { |
107 | union cvmx_pcie_address pcie_addr; |
108 | pcie_addr.u64 = 0; |
109 | pcie_addr.io.upper = 0; |
110 | pcie_addr.io.io = 1; |
111 | pcie_addr.io.did = 3; |
112 | pcie_addr.io.subdid = 2; |
113 | pcie_addr.io.es = 1; |
114 | pcie_addr.io.port = pcie_port; |
115 | return pcie_addr.u64; |
116 | } |
117 | |
118 | /** |
119 | * Size of the IO address region returned at address |
120 | * cvmx_pcie_get_io_base_address() |
121 | * |
122 | * @pcie_port: PCIe port the IO is for |
123 | * |
124 | * Returns Size of the IO window |
125 | */ |
126 | static inline uint64_t cvmx_pcie_get_io_size(int pcie_port) |
127 | { |
128 | return 1ull << 32; |
129 | } |
130 | |
131 | /** |
132 | * Return the Core virtual base address for PCIe MEM access. Memory is |
133 | * read/written as an offset from this address. |
134 | * |
135 | * @pcie_port: PCIe port the IO is for |
136 | * |
137 | * Returns 64bit Octeon IO base address for read/write |
138 | */ |
139 | static inline uint64_t cvmx_pcie_get_mem_base_address(int pcie_port) |
140 | { |
141 | union cvmx_pcie_address pcie_addr; |
142 | pcie_addr.u64 = 0; |
143 | pcie_addr.mem.upper = 0; |
144 | pcie_addr.mem.io = 1; |
145 | pcie_addr.mem.did = 3; |
146 | pcie_addr.mem.subdid = 3 + pcie_port; |
147 | return pcie_addr.u64; |
148 | } |
149 | |
150 | /** |
151 | * Size of the Mem address region returned at address |
152 | * cvmx_pcie_get_mem_base_address() |
153 | * |
154 | * @pcie_port: PCIe port the IO is for |
155 | * |
156 | * Returns Size of the Mem window |
157 | */ |
158 | static inline uint64_t cvmx_pcie_get_mem_size(int pcie_port) |
159 | { |
160 | return 1ull << 36; |
161 | } |
162 | |
163 | /** |
164 | * Read a PCIe config space register indirectly. This is used for |
165 | * registers of the form PCIEEP_CFG??? and PCIERC?_CFG???. |
166 | * |
167 | * @pcie_port: PCIe port to read from |
168 | * @cfg_offset: Address to read |
169 | * |
170 | * Returns Value read |
171 | */ |
172 | static uint32_t cvmx_pcie_cfgx_read(int pcie_port, uint32_t cfg_offset) |
173 | { |
174 | if (octeon_has_feature(OCTEON_FEATURE_NPEI)) { |
175 | union cvmx_pescx_cfg_rd pescx_cfg_rd; |
176 | pescx_cfg_rd.u64 = 0; |
177 | pescx_cfg_rd.s.addr = cfg_offset; |
178 | cvmx_write_csr(CVMX_PESCX_CFG_RD(pcie_port), pescx_cfg_rd.u64); |
179 | pescx_cfg_rd.u64 = cvmx_read_csr(CVMX_PESCX_CFG_RD(pcie_port)); |
180 | return pescx_cfg_rd.s.data; |
181 | } else { |
182 | union cvmx_pemx_cfg_rd pemx_cfg_rd; |
183 | pemx_cfg_rd.u64 = 0; |
184 | pemx_cfg_rd.s.addr = cfg_offset; |
185 | cvmx_write_csr(CVMX_PEMX_CFG_RD(pcie_port), pemx_cfg_rd.u64); |
186 | pemx_cfg_rd.u64 = cvmx_read_csr(CVMX_PEMX_CFG_RD(pcie_port)); |
187 | return pemx_cfg_rd.s.data; |
188 | } |
189 | } |
190 | |
191 | /** |
192 | * Write a PCIe config space register indirectly. This is used for |
193 | * registers of the form PCIEEP_CFG??? and PCIERC?_CFG???. |
194 | * |
195 | * @pcie_port: PCIe port to write to |
196 | * @cfg_offset: Address to write |
197 | * @val: Value to write |
198 | */ |
199 | static void cvmx_pcie_cfgx_write(int pcie_port, uint32_t cfg_offset, |
200 | uint32_t val) |
201 | { |
202 | if (octeon_has_feature(OCTEON_FEATURE_NPEI)) { |
203 | union cvmx_pescx_cfg_wr pescx_cfg_wr; |
204 | pescx_cfg_wr.u64 = 0; |
205 | pescx_cfg_wr.s.addr = cfg_offset; |
206 | pescx_cfg_wr.s.data = val; |
207 | cvmx_write_csr(CVMX_PESCX_CFG_WR(pcie_port), pescx_cfg_wr.u64); |
208 | } else { |
209 | union cvmx_pemx_cfg_wr pemx_cfg_wr; |
210 | pemx_cfg_wr.u64 = 0; |
211 | pemx_cfg_wr.s.addr = cfg_offset; |
212 | pemx_cfg_wr.s.data = val; |
213 | cvmx_write_csr(CVMX_PEMX_CFG_WR(pcie_port), pemx_cfg_wr.u64); |
214 | } |
215 | } |
216 | |
217 | /** |
218 | * Build a PCIe config space request address for a device |
219 | * |
220 | * @pcie_port: PCIe port to access |
221 | * @bus: Sub bus |
222 | * @dev: Device ID |
223 | * @fn: Device sub function |
224 | * @reg: Register to access |
225 | * |
226 | * Returns 64bit Octeon IO address |
227 | */ |
228 | static inline uint64_t __cvmx_pcie_build_config_addr(int pcie_port, int bus, |
229 | int dev, int fn, int reg) |
230 | { |
231 | union cvmx_pcie_address pcie_addr; |
232 | union cvmx_pciercx_cfg006 pciercx_cfg006; |
233 | |
234 | pciercx_cfg006.u32 = |
235 | cvmx_pcie_cfgx_read(pcie_port, cfg_offset: CVMX_PCIERCX_CFG006(pcie_port)); |
236 | if ((bus <= pciercx_cfg006.s.pbnum) && (dev != 0)) |
237 | return 0; |
238 | |
239 | pcie_addr.u64 = 0; |
240 | pcie_addr.config.upper = 2; |
241 | pcie_addr.config.io = 1; |
242 | pcie_addr.config.did = 3; |
243 | pcie_addr.config.subdid = 1; |
244 | pcie_addr.config.es = 1; |
245 | pcie_addr.config.port = pcie_port; |
246 | pcie_addr.config.ty = (bus > pciercx_cfg006.s.pbnum); |
247 | pcie_addr.config.bus = bus; |
248 | pcie_addr.config.dev = dev; |
249 | pcie_addr.config.func = fn; |
250 | pcie_addr.config.reg = reg; |
251 | return pcie_addr.u64; |
252 | } |
253 | |
254 | /** |
255 | * Read 8bits from a Device's config space |
256 | * |
257 | * @pcie_port: PCIe port the device is on |
258 | * @bus: Sub bus |
259 | * @dev: Device ID |
260 | * @fn: Device sub function |
261 | * @reg: Register to access |
262 | * |
263 | * Returns Result of the read |
264 | */ |
265 | static uint8_t cvmx_pcie_config_read8(int pcie_port, int bus, int dev, |
266 | int fn, int reg) |
267 | { |
268 | uint64_t address = |
269 | __cvmx_pcie_build_config_addr(pcie_port, bus, dev, fn, reg); |
270 | if (address) |
271 | return cvmx_read64_uint8(address); |
272 | else |
273 | return 0xff; |
274 | } |
275 | |
276 | /** |
277 | * Read 16bits from a Device's config space |
278 | * |
279 | * @pcie_port: PCIe port the device is on |
280 | * @bus: Sub bus |
281 | * @dev: Device ID |
282 | * @fn: Device sub function |
283 | * @reg: Register to access |
284 | * |
285 | * Returns Result of the read |
286 | */ |
287 | static uint16_t cvmx_pcie_config_read16(int pcie_port, int bus, int dev, |
288 | int fn, int reg) |
289 | { |
290 | uint64_t address = |
291 | __cvmx_pcie_build_config_addr(pcie_port, bus, dev, fn, reg); |
292 | if (address) |
293 | return le16_to_cpu(cvmx_read64_uint16(address)); |
294 | else |
295 | return 0xffff; |
296 | } |
297 | |
298 | /** |
299 | * Read 32bits from a Device's config space |
300 | * |
301 | * @pcie_port: PCIe port the device is on |
302 | * @bus: Sub bus |
303 | * @dev: Device ID |
304 | * @fn: Device sub function |
305 | * @reg: Register to access |
306 | * |
307 | * Returns Result of the read |
308 | */ |
309 | static uint32_t cvmx_pcie_config_read32(int pcie_port, int bus, int dev, |
310 | int fn, int reg) |
311 | { |
312 | uint64_t address = |
313 | __cvmx_pcie_build_config_addr(pcie_port, bus, dev, fn, reg); |
314 | if (address) |
315 | return le32_to_cpu(cvmx_read64_uint32(address)); |
316 | else |
317 | return 0xffffffff; |
318 | } |
319 | |
320 | /** |
321 | * Write 8bits to a Device's config space |
322 | * |
323 | * @pcie_port: PCIe port the device is on |
324 | * @bus: Sub bus |
325 | * @dev: Device ID |
326 | * @fn: Device sub function |
327 | * @reg: Register to access |
328 | * @val: Value to write |
329 | */ |
330 | static void cvmx_pcie_config_write8(int pcie_port, int bus, int dev, int fn, |
331 | int reg, uint8_t val) |
332 | { |
333 | uint64_t address = |
334 | __cvmx_pcie_build_config_addr(pcie_port, bus, dev, fn, reg); |
335 | if (address) |
336 | cvmx_write64_uint8(address, val); |
337 | } |
338 | |
339 | /** |
340 | * Write 16bits to a Device's config space |
341 | * |
342 | * @pcie_port: PCIe port the device is on |
343 | * @bus: Sub bus |
344 | * @dev: Device ID |
345 | * @fn: Device sub function |
346 | * @reg: Register to access |
347 | * @val: Value to write |
348 | */ |
349 | static void cvmx_pcie_config_write16(int pcie_port, int bus, int dev, int fn, |
350 | int reg, uint16_t val) |
351 | { |
352 | uint64_t address = |
353 | __cvmx_pcie_build_config_addr(pcie_port, bus, dev, fn, reg); |
354 | if (address) |
355 | cvmx_write64_uint16(address, cpu_to_le16(val)); |
356 | } |
357 | |
358 | /** |
359 | * Write 32bits to a Device's config space |
360 | * |
361 | * @pcie_port: PCIe port the device is on |
362 | * @bus: Sub bus |
363 | * @dev: Device ID |
364 | * @fn: Device sub function |
365 | * @reg: Register to access |
366 | * @val: Value to write |
367 | */ |
368 | static void cvmx_pcie_config_write32(int pcie_port, int bus, int dev, int fn, |
369 | int reg, uint32_t val) |
370 | { |
371 | uint64_t address = |
372 | __cvmx_pcie_build_config_addr(pcie_port, bus, dev, fn, reg); |
373 | if (address) |
374 | cvmx_write64_uint32(address, cpu_to_le32(val)); |
375 | } |
376 | |
377 | /** |
378 | * Initialize the RC config space CSRs |
379 | * |
380 | * @pcie_port: PCIe port to initialize |
381 | */ |
382 | static void __cvmx_pcie_rc_initialize_config_space(int pcie_port) |
383 | { |
384 | union cvmx_pciercx_cfg030 pciercx_cfg030; |
385 | union cvmx_pciercx_cfg070 pciercx_cfg070; |
386 | union cvmx_pciercx_cfg001 pciercx_cfg001; |
387 | union cvmx_pciercx_cfg032 pciercx_cfg032; |
388 | union cvmx_pciercx_cfg006 pciercx_cfg006; |
389 | union cvmx_pciercx_cfg008 pciercx_cfg008; |
390 | union cvmx_pciercx_cfg009 pciercx_cfg009; |
391 | union cvmx_pciercx_cfg010 pciercx_cfg010; |
392 | union cvmx_pciercx_cfg011 pciercx_cfg011; |
393 | union cvmx_pciercx_cfg035 pciercx_cfg035; |
394 | union cvmx_pciercx_cfg075 pciercx_cfg075; |
395 | union cvmx_pciercx_cfg034 pciercx_cfg034; |
396 | |
397 | /* Max Payload Size (PCIE*_CFG030[MPS]) */ |
398 | /* Max Read Request Size (PCIE*_CFG030[MRRS]) */ |
399 | /* Relaxed-order, no-snoop enables (PCIE*_CFG030[RO_EN,NS_EN] */ |
400 | /* Error Message Enables (PCIE*_CFG030[CE_EN,NFE_EN,FE_EN,UR_EN]) */ |
401 | |
402 | pciercx_cfg030.u32 = cvmx_pcie_cfgx_read(pcie_port, cfg_offset: CVMX_PCIERCX_CFG030(pcie_port)); |
403 | if (OCTEON_IS_MODEL(OCTEON_CN5XXX)) { |
404 | pciercx_cfg030.s.mps = MPS_CN5XXX; |
405 | pciercx_cfg030.s.mrrs = MRRS_CN5XXX; |
406 | } else { |
407 | pciercx_cfg030.s.mps = MPS_CN6XXX; |
408 | pciercx_cfg030.s.mrrs = MRRS_CN6XXX; |
409 | } |
410 | /* |
411 | * Enable relaxed order processing. This will allow devices to |
412 | * affect read response ordering. |
413 | */ |
414 | pciercx_cfg030.s.ro_en = 1; |
415 | /* Enable no snoop processing. Not used by Octeon */ |
416 | pciercx_cfg030.s.ns_en = 1; |
417 | /* Correctable error reporting enable. */ |
418 | pciercx_cfg030.s.ce_en = 1; |
419 | /* Non-fatal error reporting enable. */ |
420 | pciercx_cfg030.s.nfe_en = 1; |
421 | /* Fatal error reporting enable. */ |
422 | pciercx_cfg030.s.fe_en = 1; |
423 | /* Unsupported request reporting enable. */ |
424 | pciercx_cfg030.s.ur_en = 1; |
425 | cvmx_pcie_cfgx_write(pcie_port, cfg_offset: CVMX_PCIERCX_CFG030(pcie_port), val: pciercx_cfg030.u32); |
426 | |
427 | |
428 | if (octeon_has_feature(OCTEON_FEATURE_NPEI)) { |
429 | union cvmx_npei_ctl_status2 npei_ctl_status2; |
430 | /* |
431 | * Max Payload Size (NPEI_CTL_STATUS2[MPS]) must match |
432 | * PCIE*_CFG030[MPS]. Max Read Request Size |
433 | * (NPEI_CTL_STATUS2[MRRS]) must not exceed |
434 | * PCIE*_CFG030[MRRS] |
435 | */ |
436 | npei_ctl_status2.u64 = cvmx_read_csr(CVMX_PEXP_NPEI_CTL_STATUS2); |
437 | /* Max payload size = 128 bytes for best Octeon DMA performance */ |
438 | npei_ctl_status2.s.mps = MPS_CN5XXX; |
439 | /* Max read request size = 128 bytes for best Octeon DMA performance */ |
440 | npei_ctl_status2.s.mrrs = MRRS_CN5XXX; |
441 | if (pcie_port) |
442 | npei_ctl_status2.s.c1_b1_s = 3; /* Port1 BAR1 Size 256MB */ |
443 | else |
444 | npei_ctl_status2.s.c0_b1_s = 3; /* Port0 BAR1 Size 256MB */ |
445 | |
446 | cvmx_write_csr(CVMX_PEXP_NPEI_CTL_STATUS2, npei_ctl_status2.u64); |
447 | } else { |
448 | /* |
449 | * Max Payload Size (DPI_SLI_PRTX_CFG[MPS]) must match |
450 | * PCIE*_CFG030[MPS]. Max Read Request Size |
451 | * (DPI_SLI_PRTX_CFG[MRRS]) must not exceed |
452 | * PCIE*_CFG030[MRRS]. |
453 | */ |
454 | union cvmx_dpi_sli_prtx_cfg prt_cfg; |
455 | union cvmx_sli_s2m_portx_ctl sli_s2m_portx_ctl; |
456 | prt_cfg.u64 = cvmx_read_csr(CVMX_DPI_SLI_PRTX_CFG(pcie_port)); |
457 | prt_cfg.s.mps = MPS_CN6XXX; |
458 | prt_cfg.s.mrrs = MRRS_CN6XXX; |
459 | /* Max outstanding load request. */ |
460 | prt_cfg.s.molr = 32; |
461 | cvmx_write_csr(CVMX_DPI_SLI_PRTX_CFG(pcie_port), prt_cfg.u64); |
462 | |
463 | sli_s2m_portx_ctl.u64 = cvmx_read_csr(CVMX_PEXP_SLI_S2M_PORTX_CTL(pcie_port)); |
464 | sli_s2m_portx_ctl.s.mrrs = MRRS_CN6XXX; |
465 | cvmx_write_csr(CVMX_PEXP_SLI_S2M_PORTX_CTL(pcie_port), sli_s2m_portx_ctl.u64); |
466 | } |
467 | |
468 | /* ECRC Generation (PCIE*_CFG070[GE,CE]) */ |
469 | pciercx_cfg070.u32 = cvmx_pcie_cfgx_read(pcie_port, cfg_offset: CVMX_PCIERCX_CFG070(pcie_port)); |
470 | pciercx_cfg070.s.ge = 1; /* ECRC generation enable. */ |
471 | pciercx_cfg070.s.ce = 1; /* ECRC check enable. */ |
472 | cvmx_pcie_cfgx_write(pcie_port, cfg_offset: CVMX_PCIERCX_CFG070(pcie_port), val: pciercx_cfg070.u32); |
473 | |
474 | /* |
475 | * Access Enables (PCIE*_CFG001[MSAE,ME]) |
476 | * ME and MSAE should always be set. |
477 | * Interrupt Disable (PCIE*_CFG001[I_DIS]) |
478 | * System Error Message Enable (PCIE*_CFG001[SEE]) |
479 | */ |
480 | pciercx_cfg001.u32 = cvmx_pcie_cfgx_read(pcie_port, cfg_offset: CVMX_PCIERCX_CFG001(pcie_port)); |
481 | pciercx_cfg001.s.msae = 1; /* Memory space enable. */ |
482 | pciercx_cfg001.s.me = 1; /* Bus master enable. */ |
483 | pciercx_cfg001.s.i_dis = 1; /* INTx assertion disable. */ |
484 | pciercx_cfg001.s.see = 1; /* SERR# enable */ |
485 | cvmx_pcie_cfgx_write(pcie_port, cfg_offset: CVMX_PCIERCX_CFG001(pcie_port), val: pciercx_cfg001.u32); |
486 | |
487 | /* Advanced Error Recovery Message Enables */ |
488 | /* (PCIE*_CFG066,PCIE*_CFG067,PCIE*_CFG069) */ |
489 | cvmx_pcie_cfgx_write(pcie_port, cfg_offset: CVMX_PCIERCX_CFG066(pcie_port), val: 0); |
490 | /* Use CVMX_PCIERCX_CFG067 hardware default */ |
491 | cvmx_pcie_cfgx_write(pcie_port, cfg_offset: CVMX_PCIERCX_CFG069(pcie_port), val: 0); |
492 | |
493 | |
494 | /* Active State Power Management (PCIE*_CFG032[ASLPC]) */ |
495 | pciercx_cfg032.u32 = cvmx_pcie_cfgx_read(pcie_port, cfg_offset: CVMX_PCIERCX_CFG032(pcie_port)); |
496 | pciercx_cfg032.s.aslpc = 0; /* Active state Link PM control. */ |
497 | cvmx_pcie_cfgx_write(pcie_port, cfg_offset: CVMX_PCIERCX_CFG032(pcie_port), val: pciercx_cfg032.u32); |
498 | |
499 | /* |
500 | * Link Width Mode (PCIERCn_CFG452[LME]) - Set during |
501 | * cvmx_pcie_rc_initialize_link() |
502 | * |
503 | * Primary Bus Number (PCIERCn_CFG006[PBNUM]) |
504 | * |
505 | * We set the primary bus number to 1 so IDT bridges are |
506 | * happy. They don't like zero. |
507 | */ |
508 | pciercx_cfg006.u32 = 0; |
509 | pciercx_cfg006.s.pbnum = 1; |
510 | pciercx_cfg006.s.sbnum = 1; |
511 | pciercx_cfg006.s.subbnum = 1; |
512 | cvmx_pcie_cfgx_write(pcie_port, cfg_offset: CVMX_PCIERCX_CFG006(pcie_port), val: pciercx_cfg006.u32); |
513 | |
514 | |
515 | /* |
516 | * Memory-mapped I/O BAR (PCIERCn_CFG008) |
517 | * Most applications should disable the memory-mapped I/O BAR by |
518 | * setting PCIERCn_CFG008[ML_ADDR] < PCIERCn_CFG008[MB_ADDR] |
519 | */ |
520 | pciercx_cfg008.u32 = 0; |
521 | pciercx_cfg008.s.mb_addr = 0x100; |
522 | pciercx_cfg008.s.ml_addr = 0; |
523 | cvmx_pcie_cfgx_write(pcie_port, cfg_offset: CVMX_PCIERCX_CFG008(pcie_port), val: pciercx_cfg008.u32); |
524 | |
525 | |
526 | /* |
527 | * Prefetchable BAR (PCIERCn_CFG009,PCIERCn_CFG010,PCIERCn_CFG011) |
528 | * Most applications should disable the prefetchable BAR by setting |
529 | * PCIERCn_CFG011[UMEM_LIMIT],PCIERCn_CFG009[LMEM_LIMIT] < |
530 | * PCIERCn_CFG010[UMEM_BASE],PCIERCn_CFG009[LMEM_BASE] |
531 | */ |
532 | pciercx_cfg009.u32 = cvmx_pcie_cfgx_read(pcie_port, cfg_offset: CVMX_PCIERCX_CFG009(pcie_port)); |
533 | pciercx_cfg010.u32 = cvmx_pcie_cfgx_read(pcie_port, cfg_offset: CVMX_PCIERCX_CFG010(pcie_port)); |
534 | pciercx_cfg011.u32 = cvmx_pcie_cfgx_read(pcie_port, cfg_offset: CVMX_PCIERCX_CFG011(pcie_port)); |
535 | pciercx_cfg009.s.lmem_base = 0x100; |
536 | pciercx_cfg009.s.lmem_limit = 0; |
537 | pciercx_cfg010.s.umem_base = 0x100; |
538 | pciercx_cfg011.s.umem_limit = 0; |
539 | cvmx_pcie_cfgx_write(pcie_port, cfg_offset: CVMX_PCIERCX_CFG009(pcie_port), val: pciercx_cfg009.u32); |
540 | cvmx_pcie_cfgx_write(pcie_port, cfg_offset: CVMX_PCIERCX_CFG010(pcie_port), val: pciercx_cfg010.u32); |
541 | cvmx_pcie_cfgx_write(pcie_port, cfg_offset: CVMX_PCIERCX_CFG011(pcie_port), val: pciercx_cfg011.u32); |
542 | |
543 | /* |
544 | * System Error Interrupt Enables (PCIERCn_CFG035[SECEE,SEFEE,SENFEE]) |
545 | * PME Interrupt Enables (PCIERCn_CFG035[PMEIE]) |
546 | */ |
547 | pciercx_cfg035.u32 = cvmx_pcie_cfgx_read(pcie_port, cfg_offset: CVMX_PCIERCX_CFG035(pcie_port)); |
548 | pciercx_cfg035.s.secee = 1; /* System error on correctable error enable. */ |
549 | pciercx_cfg035.s.sefee = 1; /* System error on fatal error enable. */ |
550 | pciercx_cfg035.s.senfee = 1; /* System error on non-fatal error enable. */ |
551 | pciercx_cfg035.s.pmeie = 1; /* PME interrupt enable. */ |
552 | cvmx_pcie_cfgx_write(pcie_port, cfg_offset: CVMX_PCIERCX_CFG035(pcie_port), val: pciercx_cfg035.u32); |
553 | |
554 | /* |
555 | * Advanced Error Recovery Interrupt Enables |
556 | * (PCIERCn_CFG075[CERE,NFERE,FERE]) |
557 | */ |
558 | pciercx_cfg075.u32 = cvmx_pcie_cfgx_read(pcie_port, cfg_offset: CVMX_PCIERCX_CFG075(pcie_port)); |
559 | pciercx_cfg075.s.cere = 1; /* Correctable error reporting enable. */ |
560 | pciercx_cfg075.s.nfere = 1; /* Non-fatal error reporting enable. */ |
561 | pciercx_cfg075.s.fere = 1; /* Fatal error reporting enable. */ |
562 | cvmx_pcie_cfgx_write(pcie_port, cfg_offset: CVMX_PCIERCX_CFG075(pcie_port), val: pciercx_cfg075.u32); |
563 | |
564 | /* |
565 | * HP Interrupt Enables (PCIERCn_CFG034[HPINT_EN], |
566 | * PCIERCn_CFG034[DLLS_EN,CCINT_EN]) |
567 | */ |
568 | pciercx_cfg034.u32 = cvmx_pcie_cfgx_read(pcie_port, cfg_offset: CVMX_PCIERCX_CFG034(pcie_port)); |
569 | pciercx_cfg034.s.hpint_en = 1; /* Hot-plug interrupt enable. */ |
570 | pciercx_cfg034.s.dlls_en = 1; /* Data Link Layer state changed enable */ |
571 | pciercx_cfg034.s.ccint_en = 1; /* Command completed interrupt enable. */ |
572 | cvmx_pcie_cfgx_write(pcie_port, cfg_offset: CVMX_PCIERCX_CFG034(pcie_port), val: pciercx_cfg034.u32); |
573 | } |
574 | |
575 | /** |
576 | * Initialize a host mode PCIe gen 1 link. This function takes a PCIe |
577 | * port from reset to a link up state. Software can then begin |
578 | * configuring the rest of the link. |
579 | * |
580 | * @pcie_port: PCIe port to initialize |
581 | * |
582 | * Returns Zero on success |
583 | */ |
584 | static int __cvmx_pcie_rc_initialize_link_gen1(int pcie_port) |
585 | { |
586 | uint64_t start_cycle; |
587 | union cvmx_pescx_ctl_status pescx_ctl_status; |
588 | union cvmx_pciercx_cfg452 pciercx_cfg452; |
589 | union cvmx_pciercx_cfg032 pciercx_cfg032; |
590 | union cvmx_pciercx_cfg448 pciercx_cfg448; |
591 | |
592 | /* Set the lane width */ |
593 | pciercx_cfg452.u32 = cvmx_pcie_cfgx_read(pcie_port, cfg_offset: CVMX_PCIERCX_CFG452(pcie_port)); |
594 | pescx_ctl_status.u64 = cvmx_read_csr(CVMX_PESCX_CTL_STATUS(pcie_port)); |
595 | if (pescx_ctl_status.s.qlm_cfg == 0) |
596 | /* We're in 8 lane (56XX) or 4 lane (54XX) mode */ |
597 | pciercx_cfg452.s.lme = 0xf; |
598 | else |
599 | /* We're in 4 lane (56XX) or 2 lane (52XX) mode */ |
600 | pciercx_cfg452.s.lme = 0x7; |
601 | cvmx_pcie_cfgx_write(pcie_port, cfg_offset: CVMX_PCIERCX_CFG452(pcie_port), val: pciercx_cfg452.u32); |
602 | |
603 | /* |
604 | * CN52XX pass 1.x has an errata where length mismatches on UR |
605 | * responses can cause bus errors on 64bit memory |
606 | * reads. Turning off length error checking fixes this. |
607 | */ |
608 | if (OCTEON_IS_MODEL(OCTEON_CN52XX_PASS1_X)) { |
609 | union cvmx_pciercx_cfg455 pciercx_cfg455; |
610 | pciercx_cfg455.u32 = cvmx_pcie_cfgx_read(pcie_port, cfg_offset: CVMX_PCIERCX_CFG455(pcie_port)); |
611 | pciercx_cfg455.s.m_cpl_len_err = 1; |
612 | cvmx_pcie_cfgx_write(pcie_port, cfg_offset: CVMX_PCIERCX_CFG455(pcie_port), val: pciercx_cfg455.u32); |
613 | } |
614 | |
615 | /* Lane swap needs to be manually enabled for CN52XX */ |
616 | if (OCTEON_IS_MODEL(OCTEON_CN52XX) && (pcie_port == 1)) { |
617 | pescx_ctl_status.s.lane_swp = 1; |
618 | cvmx_write_csr(CVMX_PESCX_CTL_STATUS(pcie_port), pescx_ctl_status.u64); |
619 | } |
620 | |
621 | /* Bring up the link */ |
622 | pescx_ctl_status.u64 = cvmx_read_csr(CVMX_PESCX_CTL_STATUS(pcie_port)); |
623 | pescx_ctl_status.s.lnk_enb = 1; |
624 | cvmx_write_csr(CVMX_PESCX_CTL_STATUS(pcie_port), pescx_ctl_status.u64); |
625 | |
626 | /* |
627 | * CN52XX pass 1.0: Due to a bug in 2nd order CDR, it needs to |
628 | * be disabled. |
629 | */ |
630 | if (OCTEON_IS_MODEL(OCTEON_CN52XX_PASS1_0)) |
631 | __cvmx_helper_errata_qlm_disable_2nd_order_cdr(0); |
632 | |
633 | /* Wait for the link to come up */ |
634 | start_cycle = cvmx_get_cycle(); |
635 | do { |
636 | if (cvmx_get_cycle() - start_cycle > 2 * octeon_get_clock_rate()) { |
637 | cvmx_dprintf("PCIe: Port %d link timeout\n" , pcie_port); |
638 | return -1; |
639 | } |
640 | __delay(loops: 10000); |
641 | pciercx_cfg032.u32 = cvmx_pcie_cfgx_read(pcie_port, cfg_offset: CVMX_PCIERCX_CFG032(pcie_port)); |
642 | } while (pciercx_cfg032.s.dlla == 0); |
643 | |
644 | /* Clear all pending errors */ |
645 | cvmx_write_csr(CVMX_PEXP_NPEI_INT_SUM, cvmx_read_csr(CVMX_PEXP_NPEI_INT_SUM)); |
646 | |
647 | /* |
648 | * Update the Replay Time Limit. Empirically, some PCIe |
649 | * devices take a little longer to respond than expected under |
650 | * load. As a workaround for this we configure the Replay Time |
651 | * Limit to the value expected for a 512 byte MPS instead of |
652 | * our actual 256 byte MPS. The numbers below are directly |
653 | * from the PCIe spec table 3-4. |
654 | */ |
655 | pciercx_cfg448.u32 = cvmx_pcie_cfgx_read(pcie_port, cfg_offset: CVMX_PCIERCX_CFG448(pcie_port)); |
656 | switch (pciercx_cfg032.s.nlw) { |
657 | case 1: /* 1 lane */ |
658 | pciercx_cfg448.s.rtl = 1677; |
659 | break; |
660 | case 2: /* 2 lanes */ |
661 | pciercx_cfg448.s.rtl = 867; |
662 | break; |
663 | case 4: /* 4 lanes */ |
664 | pciercx_cfg448.s.rtl = 462; |
665 | break; |
666 | case 8: /* 8 lanes */ |
667 | pciercx_cfg448.s.rtl = 258; |
668 | break; |
669 | } |
670 | cvmx_pcie_cfgx_write(pcie_port, cfg_offset: CVMX_PCIERCX_CFG448(pcie_port), val: pciercx_cfg448.u32); |
671 | |
672 | return 0; |
673 | } |
674 | |
675 | static void __cvmx_increment_ba(union cvmx_sli_mem_access_subidx *pmas) |
676 | { |
677 | if (OCTEON_IS_MODEL(OCTEON_CN68XX)) |
678 | pmas->cn68xx.ba++; |
679 | else |
680 | pmas->s.ba++; |
681 | } |
682 | |
683 | /** |
684 | * Initialize a PCIe gen 1 port for use in host(RC) mode. It doesn't |
685 | * enumerate the bus. |
686 | * |
687 | * @pcie_port: PCIe port to initialize |
688 | * |
689 | * Returns Zero on success |
690 | */ |
691 | static int __cvmx_pcie_rc_initialize_gen1(int pcie_port) |
692 | { |
693 | int i; |
694 | int base; |
695 | u64 addr_swizzle; |
696 | union cvmx_ciu_soft_prst ciu_soft_prst; |
697 | union cvmx_pescx_bist_status pescx_bist_status; |
698 | union cvmx_pescx_bist_status2 pescx_bist_status2; |
699 | union cvmx_npei_ctl_status npei_ctl_status; |
700 | union cvmx_npei_mem_access_ctl npei_mem_access_ctl; |
701 | union cvmx_npei_mem_access_subidx mem_access_subid; |
702 | union cvmx_npei_dbg_data npei_dbg_data; |
703 | union cvmx_pescx_ctl_status2 pescx_ctl_status2; |
704 | union cvmx_pciercx_cfg032 pciercx_cfg032; |
705 | union cvmx_npei_bar1_indexx bar1_index; |
706 | |
707 | retry: |
708 | /* |
709 | * Make sure we aren't trying to setup a target mode interface |
710 | * in host mode. |
711 | */ |
712 | npei_ctl_status.u64 = cvmx_read_csr(CVMX_PEXP_NPEI_CTL_STATUS); |
713 | if ((pcie_port == 0) && !npei_ctl_status.s.host_mode) { |
714 | cvmx_dprintf("PCIe: Port %d in endpoint mode\n" , pcie_port); |
715 | return -1; |
716 | } |
717 | |
718 | /* |
719 | * Make sure a CN52XX isn't trying to bring up port 1 when it |
720 | * is disabled. |
721 | */ |
722 | if (OCTEON_IS_MODEL(OCTEON_CN52XX)) { |
723 | npei_dbg_data.u64 = cvmx_read_csr(CVMX_PEXP_NPEI_DBG_DATA); |
724 | if ((pcie_port == 1) && npei_dbg_data.cn52xx.qlm0_link_width) { |
725 | cvmx_dprintf("PCIe: ERROR: cvmx_pcie_rc_initialize() called on port1, but port1 is disabled\n" ); |
726 | return -1; |
727 | } |
728 | } |
729 | |
730 | /* |
731 | * PCIe switch arbitration mode. '0' == fixed priority NPEI, |
732 | * PCIe0, then PCIe1. '1' == round robin. |
733 | */ |
734 | npei_ctl_status.s.arb = 1; |
735 | /* Allow up to 0x20 config retries */ |
736 | npei_ctl_status.s.cfg_rtry = 0x20; |
737 | /* |
738 | * CN52XX pass1.x has an errata where P0_NTAGS and P1_NTAGS |
739 | * don't reset. |
740 | */ |
741 | if (OCTEON_IS_MODEL(OCTEON_CN52XX_PASS1_X)) { |
742 | npei_ctl_status.s.p0_ntags = 0x20; |
743 | npei_ctl_status.s.p1_ntags = 0x20; |
744 | } |
745 | cvmx_write_csr(CVMX_PEXP_NPEI_CTL_STATUS, npei_ctl_status.u64); |
746 | |
747 | /* Bring the PCIe out of reset */ |
748 | if (cvmx_sysinfo_get()->board_type == CVMX_BOARD_TYPE_EBH5200) { |
749 | /* |
750 | * The EBH5200 board swapped the PCIe reset lines on |
751 | * the board. As a workaround for this bug, we bring |
752 | * both PCIe ports out of reset at the same time |
753 | * instead of on separate calls. So for port 0, we |
754 | * bring both out of reset and do nothing on port 1 |
755 | */ |
756 | if (pcie_port == 0) { |
757 | ciu_soft_prst.u64 = cvmx_read_csr(CVMX_CIU_SOFT_PRST); |
758 | /* |
759 | * After a chip reset the PCIe will also be in |
760 | * reset. If it isn't, most likely someone is |
761 | * trying to init it again without a proper |
762 | * PCIe reset. |
763 | */ |
764 | if (ciu_soft_prst.s.soft_prst == 0) { |
765 | /* Reset the ports */ |
766 | ciu_soft_prst.s.soft_prst = 1; |
767 | cvmx_write_csr(CVMX_CIU_SOFT_PRST, ciu_soft_prst.u64); |
768 | ciu_soft_prst.u64 = cvmx_read_csr(CVMX_CIU_SOFT_PRST1); |
769 | ciu_soft_prst.s.soft_prst = 1; |
770 | cvmx_write_csr(CVMX_CIU_SOFT_PRST1, ciu_soft_prst.u64); |
771 | /* Wait until pcie resets the ports. */ |
772 | udelay(2000); |
773 | } |
774 | ciu_soft_prst.u64 = cvmx_read_csr(CVMX_CIU_SOFT_PRST1); |
775 | ciu_soft_prst.s.soft_prst = 0; |
776 | cvmx_write_csr(CVMX_CIU_SOFT_PRST1, ciu_soft_prst.u64); |
777 | ciu_soft_prst.u64 = cvmx_read_csr(CVMX_CIU_SOFT_PRST); |
778 | ciu_soft_prst.s.soft_prst = 0; |
779 | cvmx_write_csr(CVMX_CIU_SOFT_PRST, ciu_soft_prst.u64); |
780 | } |
781 | } else { |
782 | /* |
783 | * The normal case: The PCIe ports are completely |
784 | * separate and can be brought out of reset |
785 | * independently. |
786 | */ |
787 | if (pcie_port) |
788 | ciu_soft_prst.u64 = cvmx_read_csr(CVMX_CIU_SOFT_PRST1); |
789 | else |
790 | ciu_soft_prst.u64 = cvmx_read_csr(CVMX_CIU_SOFT_PRST); |
791 | /* |
792 | * After a chip reset the PCIe will also be in |
793 | * reset. If it isn't, most likely someone is trying |
794 | * to init it again without a proper PCIe reset. |
795 | */ |
796 | if (ciu_soft_prst.s.soft_prst == 0) { |
797 | /* Reset the port */ |
798 | ciu_soft_prst.s.soft_prst = 1; |
799 | if (pcie_port) |
800 | cvmx_write_csr(CVMX_CIU_SOFT_PRST1, ciu_soft_prst.u64); |
801 | else |
802 | cvmx_write_csr(CVMX_CIU_SOFT_PRST, ciu_soft_prst.u64); |
803 | /* Wait until pcie resets the ports. */ |
804 | udelay(2000); |
805 | } |
806 | if (pcie_port) { |
807 | ciu_soft_prst.u64 = cvmx_read_csr(CVMX_CIU_SOFT_PRST1); |
808 | ciu_soft_prst.s.soft_prst = 0; |
809 | cvmx_write_csr(CVMX_CIU_SOFT_PRST1, ciu_soft_prst.u64); |
810 | } else { |
811 | ciu_soft_prst.u64 = cvmx_read_csr(CVMX_CIU_SOFT_PRST); |
812 | ciu_soft_prst.s.soft_prst = 0; |
813 | cvmx_write_csr(CVMX_CIU_SOFT_PRST, ciu_soft_prst.u64); |
814 | } |
815 | } |
816 | |
817 | /* |
818 | * Wait for PCIe reset to complete. Due to errata PCIE-700, we |
819 | * don't poll PESCX_CTL_STATUS2[PCIERST], but simply wait a |
820 | * fixed number of cycles. |
821 | */ |
822 | __delay(loops: 400000); |
823 | |
824 | /* |
825 | * PESCX_BIST_STATUS2[PCLK_RUN] was missing on pass 1 of |
826 | * CN56XX and CN52XX, so we only probe it on newer chips |
827 | */ |
828 | if (!OCTEON_IS_MODEL(OCTEON_CN56XX_PASS1_X) && !OCTEON_IS_MODEL(OCTEON_CN52XX_PASS1_X)) { |
829 | /* Clear PCLK_RUN so we can check if the clock is running */ |
830 | pescx_ctl_status2.u64 = cvmx_read_csr(CVMX_PESCX_CTL_STATUS2(pcie_port)); |
831 | pescx_ctl_status2.s.pclk_run = 1; |
832 | cvmx_write_csr(CVMX_PESCX_CTL_STATUS2(pcie_port), pescx_ctl_status2.u64); |
833 | /* Now that we cleared PCLK_RUN, wait for it to be set |
834 | * again telling us the clock is running |
835 | */ |
836 | if (CVMX_WAIT_FOR_FIELD64(CVMX_PESCX_CTL_STATUS2(pcie_port), |
837 | union cvmx_pescx_ctl_status2, pclk_run, ==, 1, 10000)) { |
838 | cvmx_dprintf("PCIe: Port %d isn't clocked, skipping.\n" , pcie_port); |
839 | return -1; |
840 | } |
841 | } |
842 | |
843 | /* |
844 | * Check and make sure PCIe came out of reset. If it doesn't |
845 | * the board probably hasn't wired the clocks up and the |
846 | * interface should be skipped. |
847 | */ |
848 | pescx_ctl_status2.u64 = cvmx_read_csr(CVMX_PESCX_CTL_STATUS2(pcie_port)); |
849 | if (pescx_ctl_status2.s.pcierst) { |
850 | cvmx_dprintf("PCIe: Port %d stuck in reset, skipping.\n" , pcie_port); |
851 | return -1; |
852 | } |
853 | |
854 | /* |
855 | * Check BIST2 status. If any bits are set skip this |
856 | * interface. This is an attempt to catch PCIE-813 on pass 1 |
857 | * parts. |
858 | */ |
859 | pescx_bist_status2.u64 = cvmx_read_csr(CVMX_PESCX_BIST_STATUS2(pcie_port)); |
860 | if (pescx_bist_status2.u64) { |
861 | cvmx_dprintf("PCIe: Port %d BIST2 failed. Most likely this port isn't hooked up, skipping.\n" , |
862 | pcie_port); |
863 | return -1; |
864 | } |
865 | |
866 | /* Check BIST status */ |
867 | pescx_bist_status.u64 = cvmx_read_csr(CVMX_PESCX_BIST_STATUS(pcie_port)); |
868 | if (pescx_bist_status.u64) |
869 | cvmx_dprintf("PCIe: BIST FAILED for port %d (0x%016llx)\n" , |
870 | pcie_port, CAST64(pescx_bist_status.u64)); |
871 | |
872 | /* Initialize the config space CSRs */ |
873 | __cvmx_pcie_rc_initialize_config_space(pcie_port); |
874 | |
875 | /* Bring the link up */ |
876 | if (__cvmx_pcie_rc_initialize_link_gen1(pcie_port)) { |
877 | cvmx_dprintf("PCIe: Failed to initialize port %d, probably the slot is empty\n" , |
878 | pcie_port); |
879 | return -1; |
880 | } |
881 | |
882 | /* Store merge control (NPEI_MEM_ACCESS_CTL[TIMER,MAX_WORD]) */ |
883 | npei_mem_access_ctl.u64 = cvmx_read_csr(CVMX_PEXP_NPEI_MEM_ACCESS_CTL); |
884 | npei_mem_access_ctl.s.max_word = 0; /* Allow 16 words to combine */ |
885 | npei_mem_access_ctl.s.timer = 127; /* Wait up to 127 cycles for more data */ |
886 | cvmx_write_csr(CVMX_PEXP_NPEI_MEM_ACCESS_CTL, npei_mem_access_ctl.u64); |
887 | |
888 | /* Setup Mem access SubDIDs */ |
889 | mem_access_subid.u64 = 0; |
890 | mem_access_subid.s.port = pcie_port; /* Port the request is sent to. */ |
891 | mem_access_subid.s.nmerge = 1; /* Due to an errata on pass 1 chips, no merging is allowed. */ |
892 | mem_access_subid.s.esr = 1; /* Endian-swap for Reads. */ |
893 | mem_access_subid.s.esw = 1; /* Endian-swap for Writes. */ |
894 | mem_access_subid.s.nsr = 0; /* Enable Snooping for Reads. Octeon doesn't care, but devices might want this more conservative setting */ |
895 | mem_access_subid.s.nsw = 0; /* Enable Snoop for Writes. */ |
896 | mem_access_subid.s.ror = 0; /* Disable Relaxed Ordering for Reads. */ |
897 | mem_access_subid.s.row = 0; /* Disable Relaxed Ordering for Writes. */ |
898 | mem_access_subid.s.ba = 0; /* PCIe Address Bits <63:34>. */ |
899 | |
900 | /* |
901 | * Setup mem access 12-15 for port 0, 16-19 for port 1, |
902 | * supplying 36 bits of address space. |
903 | */ |
904 | for (i = 12 + pcie_port * 4; i < 16 + pcie_port * 4; i++) { |
905 | cvmx_write_csr(CVMX_PEXP_NPEI_MEM_ACCESS_SUBIDX(i), mem_access_subid.u64); |
906 | mem_access_subid.s.ba += 1; /* Set each SUBID to extend the addressable range */ |
907 | } |
908 | |
909 | /* |
910 | * Disable the peer to peer forwarding register. This must be |
911 | * setup by the OS after it enumerates the bus and assigns |
912 | * addresses to the PCIe busses. |
913 | */ |
914 | for (i = 0; i < 4; i++) { |
915 | cvmx_write_csr(CVMX_PESCX_P2P_BARX_START(i, pcie_port), -1); |
916 | cvmx_write_csr(CVMX_PESCX_P2P_BARX_END(i, pcie_port), -1); |
917 | } |
918 | |
919 | /* Set Octeon's BAR0 to decode 0-16KB. It overlaps with Bar2 */ |
920 | cvmx_write_csr(CVMX_PESCX_P2N_BAR0_START(pcie_port), 0); |
921 | |
922 | /* BAR1 follows BAR2 with a gap so it has the same address as for gen2. */ |
923 | cvmx_write_csr(CVMX_PESCX_P2N_BAR1_START(pcie_port), CVMX_PCIE_BAR1_RC_BASE); |
924 | |
925 | bar1_index.u32 = 0; |
926 | bar1_index.s.addr_idx = (CVMX_PCIE_BAR1_PHYS_BASE >> 22); |
927 | bar1_index.s.ca = 1; /* Not Cached */ |
928 | bar1_index.s.end_swp = 1; /* Endian Swap mode */ |
929 | bar1_index.s.addr_v = 1; /* Valid entry */ |
930 | |
931 | base = pcie_port ? 16 : 0; |
932 | |
933 | /* Big endian swizzle for 32-bit PEXP_NCB register. */ |
934 | #ifdef __MIPSEB__ |
935 | addr_swizzle = 4; |
936 | #else |
937 | addr_swizzle = 0; |
938 | #endif |
939 | for (i = 0; i < 16; i++) { |
940 | cvmx_write64_uint32((CVMX_PEXP_NPEI_BAR1_INDEXX(base) ^ addr_swizzle), |
941 | bar1_index.u32); |
942 | base++; |
943 | /* 256MB / 16 >> 22 == 4 */ |
944 | bar1_index.s.addr_idx += (((1ull << 28) / 16ull) >> 22); |
945 | } |
946 | |
947 | /* |
948 | * Set Octeon's BAR2 to decode 0-2^39. Bar0 and Bar1 take |
949 | * precedence where they overlap. It also overlaps with the |
950 | * device addresses, so make sure the peer to peer forwarding |
951 | * is set right. |
952 | */ |
953 | cvmx_write_csr(CVMX_PESCX_P2N_BAR2_START(pcie_port), 0); |
954 | |
955 | /* |
956 | * Setup BAR2 attributes |
957 | * |
958 | * Relaxed Ordering (NPEI_CTL_PORTn[PTLP_RO,CTLP_RO, WAIT_COM]) |
959 | * - PTLP_RO,CTLP_RO should normally be set (except for debug). |
960 | * - WAIT_COM=0 will likely work for all applications. |
961 | * |
962 | * Load completion relaxed ordering (NPEI_CTL_PORTn[WAITL_COM]). |
963 | */ |
964 | if (pcie_port) { |
965 | union cvmx_npei_ctl_port1 npei_ctl_port; |
966 | npei_ctl_port.u64 = cvmx_read_csr(CVMX_PEXP_NPEI_CTL_PORT1); |
967 | npei_ctl_port.s.bar2_enb = 1; |
968 | npei_ctl_port.s.bar2_esx = 1; |
969 | npei_ctl_port.s.bar2_cax = 0; |
970 | npei_ctl_port.s.ptlp_ro = 1; |
971 | npei_ctl_port.s.ctlp_ro = 1; |
972 | npei_ctl_port.s.wait_com = 0; |
973 | npei_ctl_port.s.waitl_com = 0; |
974 | cvmx_write_csr(CVMX_PEXP_NPEI_CTL_PORT1, npei_ctl_port.u64); |
975 | } else { |
976 | union cvmx_npei_ctl_port0 npei_ctl_port; |
977 | npei_ctl_port.u64 = cvmx_read_csr(CVMX_PEXP_NPEI_CTL_PORT0); |
978 | npei_ctl_port.s.bar2_enb = 1; |
979 | npei_ctl_port.s.bar2_esx = 1; |
980 | npei_ctl_port.s.bar2_cax = 0; |
981 | npei_ctl_port.s.ptlp_ro = 1; |
982 | npei_ctl_port.s.ctlp_ro = 1; |
983 | npei_ctl_port.s.wait_com = 0; |
984 | npei_ctl_port.s.waitl_com = 0; |
985 | cvmx_write_csr(CVMX_PEXP_NPEI_CTL_PORT0, npei_ctl_port.u64); |
986 | } |
987 | |
988 | /* |
989 | * Both pass 1 and pass 2 of CN52XX and CN56XX have an errata |
990 | * that causes TLP ordering to not be preserved after multiple |
991 | * PCIe port resets. This code detects this fault and corrects |
992 | * it by aligning the TLP counters properly. Another link |
993 | * reset is then performed. See PCIE-13340 |
994 | */ |
995 | if (OCTEON_IS_MODEL(OCTEON_CN56XX_PASS2_X) || |
996 | OCTEON_IS_MODEL(OCTEON_CN52XX_PASS2_X) || |
997 | OCTEON_IS_MODEL(OCTEON_CN56XX_PASS1_X) || |
998 | OCTEON_IS_MODEL(OCTEON_CN52XX_PASS1_X)) { |
999 | union cvmx_npei_dbg_data dbg_data; |
1000 | int old_in_fif_p_count; |
1001 | int in_fif_p_count; |
1002 | int out_p_count; |
1003 | int in_p_offset = (OCTEON_IS_MODEL(OCTEON_CN52XX_PASS1_X) || OCTEON_IS_MODEL(OCTEON_CN56XX_PASS1_X)) ? 4 : 1; |
1004 | int i; |
1005 | |
1006 | /* |
1007 | * Choose a write address of 1MB. It should be |
1008 | * harmless as all bars haven't been setup. |
1009 | */ |
1010 | uint64_t write_address = (cvmx_pcie_get_mem_base_address(pcie_port) + 0x100000) | (1ull<<63); |
1011 | |
1012 | /* |
1013 | * Make sure at least in_p_offset have been executed before we try and |
1014 | * read in_fif_p_count |
1015 | */ |
1016 | i = in_p_offset; |
1017 | while (i--) { |
1018 | cvmx_write64_uint32(write_address, 0); |
1019 | __delay(loops: 10000); |
1020 | } |
1021 | |
1022 | /* |
1023 | * Read the IN_FIF_P_COUNT from the debug |
1024 | * select. IN_FIF_P_COUNT can be unstable sometimes so |
1025 | * read it twice with a write between the reads. This |
1026 | * way we can tell the value is good as it will |
1027 | * increment by one due to the write |
1028 | */ |
1029 | cvmx_write_csr(CVMX_PEXP_NPEI_DBG_SELECT, (pcie_port) ? 0xd7fc : 0xcffc); |
1030 | cvmx_read_csr(CVMX_PEXP_NPEI_DBG_SELECT); |
1031 | do { |
1032 | dbg_data.u64 = cvmx_read_csr(CVMX_PEXP_NPEI_DBG_DATA); |
1033 | old_in_fif_p_count = dbg_data.s.data & 0xff; |
1034 | cvmx_write64_uint32(write_address, 0); |
1035 | __delay(loops: 10000); |
1036 | dbg_data.u64 = cvmx_read_csr(CVMX_PEXP_NPEI_DBG_DATA); |
1037 | in_fif_p_count = dbg_data.s.data & 0xff; |
1038 | } while (in_fif_p_count != ((old_in_fif_p_count+1) & 0xff)); |
1039 | |
1040 | /* Update in_fif_p_count for its offset with respect to out_p_count */ |
1041 | in_fif_p_count = (in_fif_p_count + in_p_offset) & 0xff; |
1042 | |
1043 | /* Read the OUT_P_COUNT from the debug select */ |
1044 | cvmx_write_csr(CVMX_PEXP_NPEI_DBG_SELECT, (pcie_port) ? 0xd00f : 0xc80f); |
1045 | cvmx_read_csr(CVMX_PEXP_NPEI_DBG_SELECT); |
1046 | dbg_data.u64 = cvmx_read_csr(CVMX_PEXP_NPEI_DBG_DATA); |
1047 | out_p_count = (dbg_data.s.data>>1) & 0xff; |
1048 | |
1049 | /* Check that the two counters are aligned */ |
1050 | if (out_p_count != in_fif_p_count) { |
1051 | cvmx_dprintf("PCIe: Port %d aligning TLP counters as workaround to maintain ordering\n" , pcie_port); |
1052 | while (in_fif_p_count != 0) { |
1053 | cvmx_write64_uint32(write_address, 0); |
1054 | __delay(loops: 10000); |
1055 | in_fif_p_count = (in_fif_p_count + 1) & 0xff; |
1056 | } |
1057 | /* |
1058 | * The EBH5200 board swapped the PCIe reset |
1059 | * lines on the board. This means we must |
1060 | * bring both links down and up, which will |
1061 | * cause the PCIe0 to need alignment |
1062 | * again. Lots of messages will be displayed, |
1063 | * but everything should work |
1064 | */ |
1065 | if ((cvmx_sysinfo_get()->board_type == CVMX_BOARD_TYPE_EBH5200) && |
1066 | (pcie_port == 1)) |
1067 | cvmx_pcie_rc_initialize(pcie_port: 0); |
1068 | /* Rety bringing this port up */ |
1069 | goto retry; |
1070 | } |
1071 | } |
1072 | |
1073 | /* Display the link status */ |
1074 | pciercx_cfg032.u32 = cvmx_pcie_cfgx_read(pcie_port, cfg_offset: CVMX_PCIERCX_CFG032(pcie_port)); |
1075 | cvmx_dprintf("PCIe: Port %d link active, %d lanes\n" , pcie_port, pciercx_cfg032.s.nlw); |
1076 | |
1077 | return 0; |
1078 | } |
1079 | |
1080 | /** |
1081 | * Initialize a host mode PCIe gen 2 link. This function takes a PCIe |
1082 | * port from reset to a link up state. Software can then begin |
1083 | * configuring the rest of the link. |
1084 | * |
1085 | * @pcie_port: PCIe port to initialize |
1086 | * |
1087 | * Return Zero on success. |
1088 | */ |
1089 | static int __cvmx_pcie_rc_initialize_link_gen2(int pcie_port) |
1090 | { |
1091 | uint64_t start_cycle; |
1092 | union cvmx_pemx_ctl_status pem_ctl_status; |
1093 | union cvmx_pciercx_cfg032 pciercx_cfg032; |
1094 | union cvmx_pciercx_cfg448 pciercx_cfg448; |
1095 | |
1096 | /* Bring up the link */ |
1097 | pem_ctl_status.u64 = cvmx_read_csr(CVMX_PEMX_CTL_STATUS(pcie_port)); |
1098 | pem_ctl_status.s.lnk_enb = 1; |
1099 | cvmx_write_csr(CVMX_PEMX_CTL_STATUS(pcie_port), pem_ctl_status.u64); |
1100 | |
1101 | /* Wait for the link to come up */ |
1102 | start_cycle = cvmx_get_cycle(); |
1103 | do { |
1104 | if (cvmx_get_cycle() - start_cycle > octeon_get_clock_rate()) |
1105 | return -1; |
1106 | __delay(loops: 10000); |
1107 | pciercx_cfg032.u32 = cvmx_pcie_cfgx_read(pcie_port, cfg_offset: CVMX_PCIERCX_CFG032(pcie_port)); |
1108 | } while ((pciercx_cfg032.s.dlla == 0) || (pciercx_cfg032.s.lt == 1)); |
1109 | |
1110 | /* |
1111 | * Update the Replay Time Limit. Empirically, some PCIe |
1112 | * devices take a little longer to respond than expected under |
1113 | * load. As a workaround for this we configure the Replay Time |
1114 | * Limit to the value expected for a 512 byte MPS instead of |
1115 | * our actual 256 byte MPS. The numbers below are directly |
1116 | * from the PCIe spec table 3-4 |
1117 | */ |
1118 | pciercx_cfg448.u32 = cvmx_pcie_cfgx_read(pcie_port, cfg_offset: CVMX_PCIERCX_CFG448(pcie_port)); |
1119 | switch (pciercx_cfg032.s.nlw) { |
1120 | case 1: /* 1 lane */ |
1121 | pciercx_cfg448.s.rtl = 1677; |
1122 | break; |
1123 | case 2: /* 2 lanes */ |
1124 | pciercx_cfg448.s.rtl = 867; |
1125 | break; |
1126 | case 4: /* 4 lanes */ |
1127 | pciercx_cfg448.s.rtl = 462; |
1128 | break; |
1129 | case 8: /* 8 lanes */ |
1130 | pciercx_cfg448.s.rtl = 258; |
1131 | break; |
1132 | } |
1133 | cvmx_pcie_cfgx_write(pcie_port, cfg_offset: CVMX_PCIERCX_CFG448(pcie_port), val: pciercx_cfg448.u32); |
1134 | |
1135 | return 0; |
1136 | } |
1137 | |
1138 | |
1139 | /** |
1140 | * Initialize a PCIe gen 2 port for use in host(RC) mode. It doesn't enumerate |
1141 | * the bus. |
1142 | * |
1143 | * @pcie_port: PCIe port to initialize |
1144 | * |
1145 | * Returns Zero on success. |
1146 | */ |
1147 | static int __cvmx_pcie_rc_initialize_gen2(int pcie_port) |
1148 | { |
1149 | int i; |
1150 | union cvmx_ciu_soft_prst ciu_soft_prst; |
1151 | union cvmx_mio_rst_ctlx mio_rst_ctl; |
1152 | union cvmx_pemx_bar_ctl pemx_bar_ctl; |
1153 | union cvmx_pemx_ctl_status pemx_ctl_status; |
1154 | union cvmx_pemx_bist_status pemx_bist_status; |
1155 | union cvmx_pemx_bist_status2 pemx_bist_status2; |
1156 | union cvmx_pciercx_cfg032 pciercx_cfg032; |
1157 | union cvmx_pciercx_cfg515 pciercx_cfg515; |
1158 | union cvmx_sli_ctl_portx sli_ctl_portx; |
1159 | union cvmx_sli_mem_access_ctl sli_mem_access_ctl; |
1160 | union cvmx_sli_mem_access_subidx mem_access_subid; |
1161 | union cvmx_sriox_status_reg sriox_status_reg; |
1162 | union cvmx_pemx_bar1_indexx bar1_index; |
1163 | |
1164 | if (octeon_has_feature(OCTEON_FEATURE_SRIO)) { |
1165 | /* Make sure this interface isn't SRIO */ |
1166 | if (OCTEON_IS_MODEL(OCTEON_CN66XX)) { |
1167 | /* |
1168 | * The CN66XX requires reading the |
1169 | * MIO_QLMX_CFG register to figure out the |
1170 | * port type. |
1171 | */ |
1172 | union cvmx_mio_qlmx_cfg qlmx_cfg; |
1173 | qlmx_cfg.u64 = cvmx_read_csr(CVMX_MIO_QLMX_CFG(pcie_port)); |
1174 | |
1175 | if (qlmx_cfg.s.qlm_spd == 15) { |
1176 | pr_notice("PCIe: Port %d is disabled, skipping.\n" , pcie_port); |
1177 | return -1; |
1178 | } |
1179 | |
1180 | switch (qlmx_cfg.s.qlm_spd) { |
1181 | case 0x1: /* SRIO 1x4 short */ |
1182 | case 0x3: /* SRIO 1x4 long */ |
1183 | case 0x4: /* SRIO 2x2 short */ |
1184 | case 0x6: /* SRIO 2x2 long */ |
1185 | pr_notice("PCIe: Port %d is SRIO, skipping.\n" , pcie_port); |
1186 | return -1; |
1187 | case 0x9: /* SGMII */ |
1188 | pr_notice("PCIe: Port %d is SGMII, skipping.\n" , pcie_port); |
1189 | return -1; |
1190 | case 0xb: /* XAUI */ |
1191 | pr_notice("PCIe: Port %d is XAUI, skipping.\n" , pcie_port); |
1192 | return -1; |
1193 | case 0x0: /* PCIE gen2 */ |
1194 | case 0x8: /* PCIE gen2 (alias) */ |
1195 | case 0x2: /* PCIE gen1 */ |
1196 | case 0xa: /* PCIE gen1 (alias) */ |
1197 | break; |
1198 | default: |
1199 | pr_notice("PCIe: Port %d is unknown, skipping.\n" , pcie_port); |
1200 | return -1; |
1201 | } |
1202 | } else { |
1203 | sriox_status_reg.u64 = cvmx_read_csr(CVMX_SRIOX_STATUS_REG(pcie_port)); |
1204 | if (sriox_status_reg.s.srio) { |
1205 | pr_notice("PCIe: Port %d is SRIO, skipping.\n" , pcie_port); |
1206 | return -1; |
1207 | } |
1208 | } |
1209 | } |
1210 | |
1211 | #if 0 |
1212 | /* This code is so that the PCIe analyzer is able to see 63XX traffic */ |
1213 | pr_notice("PCIE : init for pcie analyzer.\n" ); |
1214 | cvmx_helper_qlm_jtag_init(); |
1215 | cvmx_helper_qlm_jtag_shift_zeros(pcie_port, 85); |
1216 | cvmx_helper_qlm_jtag_shift(pcie_port, 1, 1); |
1217 | cvmx_helper_qlm_jtag_shift_zeros(pcie_port, 300-86); |
1218 | cvmx_helper_qlm_jtag_shift_zeros(pcie_port, 85); |
1219 | cvmx_helper_qlm_jtag_shift(pcie_port, 1, 1); |
1220 | cvmx_helper_qlm_jtag_shift_zeros(pcie_port, 300-86); |
1221 | cvmx_helper_qlm_jtag_shift_zeros(pcie_port, 85); |
1222 | cvmx_helper_qlm_jtag_shift(pcie_port, 1, 1); |
1223 | cvmx_helper_qlm_jtag_shift_zeros(pcie_port, 300-86); |
1224 | cvmx_helper_qlm_jtag_shift_zeros(pcie_port, 85); |
1225 | cvmx_helper_qlm_jtag_shift(pcie_port, 1, 1); |
1226 | cvmx_helper_qlm_jtag_shift_zeros(pcie_port, 300-86); |
1227 | cvmx_helper_qlm_jtag_update(pcie_port); |
1228 | #endif |
1229 | |
1230 | /* Make sure we aren't trying to setup a target mode interface in host mode */ |
1231 | mio_rst_ctl.u64 = cvmx_read_csr(CVMX_MIO_RST_CTLX(pcie_port)); |
1232 | if (!mio_rst_ctl.s.host_mode) { |
1233 | pr_notice("PCIe: Port %d in endpoint mode.\n" , pcie_port); |
1234 | return -1; |
1235 | } |
1236 | |
1237 | /* CN63XX Pass 1.0 errata G-14395 requires the QLM De-emphasis be programmed */ |
1238 | if (OCTEON_IS_MODEL(OCTEON_CN63XX_PASS1_0)) { |
1239 | if (pcie_port) { |
1240 | union cvmx_ciu_qlm ciu_qlm; |
1241 | ciu_qlm.u64 = cvmx_read_csr(CVMX_CIU_QLM1); |
1242 | ciu_qlm.s.txbypass = 1; |
1243 | ciu_qlm.s.txdeemph = 5; |
1244 | ciu_qlm.s.txmargin = 0x17; |
1245 | cvmx_write_csr(CVMX_CIU_QLM1, ciu_qlm.u64); |
1246 | } else { |
1247 | union cvmx_ciu_qlm ciu_qlm; |
1248 | ciu_qlm.u64 = cvmx_read_csr(CVMX_CIU_QLM0); |
1249 | ciu_qlm.s.txbypass = 1; |
1250 | ciu_qlm.s.txdeemph = 5; |
1251 | ciu_qlm.s.txmargin = 0x17; |
1252 | cvmx_write_csr(CVMX_CIU_QLM0, ciu_qlm.u64); |
1253 | } |
1254 | } |
1255 | /* Bring the PCIe out of reset */ |
1256 | if (pcie_port) |
1257 | ciu_soft_prst.u64 = cvmx_read_csr(CVMX_CIU_SOFT_PRST1); |
1258 | else |
1259 | ciu_soft_prst.u64 = cvmx_read_csr(CVMX_CIU_SOFT_PRST); |
1260 | /* |
1261 | * After a chip reset the PCIe will also be in reset. If it |
1262 | * isn't, most likely someone is trying to init it again |
1263 | * without a proper PCIe reset |
1264 | */ |
1265 | if (ciu_soft_prst.s.soft_prst == 0) { |
1266 | /* Reset the port */ |
1267 | ciu_soft_prst.s.soft_prst = 1; |
1268 | if (pcie_port) |
1269 | cvmx_write_csr(CVMX_CIU_SOFT_PRST1, ciu_soft_prst.u64); |
1270 | else |
1271 | cvmx_write_csr(CVMX_CIU_SOFT_PRST, ciu_soft_prst.u64); |
1272 | /* Wait until pcie resets the ports. */ |
1273 | udelay(2000); |
1274 | } |
1275 | if (pcie_port) { |
1276 | ciu_soft_prst.u64 = cvmx_read_csr(CVMX_CIU_SOFT_PRST1); |
1277 | ciu_soft_prst.s.soft_prst = 0; |
1278 | cvmx_write_csr(CVMX_CIU_SOFT_PRST1, ciu_soft_prst.u64); |
1279 | } else { |
1280 | ciu_soft_prst.u64 = cvmx_read_csr(CVMX_CIU_SOFT_PRST); |
1281 | ciu_soft_prst.s.soft_prst = 0; |
1282 | cvmx_write_csr(CVMX_CIU_SOFT_PRST, ciu_soft_prst.u64); |
1283 | } |
1284 | |
1285 | /* Wait for PCIe reset to complete */ |
1286 | udelay(1000); |
1287 | |
1288 | /* |
1289 | * Check and make sure PCIe came out of reset. If it doesn't |
1290 | * the board probably hasn't wired the clocks up and the |
1291 | * interface should be skipped. |
1292 | */ |
1293 | if (CVMX_WAIT_FOR_FIELD64(CVMX_MIO_RST_CTLX(pcie_port), union cvmx_mio_rst_ctlx, rst_done, ==, 1, 10000)) { |
1294 | pr_notice("PCIe: Port %d stuck in reset, skipping.\n" , pcie_port); |
1295 | return -1; |
1296 | } |
1297 | |
1298 | /* Check BIST status */ |
1299 | pemx_bist_status.u64 = cvmx_read_csr(CVMX_PEMX_BIST_STATUS(pcie_port)); |
1300 | if (pemx_bist_status.u64) |
1301 | pr_notice("PCIe: BIST FAILED for port %d (0x%016llx)\n" , pcie_port, CAST64(pemx_bist_status.u64)); |
1302 | pemx_bist_status2.u64 = cvmx_read_csr(CVMX_PEMX_BIST_STATUS2(pcie_port)); |
1303 | /* Errata PCIE-14766 may cause the lower 6 bits to be randomly set on CN63XXp1 */ |
1304 | if (OCTEON_IS_MODEL(OCTEON_CN63XX_PASS1_X)) |
1305 | pemx_bist_status2.u64 &= ~0x3full; |
1306 | if (pemx_bist_status2.u64) |
1307 | pr_notice("PCIe: BIST2 FAILED for port %d (0x%016llx)\n" , pcie_port, CAST64(pemx_bist_status2.u64)); |
1308 | |
1309 | /* Initialize the config space CSRs */ |
1310 | __cvmx_pcie_rc_initialize_config_space(pcie_port); |
1311 | |
1312 | /* Enable gen2 speed selection */ |
1313 | pciercx_cfg515.u32 = cvmx_pcie_cfgx_read(pcie_port, cfg_offset: CVMX_PCIERCX_CFG515(pcie_port)); |
1314 | pciercx_cfg515.s.dsc = 1; |
1315 | cvmx_pcie_cfgx_write(pcie_port, cfg_offset: CVMX_PCIERCX_CFG515(pcie_port), val: pciercx_cfg515.u32); |
1316 | |
1317 | /* Bring the link up */ |
1318 | if (__cvmx_pcie_rc_initialize_link_gen2(pcie_port)) { |
1319 | /* |
1320 | * Some gen1 devices don't handle the gen 2 training |
1321 | * correctly. Disable gen2 and try again with only |
1322 | * gen1 |
1323 | */ |
1324 | union cvmx_pciercx_cfg031 pciercx_cfg031; |
1325 | pciercx_cfg031.u32 = cvmx_pcie_cfgx_read(pcie_port, cfg_offset: CVMX_PCIERCX_CFG031(pcie_port)); |
1326 | pciercx_cfg031.s.mls = 1; |
1327 | cvmx_pcie_cfgx_write(pcie_port, cfg_offset: CVMX_PCIERCX_CFG031(pcie_port), val: pciercx_cfg031.u32); |
1328 | if (__cvmx_pcie_rc_initialize_link_gen2(pcie_port)) { |
1329 | pr_notice("PCIe: Link timeout on port %d, probably the slot is empty\n" , pcie_port); |
1330 | return -1; |
1331 | } |
1332 | } |
1333 | |
1334 | /* Store merge control (SLI_MEM_ACCESS_CTL[TIMER,MAX_WORD]) */ |
1335 | sli_mem_access_ctl.u64 = cvmx_read_csr(CVMX_PEXP_SLI_MEM_ACCESS_CTL); |
1336 | sli_mem_access_ctl.s.max_word = 0; /* Allow 16 words to combine */ |
1337 | sli_mem_access_ctl.s.timer = 127; /* Wait up to 127 cycles for more data */ |
1338 | cvmx_write_csr(CVMX_PEXP_SLI_MEM_ACCESS_CTL, sli_mem_access_ctl.u64); |
1339 | |
1340 | /* Setup Mem access SubDIDs */ |
1341 | mem_access_subid.u64 = 0; |
1342 | mem_access_subid.s.port = pcie_port; /* Port the request is sent to. */ |
1343 | mem_access_subid.s.nmerge = 0; /* Allow merging as it works on CN6XXX. */ |
1344 | mem_access_subid.s.esr = 1; /* Endian-swap for Reads. */ |
1345 | mem_access_subid.s.esw = 1; /* Endian-swap for Writes. */ |
1346 | mem_access_subid.s.wtype = 0; /* "No snoop" and "Relaxed ordering" are not set */ |
1347 | mem_access_subid.s.rtype = 0; /* "No snoop" and "Relaxed ordering" are not set */ |
1348 | /* PCIe Address Bits <63:34>. */ |
1349 | if (OCTEON_IS_MODEL(OCTEON_CN68XX)) |
1350 | mem_access_subid.cn68xx.ba = 0; |
1351 | else |
1352 | mem_access_subid.s.ba = 0; |
1353 | |
1354 | /* |
1355 | * Setup mem access 12-15 for port 0, 16-19 for port 1, |
1356 | * supplying 36 bits of address space. |
1357 | */ |
1358 | for (i = 12 + pcie_port * 4; i < 16 + pcie_port * 4; i++) { |
1359 | cvmx_write_csr(CVMX_PEXP_SLI_MEM_ACCESS_SUBIDX(i), mem_access_subid.u64); |
1360 | /* Set each SUBID to extend the addressable range */ |
1361 | __cvmx_increment_ba(pmas: &mem_access_subid); |
1362 | } |
1363 | |
1364 | /* |
1365 | * Disable the peer to peer forwarding register. This must be |
1366 | * setup by the OS after it enumerates the bus and assigns |
1367 | * addresses to the PCIe busses. |
1368 | */ |
1369 | for (i = 0; i < 4; i++) { |
1370 | cvmx_write_csr(CVMX_PEMX_P2P_BARX_START(i, pcie_port), -1); |
1371 | cvmx_write_csr(CVMX_PEMX_P2P_BARX_END(i, pcie_port), -1); |
1372 | } |
1373 | |
1374 | /* Set Octeon's BAR0 to decode 0-16KB. It overlaps with Bar2 */ |
1375 | cvmx_write_csr(CVMX_PEMX_P2N_BAR0_START(pcie_port), 0); |
1376 | |
1377 | /* |
1378 | * Set Octeon's BAR2 to decode 0-2^41. Bar0 and Bar1 take |
1379 | * precedence where they overlap. It also overlaps with the |
1380 | * device addresses, so make sure the peer to peer forwarding |
1381 | * is set right. |
1382 | */ |
1383 | cvmx_write_csr(CVMX_PEMX_P2N_BAR2_START(pcie_port), 0); |
1384 | |
1385 | /* |
1386 | * Setup BAR2 attributes |
1387 | * Relaxed Ordering (NPEI_CTL_PORTn[PTLP_RO,CTLP_RO, WAIT_COM]) |
1388 | * - PTLP_RO,CTLP_RO should normally be set (except for debug). |
1389 | * - WAIT_COM=0 will likely work for all applications. |
1390 | * Load completion relaxed ordering (NPEI_CTL_PORTn[WAITL_COM]) |
1391 | */ |
1392 | pemx_bar_ctl.u64 = cvmx_read_csr(CVMX_PEMX_BAR_CTL(pcie_port)); |
1393 | pemx_bar_ctl.s.bar1_siz = 3; /* 256MB BAR1*/ |
1394 | pemx_bar_ctl.s.bar2_enb = 1; |
1395 | pemx_bar_ctl.s.bar2_esx = 1; |
1396 | pemx_bar_ctl.s.bar2_cax = 0; |
1397 | cvmx_write_csr(CVMX_PEMX_BAR_CTL(pcie_port), pemx_bar_ctl.u64); |
1398 | sli_ctl_portx.u64 = cvmx_read_csr(CVMX_PEXP_SLI_CTL_PORTX(pcie_port)); |
1399 | sli_ctl_portx.s.ptlp_ro = 1; |
1400 | sli_ctl_portx.s.ctlp_ro = 1; |
1401 | sli_ctl_portx.s.wait_com = 0; |
1402 | sli_ctl_portx.s.waitl_com = 0; |
1403 | cvmx_write_csr(CVMX_PEXP_SLI_CTL_PORTX(pcie_port), sli_ctl_portx.u64); |
1404 | |
1405 | /* BAR1 follows BAR2 */ |
1406 | cvmx_write_csr(CVMX_PEMX_P2N_BAR1_START(pcie_port), CVMX_PCIE_BAR1_RC_BASE); |
1407 | |
1408 | bar1_index.u64 = 0; |
1409 | bar1_index.s.addr_idx = (CVMX_PCIE_BAR1_PHYS_BASE >> 22); |
1410 | bar1_index.s.ca = 1; /* Not Cached */ |
1411 | bar1_index.s.end_swp = 1; /* Endian Swap mode */ |
1412 | bar1_index.s.addr_v = 1; /* Valid entry */ |
1413 | |
1414 | for (i = 0; i < 16; i++) { |
1415 | cvmx_write_csr(CVMX_PEMX_BAR1_INDEXX(i, pcie_port), bar1_index.u64); |
1416 | /* 256MB / 16 >> 22 == 4 */ |
1417 | bar1_index.s.addr_idx += (((1ull << 28) / 16ull) >> 22); |
1418 | } |
1419 | |
1420 | /* |
1421 | * Allow config retries for 250ms. Count is based off the 5Ghz |
1422 | * SERDES clock. |
1423 | */ |
1424 | pemx_ctl_status.u64 = cvmx_read_csr(CVMX_PEMX_CTL_STATUS(pcie_port)); |
1425 | pemx_ctl_status.s.cfg_rtry = 250 * 5000000 / 0x10000; |
1426 | cvmx_write_csr(CVMX_PEMX_CTL_STATUS(pcie_port), pemx_ctl_status.u64); |
1427 | |
1428 | /* Display the link status */ |
1429 | pciercx_cfg032.u32 = cvmx_pcie_cfgx_read(pcie_port, cfg_offset: CVMX_PCIERCX_CFG032(pcie_port)); |
1430 | pr_notice("PCIe: Port %d link active, %d lanes, speed gen%d\n" , pcie_port, pciercx_cfg032.s.nlw, pciercx_cfg032.s.ls); |
1431 | |
1432 | return 0; |
1433 | } |
1434 | |
1435 | /** |
1436 | * Initialize a PCIe port for use in host(RC) mode. It doesn't enumerate the bus. |
1437 | * |
1438 | * @pcie_port: PCIe port to initialize |
1439 | * |
1440 | * Returns Zero on success |
1441 | */ |
1442 | static int cvmx_pcie_rc_initialize(int pcie_port) |
1443 | { |
1444 | int result; |
1445 | if (octeon_has_feature(OCTEON_FEATURE_NPEI)) |
1446 | result = __cvmx_pcie_rc_initialize_gen1(pcie_port); |
1447 | else |
1448 | result = __cvmx_pcie_rc_initialize_gen2(pcie_port); |
1449 | return result; |
1450 | } |
1451 | |
1452 | /* Above was cvmx-pcie.c, below original pcie.c */ |
1453 | |
1454 | /** |
1455 | * Map a PCI device to the appropriate interrupt line |
1456 | * |
1457 | * @dev: The Linux PCI device structure for the device to map |
1458 | * @slot: The slot number for this device on __BUS 0__. Linux |
1459 | * enumerates through all the bridges and figures out the |
1460 | * slot on Bus 0 where this device eventually hooks to. |
1461 | * @pin: The PCI interrupt pin read from the device, then swizzled |
1462 | * as it goes through each bridge. |
1463 | * Returns Interrupt number for the device |
1464 | */ |
1465 | int octeon_pcie_pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) |
1466 | { |
1467 | /* |
1468 | * The EBH5600 board with the PCI to PCIe bridge mistakenly |
1469 | * wires the first slot for both device id 2 and interrupt |
1470 | * A. According to the PCI spec, device id 2 should be C. The |
1471 | * following kludge attempts to fix this. |
1472 | */ |
1473 | if (strstr(octeon_board_type_string(), "EBH5600" ) && |
1474 | dev->bus && dev->bus->parent) { |
1475 | /* |
1476 | * Iterate all the way up the device chain and find |
1477 | * the root bus. |
1478 | */ |
1479 | while (dev->bus && dev->bus->parent) |
1480 | dev = to_pci_dev(dev->bus->bridge); |
1481 | /* |
1482 | * If the root bus is number 0 and the PEX 8114 is the |
1483 | * root, assume we are behind the miswired bus. We |
1484 | * need to correct the swizzle level by two. Yuck. |
1485 | */ |
1486 | if ((dev->bus->number == 1) && |
1487 | (dev->vendor == 0x10b5) && (dev->device == 0x8114)) { |
1488 | /* |
1489 | * The pin field is one based, not zero. We |
1490 | * need to swizzle it by minus two. |
1491 | */ |
1492 | pin = ((pin - 3) & 3) + 1; |
1493 | } |
1494 | } |
1495 | /* |
1496 | * The -1 is because pin starts with one, not zero. It might |
1497 | * be that this equation needs to include the slot number, but |
1498 | * I don't have hardware to check that against. |
1499 | */ |
1500 | return pin - 1 + OCTEON_IRQ_PCI_INT0; |
1501 | } |
1502 | |
1503 | static void set_cfg_read_retry(u32 retry_cnt) |
1504 | { |
1505 | union cvmx_pemx_ctl_status pemx_ctl; |
1506 | pemx_ctl.u64 = cvmx_read_csr(CVMX_PEMX_CTL_STATUS(1)); |
1507 | pemx_ctl.s.cfg_rtry = retry_cnt; |
1508 | cvmx_write_csr(CVMX_PEMX_CTL_STATUS(1), pemx_ctl.u64); |
1509 | } |
1510 | |
1511 | |
1512 | static u32 disable_cfg_read_retry(void) |
1513 | { |
1514 | u32 retry_cnt; |
1515 | |
1516 | union cvmx_pemx_ctl_status pemx_ctl; |
1517 | pemx_ctl.u64 = cvmx_read_csr(CVMX_PEMX_CTL_STATUS(1)); |
1518 | retry_cnt = pemx_ctl.s.cfg_rtry; |
1519 | pemx_ctl.s.cfg_rtry = 0; |
1520 | cvmx_write_csr(CVMX_PEMX_CTL_STATUS(1), pemx_ctl.u64); |
1521 | return retry_cnt; |
1522 | } |
1523 | |
1524 | static int is_cfg_retry(void) |
1525 | { |
1526 | union cvmx_pemx_int_sum pemx_int_sum; |
1527 | pemx_int_sum.u64 = cvmx_read_csr(CVMX_PEMX_INT_SUM(1)); |
1528 | if (pemx_int_sum.s.crs_dr) |
1529 | return 1; |
1530 | return 0; |
1531 | } |
1532 | |
1533 | /* |
1534 | * Read a value from configuration space |
1535 | * |
1536 | */ |
1537 | static int octeon_pcie_read_config(unsigned int pcie_port, struct pci_bus *bus, |
1538 | unsigned int devfn, int reg, int size, |
1539 | u32 *val) |
1540 | { |
1541 | union octeon_cvmemctl cvmmemctl; |
1542 | union octeon_cvmemctl cvmmemctl_save; |
1543 | int bus_number = bus->number; |
1544 | int cfg_retry = 0; |
1545 | int retry_cnt = 0; |
1546 | int max_retry_cnt = 10; |
1547 | u32 cfg_retry_cnt = 0; |
1548 | |
1549 | cvmmemctl_save.u64 = 0; |
1550 | BUG_ON(pcie_port >= ARRAY_SIZE(enable_pcie_bus_num_war)); |
1551 | /* |
1552 | * For the top level bus make sure our hardware bus number |
1553 | * matches the software one |
1554 | */ |
1555 | if (bus->parent == NULL) { |
1556 | if (enable_pcie_bus_num_war[pcie_port]) |
1557 | bus_number = 0; |
1558 | else { |
1559 | union cvmx_pciercx_cfg006 pciercx_cfg006; |
1560 | pciercx_cfg006.u32 = cvmx_pcie_cfgx_read(pcie_port, |
1561 | cfg_offset: CVMX_PCIERCX_CFG006(pcie_port)); |
1562 | if (pciercx_cfg006.s.pbnum != bus_number) { |
1563 | pciercx_cfg006.s.pbnum = bus_number; |
1564 | pciercx_cfg006.s.sbnum = bus_number; |
1565 | pciercx_cfg006.s.subbnum = bus_number; |
1566 | cvmx_pcie_cfgx_write(pcie_port, |
1567 | cfg_offset: CVMX_PCIERCX_CFG006(pcie_port), |
1568 | val: pciercx_cfg006.u32); |
1569 | } |
1570 | } |
1571 | } |
1572 | |
1573 | /* |
1574 | * PCIe only has a single device connected to Octeon. It is |
1575 | * always device ID 0. Don't bother doing reads for other |
1576 | * device IDs on the first segment. |
1577 | */ |
1578 | if ((bus->parent == NULL) && (devfn >> 3 != 0)) |
1579 | return PCIBIOS_FUNC_NOT_SUPPORTED; |
1580 | |
1581 | /* |
1582 | * The following is a workaround for the CN57XX, CN56XX, |
1583 | * CN55XX, and CN54XX errata with PCIe config reads from non |
1584 | * existent devices. These chips will hang the PCIe link if a |
1585 | * config read is performed that causes a UR response. |
1586 | */ |
1587 | if (OCTEON_IS_MODEL(OCTEON_CN56XX_PASS1) || |
1588 | OCTEON_IS_MODEL(OCTEON_CN56XX_PASS1_1)) { |
1589 | /* |
1590 | * For our EBH5600 board, port 0 has a bridge with two |
1591 | * PCI-X slots. We need a new special checks to make |
1592 | * sure we only probe valid stuff. The PCIe->PCI-X |
1593 | * bridge only respondes to device ID 0, function |
1594 | * 0-1 |
1595 | */ |
1596 | if ((bus->parent == NULL) && (devfn >= 2)) |
1597 | return PCIBIOS_FUNC_NOT_SUPPORTED; |
1598 | /* |
1599 | * The PCI-X slots are device ID 2,3. Choose one of |
1600 | * the below "if" blocks based on what is plugged into |
1601 | * the board. |
1602 | */ |
1603 | #if 1 |
1604 | /* Use this option if you aren't using either slot */ |
1605 | if (bus_number == 2) |
1606 | return PCIBIOS_FUNC_NOT_SUPPORTED; |
1607 | #elif 0 |
1608 | /* |
1609 | * Use this option if you are using the first slot but |
1610 | * not the second. |
1611 | */ |
1612 | if ((bus_number == 2) && (devfn >> 3 != 2)) |
1613 | return PCIBIOS_FUNC_NOT_SUPPORTED; |
1614 | #elif 0 |
1615 | /* |
1616 | * Use this option if you are using the second slot |
1617 | * but not the first. |
1618 | */ |
1619 | if ((bus_number == 2) && (devfn >> 3 != 3)) |
1620 | return PCIBIOS_FUNC_NOT_SUPPORTED; |
1621 | #elif 0 |
1622 | /* Use this opion if you are using both slots */ |
1623 | if ((bus_number == 2) && |
1624 | !((devfn == (2 << 3)) || (devfn == (3 << 3)))) |
1625 | return PCIBIOS_FUNC_NOT_SUPPORTED; |
1626 | #endif |
1627 | |
1628 | /* The following #if gives a more complicated example. This is |
1629 | the required checks for running a Nitrox CN16XX-NHBX in the |
1630 | slot of the EBH5600. This card has a PLX PCIe bridge with |
1631 | four Nitrox PLX parts behind it */ |
1632 | #if 0 |
1633 | /* PLX bridge with 4 ports */ |
1634 | if ((bus_number == 4) && |
1635 | !((devfn >> 3 >= 1) && (devfn >> 3 <= 4))) |
1636 | return PCIBIOS_FUNC_NOT_SUPPORTED; |
1637 | /* Nitrox behind PLX 1 */ |
1638 | if ((bus_number == 5) && (devfn >> 3 != 0)) |
1639 | return PCIBIOS_FUNC_NOT_SUPPORTED; |
1640 | /* Nitrox behind PLX 2 */ |
1641 | if ((bus_number == 6) && (devfn >> 3 != 0)) |
1642 | return PCIBIOS_FUNC_NOT_SUPPORTED; |
1643 | /* Nitrox behind PLX 3 */ |
1644 | if ((bus_number == 7) && (devfn >> 3 != 0)) |
1645 | return PCIBIOS_FUNC_NOT_SUPPORTED; |
1646 | /* Nitrox behind PLX 4 */ |
1647 | if ((bus_number == 8) && (devfn >> 3 != 0)) |
1648 | return PCIBIOS_FUNC_NOT_SUPPORTED; |
1649 | #endif |
1650 | |
1651 | /* |
1652 | * Shorten the DID timeout so bus errors for PCIe |
1653 | * config reads from non existent devices happen |
1654 | * faster. This allows us to continue booting even if |
1655 | * the above "if" checks are wrong. Once one of these |
1656 | * errors happens, the PCIe port is dead. |
1657 | */ |
1658 | cvmmemctl_save.u64 = __read_64bit_c0_register($11, 7); |
1659 | cvmmemctl.u64 = cvmmemctl_save.u64; |
1660 | cvmmemctl.s.didtto = 2; |
1661 | __write_64bit_c0_register($11, 7, cvmmemctl.u64); |
1662 | } |
1663 | |
1664 | if ((OCTEON_IS_MODEL(OCTEON_CN63XX)) && (enable_pcie_14459_war)) |
1665 | cfg_retry_cnt = disable_cfg_read_retry(); |
1666 | |
1667 | pr_debug("pcie_cfg_rd port=%d b=%d devfn=0x%03x reg=0x%03x" |
1668 | " size=%d " , pcie_port, bus_number, devfn, reg, size); |
1669 | do { |
1670 | switch (size) { |
1671 | case 4: |
1672 | *val = cvmx_pcie_config_read32(pcie_port, bus: bus_number, |
1673 | dev: devfn >> 3, fn: devfn & 0x7, reg); |
1674 | break; |
1675 | case 2: |
1676 | *val = cvmx_pcie_config_read16(pcie_port, bus: bus_number, |
1677 | dev: devfn >> 3, fn: devfn & 0x7, reg); |
1678 | break; |
1679 | case 1: |
1680 | *val = cvmx_pcie_config_read8(pcie_port, bus: bus_number, |
1681 | dev: devfn >> 3, fn: devfn & 0x7, reg); |
1682 | break; |
1683 | default: |
1684 | if (OCTEON_IS_MODEL(OCTEON_CN63XX)) |
1685 | set_cfg_read_retry(cfg_retry_cnt); |
1686 | return PCIBIOS_FUNC_NOT_SUPPORTED; |
1687 | } |
1688 | if ((OCTEON_IS_MODEL(OCTEON_CN63XX)) && |
1689 | (enable_pcie_14459_war)) { |
1690 | cfg_retry = is_cfg_retry(); |
1691 | retry_cnt++; |
1692 | if (retry_cnt > max_retry_cnt) { |
1693 | pr_err(" pcie cfg_read retries failed. retry_cnt=%d\n" , |
1694 | retry_cnt); |
1695 | cfg_retry = 0; |
1696 | } |
1697 | } |
1698 | } while (cfg_retry); |
1699 | |
1700 | if ((OCTEON_IS_MODEL(OCTEON_CN63XX)) && (enable_pcie_14459_war)) |
1701 | set_cfg_read_retry(cfg_retry_cnt); |
1702 | pr_debug("val=%08x : tries=%02d\n" , *val, retry_cnt); |
1703 | if (OCTEON_IS_MODEL(OCTEON_CN56XX_PASS1) || |
1704 | OCTEON_IS_MODEL(OCTEON_CN56XX_PASS1_1)) |
1705 | write_c0_cvmmemctl(cvmmemctl_save.u64); |
1706 | return PCIBIOS_SUCCESSFUL; |
1707 | } |
1708 | |
1709 | static int octeon_pcie0_read_config(struct pci_bus *bus, unsigned int devfn, |
1710 | int reg, int size, u32 *val) |
1711 | { |
1712 | return octeon_pcie_read_config(pcie_port: 0, bus, devfn, reg, size, val); |
1713 | } |
1714 | |
1715 | static int octeon_pcie1_read_config(struct pci_bus *bus, unsigned int devfn, |
1716 | int reg, int size, u32 *val) |
1717 | { |
1718 | return octeon_pcie_read_config(pcie_port: 1, bus, devfn, reg, size, val); |
1719 | } |
1720 | |
1721 | static int octeon_dummy_read_config(struct pci_bus *bus, unsigned int devfn, |
1722 | int reg, int size, u32 *val) |
1723 | { |
1724 | return PCIBIOS_FUNC_NOT_SUPPORTED; |
1725 | } |
1726 | |
1727 | /* |
1728 | * Write a value to PCI configuration space |
1729 | */ |
1730 | static int octeon_pcie_write_config(unsigned int pcie_port, struct pci_bus *bus, |
1731 | unsigned int devfn, int reg, |
1732 | int size, u32 val) |
1733 | { |
1734 | int bus_number = bus->number; |
1735 | |
1736 | BUG_ON(pcie_port >= ARRAY_SIZE(enable_pcie_bus_num_war)); |
1737 | |
1738 | if ((bus->parent == NULL) && (enable_pcie_bus_num_war[pcie_port])) |
1739 | bus_number = 0; |
1740 | |
1741 | pr_debug("pcie_cfg_wr port=%d b=%d devfn=0x%03x" |
1742 | " reg=0x%03x size=%d val=%08x\n" , pcie_port, bus_number, devfn, |
1743 | reg, size, val); |
1744 | |
1745 | |
1746 | switch (size) { |
1747 | case 4: |
1748 | cvmx_pcie_config_write32(pcie_port, bus: bus_number, dev: devfn >> 3, |
1749 | fn: devfn & 0x7, reg, val); |
1750 | break; |
1751 | case 2: |
1752 | cvmx_pcie_config_write16(pcie_port, bus: bus_number, dev: devfn >> 3, |
1753 | fn: devfn & 0x7, reg, val); |
1754 | break; |
1755 | case 1: |
1756 | cvmx_pcie_config_write8(pcie_port, bus: bus_number, dev: devfn >> 3, |
1757 | fn: devfn & 0x7, reg, val); |
1758 | break; |
1759 | default: |
1760 | return PCIBIOS_FUNC_NOT_SUPPORTED; |
1761 | } |
1762 | return PCIBIOS_SUCCESSFUL; |
1763 | } |
1764 | |
1765 | static int octeon_pcie0_write_config(struct pci_bus *bus, unsigned int devfn, |
1766 | int reg, int size, u32 val) |
1767 | { |
1768 | return octeon_pcie_write_config(pcie_port: 0, bus, devfn, reg, size, val); |
1769 | } |
1770 | |
1771 | static int octeon_pcie1_write_config(struct pci_bus *bus, unsigned int devfn, |
1772 | int reg, int size, u32 val) |
1773 | { |
1774 | return octeon_pcie_write_config(pcie_port: 1, bus, devfn, reg, size, val); |
1775 | } |
1776 | |
1777 | static int octeon_dummy_write_config(struct pci_bus *bus, unsigned int devfn, |
1778 | int reg, int size, u32 val) |
1779 | { |
1780 | return PCIBIOS_FUNC_NOT_SUPPORTED; |
1781 | } |
1782 | |
1783 | static struct pci_ops octeon_pcie0_ops = { |
1784 | .read = octeon_pcie0_read_config, |
1785 | .write = octeon_pcie0_write_config, |
1786 | }; |
1787 | |
1788 | static struct resource octeon_pcie0_mem_resource = { |
1789 | .name = "Octeon PCIe0 MEM" , |
1790 | .flags = IORESOURCE_MEM, |
1791 | }; |
1792 | |
1793 | static struct resource octeon_pcie0_io_resource = { |
1794 | .name = "Octeon PCIe0 IO" , |
1795 | .flags = IORESOURCE_IO, |
1796 | }; |
1797 | |
1798 | static struct pci_controller octeon_pcie0_controller = { |
1799 | .pci_ops = &octeon_pcie0_ops, |
1800 | .mem_resource = &octeon_pcie0_mem_resource, |
1801 | .io_resource = &octeon_pcie0_io_resource, |
1802 | }; |
1803 | |
1804 | static struct pci_ops octeon_pcie1_ops = { |
1805 | .read = octeon_pcie1_read_config, |
1806 | .write = octeon_pcie1_write_config, |
1807 | }; |
1808 | |
1809 | static struct resource octeon_pcie1_mem_resource = { |
1810 | .name = "Octeon PCIe1 MEM" , |
1811 | .flags = IORESOURCE_MEM, |
1812 | }; |
1813 | |
1814 | static struct resource octeon_pcie1_io_resource = { |
1815 | .name = "Octeon PCIe1 IO" , |
1816 | .flags = IORESOURCE_IO, |
1817 | }; |
1818 | |
1819 | static struct pci_controller octeon_pcie1_controller = { |
1820 | .pci_ops = &octeon_pcie1_ops, |
1821 | .mem_resource = &octeon_pcie1_mem_resource, |
1822 | .io_resource = &octeon_pcie1_io_resource, |
1823 | }; |
1824 | |
1825 | static struct pci_ops octeon_dummy_ops = { |
1826 | .read = octeon_dummy_read_config, |
1827 | .write = octeon_dummy_write_config, |
1828 | }; |
1829 | |
1830 | static struct resource octeon_dummy_mem_resource = { |
1831 | .name = "Virtual PCIe MEM" , |
1832 | .flags = IORESOURCE_MEM, |
1833 | }; |
1834 | |
1835 | static struct resource octeon_dummy_io_resource = { |
1836 | .name = "Virtual PCIe IO" , |
1837 | .flags = IORESOURCE_IO, |
1838 | }; |
1839 | |
1840 | static struct pci_controller octeon_dummy_controller = { |
1841 | .pci_ops = &octeon_dummy_ops, |
1842 | .mem_resource = &octeon_dummy_mem_resource, |
1843 | .io_resource = &octeon_dummy_io_resource, |
1844 | }; |
1845 | |
1846 | static int device_needs_bus_num_war(uint32_t deviceid) |
1847 | { |
1848 | #define IDT_VENDOR_ID 0x111d |
1849 | |
1850 | if ((deviceid & 0xffff) == IDT_VENDOR_ID) |
1851 | return 1; |
1852 | return 0; |
1853 | } |
1854 | |
1855 | /** |
1856 | * Initialize the Octeon PCIe controllers |
1857 | * |
1858 | * Returns |
1859 | */ |
1860 | static int __init octeon_pcie_setup(void) |
1861 | { |
1862 | int result; |
1863 | int host_mode; |
1864 | int srio_war15205 = 0, port; |
1865 | union cvmx_sli_ctl_portx sli_ctl_portx; |
1866 | union cvmx_sriox_status_reg sriox_status_reg; |
1867 | |
1868 | /* These chips don't have PCIe */ |
1869 | if (!octeon_has_feature(OCTEON_FEATURE_PCIE)) |
1870 | return 0; |
1871 | |
1872 | /* No PCIe simulation */ |
1873 | if (octeon_is_simulation()) |
1874 | return 0; |
1875 | |
1876 | /* Disable PCI if instructed on the command line */ |
1877 | if (pcie_disable) |
1878 | return 0; |
1879 | |
1880 | /* Point pcibios_map_irq() to the PCIe version of it */ |
1881 | octeon_pcibios_map_irq = octeon_pcie_pcibios_map_irq; |
1882 | |
1883 | /* |
1884 | * PCIe I/O range. It is based on port 0 but includes up until |
1885 | * port 1's end. |
1886 | */ |
1887 | set_io_port_base(CVMX_ADD_IO_SEG(cvmx_pcie_get_io_base_address(pcie_port: 0))); |
1888 | ioport_resource.start = 0; |
1889 | ioport_resource.end = |
1890 | cvmx_pcie_get_io_base_address(pcie_port: 1) - |
1891 | cvmx_pcie_get_io_base_address(pcie_port: 0) + cvmx_pcie_get_io_size(pcie_port: 1) - 1; |
1892 | |
1893 | /* |
1894 | * Create a dummy PCIe controller to swallow up bus 0. IDT bridges |
1895 | * don't work if the primary bus number is zero. Here we add a fake |
1896 | * PCIe controller that the kernel will give bus 0. This allows |
1897 | * us to not change the normal kernel bus enumeration |
1898 | */ |
1899 | octeon_dummy_controller.io_map_base = -1; |
1900 | octeon_dummy_controller.mem_resource->start = (1ull<<48); |
1901 | octeon_dummy_controller.mem_resource->end = (1ull<<48); |
1902 | register_pci_controller(&octeon_dummy_controller); |
1903 | |
1904 | if (octeon_has_feature(OCTEON_FEATURE_NPEI)) { |
1905 | union cvmx_npei_ctl_status npei_ctl_status; |
1906 | npei_ctl_status.u64 = cvmx_read_csr(CVMX_PEXP_NPEI_CTL_STATUS); |
1907 | host_mode = npei_ctl_status.s.host_mode; |
1908 | octeon_dma_bar_type = OCTEON_DMA_BAR_TYPE_PCIE; |
1909 | } else { |
1910 | union cvmx_mio_rst_ctlx mio_rst_ctl; |
1911 | mio_rst_ctl.u64 = cvmx_read_csr(CVMX_MIO_RST_CTLX(0)); |
1912 | host_mode = mio_rst_ctl.s.host_mode; |
1913 | octeon_dma_bar_type = OCTEON_DMA_BAR_TYPE_PCIE2; |
1914 | } |
1915 | |
1916 | if (host_mode) { |
1917 | pr_notice("PCIe: Initializing port 0\n" ); |
1918 | /* CN63XX pass 1_x/2.0 errata PCIe-15205 */ |
1919 | if (OCTEON_IS_MODEL(OCTEON_CN63XX_PASS1_X) || |
1920 | OCTEON_IS_MODEL(OCTEON_CN63XX_PASS2_0)) { |
1921 | sriox_status_reg.u64 = cvmx_read_csr(CVMX_SRIOX_STATUS_REG(0)); |
1922 | if (sriox_status_reg.s.srio) { |
1923 | srio_war15205 += 1; /* Port is SRIO */ |
1924 | port = 0; |
1925 | } |
1926 | } |
1927 | result = cvmx_pcie_rc_initialize(pcie_port: 0); |
1928 | if (result == 0) { |
1929 | uint32_t device0; |
1930 | /* Memory offsets are physical addresses */ |
1931 | octeon_pcie0_controller.mem_offset = |
1932 | cvmx_pcie_get_mem_base_address(pcie_port: 0); |
1933 | /* IO offsets are Mips virtual addresses */ |
1934 | octeon_pcie0_controller.io_map_base = |
1935 | CVMX_ADD_IO_SEG(cvmx_pcie_get_io_base_address |
1936 | (pcie_port: 0)); |
1937 | octeon_pcie0_controller.io_offset = 0; |
1938 | /* |
1939 | * To keep things similar to PCI, we start |
1940 | * device addresses at the same place as PCI |
1941 | * uisng big bar support. This normally |
1942 | * translates to 4GB-256MB, which is the same |
1943 | * as most x86 PCs. |
1944 | */ |
1945 | octeon_pcie0_controller.mem_resource->start = |
1946 | cvmx_pcie_get_mem_base_address(0) + |
1947 | (4ul << 30) - (OCTEON_PCI_BAR1_HOLE_SIZE << 20); |
1948 | octeon_pcie0_controller.mem_resource->end = |
1949 | cvmx_pcie_get_mem_base_address(pcie_port: 0) + |
1950 | cvmx_pcie_get_mem_size(pcie_port: 0) - 1; |
1951 | /* |
1952 | * Ports must be above 16KB for the ISA bus |
1953 | * filtering in the PCI-X to PCI bridge. |
1954 | */ |
1955 | octeon_pcie0_controller.io_resource->start = 4 << 10; |
1956 | octeon_pcie0_controller.io_resource->end = |
1957 | cvmx_pcie_get_io_size(pcie_port: 0) - 1; |
1958 | msleep(msecs: 100); /* Some devices need extra time */ |
1959 | register_pci_controller(&octeon_pcie0_controller); |
1960 | device0 = cvmx_pcie_config_read32(pcie_port: 0, bus: 0, dev: 0, fn: 0, reg: 0); |
1961 | enable_pcie_bus_num_war[0] = |
1962 | device_needs_bus_num_war(deviceid: device0); |
1963 | } |
1964 | } else { |
1965 | pr_notice("PCIe: Port 0 in endpoint mode, skipping.\n" ); |
1966 | /* CN63XX pass 1_x/2.0 errata PCIe-15205 */ |
1967 | if (OCTEON_IS_MODEL(OCTEON_CN63XX_PASS1_X) || |
1968 | OCTEON_IS_MODEL(OCTEON_CN63XX_PASS2_0)) { |
1969 | srio_war15205 += 1; |
1970 | port = 0; |
1971 | } |
1972 | } |
1973 | |
1974 | if (octeon_has_feature(OCTEON_FEATURE_NPEI)) { |
1975 | host_mode = 1; |
1976 | /* Skip the 2nd port on CN52XX if port 0 is in 4 lane mode */ |
1977 | if (OCTEON_IS_MODEL(OCTEON_CN52XX)) { |
1978 | union cvmx_npei_dbg_data dbg_data; |
1979 | dbg_data.u64 = cvmx_read_csr(CVMX_PEXP_NPEI_DBG_DATA); |
1980 | if (dbg_data.cn52xx.qlm0_link_width) |
1981 | host_mode = 0; |
1982 | } |
1983 | } else { |
1984 | union cvmx_mio_rst_ctlx mio_rst_ctl; |
1985 | mio_rst_ctl.u64 = cvmx_read_csr(CVMX_MIO_RST_CTLX(1)); |
1986 | host_mode = mio_rst_ctl.s.host_mode; |
1987 | } |
1988 | |
1989 | if (host_mode) { |
1990 | pr_notice("PCIe: Initializing port 1\n" ); |
1991 | /* CN63XX pass 1_x/2.0 errata PCIe-15205 */ |
1992 | if (OCTEON_IS_MODEL(OCTEON_CN63XX_PASS1_X) || |
1993 | OCTEON_IS_MODEL(OCTEON_CN63XX_PASS2_0)) { |
1994 | sriox_status_reg.u64 = cvmx_read_csr(CVMX_SRIOX_STATUS_REG(1)); |
1995 | if (sriox_status_reg.s.srio) { |
1996 | srio_war15205 += 1; /* Port is SRIO */ |
1997 | port = 1; |
1998 | } |
1999 | } |
2000 | result = cvmx_pcie_rc_initialize(pcie_port: 1); |
2001 | if (result == 0) { |
2002 | uint32_t device0; |
2003 | /* Memory offsets are physical addresses */ |
2004 | octeon_pcie1_controller.mem_offset = |
2005 | cvmx_pcie_get_mem_base_address(pcie_port: 1); |
2006 | /* |
2007 | * To calculate the address for accessing the 2nd PCIe device, |
2008 | * either 'io_map_base' (pci_iomap()), or 'mips_io_port_base' |
2009 | * (ioport_map()) value is added to |
2010 | * pci_resource_start(dev,bar)). The 'mips_io_port_base' is set |
2011 | * only once based on first PCIe. Also changing 'io_map_base' |
2012 | * based on first slot's value so that both the routines will |
2013 | * work properly. |
2014 | */ |
2015 | octeon_pcie1_controller.io_map_base = |
2016 | CVMX_ADD_IO_SEG(cvmx_pcie_get_io_base_address(pcie_port: 0)); |
2017 | /* IO offsets are Mips virtual addresses */ |
2018 | octeon_pcie1_controller.io_offset = |
2019 | cvmx_pcie_get_io_base_address(pcie_port: 1) - |
2020 | cvmx_pcie_get_io_base_address(pcie_port: 0); |
2021 | /* |
2022 | * To keep things similar to PCI, we start device |
2023 | * addresses at the same place as PCI uisng big bar |
2024 | * support. This normally translates to 4GB-256MB, |
2025 | * which is the same as most x86 PCs. |
2026 | */ |
2027 | octeon_pcie1_controller.mem_resource->start = |
2028 | cvmx_pcie_get_mem_base_address(1) + (4ul << 30) - |
2029 | (OCTEON_PCI_BAR1_HOLE_SIZE << 20); |
2030 | octeon_pcie1_controller.mem_resource->end = |
2031 | cvmx_pcie_get_mem_base_address(pcie_port: 1) + |
2032 | cvmx_pcie_get_mem_size(pcie_port: 1) - 1; |
2033 | /* |
2034 | * Ports must be above 16KB for the ISA bus filtering |
2035 | * in the PCI-X to PCI bridge. |
2036 | */ |
2037 | octeon_pcie1_controller.io_resource->start = |
2038 | cvmx_pcie_get_io_base_address(pcie_port: 1) - |
2039 | cvmx_pcie_get_io_base_address(pcie_port: 0); |
2040 | octeon_pcie1_controller.io_resource->end = |
2041 | octeon_pcie1_controller.io_resource->start + |
2042 | cvmx_pcie_get_io_size(pcie_port: 1) - 1; |
2043 | msleep(msecs: 100); /* Some devices need extra time */ |
2044 | register_pci_controller(&octeon_pcie1_controller); |
2045 | device0 = cvmx_pcie_config_read32(pcie_port: 1, bus: 0, dev: 0, fn: 0, reg: 0); |
2046 | enable_pcie_bus_num_war[1] = |
2047 | device_needs_bus_num_war(deviceid: device0); |
2048 | } |
2049 | } else { |
2050 | pr_notice("PCIe: Port 1 not in root complex mode, skipping.\n" ); |
2051 | /* CN63XX pass 1_x/2.0 errata PCIe-15205 */ |
2052 | if (OCTEON_IS_MODEL(OCTEON_CN63XX_PASS1_X) || |
2053 | OCTEON_IS_MODEL(OCTEON_CN63XX_PASS2_0)) { |
2054 | srio_war15205 += 1; |
2055 | port = 1; |
2056 | } |
2057 | } |
2058 | |
2059 | /* |
2060 | * CN63XX pass 1_x/2.0 errata PCIe-15205 requires setting all |
2061 | * of SRIO MACs SLI_CTL_PORT*[INT*_MAP] to similar value and |
2062 | * all of PCIe Macs SLI_CTL_PORT*[INT*_MAP] to different value |
2063 | * from the previous set values |
2064 | */ |
2065 | if (OCTEON_IS_MODEL(OCTEON_CN63XX_PASS1_X) || |
2066 | OCTEON_IS_MODEL(OCTEON_CN63XX_PASS2_0)) { |
2067 | if (srio_war15205 == 1) { |
2068 | sli_ctl_portx.u64 = cvmx_read_csr(CVMX_PEXP_SLI_CTL_PORTX(port)); |
2069 | sli_ctl_portx.s.inta_map = 1; |
2070 | sli_ctl_portx.s.intb_map = 1; |
2071 | sli_ctl_portx.s.intc_map = 1; |
2072 | sli_ctl_portx.s.intd_map = 1; |
2073 | cvmx_write_csr(CVMX_PEXP_SLI_CTL_PORTX(port), sli_ctl_portx.u64); |
2074 | |
2075 | sli_ctl_portx.u64 = cvmx_read_csr(CVMX_PEXP_SLI_CTL_PORTX(!port)); |
2076 | sli_ctl_portx.s.inta_map = 0; |
2077 | sli_ctl_portx.s.intb_map = 0; |
2078 | sli_ctl_portx.s.intc_map = 0; |
2079 | sli_ctl_portx.s.intd_map = 0; |
2080 | cvmx_write_csr(CVMX_PEXP_SLI_CTL_PORTX(!port), sli_ctl_portx.u64); |
2081 | } |
2082 | } |
2083 | |
2084 | octeon_pci_dma_init(); |
2085 | |
2086 | return 0; |
2087 | } |
2088 | arch_initcall(octeon_pcie_setup); |
2089 | |