1 | // SPDX-License-Identifier: GPL-2.0 |
2 | /* |
3 | * arch/sparc/math-emu/math.c |
4 | * |
5 | * Copyright (C) 1998 Peter Maydell (pmaydell@chiark.greenend.org.uk) |
6 | * Copyright (C) 1997, 1999 Jakub Jelinek (jj@ultra.linux.cz) |
7 | * Copyright (C) 1999 David S. Miller (davem@redhat.com) |
8 | * |
9 | * This is a good place to start if you're trying to understand the |
10 | * emulation code, because it's pretty simple. What we do is |
11 | * essentially analyse the instruction to work out what the operation |
12 | * is and which registers are involved. We then execute the appropriate |
13 | * FXXXX function. [The floating point queue introduces a minor wrinkle; |
14 | * see below...] |
15 | * The fxxxxx.c files each emulate a single insn. They look relatively |
16 | * simple because the complexity is hidden away in an unholy tangle |
17 | * of preprocessor macros. |
18 | * |
19 | * The first layer of macros is single.h, double.h, quad.h. Generally |
20 | * these files define macros for working with floating point numbers |
21 | * of the three IEEE formats. FP_ADD_D(R,A,B) is for adding doubles, |
22 | * for instance. These macros are usually defined as calls to more |
23 | * generic macros (in this case _FP_ADD(D,2,R,X,Y) where the number |
24 | * of machine words required to store the given IEEE format is passed |
25 | * as a parameter. [double.h and co check the number of bits in a word |
26 | * and define FP_ADD_D & co appropriately]. |
27 | * The generic macros are defined in op-common.h. This is where all |
28 | * the grotty stuff like handling NaNs is coded. To handle the possible |
29 | * word sizes macros in op-common.h use macros like _FP_FRAC_SLL_##wc() |
30 | * where wc is the 'number of machine words' parameter (here 2). |
31 | * These are defined in the third layer of macros: op-1.h, op-2.h |
32 | * and op-4.h. These handle operations on floating point numbers composed |
33 | * of 1,2 and 4 machine words respectively. [For example, on sparc64 |
34 | * doubles are one machine word so macros in double.h eventually use |
35 | * constructs in op-1.h, but on sparc32 they use op-2.h definitions.] |
36 | * soft-fp.h is on the same level as op-common.h, and defines some |
37 | * macros which are independent of both word size and FP format. |
38 | * Finally, sfp-machine.h is the machine dependent part of the |
39 | * code: it defines the word size and what type a word is. It also |
40 | * defines how _FP_MUL_MEAT_t() maps to _FP_MUL_MEAT_n_* : op-n.h |
41 | * provide several possible flavours of multiply algorithm, most |
42 | * of which require that you supply some form of asm or C primitive to |
43 | * do the actual multiply. (such asm primitives should be defined |
44 | * in sfp-machine.h too). udivmodti4.c is the same sort of thing. |
45 | * |
46 | * There may be some errors here because I'm working from a |
47 | * SPARC architecture manual V9, and what I really want is V8... |
48 | * Also, the insns which can generate exceptions seem to be a |
49 | * greater subset of the FPops than for V9 (for example, FCMPED |
50 | * has to be emulated on V8). So I think I'm going to have |
51 | * to emulate them all just to be on the safe side... |
52 | * |
53 | * Emulation routines originate from soft-fp package, which is |
54 | * part of glibc and has appropriate copyrights in it (allegedly). |
55 | * |
56 | * NB: on sparc int == long == 4 bytes, long long == 8 bytes. |
57 | * Most bits of the kernel seem to go for long rather than int, |
58 | * so we follow that practice... |
59 | */ |
60 | |
61 | /* TODO: |
62 | * fpsave() saves the FP queue but fpload() doesn't reload it. |
63 | * Therefore when we context switch or change FPU ownership |
64 | * we have to check to see if the queue had anything in it and |
65 | * emulate it if it did. This is going to be a pain. |
66 | */ |
67 | |
68 | #include <linux/types.h> |
69 | #include <linux/sched.h> |
70 | #include <linux/mm.h> |
71 | #include <linux/perf_event.h> |
72 | #include <linux/uaccess.h> |
73 | |
74 | #include "sfp-util_32.h" |
75 | #include <math-emu/soft-fp.h> |
76 | #include <math-emu/single.h> |
77 | #include <math-emu/double.h> |
78 | #include <math-emu/quad.h> |
79 | |
80 | #define FLOATFUNC(x) extern int x(void *,void *,void *) |
81 | |
82 | /* The Vn labels indicate what version of the SPARC architecture gas thinks |
83 | * each insn is. This is from the binutils source :-> |
84 | */ |
85 | /* quadword instructions */ |
86 | #define FSQRTQ 0x02b /* v8 */ |
87 | #define FADDQ 0x043 /* v8 */ |
88 | #define FSUBQ 0x047 /* v8 */ |
89 | #define FMULQ 0x04b /* v8 */ |
90 | #define FDIVQ 0x04f /* v8 */ |
91 | #define FDMULQ 0x06e /* v8 */ |
92 | #define FQTOS 0x0c7 /* v8 */ |
93 | #define FQTOD 0x0cb /* v8 */ |
94 | #define FITOQ 0x0cc /* v8 */ |
95 | #define FSTOQ 0x0cd /* v8 */ |
96 | #define FDTOQ 0x0ce /* v8 */ |
97 | #define FQTOI 0x0d3 /* v8 */ |
98 | #define FCMPQ 0x053 /* v8 */ |
99 | #define FCMPEQ 0x057 /* v8 */ |
100 | /* single/double instructions (subnormal): should all work */ |
101 | #define FSQRTS 0x029 /* v7 */ |
102 | #define FSQRTD 0x02a /* v7 */ |
103 | #define FADDS 0x041 /* v6 */ |
104 | #define FADDD 0x042 /* v6 */ |
105 | #define FSUBS 0x045 /* v6 */ |
106 | #define FSUBD 0x046 /* v6 */ |
107 | #define FMULS 0x049 /* v6 */ |
108 | #define FMULD 0x04a /* v6 */ |
109 | #define FDIVS 0x04d /* v6 */ |
110 | #define FDIVD 0x04e /* v6 */ |
111 | #define FSMULD 0x069 /* v6 */ |
112 | #define FDTOS 0x0c6 /* v6 */ |
113 | #define FSTOD 0x0c9 /* v6 */ |
114 | #define FSTOI 0x0d1 /* v6 */ |
115 | #define FDTOI 0x0d2 /* v6 */ |
116 | #define FABSS 0x009 /* v6 */ |
117 | #define FCMPS 0x051 /* v6 */ |
118 | #define FCMPES 0x055 /* v6 */ |
119 | #define FCMPD 0x052 /* v6 */ |
120 | #define FCMPED 0x056 /* v6 */ |
121 | #define FMOVS 0x001 /* v6 */ |
122 | #define FNEGS 0x005 /* v6 */ |
123 | #define FITOS 0x0c4 /* v6 */ |
124 | #define FITOD 0x0c8 /* v6 */ |
125 | |
126 | #define FSR_TEM_SHIFT 23UL |
127 | #define FSR_TEM_MASK (0x1fUL << FSR_TEM_SHIFT) |
128 | #define FSR_AEXC_SHIFT 5UL |
129 | #define FSR_AEXC_MASK (0x1fUL << FSR_AEXC_SHIFT) |
130 | #define FSR_CEXC_SHIFT 0UL |
131 | #define FSR_CEXC_MASK (0x1fUL << FSR_CEXC_SHIFT) |
132 | |
133 | static int do_one_mathemu(u32 insn, unsigned long *fsr, unsigned long *fregs); |
134 | |
135 | /* Unlike the Sparc64 version (which has a struct fpustate), we |
136 | * pass the taskstruct corresponding to the task which currently owns the |
137 | * FPU. This is partly because we don't have the fpustate struct and |
138 | * partly because the task owning the FPU isn't always current (as is |
139 | * the case for the Sparc64 port). This is probably SMP-related... |
140 | * This function returns 1 if all queued insns were emulated successfully. |
141 | * The test for unimplemented FPop in kernel mode has been moved into |
142 | * kernel/traps.c for simplicity. |
143 | */ |
144 | int do_mathemu(struct pt_regs *regs, struct task_struct *fpt) |
145 | { |
146 | /* regs->pc isn't necessarily the PC at which the offending insn is sitting. |
147 | * The FPU maintains a queue of FPops which cause traps. |
148 | * When it hits an instruction that requires that the trapped op succeeded |
149 | * (usually because it reads a reg. that the trapped op wrote) then it |
150 | * causes this exception. We need to emulate all the insns on the queue |
151 | * and then allow the op to proceed. |
152 | * This code should also handle the case where the trap was precise, |
153 | * in which case the queue length is zero and regs->pc points at the |
154 | * single FPop to be emulated. (this case is untested, though :->) |
155 | * You'll need this case if you want to be able to emulate all FPops |
156 | * because the FPU either doesn't exist or has been software-disabled. |
157 | * [The UltraSPARC makes FP a precise trap; this isn't as stupid as it |
158 | * might sound because the Ultra does funky things with a superscalar |
159 | * architecture.] |
160 | */ |
161 | |
162 | /* You wouldn't believe how often I typed 'ftp' when I meant 'fpt' :-> */ |
163 | |
164 | int i; |
165 | int retcode = 0; /* assume all succeed */ |
166 | unsigned long insn; |
167 | |
168 | perf_sw_event(event_id: PERF_COUNT_SW_EMULATION_FAULTS, nr: 1, regs, addr: 0); |
169 | |
170 | #ifdef DEBUG_MATHEMU |
171 | printk("In do_mathemu()... pc is %08lx\n" , regs->pc); |
172 | printk("fpqdepth is %ld\n" , fpt->thread.fpqdepth); |
173 | for (i = 0; i < fpt->thread.fpqdepth; i++) |
174 | printk("%d: %08lx at %08lx\n" , i, fpt->thread.fpqueue[i].insn, |
175 | (unsigned long)fpt->thread.fpqueue[i].insn_addr); |
176 | #endif |
177 | |
178 | if (fpt->thread.fpqdepth == 0) { /* no queue, guilty insn is at regs->pc */ |
179 | #ifdef DEBUG_MATHEMU |
180 | printk("precise trap at %08lx\n" , regs->pc); |
181 | #endif |
182 | if (!get_user(insn, (u32 __user *) regs->pc)) { |
183 | retcode = do_one_mathemu(insn, fsr: &fpt->thread.fsr, fregs: fpt->thread.float_regs); |
184 | if (retcode) { |
185 | /* in this case we need to fix up PC & nPC */ |
186 | regs->pc = regs->npc; |
187 | regs->npc += 4; |
188 | } |
189 | } |
190 | return retcode; |
191 | } |
192 | |
193 | /* Normal case: need to empty the queue... */ |
194 | for (i = 0; i < fpt->thread.fpqdepth; i++) { |
195 | retcode = do_one_mathemu(insn: fpt->thread.fpqueue[i].insn, fsr: &(fpt->thread.fsr), fregs: fpt->thread.float_regs); |
196 | if (!retcode) /* insn failed, no point doing any more */ |
197 | break; |
198 | } |
199 | /* Now empty the queue and clear the queue_not_empty flag */ |
200 | if (retcode) |
201 | fpt->thread.fsr &= ~(0x3000 | FSR_CEXC_MASK); |
202 | else |
203 | fpt->thread.fsr &= ~0x3000; |
204 | fpt->thread.fpqdepth = 0; |
205 | |
206 | return retcode; |
207 | } |
208 | |
209 | /* All routines returning an exception to raise should detect |
210 | * such exceptions _before_ rounding to be consistent with |
211 | * the behavior of the hardware in the implemented cases |
212 | * (and thus with the recommendations in the V9 architecture |
213 | * manual). |
214 | * |
215 | * We return 0 if a SIGFPE should be sent, 1 otherwise. |
216 | */ |
217 | static inline int record_exception(unsigned long *pfsr, int eflag) |
218 | { |
219 | unsigned long fsr = *pfsr; |
220 | int would_trap; |
221 | |
222 | /* Determine if this exception would have generated a trap. */ |
223 | would_trap = (fsr & ((long)eflag << FSR_TEM_SHIFT)) != 0UL; |
224 | |
225 | /* If trapping, we only want to signal one bit. */ |
226 | if (would_trap != 0) { |
227 | eflag &= ((fsr & FSR_TEM_MASK) >> FSR_TEM_SHIFT); |
228 | if ((eflag & (eflag - 1)) != 0) { |
229 | if (eflag & FP_EX_INVALID) |
230 | eflag = FP_EX_INVALID; |
231 | else if (eflag & FP_EX_OVERFLOW) |
232 | eflag = FP_EX_OVERFLOW; |
233 | else if (eflag & FP_EX_UNDERFLOW) |
234 | eflag = FP_EX_UNDERFLOW; |
235 | else if (eflag & FP_EX_DIVZERO) |
236 | eflag = FP_EX_DIVZERO; |
237 | else if (eflag & FP_EX_INEXACT) |
238 | eflag = FP_EX_INEXACT; |
239 | } |
240 | } |
241 | |
242 | /* Set CEXC, here is the rule: |
243 | * |
244 | * In general all FPU ops will set one and only one |
245 | * bit in the CEXC field, this is always the case |
246 | * when the IEEE exception trap is enabled in TEM. |
247 | */ |
248 | fsr &= ~(FSR_CEXC_MASK); |
249 | fsr |= ((long)eflag << FSR_CEXC_SHIFT); |
250 | |
251 | /* Set the AEXC field, rule is: |
252 | * |
253 | * If a trap would not be generated, the |
254 | * CEXC just generated is OR'd into the |
255 | * existing value of AEXC. |
256 | */ |
257 | if (would_trap == 0) |
258 | fsr |= ((long)eflag << FSR_AEXC_SHIFT); |
259 | |
260 | /* If trapping, indicate fault trap type IEEE. */ |
261 | if (would_trap != 0) |
262 | fsr |= (1UL << 14); |
263 | |
264 | *pfsr = fsr; |
265 | |
266 | return (would_trap ? 0 : 1); |
267 | } |
268 | |
269 | typedef union { |
270 | u32 s; |
271 | u64 d; |
272 | u64 q[2]; |
273 | } *argp; |
274 | |
275 | static int do_one_mathemu(u32 insn, unsigned long *pfsr, unsigned long *fregs) |
276 | { |
277 | /* Emulate the given insn, updating fsr and fregs appropriately. */ |
278 | int type = 0; |
279 | /* r is rd, b is rs2 and a is rs1. The *u arg tells |
280 | whether the argument should be packed/unpacked (0 - do not unpack/pack, 1 - unpack/pack) |
281 | non-u args tells the size of the argument (0 - no argument, 1 - single, 2 - double, 3 - quad */ |
282 | #define TYPE(dummy, r, ru, b, bu, a, au) type = (au << 2) | (a << 0) | (bu << 5) | (b << 3) | (ru << 8) | (r << 6) |
283 | int freg; |
284 | argp rs1 = NULL, rs2 = NULL, rd = NULL; |
285 | FP_DECL_EX; |
286 | FP_DECL_S(SA); FP_DECL_S(SB); FP_DECL_S(SR); |
287 | FP_DECL_D(DA); FP_DECL_D(DB); FP_DECL_D(DR); |
288 | FP_DECL_Q(QA); FP_DECL_Q(QB); FP_DECL_Q(QR); |
289 | int IR; |
290 | long fsr; |
291 | |
292 | #ifdef DEBUG_MATHEMU |
293 | printk("In do_mathemu(), emulating %08lx\n" , insn); |
294 | #endif |
295 | |
296 | if ((insn & 0xc1f80000) == 0x81a00000) /* FPOP1 */ { |
297 | switch ((insn >> 5) & 0x1ff) { |
298 | case FSQRTQ: TYPE(3,3,1,3,1,0,0); break; |
299 | case FADDQ: |
300 | case FSUBQ: |
301 | case FMULQ: |
302 | case FDIVQ: TYPE(3,3,1,3,1,3,1); break; |
303 | case FDMULQ: TYPE(3,3,1,2,1,2,1); break; |
304 | case FQTOS: TYPE(3,1,1,3,1,0,0); break; |
305 | case FQTOD: TYPE(3,2,1,3,1,0,0); break; |
306 | case FITOQ: TYPE(3,3,1,1,0,0,0); break; |
307 | case FSTOQ: TYPE(3,3,1,1,1,0,0); break; |
308 | case FDTOQ: TYPE(3,3,1,2,1,0,0); break; |
309 | case FQTOI: TYPE(3,1,0,3,1,0,0); break; |
310 | case FSQRTS: TYPE(2,1,1,1,1,0,0); break; |
311 | case FSQRTD: TYPE(2,2,1,2,1,0,0); break; |
312 | case FADDD: |
313 | case FSUBD: |
314 | case FMULD: |
315 | case FDIVD: TYPE(2,2,1,2,1,2,1); break; |
316 | case FADDS: |
317 | case FSUBS: |
318 | case FMULS: |
319 | case FDIVS: TYPE(2,1,1,1,1,1,1); break; |
320 | case FSMULD: TYPE(2,2,1,1,1,1,1); break; |
321 | case FDTOS: TYPE(2,1,1,2,1,0,0); break; |
322 | case FSTOD: TYPE(2,2,1,1,1,0,0); break; |
323 | case FSTOI: TYPE(2,1,0,1,1,0,0); break; |
324 | case FDTOI: TYPE(2,1,0,2,1,0,0); break; |
325 | case FITOS: TYPE(2,1,1,1,0,0,0); break; |
326 | case FITOD: TYPE(2,2,1,1,0,0,0); break; |
327 | case FMOVS: |
328 | case FABSS: |
329 | case FNEGS: TYPE(2,1,0,1,0,0,0); break; |
330 | } |
331 | } else if ((insn & 0xc1f80000) == 0x81a80000) /* FPOP2 */ { |
332 | switch ((insn >> 5) & 0x1ff) { |
333 | case FCMPS: TYPE(3,0,0,1,1,1,1); break; |
334 | case FCMPES: TYPE(3,0,0,1,1,1,1); break; |
335 | case FCMPD: TYPE(3,0,0,2,1,2,1); break; |
336 | case FCMPED: TYPE(3,0,0,2,1,2,1); break; |
337 | case FCMPQ: TYPE(3,0,0,3,1,3,1); break; |
338 | case FCMPEQ: TYPE(3,0,0,3,1,3,1); break; |
339 | } |
340 | } |
341 | |
342 | if (!type) { /* oops, didn't recognise that FPop */ |
343 | #ifdef DEBUG_MATHEMU |
344 | printk("attempt to emulate unrecognised FPop!\n" ); |
345 | #endif |
346 | return 0; |
347 | } |
348 | |
349 | /* Decode the registers to be used */ |
350 | freg = (*pfsr >> 14) & 0xf; |
351 | |
352 | *pfsr &= ~0x1c000; /* clear the traptype bits */ |
353 | |
354 | freg = ((insn >> 14) & 0x1f); |
355 | switch (type & 0x3) { /* is rs1 single, double or quad? */ |
356 | case 3: |
357 | if (freg & 3) { /* quadwords must have bits 4&5 of the */ |
358 | /* encoded reg. number set to zero. */ |
359 | *pfsr |= (6 << 14); |
360 | return 0; /* simulate invalid_fp_register exception */ |
361 | } |
362 | fallthrough; |
363 | case 2: |
364 | if (freg & 1) { /* doublewords must have bit 5 zeroed */ |
365 | *pfsr |= (6 << 14); |
366 | return 0; |
367 | } |
368 | } |
369 | rs1 = (argp)&fregs[freg]; |
370 | switch (type & 0x7) { |
371 | case 7: FP_UNPACK_QP (QA, rs1); break; |
372 | case 6: FP_UNPACK_DP (DA, rs1); break; |
373 | case 5: FP_UNPACK_SP (SA, rs1); break; |
374 | } |
375 | freg = (insn & 0x1f); |
376 | switch ((type >> 3) & 0x3) { /* same again for rs2 */ |
377 | case 3: |
378 | if (freg & 3) { /* quadwords must have bits 4&5 of the */ |
379 | /* encoded reg. number set to zero. */ |
380 | *pfsr |= (6 << 14); |
381 | return 0; /* simulate invalid_fp_register exception */ |
382 | } |
383 | fallthrough; |
384 | case 2: |
385 | if (freg & 1) { /* doublewords must have bit 5 zeroed */ |
386 | *pfsr |= (6 << 14); |
387 | return 0; |
388 | } |
389 | } |
390 | rs2 = (argp)&fregs[freg]; |
391 | switch ((type >> 3) & 0x7) { |
392 | case 7: FP_UNPACK_QP (QB, rs2); break; |
393 | case 6: FP_UNPACK_DP (DB, rs2); break; |
394 | case 5: FP_UNPACK_SP (SB, rs2); break; |
395 | } |
396 | freg = ((insn >> 25) & 0x1f); |
397 | switch ((type >> 6) & 0x3) { /* and finally rd. This one's a bit different */ |
398 | case 0: /* dest is fcc. (this must be FCMPQ or FCMPEQ) */ |
399 | if (freg) { /* V8 has only one set of condition codes, so */ |
400 | /* anything but 0 in the rd field is an error */ |
401 | *pfsr |= (6 << 14); /* (should probably flag as invalid opcode */ |
402 | return 0; /* but SIGFPE will do :-> ) */ |
403 | } |
404 | break; |
405 | case 3: |
406 | if (freg & 3) { /* quadwords must have bits 4&5 of the */ |
407 | /* encoded reg. number set to zero. */ |
408 | *pfsr |= (6 << 14); |
409 | return 0; /* simulate invalid_fp_register exception */ |
410 | } |
411 | fallthrough; |
412 | case 2: |
413 | if (freg & 1) { /* doublewords must have bit 5 zeroed */ |
414 | *pfsr |= (6 << 14); |
415 | return 0; |
416 | } |
417 | fallthrough; |
418 | case 1: |
419 | rd = (void *)&fregs[freg]; |
420 | break; |
421 | } |
422 | #ifdef DEBUG_MATHEMU |
423 | printk("executing insn...\n" ); |
424 | #endif |
425 | /* do the Right Thing */ |
426 | switch ((insn >> 5) & 0x1ff) { |
427 | /* + */ |
428 | case FADDS: FP_ADD_S (SR, SA, SB); break; |
429 | case FADDD: FP_ADD_D (DR, DA, DB); break; |
430 | case FADDQ: FP_ADD_Q (QR, QA, QB); break; |
431 | /* - */ |
432 | case FSUBS: FP_SUB_S (SR, SA, SB); break; |
433 | case FSUBD: FP_SUB_D (DR, DA, DB); break; |
434 | case FSUBQ: FP_SUB_Q (QR, QA, QB); break; |
435 | /* * */ |
436 | case FMULS: FP_MUL_S (SR, SA, SB); break; |
437 | case FSMULD: FP_CONV (D, S, 2, 1, DA, SA); |
438 | FP_CONV (D, S, 2, 1, DB, SB); |
439 | case FMULD: FP_MUL_D (DR, DA, DB); break; |
440 | case FDMULQ: FP_CONV (Q, D, 4, 2, QA, DA); |
441 | FP_CONV (Q, D, 4, 2, QB, DB); |
442 | case FMULQ: FP_MUL_Q (QR, QA, QB); break; |
443 | /* / */ |
444 | case FDIVS: FP_DIV_S (SR, SA, SB); break; |
445 | case FDIVD: FP_DIV_D (DR, DA, DB); break; |
446 | case FDIVQ: FP_DIV_Q (QR, QA, QB); break; |
447 | /* sqrt */ |
448 | case FSQRTS: FP_SQRT_S (SR, SB); break; |
449 | case FSQRTD: FP_SQRT_D (DR, DB); break; |
450 | case FSQRTQ: FP_SQRT_Q (QR, QB); break; |
451 | /* mov */ |
452 | case FMOVS: rd->s = rs2->s; break; |
453 | case FABSS: rd->s = rs2->s & 0x7fffffff; break; |
454 | case FNEGS: rd->s = rs2->s ^ 0x80000000; break; |
455 | /* float to int */ |
456 | case FSTOI: FP_TO_INT_S (IR, SB, 32, 1); break; |
457 | case FDTOI: FP_TO_INT_D (IR, DB, 32, 1); break; |
458 | case FQTOI: FP_TO_INT_Q (IR, QB, 32, 1); break; |
459 | /* int to float */ |
460 | case FITOS: IR = rs2->s; FP_FROM_INT_S (SR, IR, 32, int); break; |
461 | case FITOD: IR = rs2->s; FP_FROM_INT_D (DR, IR, 32, int); break; |
462 | case FITOQ: IR = rs2->s; FP_FROM_INT_Q (QR, IR, 32, int); break; |
463 | /* float to float */ |
464 | case FSTOD: FP_CONV (D, S, 2, 1, DR, SB); break; |
465 | case FSTOQ: FP_CONV (Q, S, 4, 1, QR, SB); break; |
466 | case FDTOQ: FP_CONV (Q, D, 4, 2, QR, DB); break; |
467 | case FDTOS: FP_CONV (S, D, 1, 2, SR, DB); break; |
468 | case FQTOS: FP_CONV (S, Q, 1, 4, SR, QB); break; |
469 | case FQTOD: FP_CONV (D, Q, 2, 4, DR, QB); break; |
470 | /* comparison */ |
471 | case FCMPS: |
472 | case FCMPES: |
473 | FP_CMP_S(IR, SB, SA, 3); |
474 | if (IR == 3 && |
475 | (((insn >> 5) & 0x1ff) == FCMPES || |
476 | FP_ISSIGNAN_S(SA) || |
477 | FP_ISSIGNAN_S(SB))) |
478 | FP_SET_EXCEPTION (FP_EX_INVALID); |
479 | break; |
480 | case FCMPD: |
481 | case FCMPED: |
482 | FP_CMP_D(IR, DB, DA, 3); |
483 | if (IR == 3 && |
484 | (((insn >> 5) & 0x1ff) == FCMPED || |
485 | FP_ISSIGNAN_D(DA) || |
486 | FP_ISSIGNAN_D(DB))) |
487 | FP_SET_EXCEPTION (FP_EX_INVALID); |
488 | break; |
489 | case FCMPQ: |
490 | case FCMPEQ: |
491 | FP_CMP_Q(IR, QB, QA, 3); |
492 | if (IR == 3 && |
493 | (((insn >> 5) & 0x1ff) == FCMPEQ || |
494 | FP_ISSIGNAN_Q(QA) || |
495 | FP_ISSIGNAN_Q(QB))) |
496 | FP_SET_EXCEPTION (FP_EX_INVALID); |
497 | } |
498 | if (!FP_INHIBIT_RESULTS) { |
499 | switch ((type >> 6) & 0x7) { |
500 | case 0: fsr = *pfsr; |
501 | if (IR == -1) IR = 2; |
502 | /* fcc is always fcc0 */ |
503 | fsr &= ~0xc00; fsr |= (IR << 10); |
504 | *pfsr = fsr; |
505 | break; |
506 | case 1: rd->s = IR; break; |
507 | case 5: FP_PACK_SP (rd, SR); break; |
508 | case 6: FP_PACK_DP (rd, DR); break; |
509 | case 7: FP_PACK_QP (rd, QR); break; |
510 | } |
511 | } |
512 | if (_fex == 0) |
513 | return 1; /* success! */ |
514 | return record_exception(pfsr, eflag: _fex); |
515 | } |
516 | |