1 | // SPDX-License-Identifier: GPL-2.0 |
2 | #include <linux/clk-provider.h> |
3 | #include <linux/mfd/syscon.h> |
4 | #include <linux/slab.h> |
5 | |
6 | #include <dt-bindings/clock/at91.h> |
7 | |
8 | #include "pmc.h" |
9 | |
10 | static DEFINE_SPINLOCK(rm9200_mck_lock); |
11 | |
12 | struct sck { |
13 | char *n; |
14 | char *p; |
15 | u8 id; |
16 | }; |
17 | |
18 | struct pck { |
19 | char *n; |
20 | u8 id; |
21 | }; |
22 | |
23 | static const struct clk_master_characteristics rm9200_mck_characteristics = { |
24 | .output = { .min = 0, .max = 80000000 }, |
25 | .divisors = { 1, 2, 3, 4 }, |
26 | }; |
27 | |
28 | static u8 rm9200_pll_out[] = { 0, 2 }; |
29 | |
30 | static const struct clk_range rm9200_pll_outputs[] = { |
31 | { .min = 80000000, .max = 160000000 }, |
32 | { .min = 150000000, .max = 180000000 }, |
33 | }; |
34 | |
35 | static const struct clk_pll_characteristics rm9200_pll_characteristics = { |
36 | .input = { .min = 1000000, .max = 32000000 }, |
37 | .num_output = ARRAY_SIZE(rm9200_pll_outputs), |
38 | .output = rm9200_pll_outputs, |
39 | .out = rm9200_pll_out, |
40 | }; |
41 | |
42 | static const struct sck at91rm9200_systemck[] = { |
43 | { .n = "udpck" , .p = "usbck" , .id = 1 }, |
44 | { .n = "uhpck" , .p = "usbck" , .id = 4 }, |
45 | { .n = "pck0" , .p = "prog0" , .id = 8 }, |
46 | { .n = "pck1" , .p = "prog1" , .id = 9 }, |
47 | { .n = "pck2" , .p = "prog2" , .id = 10 }, |
48 | { .n = "pck3" , .p = "prog3" , .id = 11 }, |
49 | }; |
50 | |
51 | static const struct pck at91rm9200_periphck[] = { |
52 | { .n = "pioA_clk" , .id = 2 }, |
53 | { .n = "pioB_clk" , .id = 3 }, |
54 | { .n = "pioC_clk" , .id = 4 }, |
55 | { .n = "pioD_clk" , .id = 5 }, |
56 | { .n = "usart0_clk" , .id = 6 }, |
57 | { .n = "usart1_clk" , .id = 7 }, |
58 | { .n = "usart2_clk" , .id = 8 }, |
59 | { .n = "usart3_clk" , .id = 9 }, |
60 | { .n = "mci0_clk" , .id = 10 }, |
61 | { .n = "udc_clk" , .id = 11 }, |
62 | { .n = "twi0_clk" , .id = 12 }, |
63 | { .n = "spi0_clk" , .id = 13 }, |
64 | { .n = "ssc0_clk" , .id = 14 }, |
65 | { .n = "ssc1_clk" , .id = 15 }, |
66 | { .n = "ssc2_clk" , .id = 16 }, |
67 | { .n = "tc0_clk" , .id = 17 }, |
68 | { .n = "tc1_clk" , .id = 18 }, |
69 | { .n = "tc2_clk" , .id = 19 }, |
70 | { .n = "tc3_clk" , .id = 20 }, |
71 | { .n = "tc4_clk" , .id = 21 }, |
72 | { .n = "tc5_clk" , .id = 22 }, |
73 | { .n = "ohci_clk" , .id = 23 }, |
74 | { .n = "macb0_clk" , .id = 24 }, |
75 | }; |
76 | |
77 | static void __init at91rm9200_pmc_setup(struct device_node *np) |
78 | { |
79 | const char *slowxtal_name, *mainxtal_name; |
80 | struct pmc_data *at91rm9200_pmc; |
81 | u32 usb_div[] = { 1, 2, 0, 0 }; |
82 | const char *parent_names[6]; |
83 | struct regmap *regmap; |
84 | struct clk_hw *hw; |
85 | int i; |
86 | bool bypass; |
87 | |
88 | i = of_property_match_string(np, propname: "clock-names" , string: "slow_xtal" ); |
89 | if (i < 0) |
90 | return; |
91 | |
92 | slowxtal_name = of_clk_get_parent_name(np, index: i); |
93 | |
94 | i = of_property_match_string(np, propname: "clock-names" , string: "main_xtal" ); |
95 | if (i < 0) |
96 | return; |
97 | mainxtal_name = of_clk_get_parent_name(np, index: i); |
98 | |
99 | regmap = device_node_to_regmap(np); |
100 | if (IS_ERR(ptr: regmap)) |
101 | return; |
102 | |
103 | at91rm9200_pmc = pmc_data_allocate(PMC_PLLBCK + 1, |
104 | nck(at91rm9200_systemck), |
105 | nck(at91rm9200_periphck), ngck: 0, npck: 4); |
106 | if (!at91rm9200_pmc) |
107 | return; |
108 | |
109 | bypass = of_property_read_bool(np, propname: "atmel,osc-bypass" ); |
110 | |
111 | hw = at91_clk_register_main_osc(regmap, name: "main_osc" , parent_name: mainxtal_name, NULL, |
112 | bypass); |
113 | if (IS_ERR(ptr: hw)) |
114 | goto err_free; |
115 | |
116 | hw = at91_clk_register_rm9200_main(regmap, name: "mainck" , parent_name: "main_osc" , NULL); |
117 | if (IS_ERR(ptr: hw)) |
118 | goto err_free; |
119 | |
120 | at91rm9200_pmc->chws[PMC_MAIN] = hw; |
121 | |
122 | hw = at91_clk_register_pll(regmap, name: "pllack" , parent_name: "mainck" , id: 0, |
123 | layout: &at91rm9200_pll_layout, |
124 | characteristics: &rm9200_pll_characteristics); |
125 | if (IS_ERR(ptr: hw)) |
126 | goto err_free; |
127 | |
128 | at91rm9200_pmc->chws[PMC_PLLACK] = hw; |
129 | |
130 | hw = at91_clk_register_pll(regmap, name: "pllbck" , parent_name: "mainck" , id: 1, |
131 | layout: &at91rm9200_pll_layout, |
132 | characteristics: &rm9200_pll_characteristics); |
133 | if (IS_ERR(ptr: hw)) |
134 | goto err_free; |
135 | |
136 | at91rm9200_pmc->chws[PMC_PLLBCK] = hw; |
137 | |
138 | parent_names[0] = slowxtal_name; |
139 | parent_names[1] = "mainck" ; |
140 | parent_names[2] = "pllack" ; |
141 | parent_names[3] = "pllbck" ; |
142 | hw = at91_clk_register_master_pres(regmap, name: "masterck_pres" , num_parents: 4, |
143 | parent_names, NULL, |
144 | layout: &at91rm9200_master_layout, |
145 | characteristics: &rm9200_mck_characteristics, |
146 | lock: &rm9200_mck_lock); |
147 | if (IS_ERR(ptr: hw)) |
148 | goto err_free; |
149 | |
150 | hw = at91_clk_register_master_div(regmap, name: "masterck_div" , |
151 | parent_names: "masterck_pres" , NULL, |
152 | layout: &at91rm9200_master_layout, |
153 | characteristics: &rm9200_mck_characteristics, |
154 | lock: &rm9200_mck_lock, CLK_SET_RATE_GATE, safe_div: 0); |
155 | if (IS_ERR(ptr: hw)) |
156 | goto err_free; |
157 | |
158 | at91rm9200_pmc->chws[PMC_MCK] = hw; |
159 | |
160 | hw = at91rm9200_clk_register_usb(regmap, name: "usbck" , parent_name: "pllbck" , divisors: usb_div); |
161 | if (IS_ERR(ptr: hw)) |
162 | goto err_free; |
163 | |
164 | parent_names[0] = slowxtal_name; |
165 | parent_names[1] = "mainck" ; |
166 | parent_names[2] = "pllack" ; |
167 | parent_names[3] = "pllbck" ; |
168 | for (i = 0; i < 4; i++) { |
169 | char name[6]; |
170 | |
171 | snprintf(buf: name, size: sizeof(name), fmt: "prog%d" , i); |
172 | |
173 | hw = at91_clk_register_programmable(regmap, name, |
174 | parent_names, NULL, num_parents: 4, id: i, |
175 | layout: &at91rm9200_programmable_layout, |
176 | NULL); |
177 | if (IS_ERR(ptr: hw)) |
178 | goto err_free; |
179 | |
180 | at91rm9200_pmc->pchws[i] = hw; |
181 | } |
182 | |
183 | for (i = 0; i < ARRAY_SIZE(at91rm9200_systemck); i++) { |
184 | hw = at91_clk_register_system(regmap, name: at91rm9200_systemck[i].n, |
185 | parent_name: at91rm9200_systemck[i].p, NULL, |
186 | id: at91rm9200_systemck[i].id, flags: 0); |
187 | if (IS_ERR(ptr: hw)) |
188 | goto err_free; |
189 | |
190 | at91rm9200_pmc->shws[at91rm9200_systemck[i].id] = hw; |
191 | } |
192 | |
193 | for (i = 0; i < ARRAY_SIZE(at91rm9200_periphck); i++) { |
194 | hw = at91_clk_register_peripheral(regmap, |
195 | name: at91rm9200_periphck[i].n, |
196 | parent_name: "masterck_div" , NULL, |
197 | id: at91rm9200_periphck[i].id); |
198 | if (IS_ERR(ptr: hw)) |
199 | goto err_free; |
200 | |
201 | at91rm9200_pmc->phws[at91rm9200_periphck[i].id] = hw; |
202 | } |
203 | |
204 | of_clk_add_hw_provider(np, get: of_clk_hw_pmc_get, data: at91rm9200_pmc); |
205 | |
206 | return; |
207 | |
208 | err_free: |
209 | kfree(objp: at91rm9200_pmc); |
210 | } |
211 | /* |
212 | * While the TCB can be used as the clocksource, the system timer is most likely |
213 | * to be used instead. However, the pinctrl driver doesn't support probe |
214 | * deferring properly. Once this is fixed, this can be switched to a platform |
215 | * driver. |
216 | */ |
217 | CLK_OF_DECLARE(at91rm9200_pmc, "atmel,at91rm9200-pmc" , at91rm9200_pmc_setup); |
218 | |