1 | // SPDX-License-Identifier: GPL-2.0 |
2 | #include <linux/clk-provider.h> |
3 | #include <linux/mfd/syscon.h> |
4 | #include <linux/slab.h> |
5 | |
6 | #include <dt-bindings/clock/at91.h> |
7 | |
8 | #include "pmc.h" |
9 | |
10 | static DEFINE_SPINLOCK(mck_lock); |
11 | |
12 | static const struct clk_master_characteristics mck_characteristics = { |
13 | .output = { .min = 0, .max = 166000000 }, |
14 | .divisors = { 1, 2, 4, 3 }, |
15 | }; |
16 | |
17 | static u8 plla_out[] = { 0 }; |
18 | |
19 | static u16 plla_icpll[] = { 0 }; |
20 | |
21 | static const struct clk_range plla_outputs[] = { |
22 | { .min = 400000000, .max = 1000000000 }, |
23 | }; |
24 | |
25 | static const struct clk_pll_characteristics plla_characteristics = { |
26 | .input = { .min = 8000000, .max = 50000000 }, |
27 | .num_output = ARRAY_SIZE(plla_outputs), |
28 | .output = plla_outputs, |
29 | .icpll = plla_icpll, |
30 | .out = plla_out, |
31 | }; |
32 | |
33 | static const struct clk_pcr_layout sama5d3_pcr_layout = { |
34 | .offset = 0x10c, |
35 | .cmd = BIT(12), |
36 | .pid_mask = GENMASK(6, 0), |
37 | .div_mask = GENMASK(17, 16), |
38 | }; |
39 | |
40 | static const struct { |
41 | char *n; |
42 | char *p; |
43 | unsigned long flags; |
44 | u8 id; |
45 | } sama5d3_systemck[] = { |
46 | /* |
47 | * ddrck feeds DDR controller and is enabled by bootloader thus we need |
48 | * to keep it enabled in case there is no Linux consumer for it. |
49 | */ |
50 | { .n = "ddrck" , .p = "masterck_div" , .id = 2, .flags = CLK_IS_CRITICAL }, |
51 | { .n = "lcdck" , .p = "masterck_div" , .id = 3 }, |
52 | { .n = "smdck" , .p = "smdclk" , .id = 4 }, |
53 | { .n = "uhpck" , .p = "usbck" , .id = 6 }, |
54 | { .n = "udpck" , .p = "usbck" , .id = 7 }, |
55 | { .n = "pck0" , .p = "prog0" , .id = 8 }, |
56 | { .n = "pck1" , .p = "prog1" , .id = 9 }, |
57 | { .n = "pck2" , .p = "prog2" , .id = 10 }, |
58 | }; |
59 | |
60 | static const struct { |
61 | char *n; |
62 | u8 id; |
63 | struct clk_range r; |
64 | unsigned long flags; |
65 | } sama5d3_periphck[] = { |
66 | { .n = "dbgu_clk" , .id = 2, }, |
67 | { .n = "hsmc_clk" , .id = 5, }, |
68 | { .n = "pioA_clk" , .id = 6, }, |
69 | { .n = "pioB_clk" , .id = 7, }, |
70 | { .n = "pioC_clk" , .id = 8, }, |
71 | { .n = "pioD_clk" , .id = 9, }, |
72 | { .n = "pioE_clk" , .id = 10, }, |
73 | { .n = "usart0_clk" , .id = 12, .r = { .min = 0, .max = 83000000 }, }, |
74 | { .n = "usart1_clk" , .id = 13, .r = { .min = 0, .max = 83000000 }, }, |
75 | { .n = "usart2_clk" , .id = 14, .r = { .min = 0, .max = 83000000 }, }, |
76 | { .n = "usart3_clk" , .id = 15, .r = { .min = 0, .max = 83000000 }, }, |
77 | { .n = "uart0_clk" , .id = 16, .r = { .min = 0, .max = 83000000 }, }, |
78 | { .n = "uart1_clk" , .id = 17, .r = { .min = 0, .max = 83000000 }, }, |
79 | { .n = "twi0_clk" , .id = 18, .r = { .min = 0, .max = 41500000 }, }, |
80 | { .n = "twi1_clk" , .id = 19, .r = { .min = 0, .max = 41500000 }, }, |
81 | { .n = "twi2_clk" , .id = 20, .r = { .min = 0, .max = 41500000 }, }, |
82 | { .n = "mci0_clk" , .id = 21, }, |
83 | { .n = "mci1_clk" , .id = 22, }, |
84 | { .n = "mci2_clk" , .id = 23, }, |
85 | { .n = "spi0_clk" , .id = 24, .r = { .min = 0, .max = 166000000 }, }, |
86 | { .n = "spi1_clk" , .id = 25, .r = { .min = 0, .max = 166000000 }, }, |
87 | { .n = "tcb0_clk" , .id = 26, .r = { .min = 0, .max = 166000000 }, }, |
88 | { .n = "tcb1_clk" , .id = 27, .r = { .min = 0, .max = 166000000 }, }, |
89 | { .n = "pwm_clk" , .id = 28, }, |
90 | { .n = "adc_clk" , .id = 29, .r = { .min = 0, .max = 83000000 }, }, |
91 | { .n = "dma0_clk" , .id = 30, }, |
92 | { .n = "dma1_clk" , .id = 31, }, |
93 | { .n = "uhphs_clk" , .id = 32, }, |
94 | { .n = "udphs_clk" , .id = 33, }, |
95 | { .n = "macb0_clk" , .id = 34, }, |
96 | { .n = "macb1_clk" , .id = 35, }, |
97 | { .n = "lcdc_clk" , .id = 36, }, |
98 | { .n = "isi_clk" , .id = 37, }, |
99 | { .n = "ssc0_clk" , .id = 38, .r = { .min = 0, .max = 83000000 }, }, |
100 | { .n = "ssc1_clk" , .id = 39, .r = { .min = 0, .max = 83000000 }, }, |
101 | { .n = "can0_clk" , .id = 40, .r = { .min = 0, .max = 83000000 }, }, |
102 | { .n = "can1_clk" , .id = 41, .r = { .min = 0, .max = 83000000 }, }, |
103 | { .n = "sha_clk" , .id = 42, }, |
104 | { .n = "aes_clk" , .id = 43, }, |
105 | { .n = "tdes_clk" , .id = 44, }, |
106 | { .n = "trng_clk" , .id = 45, }, |
107 | { .n = "fuse_clk" , .id = 48, }, |
108 | /* |
109 | * mpddr_clk feeds DDR controller and is enabled by bootloader thus we |
110 | * need to keep it enabled in case there is no Linux consumer for it. |
111 | */ |
112 | { .n = "mpddr_clk" , .id = 49, .flags = CLK_IS_CRITICAL }, |
113 | }; |
114 | |
115 | static void __init sama5d3_pmc_setup(struct device_node *np) |
116 | { |
117 | const char *slck_name, *mainxtal_name; |
118 | struct pmc_data *sama5d3_pmc; |
119 | const char *parent_names[5]; |
120 | struct regmap *regmap; |
121 | struct clk_hw *hw; |
122 | int i; |
123 | bool bypass; |
124 | |
125 | i = of_property_match_string(np, propname: "clock-names" , string: "slow_clk" ); |
126 | if (i < 0) |
127 | return; |
128 | |
129 | slck_name = of_clk_get_parent_name(np, index: i); |
130 | |
131 | i = of_property_match_string(np, propname: "clock-names" , string: "main_xtal" ); |
132 | if (i < 0) |
133 | return; |
134 | mainxtal_name = of_clk_get_parent_name(np, index: i); |
135 | |
136 | regmap = device_node_to_regmap(np); |
137 | if (IS_ERR(ptr: regmap)) |
138 | return; |
139 | |
140 | sama5d3_pmc = pmc_data_allocate(PMC_PLLACK + 1, |
141 | nck(sama5d3_systemck), |
142 | nck(sama5d3_periphck), ngck: 0, npck: 3); |
143 | if (!sama5d3_pmc) |
144 | return; |
145 | |
146 | hw = at91_clk_register_main_rc_osc(regmap, name: "main_rc_osc" , frequency: 12000000, |
147 | accuracy: 50000000); |
148 | if (IS_ERR(ptr: hw)) |
149 | goto err_free; |
150 | |
151 | bypass = of_property_read_bool(np, propname: "atmel,osc-bypass" ); |
152 | |
153 | hw = at91_clk_register_main_osc(regmap, name: "main_osc" , parent_name: mainxtal_name, NULL, |
154 | bypass); |
155 | if (IS_ERR(ptr: hw)) |
156 | goto err_free; |
157 | |
158 | parent_names[0] = "main_rc_osc" ; |
159 | parent_names[1] = "main_osc" ; |
160 | hw = at91_clk_register_sam9x5_main(regmap, name: "mainck" , parent_names, NULL, num_parents: 2); |
161 | if (IS_ERR(ptr: hw)) |
162 | goto err_free; |
163 | |
164 | hw = at91_clk_register_pll(regmap, name: "pllack" , parent_name: "mainck" , id: 0, |
165 | layout: &sama5d3_pll_layout, characteristics: &plla_characteristics); |
166 | if (IS_ERR(ptr: hw)) |
167 | goto err_free; |
168 | |
169 | hw = at91_clk_register_plldiv(regmap, name: "plladivck" , parent_name: "pllack" ); |
170 | if (IS_ERR(ptr: hw)) |
171 | goto err_free; |
172 | |
173 | sama5d3_pmc->chws[PMC_PLLACK] = hw; |
174 | |
175 | hw = at91_clk_register_utmi(regmap_pmc: regmap, NULL, name: "utmick" , parent_name: "mainck" , NULL); |
176 | if (IS_ERR(ptr: hw)) |
177 | goto err_free; |
178 | |
179 | sama5d3_pmc->chws[PMC_UTMI] = hw; |
180 | |
181 | parent_names[0] = slck_name; |
182 | parent_names[1] = "mainck" ; |
183 | parent_names[2] = "plladivck" ; |
184 | parent_names[3] = "utmick" ; |
185 | hw = at91_clk_register_master_pres(regmap, name: "masterck_pres" , num_parents: 4, |
186 | parent_names, NULL, |
187 | layout: &at91sam9x5_master_layout, |
188 | characteristics: &mck_characteristics, lock: &mck_lock); |
189 | if (IS_ERR(ptr: hw)) |
190 | goto err_free; |
191 | |
192 | hw = at91_clk_register_master_div(regmap, name: "masterck_div" , |
193 | parent_names: "masterck_pres" , NULL, |
194 | layout: &at91sam9x5_master_layout, |
195 | characteristics: &mck_characteristics, lock: &mck_lock, |
196 | CLK_SET_RATE_GATE, safe_div: 0); |
197 | if (IS_ERR(ptr: hw)) |
198 | goto err_free; |
199 | |
200 | sama5d3_pmc->chws[PMC_MCK] = hw; |
201 | |
202 | parent_names[0] = "plladivck" ; |
203 | parent_names[1] = "utmick" ; |
204 | hw = at91sam9x5_clk_register_usb(regmap, name: "usbck" , parent_names, num_parents: 2); |
205 | if (IS_ERR(ptr: hw)) |
206 | goto err_free; |
207 | |
208 | hw = at91sam9x5_clk_register_smd(regmap, name: "smdclk" , parent_names, num_parents: 2); |
209 | if (IS_ERR(ptr: hw)) |
210 | goto err_free; |
211 | |
212 | parent_names[0] = slck_name; |
213 | parent_names[1] = "mainck" ; |
214 | parent_names[2] = "plladivck" ; |
215 | parent_names[3] = "utmick" ; |
216 | parent_names[4] = "masterck_div" ; |
217 | for (i = 0; i < 3; i++) { |
218 | char name[6]; |
219 | |
220 | snprintf(buf: name, size: sizeof(name), fmt: "prog%d" , i); |
221 | |
222 | hw = at91_clk_register_programmable(regmap, name, |
223 | parent_names, NULL, num_parents: 5, id: i, |
224 | layout: &at91sam9x5_programmable_layout, |
225 | NULL); |
226 | if (IS_ERR(ptr: hw)) |
227 | goto err_free; |
228 | |
229 | sama5d3_pmc->pchws[i] = hw; |
230 | } |
231 | |
232 | for (i = 0; i < ARRAY_SIZE(sama5d3_systemck); i++) { |
233 | hw = at91_clk_register_system(regmap, name: sama5d3_systemck[i].n, |
234 | parent_name: sama5d3_systemck[i].p, NULL, |
235 | id: sama5d3_systemck[i].id, |
236 | flags: sama5d3_systemck[i].flags); |
237 | if (IS_ERR(ptr: hw)) |
238 | goto err_free; |
239 | |
240 | sama5d3_pmc->shws[sama5d3_systemck[i].id] = hw; |
241 | } |
242 | |
243 | for (i = 0; i < ARRAY_SIZE(sama5d3_periphck); i++) { |
244 | hw = at91_clk_register_sam9x5_peripheral(regmap, lock: &pmc_pcr_lock, |
245 | layout: &sama5d3_pcr_layout, |
246 | name: sama5d3_periphck[i].n, |
247 | parent_name: "masterck_div" , NULL, |
248 | id: sama5d3_periphck[i].id, |
249 | range: &sama5d3_periphck[i].r, |
250 | INT_MIN, |
251 | flags: sama5d3_periphck[i].flags); |
252 | if (IS_ERR(ptr: hw)) |
253 | goto err_free; |
254 | |
255 | sama5d3_pmc->phws[sama5d3_periphck[i].id] = hw; |
256 | } |
257 | |
258 | of_clk_add_hw_provider(np, get: of_clk_hw_pmc_get, data: sama5d3_pmc); |
259 | |
260 | return; |
261 | |
262 | err_free: |
263 | kfree(objp: sama5d3_pmc); |
264 | } |
265 | /* |
266 | * The TCB is used as the clocksource so its clock is needed early. This means |
267 | * this can't be a platform driver. |
268 | */ |
269 | CLK_OF_DECLARE(sama5d3_pmc, "atmel,sama5d3-pmc" , sama5d3_pmc_setup); |
270 | |