1 | // SPDX-License-Identifier: GPL-2.0-or-later |
2 | /* |
3 | * Copyright (C) 2015 Freescale Semiconductor, Inc. |
4 | */ |
5 | |
6 | #include <dt-bindings/clock/imx6ul-clock.h> |
7 | #include <linux/clk.h> |
8 | #include <linux/clkdev.h> |
9 | #include <linux/clk-provider.h> |
10 | #include <linux/err.h> |
11 | #include <linux/init.h> |
12 | #include <linux/io.h> |
13 | #include <linux/mfd/syscon/imx6q-iomuxc-gpr.h> |
14 | #include <linux/of.h> |
15 | #include <linux/of_address.h> |
16 | #include <linux/of_irq.h> |
17 | #include <linux/types.h> |
18 | |
19 | #include "clk.h" |
20 | |
21 | static const char *pll_bypass_src_sels[] = { "osc" , "dummy" , }; |
22 | static const char *pll1_bypass_sels[] = { "pll1" , "pll1_bypass_src" , }; |
23 | static const char *pll2_bypass_sels[] = { "pll2" , "pll2_bypass_src" , }; |
24 | static const char *pll3_bypass_sels[] = { "pll3" , "pll3_bypass_src" , }; |
25 | static const char *pll4_bypass_sels[] = { "pll4" , "pll4_bypass_src" , }; |
26 | static const char *pll5_bypass_sels[] = { "pll5" , "pll5_bypass_src" , }; |
27 | static const char *pll6_bypass_sels[] = { "pll6" , "pll6_bypass_src" , }; |
28 | static const char *pll7_bypass_sels[] = { "pll7" , "pll7_bypass_src" , }; |
29 | static const char *ca7_secondary_sels[] = { "pll2_pfd2_396m" , "pll2_bus" , }; |
30 | static const char *step_sels[] = { "osc" , "ca7_secondary_sel" , }; |
31 | static const char *pll1_sw_sels[] = { "pll1_sys" , "step" , }; |
32 | static const char *axi_alt_sels[] = { "pll2_pfd2_396m" , "pll3_pfd1_540m" , }; |
33 | static const char *axi_sels[] = {"periph" , "axi_alt_sel" , }; |
34 | static const char *periph_pre_sels[] = { "pll2_bus" , "pll2_pfd2_396m" , "pll2_pfd0_352m" , "pll2_198m" , }; |
35 | static const char *periph2_pre_sels[] = { "pll2_bus" , "pll2_pfd2_396m" , "pll2_pfd0_352m" , "pll4_audio_div" , }; |
36 | static const char *periph_clk2_sels[] = { "pll3_usb_otg" , "osc" , "pll2_bypass_src" , }; |
37 | static const char *periph2_clk2_sels[] = { "pll3_usb_otg" , "osc" , }; |
38 | static const char *periph_sels[] = { "periph_pre" , "periph_clk2" , }; |
39 | static const char *periph2_sels[] = { "periph2_pre" , "periph2_clk2" , }; |
40 | static const char *usdhc_sels[] = { "pll2_pfd2_396m" , "pll2_pfd0_352m" , }; |
41 | static const char *bch_sels[] = { "pll2_pfd2_396m" , "pll2_pfd0_352m" , }; |
42 | static const char *gpmi_sels[] = { "pll2_pfd2_396m" , "pll2_pfd0_352m" , }; |
43 | static const char *eim_slow_sels[] = { "axi" , "pll3_usb_otg" , "pll2_pfd2_396m" , "pll3_pfd0_720m" , }; |
44 | static const char *spdif_sels[] = { "pll4_audio_div" , "pll3_pfd2_508m" , "pll5_video_div" , "pll3_usb_otg" , }; |
45 | static const char *sai_sels[] = { "pll3_pfd2_508m" , "pll5_video_div" , "pll4_audio_div" , }; |
46 | static const char *lcdif_pre_sels[] = { "pll2_bus" , "pll3_pfd3_454m" , "pll5_video_div" , "pll2_pfd0_352m" , "pll2_pfd1_594m" , "pll3_pfd1_540m" , }; |
47 | static const char *sim_pre_sels[] = { "pll2_bus" , "pll3_usb_otg" , "pll5_video_div" , "pll2_pfd0_352m" , "pll2_pfd2_396m" , "pll3_pfd2_508m" , }; |
48 | static const char *ldb_di0_sels[] = { "pll5_video_div" , "pll2_pfd0_352m" , "pll2_pfd2_396m" , "pll2_pfd3_594m" , "pll2_pfd1_594m" , "pll3_pfd3_454m" , }; |
49 | static const char *ldb_di0_div_sels[] = { "ldb_di0_div_3_5" , "ldb_di0_div_7" , }; |
50 | static const char *ldb_di1_div_sels[] = { "ldb_di1_div_3_5" , "ldb_di1_div_7" , }; |
51 | static const char *qspi1_sels[] = { "pll3_usb_otg" , "pll2_pfd0_352m" , "pll2_pfd2_396m" , "pll2_bus" , "pll3_pfd3_454m" , "pll3_pfd2_508m" , }; |
52 | static const char *enfc_sels[] = { "pll2_pfd0_352m" , "pll2_bus" , "pll3_usb_otg" , "pll2_pfd2_396m" , "pll3_pfd3_454m" , "dummy" , "dummy" , "dummy" , }; |
53 | static const char *can_sels[] = { "pll3_60m" , "osc" , "pll3_80m" , "dummy" , }; |
54 | static const char *ecspi_sels[] = { "pll3_60m" , "osc" , }; |
55 | static const char *uart_sels[] = { "pll3_80m" , "osc" , }; |
56 | static const char *perclk_sels[] = { "ipg" , "osc" , }; |
57 | static const char *lcdif_sels[] = { "lcdif_podf" , "ipp_di0" , "ipp_di1" , "ldb_di0" , "ldb_di1" , }; |
58 | static const char *csi_sels[] = { "osc" , "pll2_pfd2_396m" , "pll3_120m" , "pll3_pfd1_540m" , }; |
59 | static const char *sim_sels[] = { "sim_podf" , "ipp_di0" , "ipp_di1" , "ldb_di0" , "ldb_di1" , }; |
60 | /* epdc_pre_sels, epdc_sels, esai_sels only exists on i.MX6ULL */ |
61 | static const char *epdc_pre_sels[] = { "pll2_bus" , "pll3_usb_otg" , "pll5_video_div" , "pll2_pfd0_352m" , "pll2_pfd2_396m" , "pll3_pfd2_508m" , }; |
62 | static const char *esai_sels[] = { "pll4_audio_div" , "pll3_pfd2_508m" , "pll5_video_div" , "pll3_usb_otg" , }; |
63 | static const char *epdc_sels[] = { "epdc_podf" , "ipp_di0" , "ipp_di1" , "ldb_di0" , "ldb_di1" , }; |
64 | static const char *cko1_sels[] = { "dummy" , "dummy" , "dummy" , "dummy" , "dummy" , "axi" , "enfc" , "dummy" , "dummy" , |
65 | "dummy" , "lcdif_pix" , "ahb" , "ipg" , "ipg_per" , "ckil" , "pll4_audio_div" , }; |
66 | static const char *cko2_sels[] = { "dummy" , "dummy" , "dummy" , "usdhc1" , "dummy" , "dummy" , "ecspi_root" , "dummy" , |
67 | "dummy" , "dummy" , "dummy" , "dummy" , "dummy" , "dummy" , "osc" , "dummy" , |
68 | "dummy" , "usdhc2" , "sai1" , "sai2" , "sai3" , "dummy" , "dummy" , "can_root" , |
69 | "dummy" , "dummy" , "dummy" , "dummy" , "uart_serial" , "spdif" , "dummy" , "dummy" , }; |
70 | static const char *cko_sels[] = { "cko1" , "cko2" , }; |
71 | |
72 | static struct clk_hw **hws; |
73 | static struct clk_hw_onecell_data *clk_hw_data; |
74 | |
75 | static const struct clk_div_table clk_enet_ref_table[] = { |
76 | { .val = 0, .div = 20, }, |
77 | { .val = 1, .div = 10, }, |
78 | { .val = 2, .div = 5, }, |
79 | { .val = 3, .div = 4, }, |
80 | { } |
81 | }; |
82 | |
83 | static const struct clk_div_table post_div_table[] = { |
84 | { .val = 2, .div = 1, }, |
85 | { .val = 1, .div = 2, }, |
86 | { .val = 0, .div = 4, }, |
87 | { } |
88 | }; |
89 | |
90 | static const struct clk_div_table video_div_table[] = { |
91 | { .val = 0, .div = 1, }, |
92 | { .val = 1, .div = 2, }, |
93 | { .val = 2, .div = 1, }, |
94 | { .val = 3, .div = 4, }, |
95 | { } |
96 | }; |
97 | |
98 | static const char * enet1_ref_sels[] = { "enet1_ref_125m" , "enet1_ref_pad" , "dummy" , "dummy" }; |
99 | static const u32 enet1_ref_sels_table[] = { IMX6UL_GPR1_ENET1_TX_CLK_DIR, |
100 | IMX6UL_GPR1_ENET1_CLK_SEL, 0, |
101 | IMX6UL_GPR1_ENET1_TX_CLK_DIR | IMX6UL_GPR1_ENET1_CLK_SEL }; |
102 | static const u32 enet1_ref_sels_table_mask = IMX6UL_GPR1_ENET1_TX_CLK_DIR | |
103 | IMX6UL_GPR1_ENET1_CLK_SEL; |
104 | static const char * enet2_ref_sels[] = { "enet2_ref_125m" , "enet2_ref_pad" , "dummy" , "dummy" }; |
105 | static const u32 enet2_ref_sels_table[] = { IMX6UL_GPR1_ENET2_TX_CLK_DIR, |
106 | IMX6UL_GPR1_ENET2_CLK_SEL, 0, |
107 | IMX6UL_GPR1_ENET2_TX_CLK_DIR | IMX6UL_GPR1_ENET2_CLK_SEL }; |
108 | static const u32 enet2_ref_sels_table_mask = IMX6UL_GPR1_ENET2_TX_CLK_DIR | |
109 | IMX6UL_GPR1_ENET2_CLK_SEL; |
110 | |
111 | static u32 share_count_asrc; |
112 | static u32 share_count_audio; |
113 | static u32 share_count_sai1; |
114 | static u32 share_count_sai2; |
115 | static u32 share_count_sai3; |
116 | static u32 share_count_esai; |
117 | |
118 | static inline int clk_on_imx6ul(void) |
119 | { |
120 | return of_machine_is_compatible(compat: "fsl,imx6ul" ); |
121 | } |
122 | |
123 | static inline int clk_on_imx6ull(void) |
124 | { |
125 | return of_machine_is_compatible(compat: "fsl,imx6ull" ); |
126 | } |
127 | |
128 | static void __init imx6ul_clocks_init(struct device_node *ccm_node) |
129 | { |
130 | struct device_node *np; |
131 | void __iomem *base; |
132 | |
133 | clk_hw_data = kzalloc(struct_size(clk_hw_data, hws, |
134 | IMX6UL_CLK_END), GFP_KERNEL); |
135 | if (WARN_ON(!clk_hw_data)) |
136 | return; |
137 | |
138 | clk_hw_data->num = IMX6UL_CLK_END; |
139 | hws = clk_hw_data->hws; |
140 | |
141 | hws[IMX6UL_CLK_DUMMY] = imx_clk_hw_fixed(name: "dummy" , rate: 0); |
142 | |
143 | hws[IMX6UL_CLK_CKIL] = imx_get_clk_hw_by_name(np: ccm_node, name: "ckil" ); |
144 | hws[IMX6UL_CLK_OSC] = imx_get_clk_hw_by_name(np: ccm_node, name: "osc" ); |
145 | |
146 | /* ipp_di clock is external input */ |
147 | hws[IMX6UL_CLK_IPP_DI0] = imx_get_clk_hw_by_name(np: ccm_node, name: "ipp_di0" ); |
148 | hws[IMX6UL_CLK_IPP_DI1] = imx_get_clk_hw_by_name(np: ccm_node, name: "ipp_di1" ); |
149 | |
150 | np = of_find_compatible_node(NULL, NULL, compat: "fsl,imx6ul-anatop" ); |
151 | base = of_iomap(node: np, index: 0); |
152 | of_node_put(node: np); |
153 | WARN_ON(!base); |
154 | |
155 | hws[IMX6UL_PLL1_BYPASS_SRC] = imx_clk_hw_mux("pll1_bypass_src" , base + 0x00, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels)); |
156 | hws[IMX6UL_PLL2_BYPASS_SRC] = imx_clk_hw_mux("pll2_bypass_src" , base + 0x30, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels)); |
157 | hws[IMX6UL_PLL3_BYPASS_SRC] = imx_clk_hw_mux("pll3_bypass_src" , base + 0x10, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels)); |
158 | hws[IMX6UL_PLL4_BYPASS_SRC] = imx_clk_hw_mux("pll4_bypass_src" , base + 0x70, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels)); |
159 | hws[IMX6UL_PLL5_BYPASS_SRC] = imx_clk_hw_mux("pll5_bypass_src" , base + 0xa0, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels)); |
160 | hws[IMX6UL_PLL6_BYPASS_SRC] = imx_clk_hw_mux("pll6_bypass_src" , base + 0xe0, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels)); |
161 | hws[IMX6UL_PLL7_BYPASS_SRC] = imx_clk_hw_mux("pll7_bypass_src" , base + 0x20, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels)); |
162 | |
163 | hws[IMX6UL_CLK_PLL1] = imx_clk_hw_pllv3(type: IMX_PLLV3_SYS, name: "pll1" , parent_name: "osc" , base: base + 0x00, div_mask: 0x7f); |
164 | hws[IMX6UL_CLK_PLL2] = imx_clk_hw_pllv3(type: IMX_PLLV3_GENERIC, name: "pll2" , parent_name: "osc" , base: base + 0x30, div_mask: 0x1); |
165 | hws[IMX6UL_CLK_PLL3] = imx_clk_hw_pllv3(type: IMX_PLLV3_USB, name: "pll3" , parent_name: "osc" , base: base + 0x10, div_mask: 0x3); |
166 | hws[IMX6UL_CLK_PLL4] = imx_clk_hw_pllv3(type: IMX_PLLV3_AV, name: "pll4" , parent_name: "osc" , base: base + 0x70, div_mask: 0x7f); |
167 | hws[IMX6UL_CLK_PLL5] = imx_clk_hw_pllv3(type: IMX_PLLV3_AV, name: "pll5" , parent_name: "osc" , base: base + 0xa0, div_mask: 0x7f); |
168 | hws[IMX6UL_CLK_PLL6] = imx_clk_hw_pllv3(type: IMX_PLLV3_ENET, name: "pll6" , parent_name: "osc" , base: base + 0xe0, div_mask: 0x3); |
169 | hws[IMX6UL_CLK_PLL7] = imx_clk_hw_pllv3(type: IMX_PLLV3_USB, name: "pll7" , parent_name: "osc" , base: base + 0x20, div_mask: 0x3); |
170 | |
171 | hws[IMX6UL_PLL1_BYPASS] = imx_clk_hw_mux_flags("pll1_bypass" , base + 0x00, 16, 1, pll1_bypass_sels, ARRAY_SIZE(pll1_bypass_sels), CLK_SET_RATE_PARENT); |
172 | hws[IMX6UL_PLL2_BYPASS] = imx_clk_hw_mux_flags("pll2_bypass" , base + 0x30, 16, 1, pll2_bypass_sels, ARRAY_SIZE(pll2_bypass_sels), CLK_SET_RATE_PARENT); |
173 | hws[IMX6UL_PLL3_BYPASS] = imx_clk_hw_mux_flags("pll3_bypass" , base + 0x10, 16, 1, pll3_bypass_sels, ARRAY_SIZE(pll3_bypass_sels), CLK_SET_RATE_PARENT); |
174 | hws[IMX6UL_PLL4_BYPASS] = imx_clk_hw_mux_flags("pll4_bypass" , base + 0x70, 16, 1, pll4_bypass_sels, ARRAY_SIZE(pll4_bypass_sels), CLK_SET_RATE_PARENT); |
175 | hws[IMX6UL_PLL5_BYPASS] = imx_clk_hw_mux_flags("pll5_bypass" , base + 0xa0, 16, 1, pll5_bypass_sels, ARRAY_SIZE(pll5_bypass_sels), CLK_SET_RATE_PARENT); |
176 | hws[IMX6UL_PLL6_BYPASS] = imx_clk_hw_mux_flags("pll6_bypass" , base + 0xe0, 16, 1, pll6_bypass_sels, ARRAY_SIZE(pll6_bypass_sels), CLK_SET_RATE_PARENT); |
177 | hws[IMX6UL_PLL7_BYPASS] = imx_clk_hw_mux_flags("pll7_bypass" , base + 0x20, 16, 1, pll7_bypass_sels, ARRAY_SIZE(pll7_bypass_sels), CLK_SET_RATE_PARENT); |
178 | |
179 | /* Do not bypass PLLs initially */ |
180 | clk_set_parent(clk: hws[IMX6UL_PLL1_BYPASS]->clk, parent: hws[IMX6UL_CLK_PLL1]->clk); |
181 | clk_set_parent(clk: hws[IMX6UL_PLL2_BYPASS]->clk, parent: hws[IMX6UL_CLK_PLL2]->clk); |
182 | clk_set_parent(clk: hws[IMX6UL_PLL3_BYPASS]->clk, parent: hws[IMX6UL_CLK_PLL3]->clk); |
183 | clk_set_parent(clk: hws[IMX6UL_PLL4_BYPASS]->clk, parent: hws[IMX6UL_CLK_PLL4]->clk); |
184 | clk_set_parent(clk: hws[IMX6UL_PLL5_BYPASS]->clk, parent: hws[IMX6UL_CLK_PLL5]->clk); |
185 | clk_set_parent(clk: hws[IMX6UL_PLL6_BYPASS]->clk, parent: hws[IMX6UL_CLK_PLL6]->clk); |
186 | clk_set_parent(clk: hws[IMX6UL_PLL7_BYPASS]->clk, parent: hws[IMX6UL_CLK_PLL7]->clk); |
187 | |
188 | hws[IMX6UL_CLK_PLL1_SYS] = imx_clk_hw_fixed_factor(name: "pll1_sys" , parent: "pll1_bypass" , mult: 1, div: 1); |
189 | hws[IMX6UL_CLK_PLL2_BUS] = imx_clk_hw_gate("pll2_bus" , "pll2_bypass" , base + 0x30, 13); |
190 | hws[IMX6UL_CLK_PLL3_USB_OTG] = imx_clk_hw_gate("pll3_usb_otg" , "pll3_bypass" , base + 0x10, 13); |
191 | hws[IMX6UL_CLK_PLL4_AUDIO] = imx_clk_hw_gate("pll4_audio" , "pll4_bypass" , base + 0x70, 13); |
192 | hws[IMX6UL_CLK_PLL5_VIDEO] = imx_clk_hw_gate("pll5_video" , "pll5_bypass" , base + 0xa0, 13); |
193 | hws[IMX6UL_CLK_PLL6_ENET] = imx_clk_hw_fixed_factor(name: "pll6_enet" , parent: "pll6_bypass" , mult: 1, div: 1); |
194 | hws[IMX6UL_CLK_PLL7_USB_HOST] = imx_clk_hw_gate("pll7_usb_host" , "pll7_bypass" , base + 0x20, 13); |
195 | |
196 | /* |
197 | * Bit 20 is the reserved and read-only bit, we do this only for: |
198 | * - Do nothing for usbphy clk_enable/disable |
199 | * - Keep refcount when do usbphy clk_enable/disable, in that case, |
200 | * the clk framework many need to enable/disable usbphy's parent |
201 | */ |
202 | hws[IMX6UL_CLK_USBPHY1] = imx_clk_hw_gate("usbphy1" , "pll3_usb_otg" , base + 0x10, 20); |
203 | hws[IMX6UL_CLK_USBPHY2] = imx_clk_hw_gate("usbphy2" , "pll7_usb_host" , base + 0x20, 20); |
204 | |
205 | /* |
206 | * usbphy*_gate needs to be on after system boots up, and software |
207 | * never needs to control it anymore. |
208 | */ |
209 | hws[IMX6UL_CLK_USBPHY1_GATE] = imx_clk_hw_gate("usbphy1_gate" , "dummy" , base + 0x10, 6); |
210 | hws[IMX6UL_CLK_USBPHY2_GATE] = imx_clk_hw_gate("usbphy2_gate" , "dummy" , base + 0x20, 6); |
211 | |
212 | /* name parent_name reg idx */ |
213 | hws[IMX6UL_CLK_PLL2_PFD0] = imx_clk_hw_pfd(name: "pll2_pfd0_352m" , parent_name: "pll2_bus" , reg: base + 0x100, idx: 0); |
214 | hws[IMX6UL_CLK_PLL2_PFD1] = imx_clk_hw_pfd(name: "pll2_pfd1_594m" , parent_name: "pll2_bus" , reg: base + 0x100, idx: 1); |
215 | hws[IMX6UL_CLK_PLL2_PFD2] = imx_clk_hw_pfd(name: "pll2_pfd2_396m" , parent_name: "pll2_bus" , reg: base + 0x100, idx: 2); |
216 | hws[IMX6UL_CLK_PLL2_PFD3] = imx_clk_hw_pfd(name: "pll2_pfd3_594m" , parent_name: "pll2_bus" , reg: base + 0x100, idx: 3); |
217 | hws[IMX6UL_CLK_PLL3_PFD0] = imx_clk_hw_pfd(name: "pll3_pfd0_720m" , parent_name: "pll3_usb_otg" , reg: base + 0xf0, idx: 0); |
218 | hws[IMX6UL_CLK_PLL3_PFD1] = imx_clk_hw_pfd(name: "pll3_pfd1_540m" , parent_name: "pll3_usb_otg" , reg: base + 0xf0, idx: 1); |
219 | hws[IMX6UL_CLK_PLL3_PFD2] = imx_clk_hw_pfd(name: "pll3_pfd2_508m" , parent_name: "pll3_usb_otg" , reg: base + 0xf0, idx: 2); |
220 | hws[IMX6UL_CLK_PLL3_PFD3] = imx_clk_hw_pfd(name: "pll3_pfd3_454m" , parent_name: "pll3_usb_otg" , reg: base + 0xf0, idx: 3); |
221 | |
222 | hws[IMX6UL_CLK_ENET_REF] = clk_hw_register_divider_table(NULL, "enet1_ref" , "pll6_enet" , 0, |
223 | base + 0xe0, 0, 2, 0, clk_enet_ref_table, &imx_ccm_lock); |
224 | hws[IMX6UL_CLK_ENET2_REF] = clk_hw_register_divider_table(NULL, "enet2_ref" , "pll6_enet" , 0, |
225 | base + 0xe0, 2, 2, 0, clk_enet_ref_table, &imx_ccm_lock); |
226 | |
227 | hws[IMX6UL_CLK_ENET1_REF_125M] = imx_clk_hw_gate("enet1_ref_125m" , "enet1_ref" , base + 0xe0, 13); |
228 | hws[IMX6UL_CLK_ENET2_REF_125M] = imx_clk_hw_gate("enet2_ref_125m" , "enet2_ref" , base + 0xe0, 20); |
229 | hws[IMX6UL_CLK_ENET_PTP_REF] = imx_clk_hw_fixed_factor(name: "enet_ptp_ref" , parent: "pll6_enet" , mult: 1, div: 20); |
230 | hws[IMX6UL_CLK_ENET_PTP] = imx_clk_hw_gate("enet_ptp" , "enet_ptp_ref" , base + 0xe0, 21); |
231 | |
232 | hws[IMX6UL_CLK_PLL4_POST_DIV] = clk_hw_register_divider_table(NULL, "pll4_post_div" , "pll4_audio" , |
233 | CLK_SET_RATE_PARENT | CLK_SET_RATE_GATE, base + 0x70, 19, 2, 0, post_div_table, &imx_ccm_lock); |
234 | hws[IMX6UL_CLK_PLL4_AUDIO_DIV] = clk_hw_register_divider(NULL, "pll4_audio_div" , "pll4_post_div" , |
235 | CLK_SET_RATE_PARENT | CLK_SET_RATE_GATE, base + 0x170, 15, 1, 0, &imx_ccm_lock); |
236 | hws[IMX6UL_CLK_PLL5_POST_DIV] = clk_hw_register_divider_table(NULL, "pll5_post_div" , "pll5_video" , |
237 | CLK_SET_RATE_PARENT | CLK_SET_RATE_GATE, base + 0xa0, 19, 2, 0, post_div_table, &imx_ccm_lock); |
238 | hws[IMX6UL_CLK_PLL5_VIDEO_DIV] = clk_hw_register_divider_table(NULL, "pll5_video_div" , "pll5_post_div" , |
239 | CLK_SET_RATE_PARENT | CLK_SET_RATE_GATE, base + 0x170, 30, 2, 0, video_div_table, &imx_ccm_lock); |
240 | |
241 | /* name parent_name mult div */ |
242 | hws[IMX6UL_CLK_PLL2_198M] = imx_clk_hw_fixed_factor(name: "pll2_198m" , parent: "pll2_pfd2_396m" , mult: 1, div: 2); |
243 | hws[IMX6UL_CLK_PLL3_80M] = imx_clk_hw_fixed_factor(name: "pll3_80m" , parent: "pll3_usb_otg" , mult: 1, div: 6); |
244 | hws[IMX6UL_CLK_PLL3_60M] = imx_clk_hw_fixed_factor(name: "pll3_60m" , parent: "pll3_usb_otg" , mult: 1, div: 8); |
245 | hws[IMX6UL_CLK_GPT_3M] = imx_clk_hw_fixed_factor(name: "gpt_3m" , parent: "osc" , mult: 1, div: 8); |
246 | |
247 | np = ccm_node; |
248 | base = of_iomap(node: np, index: 0); |
249 | WARN_ON(!base); |
250 | |
251 | hws[IMX6UL_CA7_SECONDARY_SEL] = imx_clk_hw_mux("ca7_secondary_sel" , base + 0xc, 3, 1, ca7_secondary_sels, ARRAY_SIZE(ca7_secondary_sels)); |
252 | hws[IMX6UL_CLK_STEP] = imx_clk_hw_mux("step" , base + 0x0c, 8, 1, step_sels, ARRAY_SIZE(step_sels)); |
253 | hws[IMX6UL_CLK_PLL1_SW] = imx_clk_hw_mux_flags("pll1_sw" , base + 0x0c, 2, 1, pll1_sw_sels, ARRAY_SIZE(pll1_sw_sels), 0); |
254 | hws[IMX6UL_CLK_AXI_ALT_SEL] = imx_clk_hw_mux("axi_alt_sel" , base + 0x14, 7, 1, axi_alt_sels, ARRAY_SIZE(axi_alt_sels)); |
255 | hws[IMX6UL_CLK_AXI_SEL] = imx_clk_hw_mux_flags("axi_sel" , base + 0x14, 6, 1, axi_sels, ARRAY_SIZE(axi_sels), 0); |
256 | hws[IMX6UL_CLK_PERIPH_PRE] = imx_clk_hw_mux("periph_pre" , base + 0x18, 18, 2, periph_pre_sels, ARRAY_SIZE(periph_pre_sels)); |
257 | hws[IMX6UL_CLK_PERIPH2_PRE] = imx_clk_hw_mux("periph2_pre" , base + 0x18, 21, 2, periph2_pre_sels, ARRAY_SIZE(periph2_pre_sels)); |
258 | hws[IMX6UL_CLK_PERIPH_CLK2_SEL] = imx_clk_hw_mux("periph_clk2_sel" , base + 0x18, 12, 2, periph_clk2_sels, ARRAY_SIZE(periph_clk2_sels)); |
259 | hws[IMX6UL_CLK_PERIPH2_CLK2_SEL] = imx_clk_hw_mux("periph2_clk2_sel" , base + 0x18, 20, 1, periph2_clk2_sels, ARRAY_SIZE(periph2_clk2_sels)); |
260 | hws[IMX6UL_CLK_EIM_SLOW_SEL] = imx_clk_hw_mux("eim_slow_sel" , base + 0x1c, 29, 2, eim_slow_sels, ARRAY_SIZE(eim_slow_sels)); |
261 | hws[IMX6UL_CLK_GPMI_SEL] = imx_clk_hw_mux("gpmi_sel" , base + 0x1c, 19, 1, gpmi_sels, ARRAY_SIZE(gpmi_sels)); |
262 | hws[IMX6UL_CLK_BCH_SEL] = imx_clk_hw_mux("bch_sel" , base + 0x1c, 18, 1, bch_sels, ARRAY_SIZE(bch_sels)); |
263 | hws[IMX6UL_CLK_USDHC2_SEL] = imx_clk_hw_mux("usdhc2_sel" , base + 0x1c, 17, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels)); |
264 | hws[IMX6UL_CLK_USDHC1_SEL] = imx_clk_hw_mux("usdhc1_sel" , base + 0x1c, 16, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels)); |
265 | hws[IMX6UL_CLK_SAI3_SEL] = imx_clk_hw_mux("sai3_sel" , base + 0x1c, 14, 2, sai_sels, ARRAY_SIZE(sai_sels)); |
266 | hws[IMX6UL_CLK_SAI2_SEL] = imx_clk_hw_mux("sai2_sel" , base + 0x1c, 12, 2, sai_sels, ARRAY_SIZE(sai_sels)); |
267 | hws[IMX6UL_CLK_SAI1_SEL] = imx_clk_hw_mux("sai1_sel" , base + 0x1c, 10, 2, sai_sels, ARRAY_SIZE(sai_sels)); |
268 | hws[IMX6UL_CLK_QSPI1_SEL] = imx_clk_hw_mux("qspi1_sel" , base + 0x1c, 7, 3, qspi1_sels, ARRAY_SIZE(qspi1_sels)); |
269 | hws[IMX6UL_CLK_PERCLK_SEL] = imx_clk_hw_mux("perclk_sel" , base + 0x1c, 6, 1, perclk_sels, ARRAY_SIZE(perclk_sels)); |
270 | hws[IMX6UL_CLK_CAN_SEL] = imx_clk_hw_mux("can_sel" , base + 0x20, 8, 2, can_sels, ARRAY_SIZE(can_sels)); |
271 | if (clk_on_imx6ull()) |
272 | hws[IMX6ULL_CLK_ESAI_SEL] = imx_clk_hw_mux("esai_sel" , base + 0x20, 19, 2, esai_sels, ARRAY_SIZE(esai_sels)); |
273 | hws[IMX6UL_CLK_UART_SEL] = imx_clk_hw_mux("uart_sel" , base + 0x24, 6, 1, uart_sels, ARRAY_SIZE(uart_sels)); |
274 | hws[IMX6UL_CLK_ENFC_SEL] = imx_clk_hw_mux("enfc_sel" , base + 0x2c, 15, 3, enfc_sels, ARRAY_SIZE(enfc_sels)); |
275 | hws[IMX6UL_CLK_LDB_DI0_SEL] = imx_clk_hw_mux("ldb_di0_sel" , base + 0x2c, 9, 3, ldb_di0_sels, ARRAY_SIZE(ldb_di0_sels)); |
276 | hws[IMX6UL_CLK_SPDIF_SEL] = imx_clk_hw_mux("spdif_sel" , base + 0x30, 20, 2, spdif_sels, ARRAY_SIZE(spdif_sels)); |
277 | if (clk_on_imx6ul()) { |
278 | hws[IMX6UL_CLK_SIM_PRE_SEL] = imx_clk_hw_mux("sim_pre_sel" , base + 0x34, 15, 3, sim_pre_sels, ARRAY_SIZE(sim_pre_sels)); |
279 | hws[IMX6UL_CLK_SIM_SEL] = imx_clk_hw_mux("sim_sel" , base + 0x34, 9, 3, sim_sels, ARRAY_SIZE(sim_sels)); |
280 | } else if (clk_on_imx6ull()) { |
281 | hws[IMX6ULL_CLK_EPDC_PRE_SEL] = imx_clk_hw_mux("epdc_pre_sel" , base + 0x34, 15, 3, epdc_pre_sels, ARRAY_SIZE(epdc_pre_sels)); |
282 | hws[IMX6ULL_CLK_EPDC_SEL] = imx_clk_hw_mux("epdc_sel" , base + 0x34, 9, 3, epdc_sels, ARRAY_SIZE(epdc_sels)); |
283 | } |
284 | hws[IMX6UL_CLK_ECSPI_SEL] = imx_clk_hw_mux("ecspi_sel" , base + 0x38, 18, 1, ecspi_sels, ARRAY_SIZE(ecspi_sels)); |
285 | hws[IMX6UL_CLK_LCDIF_PRE_SEL] = imx_clk_hw_mux_flags("lcdif_pre_sel" , base + 0x38, 15, 3, lcdif_pre_sels, ARRAY_SIZE(lcdif_pre_sels), CLK_SET_RATE_PARENT); |
286 | hws[IMX6UL_CLK_LCDIF_SEL] = imx_clk_hw_mux("lcdif_sel" , base + 0x38, 9, 3, lcdif_sels, ARRAY_SIZE(lcdif_sels)); |
287 | hws[IMX6UL_CLK_CSI_SEL] = imx_clk_hw_mux("csi_sel" , base + 0x3c, 9, 2, csi_sels, ARRAY_SIZE(csi_sels)); |
288 | |
289 | hws[IMX6UL_CLK_LDB_DI0_DIV_SEL] = imx_clk_hw_mux("ldb_di0" , base + 0x20, 10, 1, ldb_di0_div_sels, ARRAY_SIZE(ldb_di0_div_sels)); |
290 | hws[IMX6UL_CLK_LDB_DI1_DIV_SEL] = imx_clk_hw_mux("ldb_di1" , base + 0x20, 11, 1, ldb_di1_div_sels, ARRAY_SIZE(ldb_di1_div_sels)); |
291 | |
292 | hws[IMX6UL_CLK_CKO1_SEL] = imx_clk_hw_mux("cko1_sel" , base + 0x60, 0, 4, cko1_sels, ARRAY_SIZE(cko1_sels)); |
293 | hws[IMX6UL_CLK_CKO2_SEL] = imx_clk_hw_mux("cko2_sel" , base + 0x60, 16, 5, cko2_sels, ARRAY_SIZE(cko2_sels)); |
294 | hws[IMX6UL_CLK_CKO] = imx_clk_hw_mux("cko" , base + 0x60, 8, 1, cko_sels, ARRAY_SIZE(cko_sels)); |
295 | |
296 | hws[IMX6UL_CLK_LDB_DI0_DIV_3_5] = imx_clk_hw_fixed_factor(name: "ldb_di0_div_3_5" , parent: "ldb_di0_sel" , mult: 2, div: 7); |
297 | hws[IMX6UL_CLK_LDB_DI0_DIV_7] = imx_clk_hw_fixed_factor(name: "ldb_di0_div_7" , parent: "ldb_di0_sel" , mult: 1, div: 7); |
298 | hws[IMX6UL_CLK_LDB_DI1_DIV_3_5] = imx_clk_hw_fixed_factor(name: "ldb_di1_div_3_5" , parent: "qspi1_sel" , mult: 2, div: 7); |
299 | hws[IMX6UL_CLK_LDB_DI1_DIV_7] = imx_clk_hw_fixed_factor(name: "ldb_di1_div_7" , parent: "qspi1_sel" , mult: 1, div: 7); |
300 | |
301 | hws[IMX6UL_CLK_PERIPH] = imx_clk_hw_busy_mux(name: "periph" , reg: base + 0x14, shift: 25, width: 1, busy_reg: base + 0x48, busy_shift: 5, parent_names: periph_sels, ARRAY_SIZE(periph_sels)); |
302 | hws[IMX6UL_CLK_PERIPH2] = imx_clk_hw_busy_mux(name: "periph2" , reg: base + 0x14, shift: 26, width: 1, busy_reg: base + 0x48, busy_shift: 3, parent_names: periph2_sels, ARRAY_SIZE(periph2_sels)); |
303 | |
304 | hws[IMX6UL_CLK_PERIPH_CLK2] = imx_clk_hw_divider("periph_clk2" , "periph_clk2_sel" , base + 0x14, 27, 3); |
305 | hws[IMX6UL_CLK_PERIPH2_CLK2] = imx_clk_hw_divider("periph2_clk2" , "periph2_clk2_sel" , base + 0x14, 0, 3); |
306 | hws[IMX6UL_CLK_IPG] = imx_clk_hw_divider("ipg" , "ahb" , base + 0x14, 8, 2); |
307 | hws[IMX6UL_CLK_LCDIF_PODF] = imx_clk_hw_divider("lcdif_podf" , "lcdif_pred" , base + 0x18, 23, 3); |
308 | hws[IMX6UL_CLK_QSPI1_PDOF] = imx_clk_hw_divider("qspi1_podf" , "qspi1_sel" , base + 0x1c, 26, 3); |
309 | hws[IMX6UL_CLK_EIM_SLOW_PODF] = imx_clk_hw_divider("eim_slow_podf" , "eim_slow_sel" , base + 0x1c, 23, 3); |
310 | hws[IMX6UL_CLK_PERCLK] = imx_clk_hw_divider("perclk" , "perclk_sel" , base + 0x1c, 0, 6); |
311 | hws[IMX6UL_CLK_CAN_PODF] = imx_clk_hw_divider("can_podf" , "can_sel" , base + 0x20, 2, 6); |
312 | hws[IMX6UL_CLK_GPMI_PODF] = imx_clk_hw_divider("gpmi_podf" , "gpmi_sel" , base + 0x24, 22, 3); |
313 | hws[IMX6UL_CLK_BCH_PODF] = imx_clk_hw_divider("bch_podf" , "bch_sel" , base + 0x24, 19, 3); |
314 | hws[IMX6UL_CLK_USDHC2_PODF] = imx_clk_hw_divider("usdhc2_podf" , "usdhc2_sel" , base + 0x24, 16, 3); |
315 | hws[IMX6UL_CLK_USDHC1_PODF] = imx_clk_hw_divider("usdhc1_podf" , "usdhc1_sel" , base + 0x24, 11, 3); |
316 | hws[IMX6UL_CLK_UART_PODF] = imx_clk_hw_divider("uart_podf" , "uart_sel" , base + 0x24, 0, 6); |
317 | hws[IMX6UL_CLK_SAI3_PRED] = imx_clk_hw_divider("sai3_pred" , "sai3_sel" , base + 0x28, 22, 3); |
318 | hws[IMX6UL_CLK_SAI3_PODF] = imx_clk_hw_divider("sai3_podf" , "sai3_pred" , base + 0x28, 16, 6); |
319 | hws[IMX6UL_CLK_SAI1_PRED] = imx_clk_hw_divider("sai1_pred" , "sai1_sel" , base + 0x28, 6, 3); |
320 | hws[IMX6UL_CLK_SAI1_PODF] = imx_clk_hw_divider("sai1_podf" , "sai1_pred" , base + 0x28, 0, 6); |
321 | if (clk_on_imx6ull()) { |
322 | hws[IMX6ULL_CLK_ESAI_PRED] = imx_clk_hw_divider("esai_pred" , "esai_sel" , base + 0x28, 9, 3); |
323 | hws[IMX6ULL_CLK_ESAI_PODF] = imx_clk_hw_divider("esai_podf" , "esai_pred" , base + 0x28, 25, 3); |
324 | } |
325 | hws[IMX6UL_CLK_ENFC_PRED] = imx_clk_hw_divider("enfc_pred" , "enfc_sel" , base + 0x2c, 18, 3); |
326 | hws[IMX6UL_CLK_ENFC_PODF] = imx_clk_hw_divider("enfc_podf" , "enfc_pred" , base + 0x2c, 21, 6); |
327 | hws[IMX6UL_CLK_SAI2_PRED] = imx_clk_hw_divider("sai2_pred" , "sai2_sel" , base + 0x2c, 6, 3); |
328 | hws[IMX6UL_CLK_SAI2_PODF] = imx_clk_hw_divider("sai2_podf" , "sai2_pred" , base + 0x2c, 0, 6); |
329 | hws[IMX6UL_CLK_SPDIF_PRED] = imx_clk_hw_divider("spdif_pred" , "spdif_sel" , base + 0x30, 25, 3); |
330 | hws[IMX6UL_CLK_SPDIF_PODF] = imx_clk_hw_divider("spdif_podf" , "spdif_pred" , base + 0x30, 22, 3); |
331 | if (clk_on_imx6ul()) |
332 | hws[IMX6UL_CLK_SIM_PODF] = imx_clk_hw_divider("sim_podf" , "sim_pre_sel" , base + 0x34, 12, 3); |
333 | else if (clk_on_imx6ull()) |
334 | hws[IMX6ULL_CLK_EPDC_PODF] = imx_clk_hw_divider("epdc_podf" , "epdc_pre_sel" , base + 0x34, 12, 3); |
335 | hws[IMX6UL_CLK_ECSPI_PODF] = imx_clk_hw_divider("ecspi_podf" , "ecspi_sel" , base + 0x38, 19, 6); |
336 | hws[IMX6UL_CLK_LCDIF_PRED] = imx_clk_hw_divider("lcdif_pred" , "lcdif_pre_sel" , base + 0x38, 12, 3); |
337 | hws[IMX6UL_CLK_CSI_PODF] = imx_clk_hw_divider("csi_podf" , "csi_sel" , base + 0x3c, 11, 3); |
338 | |
339 | hws[IMX6UL_CLK_CKO1_PODF] = imx_clk_hw_divider("cko1_podf" , "cko1_sel" , base + 0x60, 4, 3); |
340 | hws[IMX6UL_CLK_CKO2_PODF] = imx_clk_hw_divider("cko2_podf" , "cko2_sel" , base + 0x60, 21, 3); |
341 | |
342 | hws[IMX6UL_CLK_ARM] = imx_clk_hw_busy_divider(name: "arm" , parent_name: "pll1_sw" , reg: base + 0x10, shift: 0, width: 3, busy_reg: base + 0x48, busy_shift: 16); |
343 | hws[IMX6UL_CLK_MMDC_PODF] = imx_clk_hw_busy_divider(name: "mmdc_podf" , parent_name: "periph2" , reg: base + 0x14, shift: 3, width: 3, busy_reg: base + 0x48, busy_shift: 2); |
344 | hws[IMX6UL_CLK_AXI_PODF] = imx_clk_hw_busy_divider(name: "axi_podf" , parent_name: "axi_sel" , reg: base + 0x14, shift: 16, width: 3, busy_reg: base + 0x48, busy_shift: 0); |
345 | hws[IMX6UL_CLK_AHB] = imx_clk_hw_busy_divider(name: "ahb" , parent_name: "periph" , reg: base + 0x14, shift: 10, width: 3, busy_reg: base + 0x48, busy_shift: 1); |
346 | |
347 | /* CCGR0 */ |
348 | hws[IMX6UL_CLK_AIPSTZ1] = imx_clk_hw_gate2_flags("aips_tz1" , "ahb" , base + 0x68, 0, CLK_IS_CRITICAL); |
349 | hws[IMX6UL_CLK_AIPSTZ2] = imx_clk_hw_gate2_flags("aips_tz2" , "ahb" , base + 0x68, 2, CLK_IS_CRITICAL); |
350 | hws[IMX6UL_CLK_APBHDMA] = imx_clk_hw_gate2("apbh_dma" , "bch_podf" , base + 0x68, 4); |
351 | hws[IMX6UL_CLK_ASRC_IPG] = imx_clk_hw_gate2_shared("asrc_ipg" , "ahb" , base + 0x68, 6, &share_count_asrc); |
352 | hws[IMX6UL_CLK_ASRC_MEM] = imx_clk_hw_gate2_shared("asrc_mem" , "ahb" , base + 0x68, 6, &share_count_asrc); |
353 | if (clk_on_imx6ul()) { |
354 | hws[IMX6UL_CLK_CAAM_MEM] = imx_clk_hw_gate2("caam_mem" , "ahb" , base + 0x68, 8); |
355 | hws[IMX6UL_CLK_CAAM_ACLK] = imx_clk_hw_gate2("caam_aclk" , "ahb" , base + 0x68, 10); |
356 | hws[IMX6UL_CLK_CAAM_IPG] = imx_clk_hw_gate2("caam_ipg" , "ipg" , base + 0x68, 12); |
357 | } else if (clk_on_imx6ull()) { |
358 | hws[IMX6ULL_CLK_DCP_CLK] = imx_clk_hw_gate2("dcp" , "ahb" , base + 0x68, 10); |
359 | hws[IMX6UL_CLK_ENET] = imx_clk_hw_gate2("enet" , "ipg" , base + 0x68, 12); |
360 | hws[IMX6UL_CLK_ENET_AHB] = imx_clk_hw_gate2("enet_ahb" , "ahb" , base + 0x68, 12); |
361 | } |
362 | hws[IMX6UL_CLK_CAN1_IPG] = imx_clk_hw_gate2("can1_ipg" , "ipg" , base + 0x68, 14); |
363 | hws[IMX6UL_CLK_CAN1_SERIAL] = imx_clk_hw_gate2("can1_serial" , "can_podf" , base + 0x68, 16); |
364 | hws[IMX6UL_CLK_CAN2_IPG] = imx_clk_hw_gate2("can2_ipg" , "ipg" , base + 0x68, 18); |
365 | hws[IMX6UL_CLK_CAN2_SERIAL] = imx_clk_hw_gate2("can2_serial" , "can_podf" , base + 0x68, 20); |
366 | hws[IMX6UL_CLK_GPT2_BUS] = imx_clk_hw_gate2("gpt2_bus" , "perclk" , base + 0x68, 24); |
367 | hws[IMX6UL_CLK_GPT2_SERIAL] = imx_clk_hw_gate2("gpt2_serial" , "perclk" , base + 0x68, 26); |
368 | hws[IMX6UL_CLK_UART2_IPG] = imx_clk_hw_gate2("uart2_ipg" , "ipg" , base + 0x68, 28); |
369 | hws[IMX6UL_CLK_UART2_SERIAL] = imx_clk_hw_gate2("uart2_serial" , "uart_podf" , base + 0x68, 28); |
370 | if (clk_on_imx6ull()) |
371 | hws[IMX6UL_CLK_AIPSTZ3] = imx_clk_hw_gate2("aips_tz3" , "ahb" , base + 0x80, 18); |
372 | hws[IMX6UL_CLK_GPIO2] = imx_clk_hw_gate2("gpio2" , "ipg" , base + 0x68, 30); |
373 | |
374 | /* CCGR1 */ |
375 | hws[IMX6UL_CLK_ECSPI1] = imx_clk_hw_gate2("ecspi1" , "ecspi_podf" , base + 0x6c, 0); |
376 | hws[IMX6UL_CLK_ECSPI2] = imx_clk_hw_gate2("ecspi2" , "ecspi_podf" , base + 0x6c, 2); |
377 | hws[IMX6UL_CLK_ECSPI3] = imx_clk_hw_gate2("ecspi3" , "ecspi_podf" , base + 0x6c, 4); |
378 | hws[IMX6UL_CLK_ECSPI4] = imx_clk_hw_gate2("ecspi4" , "ecspi_podf" , base + 0x6c, 6); |
379 | hws[IMX6UL_CLK_ADC2] = imx_clk_hw_gate2("adc2" , "ipg" , base + 0x6c, 8); |
380 | hws[IMX6UL_CLK_UART3_IPG] = imx_clk_hw_gate2("uart3_ipg" , "ipg" , base + 0x6c, 10); |
381 | hws[IMX6UL_CLK_UART3_SERIAL] = imx_clk_hw_gate2("uart3_serial" , "uart_podf" , base + 0x6c, 10); |
382 | hws[IMX6UL_CLK_EPIT1] = imx_clk_hw_gate2("epit1" , "perclk" , base + 0x6c, 12); |
383 | hws[IMX6UL_CLK_EPIT2] = imx_clk_hw_gate2("epit2" , "perclk" , base + 0x6c, 14); |
384 | hws[IMX6UL_CLK_ADC1] = imx_clk_hw_gate2("adc1" , "ipg" , base + 0x6c, 16); |
385 | hws[IMX6UL_CLK_GPT1_BUS] = imx_clk_hw_gate2("gpt1_bus" , "perclk" , base + 0x6c, 20); |
386 | hws[IMX6UL_CLK_GPT1_SERIAL] = imx_clk_hw_gate2("gpt1_serial" , "perclk" , base + 0x6c, 22); |
387 | hws[IMX6UL_CLK_UART4_IPG] = imx_clk_hw_gate2("uart4_ipg" , "ipg" , base + 0x6c, 24); |
388 | hws[IMX6UL_CLK_UART4_SERIAL] = imx_clk_hw_gate2("uart4_serial" , "uart_podf" , base + 0x6c, 24); |
389 | hws[IMX6UL_CLK_GPIO1] = imx_clk_hw_gate2("gpio1" , "ipg" , base + 0x6c, 26); |
390 | hws[IMX6UL_CLK_GPIO5] = imx_clk_hw_gate2("gpio5" , "ipg" , base + 0x6c, 30); |
391 | |
392 | /* CCGR2 */ |
393 | if (clk_on_imx6ull()) { |
394 | hws[IMX6ULL_CLK_ESAI_EXTAL] = imx_clk_hw_gate2_shared("esai_extal" , "esai_podf" , base + 0x70, 0, &share_count_esai); |
395 | hws[IMX6ULL_CLK_ESAI_IPG] = imx_clk_hw_gate2_shared("esai_ipg" , "ahb" , base + 0x70, 0, &share_count_esai); |
396 | hws[IMX6ULL_CLK_ESAI_MEM] = imx_clk_hw_gate2_shared("esai_mem" , "ahb" , base + 0x70, 0, &share_count_esai); |
397 | } |
398 | hws[IMX6UL_CLK_I2C1] = imx_clk_hw_gate2("i2c1" , "perclk" , base + 0x70, 6); |
399 | hws[IMX6UL_CLK_I2C2] = imx_clk_hw_gate2("i2c2" , "perclk" , base + 0x70, 8); |
400 | hws[IMX6UL_CLK_I2C3] = imx_clk_hw_gate2("i2c3" , "perclk" , base + 0x70, 10); |
401 | hws[IMX6UL_CLK_OCOTP] = imx_clk_hw_gate2("ocotp" , "ipg" , base + 0x70, 12); |
402 | hws[IMX6UL_CLK_IOMUXC] = imx_clk_hw_gate2("iomuxc" , "lcdif_podf" , base + 0x70, 14); |
403 | hws[IMX6UL_CLK_GPIO3] = imx_clk_hw_gate2("gpio3" , "ipg" , base + 0x70, 26); |
404 | hws[IMX6UL_CLK_LCDIF_APB] = imx_clk_hw_gate2("lcdif_apb" , "axi" , base + 0x70, 28); |
405 | hws[IMX6UL_CLK_PXP] = imx_clk_hw_gate2("pxp" , "axi" , base + 0x70, 30); |
406 | |
407 | /* CCGR3 */ |
408 | /* |
409 | * Although the imx6ull reference manual lists CCGR2 as the csi clk |
410 | * gate register, tests have shown that it is actually the CCGR3 |
411 | * register bit 0/1, same as for the imx6ul. |
412 | */ |
413 | hws[IMX6UL_CLK_CSI] = imx_clk_hw_gate2("csi" , "csi_podf" , base + 0x74, 0); |
414 | hws[IMX6UL_CLK_UART5_IPG] = imx_clk_hw_gate2("uart5_ipg" , "ipg" , base + 0x74, 2); |
415 | hws[IMX6UL_CLK_UART5_SERIAL] = imx_clk_hw_gate2("uart5_serial" , "uart_podf" , base + 0x74, 2); |
416 | if (clk_on_imx6ul()) { |
417 | hws[IMX6UL_CLK_ENET] = imx_clk_hw_gate2("enet" , "ipg" , base + 0x74, 4); |
418 | hws[IMX6UL_CLK_ENET_AHB] = imx_clk_hw_gate2("enet_ahb" , "ahb" , base + 0x74, 4); |
419 | } else if (clk_on_imx6ull()) { |
420 | hws[IMX6ULL_CLK_EPDC_ACLK] = imx_clk_hw_gate2("epdc_aclk" , "axi" , base + 0x74, 4); |
421 | hws[IMX6ULL_CLK_EPDC_PIX] = imx_clk_hw_gate2("epdc_pix" , "epdc_podf" , base + 0x74, 4); |
422 | } |
423 | hws[IMX6UL_CLK_UART6_IPG] = imx_clk_hw_gate2("uart6_ipg" , "ipg" , base + 0x74, 6); |
424 | hws[IMX6UL_CLK_UART6_SERIAL] = imx_clk_hw_gate2("uart6_serial" , "uart_podf" , base + 0x74, 6); |
425 | hws[IMX6UL_CLK_LCDIF_PIX] = imx_clk_hw_gate2("lcdif_pix" , "lcdif_podf" , base + 0x74, 10); |
426 | hws[IMX6UL_CLK_GPIO4] = imx_clk_hw_gate2("gpio4" , "ipg" , base + 0x74, 12); |
427 | hws[IMX6UL_CLK_QSPI] = imx_clk_hw_gate2("qspi1" , "qspi1_podf" , base + 0x74, 14); |
428 | hws[IMX6UL_CLK_WDOG1] = imx_clk_hw_gate2("wdog1" , "ipg" , base + 0x74, 16); |
429 | hws[IMX6UL_CLK_MMDC_P0_FAST] = imx_clk_hw_gate_flags("mmdc_p0_fast" , "mmdc_podf" , base + 0x74, 20, CLK_IS_CRITICAL); |
430 | hws[IMX6UL_CLK_MMDC_P0_IPG] = imx_clk_hw_gate2_flags("mmdc_p0_ipg" , "ipg" , base + 0x74, 24, CLK_IS_CRITICAL); |
431 | hws[IMX6UL_CLK_MMDC_P1_IPG] = imx_clk_hw_gate2_flags("mmdc_p1_ipg" , "ipg" , base + 0x74, 26, CLK_IS_CRITICAL); |
432 | hws[IMX6UL_CLK_AXI] = imx_clk_hw_gate_flags("axi" , "axi_podf" , base + 0x74, 28, CLK_IS_CRITICAL); |
433 | |
434 | /* CCGR4 */ |
435 | hws[IMX6UL_CLK_PER_BCH] = imx_clk_hw_gate2("per_bch" , "bch_podf" , base + 0x78, 12); |
436 | hws[IMX6UL_CLK_PWM1] = imx_clk_hw_gate2("pwm1" , "perclk" , base + 0x78, 16); |
437 | hws[IMX6UL_CLK_PWM2] = imx_clk_hw_gate2("pwm2" , "perclk" , base + 0x78, 18); |
438 | hws[IMX6UL_CLK_PWM3] = imx_clk_hw_gate2("pwm3" , "perclk" , base + 0x78, 20); |
439 | hws[IMX6UL_CLK_PWM4] = imx_clk_hw_gate2("pwm4" , "perclk" , base + 0x78, 22); |
440 | hws[IMX6UL_CLK_GPMI_BCH_APB] = imx_clk_hw_gate2("gpmi_bch_apb" , "bch_podf" , base + 0x78, 24); |
441 | hws[IMX6UL_CLK_GPMI_BCH] = imx_clk_hw_gate2("gpmi_bch" , "gpmi_podf" , base + 0x78, 26); |
442 | hws[IMX6UL_CLK_GPMI_IO] = imx_clk_hw_gate2("gpmi_io" , "enfc_podf" , base + 0x78, 28); |
443 | hws[IMX6UL_CLK_GPMI_APB] = imx_clk_hw_gate2("gpmi_apb" , "bch_podf" , base + 0x78, 30); |
444 | |
445 | /* CCGR5 */ |
446 | hws[IMX6UL_CLK_ROM] = imx_clk_hw_gate2_flags("rom" , "ahb" , base + 0x7c, 0, CLK_IS_CRITICAL); |
447 | hws[IMX6UL_CLK_SDMA] = imx_clk_hw_gate2("sdma" , "ahb" , base + 0x7c, 6); |
448 | hws[IMX6UL_CLK_KPP] = imx_clk_hw_gate2("kpp" , "ipg" , base + 0x7c, 8); |
449 | hws[IMX6UL_CLK_WDOG2] = imx_clk_hw_gate2("wdog2" , "ipg" , base + 0x7c, 10); |
450 | hws[IMX6UL_CLK_SPBA] = imx_clk_hw_gate2("spba" , "ipg" , base + 0x7c, 12); |
451 | hws[IMX6UL_CLK_SPDIF] = imx_clk_hw_gate2_shared("spdif" , "spdif_podf" , base + 0x7c, 14, &share_count_audio); |
452 | hws[IMX6UL_CLK_SPDIF_GCLK] = imx_clk_hw_gate2_shared("spdif_gclk" , "ipg" , base + 0x7c, 14, &share_count_audio); |
453 | hws[IMX6UL_CLK_SAI3] = imx_clk_hw_gate2_shared("sai3" , "sai3_podf" , base + 0x7c, 22, &share_count_sai3); |
454 | hws[IMX6UL_CLK_SAI3_IPG] = imx_clk_hw_gate2_shared("sai3_ipg" , "ipg" , base + 0x7c, 22, &share_count_sai3); |
455 | hws[IMX6UL_CLK_UART1_IPG] = imx_clk_hw_gate2("uart1_ipg" , "ipg" , base + 0x7c, 24); |
456 | hws[IMX6UL_CLK_UART1_SERIAL] = imx_clk_hw_gate2("uart1_serial" , "uart_podf" , base + 0x7c, 24); |
457 | hws[IMX6UL_CLK_UART7_IPG] = imx_clk_hw_gate2("uart7_ipg" , "ipg" , base + 0x7c, 26); |
458 | hws[IMX6UL_CLK_UART7_SERIAL] = imx_clk_hw_gate2("uart7_serial" , "uart_podf" , base + 0x7c, 26); |
459 | hws[IMX6UL_CLK_SAI1] = imx_clk_hw_gate2_shared("sai1" , "sai1_podf" , base + 0x7c, 28, &share_count_sai1); |
460 | hws[IMX6UL_CLK_SAI1_IPG] = imx_clk_hw_gate2_shared("sai1_ipg" , "ipg" , base + 0x7c, 28, &share_count_sai1); |
461 | hws[IMX6UL_CLK_SAI2] = imx_clk_hw_gate2_shared("sai2" , "sai2_podf" , base + 0x7c, 30, &share_count_sai2); |
462 | hws[IMX6UL_CLK_SAI2_IPG] = imx_clk_hw_gate2_shared("sai2_ipg" , "ipg" , base + 0x7c, 30, &share_count_sai2); |
463 | |
464 | /* CCGR6 */ |
465 | hws[IMX6UL_CLK_USBOH3] = imx_clk_hw_gate2("usboh3" , "ipg" , base + 0x80, 0); |
466 | hws[IMX6UL_CLK_USDHC1] = imx_clk_hw_gate2("usdhc1" , "usdhc1_podf" , base + 0x80, 2); |
467 | hws[IMX6UL_CLK_USDHC2] = imx_clk_hw_gate2("usdhc2" , "usdhc2_podf" , base + 0x80, 4); |
468 | if (clk_on_imx6ul()) { |
469 | hws[IMX6UL_CLK_SIM1] = imx_clk_hw_gate2("sim1" , "sim_sel" , base + 0x80, 6); |
470 | hws[IMX6UL_CLK_SIM2] = imx_clk_hw_gate2("sim2" , "sim_sel" , base + 0x80, 8); |
471 | } |
472 | hws[IMX6UL_CLK_EIM] = imx_clk_hw_gate2("eim" , "eim_slow_podf" , base + 0x80, 10); |
473 | hws[IMX6UL_CLK_PWM8] = imx_clk_hw_gate2("pwm8" , "perclk" , base + 0x80, 16); |
474 | hws[IMX6UL_CLK_UART8_IPG] = imx_clk_hw_gate2("uart8_ipg" , "ipg" , base + 0x80, 14); |
475 | hws[IMX6UL_CLK_UART8_SERIAL] = imx_clk_hw_gate2("uart8_serial" , "uart_podf" , base + 0x80, 14); |
476 | hws[IMX6UL_CLK_WDOG3] = imx_clk_hw_gate2("wdog3" , "ipg" , base + 0x80, 20); |
477 | hws[IMX6UL_CLK_I2C4] = imx_clk_hw_gate2("i2c4" , "perclk" , base + 0x80, 24); |
478 | hws[IMX6UL_CLK_PWM5] = imx_clk_hw_gate2("pwm5" , "perclk" , base + 0x80, 26); |
479 | hws[IMX6UL_CLK_PWM6] = imx_clk_hw_gate2("pwm6" , "perclk" , base + 0x80, 28); |
480 | hws[IMX6UL_CLK_PWM7] = imx_clk_hw_gate2("pwm7" , "perclk" , base + 0x80, 30); |
481 | |
482 | /* CCOSR */ |
483 | hws[IMX6UL_CLK_CKO1] = imx_clk_hw_gate("cko1" , "cko1_podf" , base + 0x60, 7); |
484 | hws[IMX6UL_CLK_CKO2] = imx_clk_hw_gate("cko2" , "cko2_podf" , base + 0x60, 24); |
485 | |
486 | /* mask handshake of mmdc */ |
487 | imx_mmdc_mask_handshake(ccm_base: base, chn: 0); |
488 | |
489 | hws[IMX6UL_CLK_ENET1_REF_PAD] = imx_obtain_fixed_of_clock(np: ccm_node, name: "enet1_ref_pad" , rate: 0); |
490 | |
491 | hws[IMX6UL_CLK_ENET1_REF_SEL] = imx_clk_gpr_mux(name: "enet1_ref_sel" , compatible: "fsl,imx6ul-iomuxc-gpr" , |
492 | IOMUXC_GPR1, parent_names: enet1_ref_sels, ARRAY_SIZE(enet1_ref_sels), |
493 | mux_table: enet1_ref_sels_table, mask: enet1_ref_sels_table_mask); |
494 | hws[IMX6UL_CLK_ENET2_REF_PAD] = imx_obtain_fixed_of_clock(np: ccm_node, name: "enet2_ref_pad" , rate: 0); |
495 | |
496 | hws[IMX6UL_CLK_ENET2_REF_SEL] = imx_clk_gpr_mux(name: "enet2_ref_sel" , compatible: "fsl,imx6ul-iomuxc-gpr" , |
497 | IOMUXC_GPR1, parent_names: enet2_ref_sels, ARRAY_SIZE(enet2_ref_sels), |
498 | mux_table: enet2_ref_sels_table, mask: enet2_ref_sels_table_mask); |
499 | |
500 | imx_check_clk_hws(clks: hws, IMX6UL_CLK_END); |
501 | |
502 | of_clk_add_hw_provider(np, get: of_clk_hw_onecell_get, data: clk_hw_data); |
503 | |
504 | /* |
505 | * Lower the AHB clock rate before changing the parent clock source, |
506 | * as AHB clock rate can NOT be higher than 133MHz, but its parent |
507 | * will be switched from 396MHz PFD to 528MHz PLL in order to increase |
508 | * AXI clock rate, so we need to lower AHB rate first to make sure at |
509 | * any time, AHB rate is <= 133MHz. |
510 | */ |
511 | clk_set_rate(clk: hws[IMX6UL_CLK_AHB]->clk, rate: 99000000); |
512 | |
513 | /* Change periph_pre clock to pll2_bus to adjust AXI rate to 264MHz */ |
514 | clk_set_parent(clk: hws[IMX6UL_CLK_PERIPH_CLK2_SEL]->clk, parent: hws[IMX6UL_CLK_OSC]->clk); |
515 | clk_set_parent(clk: hws[IMX6UL_CLK_PERIPH]->clk, parent: hws[IMX6UL_CLK_PERIPH_CLK2]->clk); |
516 | clk_set_parent(clk: hws[IMX6UL_CLK_PERIPH_PRE]->clk, parent: hws[IMX6UL_CLK_PLL2_BUS]->clk); |
517 | clk_set_parent(clk: hws[IMX6UL_CLK_PERIPH]->clk, parent: hws[IMX6UL_CLK_PERIPH_PRE]->clk); |
518 | |
519 | /* Make sure AHB rate is 132MHz */ |
520 | clk_set_rate(clk: hws[IMX6UL_CLK_AHB]->clk, rate: 132000000); |
521 | |
522 | /* set perclk to from OSC */ |
523 | clk_set_parent(clk: hws[IMX6UL_CLK_PERCLK_SEL]->clk, parent: hws[IMX6UL_CLK_OSC]->clk); |
524 | |
525 | clk_set_rate(clk: hws[IMX6UL_CLK_ENET_REF]->clk, rate: 50000000); |
526 | clk_set_rate(clk: hws[IMX6UL_CLK_ENET2_REF]->clk, rate: 50000000); |
527 | clk_set_rate(clk: hws[IMX6UL_CLK_CSI]->clk, rate: 24000000); |
528 | |
529 | if (clk_on_imx6ull()) |
530 | clk_prepare_enable(clk: hws[IMX6UL_CLK_AIPSTZ3]->clk); |
531 | |
532 | if (IS_ENABLED(CONFIG_USB_MXS_PHY)) { |
533 | clk_prepare_enable(clk: hws[IMX6UL_CLK_USBPHY1_GATE]->clk); |
534 | clk_prepare_enable(clk: hws[IMX6UL_CLK_USBPHY2_GATE]->clk); |
535 | } |
536 | |
537 | clk_set_parent(clk: hws[IMX6UL_CLK_CAN_SEL]->clk, parent: hws[IMX6UL_CLK_PLL3_80M]->clk); |
538 | if (clk_on_imx6ul()) |
539 | clk_set_parent(clk: hws[IMX6UL_CLK_SIM_PRE_SEL]->clk, parent: hws[IMX6UL_CLK_PLL3_USB_OTG]->clk); |
540 | else if (clk_on_imx6ull()) |
541 | clk_set_parent(clk: hws[IMX6ULL_CLK_EPDC_PRE_SEL]->clk, parent: hws[IMX6UL_CLK_PLL3_PFD2]->clk); |
542 | |
543 | clk_set_parent(clk: hws[IMX6UL_CLK_ENFC_SEL]->clk, parent: hws[IMX6UL_CLK_PLL2_PFD2]->clk); |
544 | |
545 | clk_set_parent(clk: hws[IMX6UL_CLK_ENET1_REF_SEL]->clk, parent: hws[IMX6UL_CLK_ENET_REF]->clk); |
546 | clk_set_parent(clk: hws[IMX6UL_CLK_ENET2_REF_SEL]->clk, parent: hws[IMX6UL_CLK_ENET2_REF]->clk); |
547 | |
548 | imx_register_uart_clocks(); |
549 | } |
550 | |
551 | CLK_OF_DECLARE(imx6ul, "fsl,imx6ul-ccm" , imx6ul_clocks_init); |
552 | |